JP2006202874A - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce dispersion of film thickness of an insulting film between a semiconductor layer and a gate electrode which constitute TFT, by improving a manufacture process. <P>SOLUTION: A manufacturing method is provided with a semiconductor layer forming process for forming a semiconductor layer 4 in an insulating substrate 10, a first insulating film forming process for forming a first insulating film 3 so that it covers a semiconductor layer 2, a second insulating film forming process for forming a second insulating film 7 so that it covers the first insulating film 3, a resist forming process for pattern-forming resist 11 on a conductive film formed to cover the second insulating film 7, and a gate electrode forming process for forming the gate electrode 12a by etching the conductive film with resist 11 as a mask. The gate electrode forming process is provided with an insulating film removing process for etching a part of the second insulating film 7 in a thickness direction with the conductive film exposed from resist 11, and etching the second insulating film 7 exposed from resist 11 after the gate electrode forming process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a thin film transistor and a thin film transistor, and more particularly to a thin film transistor having a top gate structure.

  A thin film transistor (hereinafter abbreviated as TFT) is formed by forming a semiconductor film on an insulating substrate, and is widely used as a switching element of a liquid crystal display device. This TFT includes a bottom gate structure in which the gate electrode is positioned on the lower side (substrate side) with respect to the semiconductor film and a TFT having a top gate structure in which the gate electrode is positioned on the upper side with respect to the semiconductor film.

  The top gate TFT is manufactured as follows, for example.

  13 to 16 are sectional views partially showing a manufacturing process of a TFT having a top gate structure.

  First, a base coat film 101 is formed by forming a silicon oxide film over the entire substrate such as the glass substrate 100 by a plasma CVD (Chemical Vapor Deposition) method.

  Next, after an amorphous silicon film is formed over the entire substrate on the base coat film 101 by plasma CVD, heat treatment is performed, and crystallization (transformation into a polysilicon film) is performed to form a semiconductor film. After that, the semiconductor layer 102 is formed by pattern formation by a photolithography method.

  Subsequently, a gate insulating film 103 is formed by forming a silicon oxide film over the entire substrate over the base coat film 101 over which the semiconductor layer 102 is formed by a plasma CVD method.

  Further, after a tantalum nitride film 104 and a tungsten film 105 are sequentially formed on the entire substrate on the gate insulating film 103 by a sputtering method, a photoresist is applied and prebaked by a spin coating method.

  Thereafter, the photoresist is exposed through a photomask, developed, and post-baked to form a resist pattern 111 as shown in FIG.

  Next, the tungsten film 105 not covered with the resist pattern 111 is removed by a dry etching method to form a tungsten layer 105a as shown in FIG.

  Further, the tantalum nitride film 104 not covered with the resist pattern 111 is removed by a dry etching method to form a tantalum nitride layer 104a as shown in FIG.

  Subsequently, after removing the resist pattern 111 by ashing, the semiconductor layer 102 is doped with an impurity such as phosphorus through the gate insulating film 103 using the tantalum nitride layer 104a and the tungsten layer 105a as a mask. Thus, the source region 102a, the drain region 102b, and the channel region 102c are formed in the semiconductor layer 102.

  Thereafter, a silicon nitride film and a silicon oxide film are sequentially formed over the entire substrate on the gate insulating film 103 on which the tantalum nitride layer 104a and the tungsten layer 105a are formed by the plasma CVD method to form an interlayer insulating film 108. .

  Then, portions of the stacked film of the gate insulating film 103 and the interlayer insulating film 108 corresponding to the source region 102a and the drain region 102b are removed by etching to form contact holes.

  Finally, a titanium film, an aluminum film, and a titanium film are sequentially formed on the entire substrate on the interlayer insulating film 108 by sputtering, and then a pattern is formed by photolithography, as shown in FIG. A source electrode 106a and a drain electrode 106b are formed.

  The top gate TFT 120 is manufactured by the manufacturing process as described above.

  By the way, in the etching by the photolithography method as described above, the selection ratio of each material to be etched, such as a semiconductor film, a metal thin film, an insulating film, and the like is an important factor that determines the quality of pattern formation. Various studies have been made in particular in a semiconductor manufacturing process for forming a semiconductor element on a silicon substrate (wafer) in order to realize specific etching (see, for example, Patent Documents 1 and 2). Here, the selection ratio is the ratio of the etching rate of the material to be etched to the resist or the base film.

  Patent Document 1 discloses a dry etching method and a dry etching apparatus that can selectively etch a silicon nitride film with a high selectivity relative to a silicon oxide film.

Patent Document 2 discloses a thin film device capable of patterning a high selectivity conductive layer without etching the base film.
JP-A-7-235525 JP 2001-28442 A

  In the above-described semiconductor manufacturing process, the size of the substrate is relatively small, so that it was not particularly problematic. However, in the TFT manufacturing process, in recent years, the size of the substrate has become larger and larger in the TFT manufactured by the above-described manufacturing process. There arises a problem that the characteristics vary.

  Specifically, in the above-described manufacturing process, the metal thin film is less likely to be etched than an insulating film such as a silicon oxide film, that is, the selectivity of the metal thin film to the insulating film is low. When the gate electrode is formed by etching the metal thin film composed of the film 104 and the tungsten film 105, the surface of the gate insulating film 103 is also etched as shown in FIG.

  Although the amount of etching of the surface of the gate insulating film 103 is uniform when the inside of the substrate is viewed locally, for example, there is a large difference between the central portion and the end portion in the substrate. Therefore, the thickness of the etched gate insulating film 103 varies within the substrate surface. Further, since the doping of phosphorus into the semiconductor layer 102 is performed through the gate insulating film 103, if the in-plane uniformity of the film thickness of the gate insulating film 103 is deteriorated, the doping amount of phosphorus in the semiconductor layer 102 is not uniform. Become. As a result, portions having different electric resistances are distributed in the source region 2a and the drain region 2b doped with phosphorus in the semiconductor layer 102, so that the characteristics of the TFT 120 vary.

  Note that the variation in TFT characteristics due to the poor in-plane uniformity of the gate insulating film thickness can be suppressed to some extent by improving the performance of the manufacturing apparatus, that is, the dry etching apparatus. As described above, in the liquid crystal display device in which the size of the substrate becomes larger and larger, the manufacturing apparatus is increased in size. Therefore, it is difficult to suppress variations in TFT characteristics only by improving the performance of the manufacturing apparatus.

  The present invention has been made in view of the above points, and an object of the present invention is to reduce variations in the thickness of the insulating film between the semiconductor layer and the gate electrode constituting the thin film transistor by improving the manufacturing process. There is to do.

  In the present invention, the insulating film between the semiconductor layer and the gate electrode constituting the thin film transistor is constituted by the first insulating film and the second insulating film, and after the gate electrode is formed, the second insulating film is etched. Is.

  Specifically, a method of manufacturing a thin film transistor according to the present invention includes a semiconductor layer forming step of forming a semiconductor layer on a substrate, a first insulating film forming step of forming a first insulating film so as to cover the semiconductor layer, A second insulating film forming step of forming a second insulating film with a material different from that of the first insulating film so as to cover the first insulating film; and a conductive film for forming a conductive film formed so as to cover the second insulating film. A film forming step, a resist forming step of forming a resist pattern on the conductive film, a gate electrode forming step of forming a gate electrode by etching the conductive film using the resist as a mask, and the gate electrode forming step And an insulating film removing step of etching the second insulating film exposed from the gate electrode.

  According to the above method, the insulating film includes the first insulating film covering the semiconductor layer and the second insulating film covering the first insulating film, and in the insulating film removing step after the gate electrode forming step, the resist The second insulating film exposed from is etched. Therefore, in the gate electrode forming step, the conductive film side of the second insulating film is locally etched due to the low selection ratio of the conductive film to the second insulating film, and the film thickness of the second insulating film Even if the variation in the substrate occurs, the second insulating film is preferentially etched with respect to the first insulating film in the insulating film removing step, so that the variation of the film thickness of the second insulating film in the substrate It becomes small corresponding to the magnitude | size of the selection ratio of the 2nd insulating film with respect to 1 insulating film. Thereby, the variation in the film thickness of the insulating film due to the low selection ratio of the conductive film to the second insulating film is reduced. Therefore, by improving the manufacturing process, variation in the thickness of the insulating film between the semiconductor layer and the gate electrode constituting the thin film transistor is reduced.

  In the gate electrode forming step, a part of the second insulating film may be etched in the thickness direction together with the conductive film exposed from the resist.

  According to the above method, after the second insulating film exposed from the resist is partially etched in the thickness direction in the gate electrode forming step, the remaining second exposed from the resist in the insulating film removing step. 2 The insulating film is etched. Therefore, in the gate electrode forming step, the conductive film side of the second insulating film is locally etched due to the low selection ratio of the conductive film to the second insulating film, and the film thickness of the second insulating film Even if the variation in the substrate occurs, the second insulating film is preferentially etched with respect to the first insulating film in the insulating film removing step, so that the variation of the film thickness of the second insulating film in the substrate It becomes small corresponding to the magnitude | size of the selection ratio of the 2nd insulating film with respect to 1 insulating film. Thereby, the variation in the film thickness of the insulating film due to the low selection ratio of the conductive film to the second insulating film is reduced. Therefore, by improving the manufacturing process, variation in the thickness of the insulating film between the semiconductor layer and the gate electrode constituting the thin film transistor is reduced.

  The first insulating film may be a silicon oxide film, and the second insulating film may be a silicon nitride film.

  According to the above method, in the combination in which the first insulating film is a silicon oxide film and the second insulating film is a silicon nitride film, the selection ratio of the second insulating film to the first insulating film of the base film is generally Since it becomes high by the technique, the variation in the thickness of the insulating film between the semiconductor layer and the gate electrode constituting the thin film transistor is easily reduced.

  In the insulating film removing step, etching may be performed with a mixed gas of halogen gas and oxygen gas.

  According to the above method, the etching using a mixed gas of halogen gas and oxygen gas increases the selectivity of the silicon nitride film to the silicon oxide film, so that the insulation between the semiconductor layer constituting the thin film transistor and the gate electrode is achieved. Variations in film thickness are easily reduced.

  The semiconductor layer may be formed of a polycrystalline silicon film formed by melting and solidifying an amorphous silicon film by, for example, laser annealing.

  In a polycrystalline silicon film formed by melting and solidifying an amorphous silicon film, a protrusion called a ridge is formed on the surface, and there is a risk that a leakage current is generated between the semiconductor layer and the gate electrode by the ridge. is there. According to the above method, since the insulating film is composed of at least the first insulating film and the second insulating film and becomes thick, generation of a leakage current between the semiconductor layer and the gate electrode is suppressed.

  When the first insulating film is a silicon oxide film and the second insulating film is a silicon nitride film, the dielectric constant of the silicon nitride film is generally larger than the dielectric constant of the silicon oxide film, so that only the silicon oxide film is used. It is possible to form a thicker insulating film than the one having the same capacity as that of the insulating film composed of, and the generation of leakage current is suppressed, which is equivalent to the insulating film composed of only the silicon oxide film It is possible to form an insulating film having a larger capacity than that having a thickness of 1 mm.

  An impurity doping step of doping impurities into the semiconductor layer through the insulating film may be provided after the insulating film removing step.

  According to the above method, since the semiconductor layer is doped with the impurity through the insulating film having a small variation in film thickness, the amount of the impurity doped into the semiconductor layer becomes almost uniform. Therefore, the electric resistance in the portion of the semiconductor layer doped with impurities becomes almost uniform, and variations in characteristics of the thin film transistor are reduced.

  The insulating film removing step may be performed using an inductively coupled plasma etching apparatus.

  According to the above method, the inductively coupled plasma etching apparatus generates plasma with high density and isotropically etched by chemical reaction. Therefore, etching with a high selectivity at a relatively high etching rate. Is possible. Therefore, variation in the thickness of the insulating film between the semiconductor layer constituting the thin film transistor and the gate electrode can be effectively reduced.

  A thin film transistor according to the present invention is a thin film transistor including a semiconductor layer provided on a substrate, an insulating film covering the semiconductor layer, and a gate electrode provided on the insulating film, and the insulating film includes: A first insulating film covering the semiconductor layer and a second insulating layer provided on the first insulating film, and the second insulating layer is provided only in an overlapping portion with the gate electrode. Yes.

  The variation in the thickness of the insulating film between the semiconductor layer and the gate electrode constituting the thin film transistor becomes a base film when forming the gate electrode, and the variation in the thickness of the second insulating film forming the second insulating layer, That is, it is caused by the variation in the thickness of the second insulating film exposed from the gate electrode. According to the above configuration, the second insulating layer is disposed only in the overlapping portion with the gate electrode, and the second insulating film in the portion that causes the variation in the film thickness of the insulating film is removed and does not exist. Variation in the thickness of the insulating film between the semiconductor layer and the gate electrode constituting the gate electrode is reduced.

  The first insulating film may be a silicon oxide film, and the second insulating layer may be a silicon nitride film.

  According to the above configuration, the combination that the first insulating film is a silicon oxide film and the second insulating layer is a silicon nitride film is the second insulating film that forms the second insulating layer with respect to the first insulating film of the base film. Therefore, the variation in the thickness of the insulating film between the semiconductor layer constituting the thin film transistor and the gate electrode is easily reduced.

  The semiconductor layer may be composed of a polycrystalline silicon film formed by melting and solidifying an amorphous silicon film.

  In a polycrystalline silicon film formed by melting and solidifying an amorphous silicon film, a protrusion called a ridge is formed on the surface, and there is a risk that a leakage current is generated between the semiconductor layer and the gate electrode by the ridge. is there. According to the above configuration, since the insulating film is formed of at least the first insulating film and the second insulating layer and has a large thickness, generation of a leakage current between the semiconductor layer and the gate electrode is suppressed.

  According to the thin film transistor manufacturing method of the present invention, the insulating film is constituted by the first insulating film and the second insulating film, and after the gate electrode is formed, the insulating film removing step of etching the second insulating film is provided. By improving the manufacturing process, variation in the thickness of the insulating film between the semiconductor layer constituting the thin film transistor and the gate electrode can be reduced. Thereby, variation in characteristics of the thin film transistor can be reduced.

  Hereinafter, a thin film transistor manufacturing method and a thin film transistor according to an embodiment of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiments.

  First, a TFT manufactured by the method for manufacturing a thin film transistor (TFT) of the present invention will be described.

  FIG. 1 is a schematic cross-sectional view of the TFT 20 of this embodiment.

  As shown in FIG. 1, the TFT 20 includes a semiconductor layer 2, a gate electrode 13a, a source electrode 6a, and a drain electrode 6b.

  The TFT 20 has a multilayer laminated structure in which the base coat film 1, the first insulating film 3, and the interlayer insulating film 8 a are sequentially laminated on the insulating substrate 10.

  A semiconductor layer 2 having a source region 2a, a drain region 2b, and a channel region 2c is provided between the base coat film 1 and the first insulating film 3.

  Between the first insulating film 3 and the interlayer insulating film 8a, a second insulating layer 7a, a first conductive layer 4a, and a second conductive layer 5a are provided so as to overlap the channel region 2c of the semiconductor layer 2. Yes.

  Here, the first conductive layer 4a and the second conductive layer 5a constitute a gate electrode 13a, and the gate insulating film 12 which is an insulating film between the semiconductor layer 2 and the gate electrode 13a is formed by the first insulating film 3 and the second conductive layer 5a. It is composed of two insulating layers 7a.

  On the interlayer insulating film 8a, a source electrode 6a connected to the source region 2a of the semiconductor layer 2 through the contact hole 9a, and a drain electrode 6b connected to the drain region 2b of the semiconductor layer 2 through the contact hole 9b. And are provided.

  The TFT 20 has a top gate structure in which the gate electrode 13a is provided on the upper side of the semiconductor layer 2 (the side opposite to the insulating substrate 10).

  The TFT 20 is used as a switching element of an active matrix liquid crystal display device. In the liquid crystal display device having the TFT 20, for example, when the gate signal from the gate line is sent to the gate electrode 13a and the TFT 20 is turned on, the source signal is sent from the source line to the source electrode 6a and the drain electrode. A predetermined charge is written into the pixel electrode via 6b.

  Next, the manufacturing method of the TFT 20 described above will be described for each step using the schematic cross-sectional views of FIGS.

  The manufacturing process of this embodiment includes a base coat forming process, a semiconductor layer forming process, an insulating film forming process, a conductive film forming process, a resist forming process, a gate electrode forming process, an insulating film forming process, an impurity doping process, and an interlayer insulating film forming process. And a source electrode / drain electrode forming step.

  First, in the base coat film forming step, a silicon oxide film (thickness of about 200 nm) is formed on the entire substrate on the insulating substrate 10 such as a glass substrate by plasma CVD to form the base coat film 1.

Next, in the semiconductor layer forming step, an amorphous silicon film (thickness of about 50 nm) is formed on the entire substrate on the base coat film 1 by plasma CVD using monosilane (SiH ₄ ) as a source gas, It is melted and solidified by laser annealing or the like and crystallized (transformed into a polycrystalline silicon film). Thereafter, as shown in FIG. 2, a semiconductor layer 2 is formed by pattern formation by a photolithography method.

  Here, the semiconductor layer 2 may be formed by modifying the amorphous silicon film as described above, but a polycrystalline silicon film may be directly formed.

  Subsequently, an insulating film forming step is performed. This insulating film forming step includes a first insulating film forming step and a second insulating film forming step.

  First, in the first insulating film forming step, a silicon oxide film (having a thickness of about 100 nm) is formed by plasma CVD on the entire substrate on the base coat film 1 on which the semiconductor layer 2 is formed. Form.

  Next, in the second insulating film forming step, a silicon nitride film (having a thickness of about 50 nm) is formed by plasma CVD so as to cover the first insulating film 3 to form the second insulating film 7.

  Thereafter, in the conductive film forming step, a tantalum nitride film 4 (thickness of about 50 nm) and a tungsten film 5 (thickness of about 370 nm) are sequentially formed so as to cover the second insulating film 7 by sputtering. 13 is formed.

  Subsequently, a resist forming process is performed.

  First, a photoresist is applied with a thickness of about 1.4 μm by spin coating so as to cover the conductive film 13, and then the photoresist is pre-baked.

  Next, the photoresist is exposed through a photomask, developed and post-baked to form a pattern as shown in FIG.

  Subsequently, a gate electrode forming step is performed.

  The following etching is desirably performed using a general inductively coupled plasma etching apparatus (hereinafter, ICP etching apparatus). The pattern formation of the semiconductor layer 2 may also be performed using an ICP etching apparatus.

  The ICP etching apparatus includes a processing chamber for storing and etching a processing substrate, an exhaust system for setting a vacuum to the processing chamber, and a processing gas supply system for supplying a processing gas to the processing chamber. A dielectric wall installed in the upper part of the processing chamber, a high-frequency antenna provided on the upper part of the dielectric wall for forming an induction electric field in the processing chamber for converting the processing gas into plasma, and the above In order to effectively draw ions in the plasma excited in the processing chamber to the processing substrate, it is constituted by a lower electrode (substrate stage) to which high frequency power can be applied.

  First, for example, the power supplied to the high-frequency antenna is 2000 W, the bias power supplied to the substrate stage is 500 W, the pressure in the processing chamber is 2.0 Pa, the flow rate of tetrafluoromethane gas is 200 sccm, and the flow rate of chlorine gas is 100 sccm. In addition, the flow rate of oxygen gas is set to 200 sccm, dry etching is performed using the resist 11 as a mask, and the tungsten film 5 exposed from the resist 11 is removed. As shown in FIG. Layer 5a is formed. In this case, the selection ratio of the tungsten film 5 to the tantalum nitride film 4 is 10 or more.

  Here, sccm means “standard cubic centimeters per minute” and is a unit indicating a flow rate (cc) per minute.

  Next, for example, the power supplied to the high-frequency antenna is 2000 W, the bias power supplied to the substrate stage is 150 W, the pressure in the processing chamber is 2.0 Pa, the flow rate of tetrafluoromethane gas is 100 sccm, and the flow rate of chlorine gas is Set to 100 sccm, dry etching is performed using the resist 11 as a mask, and the tantalum nitride film 4 exposed from the resist 11 is removed to form a first conductive layer 4a as shown in FIG. Thereby, the gate electrode 13a constituted by the second conductive layer 5a and the first conductive layer 4a is formed. At this time, the selection ratio of the tantalum nitride film 4 to the second insulating film 7 (silicon nitride film) is about 2, and the surface of the second insulating film 7 is also etched.

  Since the amount of etching of the surface of the second insulating film 7 varies depending on the position in the surface of the insulating substrate 10, for example, as shown in FIG. A step difference t1 is generated. The left side of FIG. 10 is a schematic cross-sectional view of a portion where the etching rate is fast in the surface of the insulating substrate 10, and the right side of FIG. 10 is a schematic cross-sectional view of a portion where the etching rate is slow in the surface of the insulating substrate 10. is there.

  Subsequently, an insulating film removing process is performed.

  For example, the power supplied to the high-frequency antenna is 2000 W, the bias power supplied to the substrate stage is 150 W, the pressure in the processing chamber is 1.3 Pa, the flow rate of hydrogen bromide gas is 100 sccm, and the flow rate of oxygen gas is 20 sccm. These are set, dry etching is performed using the resist 11 as a mask, the second insulating film 7 exposed from the resist 11 is removed, and a second insulating layer 7a is formed as shown in FIG. In this case, the selection ratio of the second insulating film 7 to the first insulating film 3 is 20 or more.

  In this insulating film removal step, when dry etching proceeds to the second insulating film 7 from the state of the film thickness difference t1 as shown in FIG. 10, as shown in FIG. 11, the film is almost the same as the film thickness difference t1. A second insulating film remaining portion 7b having a thickness t2 is once formed. FIG. 11 is a schematic cross-sectional view corresponding to FIG. 10 and shows a state in which the removal of the second insulating film 7 is completed at the left portion where the etching rate is high. Then, when the dry etching further proceeds, as shown in FIG. 12, the second insulating film remaining portion 7b is removed, and the surface of the first insulating film 3 is also partially removed, so that the film thickness difference t1 (t2) is exceeded. A small film thickness difference t3 is obtained. FIG. 12 is a schematic cross-sectional view corresponding to FIGS. 10 and 11 and shows a state in which the removal of the second insulating film 7 (second insulating film remaining portion 7b) is completed at the right side where the etching rate is slow. ing.

  Specifically, when the selection ratio of the second insulating film 7 to the first insulating film 3 is 20 as described above, the film thickness difference t3 becomes small corresponding to the selection ratio, and the film thickness difference t1 1/20.

  Subsequently, an impurity doping step is performed.

  First, the resist 11 on the gate electrode 13a is removed by ashing.

  Next, using the gate electrode 13a as a mask, the semiconductor layer 2 is doped with phosphorus through the gate insulating film 12 (first insulating film 3), the channel region 2c is overlapped with the gate electrode 13a, and the source region 2a and Drain region 2b is formed.

  Thereafter, heat treatment is performed to activate the doped phosphorus. Note that when phosphorus is doped as an impurity element, an N-channel TFT is formed, and when boron is doped, a P-channel TFT is formed.

  Subsequently, an interlayer insulating film forming step is performed.

  First, a silicon nitride film (thickness: about 250 nm) and a silicon oxide film (thickness: about 500 nm) are sequentially formed by CVD on the entire substrate on the gate insulating film 12 on which the gate electrode 13a is formed. As shown in FIG. 7, an interlayer insulating film forming film 8 is formed.

  Next, portions corresponding to the source region 2a and the drain region 2b of the laminated film of the gate insulating film 12 and the interlayer insulating film forming film 8 are removed by etching to have contact holes 9a and 9b as shown in FIG. Interlayer insulating film 8a is formed.

  Subsequently, a source electrode / drain electrode forming step is performed.

  First, a titanium film (thickness about 50 nm), an aluminum film (thickness about 300 nm), and a titanium film (thickness about 50 nm) are sequentially formed on the entire substrate on the interlayer insulating film 8a by sputtering. As shown in FIG. 9, the source conductive layer 6 is formed.

  Next, the source conductive layer 6 is patterned by photolithography to form a source electrode 2a and a drain electrode 6b as shown in FIG.

  The TFT 20 is manufactured as described above.

  According to the manufacturing method of the TFT 20 of the present invention, the gate insulating film 12 is formed by the first insulating film 3 covering the semiconductor layer 2 and the second insulating film 7 covering the first insulating film 3 to form the gate electrode. In the step, after etching a part of the second insulating film 7 exposed from the resist 11 in the thickness direction, the remaining second insulating film remaining portion 7b exposed from the resist 11 is etched in the insulating film removing step. Will do.

  Therefore, in the gate electrode formation process, the first conductive film 4 side of the second insulating film 7 is locally etched due to the low selection ratio of the first conductive film 4 to the second insulating film 7. Even if the film thickness of the second insulating film 7 varies in the insulating substrate 10, the second insulating film 7 is etched with priority over the first insulating film 3 in the insulating film removing step. The variation of the film thickness of the second insulating film 7 in the substrate is reduced corresponding to the size of the selection ratio of the second insulating film 7 to the first insulating film 3.

  Thereby, the variation in the film thickness of the gate insulating film 12 due to the low selection ratio of the first conductive film 4 to the second insulating film 7 is reduced. Therefore, by improving the manufacturing process, variations in the film thickness of the insulating film between the semiconductor layer 2 constituting the TFT 20 and the gate electrode 13a, that is, the gate insulating film 12 can be reduced.

  Further, as in the above-described embodiment, the combination in which the first insulating film 3 is a silicon oxide film and the second insulating film 7 is a silicon nitride film is a selection of the second insulating film 7 with respect to the first insulating film 3 as a base film. Since the ratio is increased by a general method of using hydrogen bromide gas and oxygen gas as an etching gas, the variation in the film thickness of the gate insulating film 12 is easily reduced.

  In addition to the combination of hydrogen bromide gas and oxygen gas, the combination of halogen gas and oxygen gas, such as the combination of hydrogen bromide gas, chlorine gas and oxygen gas, the combination of chlorine gas and oxygen gas, etc., is also oxidized. A high selection ratio of the silicon nitride film to the silicon film can be ensured.

  Meanwhile, in recent years, TFTs in liquid crystal display devices are required to have high-speed response. The high-speed response (current driving capability) of this TFT depends on the capacity of the TFT gate electrode and the channel region of the semiconductor layer, and the TFT response improves as the TFT capacity increases. To do. Therefore, in order to improve the response of the TFT, it is preferable to form a thin gate insulating film of the TFT. On the other hand, if the thickness of the gate insulating film becomes too thin, a leak current is likely to occur between the gate electrode and the semiconductor layer. In particular, in a polycrystalline silicon film formed by melting and solidifying an amorphous silicon film, a protrusion called a ridge is formed on the surface, and a leakage current is generated between the semiconductor layer 2 and the gate electrode 13a by the ridge. May occur.

  However, according to the TFT manufacturing method of the present invention, the gate insulating film 12 is constituted by the first insulating film 3 and the second insulating layer 7a and becomes thick, so that the gap between the semiconductor layer 2 and the gate electrode 13a is increased. Generation of leakage current can be suppressed.

  More generally, since the dielectric constant of the silicon nitride film is larger than the dielectric constant of the silicon oxide film, in the TFT 20 of the present invention in which the first insulating film 3 is a silicon oxide film and the second insulating film 7 is a silicon nitride film. It is possible to form a thicker gate insulating film than that having a capacity equivalent to that of a gate insulating film composed only of a silicon oxide film, and the generation of leakage current is suppressed, and the silicon oxide film It is possible to form an insulating film having a larger capacity than that having a film thickness equivalent to that of the gate insulating film composed of only the gate insulating film.

  Further, in the impurity doping step, phosphorus is doped into the semiconductor layer 2 through the gate insulating film 12 having a small variation in film thickness, so that the source region 2a and the drain region 2b of the semiconductor layer 2 are doped with phosphorus. The amount is almost uniform. Therefore, the electrical resistance in the source region 2a and the drain region 2b of the semiconductor layer 2 becomes substantially uniform, and variations in characteristics of the TFT 20 can be reduced.

  Further, since the etching in the insulating film removing step is performed using an ICP etching apparatus, plasma can be generated at a high density in the processing chamber, and isotropic etching can be performed chemically. it can. Therefore, etching with a high selectivity can be performed at a relatively high etching rate, and variations in the film thickness of the gate insulating film 12 can be effectively reduced.

  Further, the above embodiment is premised on the problem of reducing the variation in the film thickness of the gate insulating film 12 in the surface of the insulating substrate 10, and the variation in the film thickness with respect to the gate insulating film in the same substrate. However, the TFT manufacturing method of the present invention can also suppress variations in the film thickness of the gate insulating film between substrates processed separately.

  As described above, the present invention can reduce variations in characteristics of TFTs, and thus is useful for a liquid crystal display device using TFTs.

It is a cross-sectional schematic diagram of TFT20 which concerns on embodiment of this invention. It is drawing for demonstrating the manufacturing process of TFT20 which concerns on embodiment of this invention, and is a cross-sectional schematic diagram which shows the state in which the basecoat film and the semiconductor layer were formed on the insulating substrate. FIG. 3 is a schematic cross-sectional view illustrating a state where an insulating film, a conductive film, and a resist are formed with respect to FIG. FIG. 4 is a schematic cross-sectional view showing a state where a first conductive layer is formed with respect to FIG. 3. FIG. 5 is a schematic cross-sectional view showing a state where a second conductive layer (gate electrode) is formed with respect to FIG. 4. FIG. 6 is a schematic cross-sectional view showing a state where a second insulating layer is formed with respect to FIG. 5. FIG. 7 is a schematic cross-sectional view illustrating a state in which the resist is removed and an interlayer insulating film is formed with respect to FIG. 6. FIG. 8 is a schematic cross-sectional view showing a state where contact holes are formed with respect to FIG. 7. FIG. 9 is a schematic cross-sectional view illustrating a state where a source conductive layer is formed with respect to FIG. 8. FIG. 6 is a schematic cross-sectional view showing the second insulating film shown in FIG. 5 in more detail. FIG. 11 is a schematic cross-sectional view showing a state in which most of the second insulating film exposed from the resist is removed from FIG. 10. FIG. 12 is a schematic cross-sectional view showing a state in which the second insulating film exposed from the resist is completely removed with respect to FIG. It is a drawing for explaining a manufacturing process of a conventional TFT 120, and is a schematic cross-sectional view showing a state in which a base coat film, a semiconductor layer, a gate insulating film, a tantalum nitride film, a tungsten film, and a resist are formed on a glass substrate. . It is a cross-sectional schematic diagram which shows the state in which the tungsten layer was formed with respect to FIG. 15 is a schematic cross-sectional view showing a state in which a tantalum nitride layer (gate electrode) is formed with respect to FIG. It is a cross-sectional schematic diagram of a conventional TFT 120.

Explanation of symbols

2 semiconductor layer 2a channel region 2b source region 2c drain region 3 first insulating film 4 tantalum nitride film 4a first conductive layer 5 tungsten film 5a second conductive layer 6a source electrode 6b drain electrode 7 second insulating film 7a second insulating layer 7b Second insulating film remainder 10 Insulating substrate 11 Resist 12 Gate insulating film 13 Conductive film 13a Gate electrode 20 Thin film transistor (TFT)

Claims (10)

A semiconductor layer forming step of forming a semiconductor layer on the substrate;
A first insulating film forming step of forming a first insulating film so as to cover the semiconductor layer;
A second insulating film forming step of forming a second insulating film with a material different from that of the first insulating film so as to cover the first insulating film;
A conductive film forming step of forming a conductive film formed so as to cover the second insulating film;
A resist forming step of patterning a resist on the conductive film;
A gate electrode forming step of forming a gate electrode by etching the conductive film using the resist as a mask;
A method of manufacturing a thin film transistor, comprising: an insulating film removing step of etching the second insulating film exposed from the gate electrode after the gate electrode forming step. In the manufacturing method of the thin-film transistor of Claim 1,
In the gate electrode formation step, a method of manufacturing a thin film transistor, wherein a part of the second insulating film is etched in a thickness direction together with the conductive film exposed from the resist. In the manufacturing method of the thin-film transistor of Claim 1,
The method for manufacturing a thin film transistor, wherein the first insulating film is a silicon oxide film and the second insulating film is a silicon nitride film. In the manufacturing method of the thin-film transistor of Claim 3,
The insulating film removing step is a method for manufacturing a thin film transistor in which etching is performed using a mixed gas of a halogen gas and an oxygen gas. In the manufacturing method of the thin-film transistor of Claim 1,
The method for manufacturing a thin film transistor, wherein the semiconductor layer is formed of a polycrystalline silicon film formed by melting and solidifying an amorphous silicon film. In the manufacturing method of the thin-film transistor of Claim 1,
A method of manufacturing a thin film transistor, comprising an impurity doping step of doping impurities into the semiconductor layer through the first insulating film after the insulating film removing step. In the manufacturing method of the thin-film transistor of Claim 1,
The said insulating film removal process is a manufacturing method of the thin-film transistor performed using an inductively coupled plasma etching apparatus. A thin film transistor comprising a semiconductor layer provided on a substrate, an insulating film covering the semiconductor layer, and a gate electrode provided on the insulating film,
The insulating film includes a first insulating film that covers the semiconductor layer, and a second insulating layer provided on the first insulating film,
The second insulating layer is a thin film transistor provided only in an overlapping portion with the gate electrode. The thin film transistor according to claim 8,
The first insulating film is a silicon oxide film, and the second insulating layer is a silicon nitride film. The thin film transistor according to claim 8,
The semiconductor layer is a thin film transistor formed of a polycrystalline silicon film formed by melting and solidifying an amorphous silicon film.

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