JP2006287261A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device the characteristic of the capacitor covered with an inter-layer insulation film of which can be enhanced, and to provide a manufacturing method thereof. <P>SOLUTION: The semiconductor device includes: a silicon substrate 51; a first insulation film 59 formed above the silicon substrate 51; a lower electrode 69a formed on the first insulation film 59; a capacitor including a dielectric film 70a and an upper electrode 71a; a first capacitor protection insulation film 73 formed above the capacitor by a sputter method; a second capacitor protection insulation film 72 formed on the first capacitor protection insulation film 73 by a plasma CVD method; and a second insulation film 74 formed on the second capacitor protection insulation film 72. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a capacitor and a manufacturing method thereof.

  Flash memories and ferroelectric memories (FeRAM) are known as nonvolatile memories that can store information even when the power is turned off.

  A flash memory has a floating gate embedded in a gate insulating film of an insulated gate field effect transistor (IGFET), and stores information by accumulating charges as stored information in the floating gate. For writing and erasing information, it is necessary to pass a tunnel current through the gate insulating film, which requires a relatively high voltage.

  The FeRAM has a ferroelectric capacitor that stores information using the hysteresis characteristics of the ferroelectric. In a ferroelectric capacitor, the ferroelectric film formed between the upper electrode and the lower electrode generates polarization according to the voltage value applied between the upper electrode and the lower electrode, and maintains the polarization even when the applied voltage is removed. Have spontaneous polarization. If the polarity of the applied voltage is reversed, the polarity of the spontaneous polarization is also reversed. Information can be read by detecting the polarity and magnitude of this spontaneous polarization.

  FeRAM has an advantage that it operates at a lower voltage than a flash memory and can perform high-speed writing with power saving.

As described in, for example, Patent Document 1, an FeRAM memory cell includes a MOS transistor formed on a silicon substrate, a first interlayer insulating film formed on the silicon substrate and the MOS transistor, and a first interlayer insulating film. Embedded in the ferroelectric capacitor formed thereon, the second interlayer insulating film formed on the ferroelectric capacitor and the first interlayer insulating film, and the hole formed in the first and second interlayer insulating films. A conductive plug connected to the MOS transistor, a first wiring pattern connecting the conductive plug and the upper electrode of the ferroelectric capacitor, and the first wiring pattern and the second interlayer insulating film. A third interlayer insulating film; and a second wiring pattern formed on the third interlayer insulating film.
JP 2001-60669 A

  An object of the present invention is to provide a semiconductor device capable of improving the characteristics of a capacitor covered with an interlayer insulating film and a method for manufacturing the same.

  The problems described above include a semiconductor substrate, a first insulating film formed above the semiconductor substrate, a capacitor formed on the first insulating film and having a lower electrode, a dielectric film, and an upper electrode, and the capacitor A first capacitor protective insulating film formed by sputtering over the first capacitor, a second capacitor protective insulating film formed by plasma CVD on the first capacitor protective insulating film, and on the second capacitor protective insulating film The problem is solved by a semiconductor device having the formed second insulating film.

  Alternatively, the problems described above include a step of forming a first insulating film above a semiconductor substrate, a step of forming a capacitor having a lower electrode, a dielectric film and an upper electrode on the first insulating film, Forming a first capacitor protective insulating film on the capacitor by a sputtering method; forming a second capacitor protective insulating film on the first capacitor protective insulating film by a plasma CVD method; and And a step of forming a second insulating film on the capacitor protection insulating film.

  When the second capacitor protective insulating film is formed by the plasma CVD method in this way, the deterioration of the capacitor can be prevented better than when the first capacitor protective insulating film is used as a single layer.

  Furthermore, by forming the second insulating film by a plasma CVD method in which a bias voltage is applied to the semiconductor substrate, it is possible to form a second insulating film with good embeddability between capacitors without the generation of voids.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
1 to 13 are cross-sectional views showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. FIG. 14 is a plan view of FIG.

  First, steps required until a sectional structure shown in FIG.

  As shown in FIG. 1, LOCOS (Local Oxidation of Silicon) is formed as an element isolation insulating film 2 on a part of the surface of a p-type silicon (semiconductor) substrate 1. As the element isolation insulating film 2, another element isolation structure of LOCOS, for example, STI (Shallow Trench Isolation) may be adopted.

  After the element isolation insulating film 2 is formed, p-type impurities and n-type impurities are selectively introduced into predetermined active regions in the memory cell region A and the peripheral circuit region B of the silicon substrate 1 to form the p-well 3 and the n-well. 4 is formed. Although not shown in FIG. 1, a p-well is also formed in the peripheral circuit region B to form a CMOS.

  Thereafter, the active region surface of the silicon substrate 1 is thermally oxidized to form a silicon oxide film as the gate insulating film 5.

  Next, an amorphous silicon film and a tungsten silicide film are formed on the entire upper surface of the silicon substrate 1, and the amorphous silicon film and the tungsten silicide film are patterned into a predetermined shape by a photolithography method to obtain gate electrodes 6a, 6b, 6c. And the wiring 7 is formed. Note that a polysilicon film may be formed instead of the amorphous silicon film.

  In the memory cell region A, two gate electrodes 6a and 6b are arranged substantially in parallel on one p-well 3, and these gate electrodes 6a and 6b constitute a part of the word line WL.

  Next, in the p-well 3 of the memory cell region A, n-type impurities are ion-implanted on both sides of the gate electrodes 6a and 6b to form n-type impurity diffusion regions 8a and 8b that become the source and drain of the n-channel MOS transistor. To do. At the same time, an n-type impurity diffusion region may be formed in a p-well (not shown) in the peripheral circuit region B. Subsequently, in the n-well 4 in the peripheral circuit region B, p-type impurities are ion-implanted on both sides of the gate electrode 6c to form p-type impurity diffusion regions 9 that become the source and drain of the p-channel MOS transistor. The n-type impurity and the p-type impurity are divided using a resist pattern.

After that, after an insulating film is formed on the entire surface of the silicon substrate 1, the insulating film is etched back to leave the side walls 10 only on both sides of the gate electrodes 6 a, 6 b, 6 c and the wiring 7. As the insulating film, silicon oxide (SiO ₂ ) is formed by, eg, CVD.

Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed as a cover film on the entire surface of the silicon substrate 1 by plasma CVD. Thereafter, silicon oxide (SiO ₂ ) is grown on the cover film to a thickness of about 1.0 μm by plasma CVD using TEOS gas. A first interlayer insulating film (first insulating film) 11 is constituted by the SiON film and the SiO ₂ film. Note that a SiO ₂ film formed by plasma CVD using TEOS is also referred to as a TEOS film below.

  Subsequently, as the densification treatment of the first interlayer insulating film 11, the first interlayer insulating film 11 is heat-treated at 700 ° C. for 30 minutes in a normal pressure nitrogen atmosphere. Thereafter, the first interlayer insulating film 11 is polished by a chemical mechanical polishing (hereinafter referred to as CMP) method to planarize the upper surface of the first interlayer insulating film 11.

  Next, contact holes 11a having depths reaching the n-type impurity diffusion regions 8a and 8b on both sides of the gate electrodes 6a and 6b in the memory cell region A and the p-type impurity diffusion layer 9 in the peripheral circuit region B by photolithography. To 11d and via holes 11e having a depth reaching the wiring 7 in the peripheral circuit region B are formed in the first interlayer insulating film 11, respectively. Thereafter, a Ti (titanium) thin film having a thickness of 20 nm and a TiN (titanium nitride) thin film having a thickness of 50 nm are sequentially formed on the upper surface of the first interlayer insulating film 11 and the inner surfaces of the holes 11a to 11f by sputtering. Further, tungsten (W) is grown on the TiN thin film by the CVD method. As a result, a tungsten film is buried in the contact holes 11a to 11d and the via hole 11e.

  Thereafter, the tungsten film, the TiN thin film, and the Ti thin film are polished by CMP until the upper surface of the first interlayer insulating film 11 is exposed. The tungsten film or the like remaining in the holes 11a to 17e after the polishing is used as conductive plugs 13a to 13e for electrically connecting wirings to be described later to the impurity diffusion regions 8a, 8b, and 9 and the wirings 14.

  In one p-well 3 in the memory cell region A, the first conductive plug 13a on the n-type impurity diffusion region 8a sandwiched between the two gate electrodes 6a and 6b is connected to a bit line to be described later. The second conductive plugs 13b on both sides of the conductive plug are connected to a capacitor to be described later.

Next, in order to prevent oxidation of the conductive plugs 13a to 13e, a SiON film 14 having a thickness of 100 nm is formed on the first interlayer insulating film 17 and the conductive plugs 13a to 13e by plasma CVD. Further, the SiO ₂ film 15 is formed to a thickness of 150 nm using TEOS as a film forming gas. Thereafter, the SiON film 14 and the SiO ₂ film 15 are heated at a temperature of 650 to 700 ° C. for degassing.

  Next, steps required until a structure shown in FIG.

First, a Ti layer and a Pt layer are sequentially deposited to a thickness of 20 nm and 175 nm on the SiO ₂ film 15 by DC sputtering to form a first conductive film 16 having a two-layer structure.

Subsequently, lead zirconate titanate (PZT; Pb (Zr _1-x Ti _x ) O ₃ ), which is a ferroelectric material, is formed on the first conductive film 16 by an RF sputtering method to a thickness of 100 to 300 nm, for example, 200 nm. The PZT film 17 is formed by forming the PZT film 17.

As a method for forming the ferroelectric material film, there are a spin-on method, a sol-gel method, a MOD (Metal Organi Deposition) method, and an MOCVD method in addition to the above-described sputtering method. In addition to PZT, ferroelectric materials include lead lanthanum zirconate titanate (PLZT), SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ (where 0 <x <1), Bi ₄ Ti ₂ O ₁₂ etc. Further, when forming a DRAM, a high dielectric material such as (BaSr) TiO ₃ (BST) or strontium titanate (STO) may be used instead of the above ferroelectric material.

  Then, as a crystallization process for the PZT film 17, RTA (Rapid Thermal Annealing) is performed in an oxygen atmosphere at a temperature of 750 ° C. for 60 seconds.

Further, an IrO _x film as a second conductive film 18 is formed on the PZT film 17 to a thickness of about 200 nm by DC sputtering.

  Next, steps required until the structure shown in FIG. 3 is formed will be described.

  First, after the second conductive film 18 is patterned to form the upper electrode 18a, the PZT film is removed, for example, in an oxygen atmosphere at 650 ° C. for 60 minutes in order to remove damage from the ferroelectric PZT film 17. 17 is annealed for recovery.

  Further, after the PZT film 17 is patterned and left as a capacitor dielectric film 17a under at least the upper electrode 18a, the dielectric film 17a is annealed in an oxygen atmosphere at 350 ° C. for 60 minutes, for example.

Subsequently, as shown in FIG. 4, a first capacitor protection insulating film 19 made of aluminum oxide (Al ₂ O ₃ ) is sputtered on the upper electrode 18a, the dielectric film 17a and the first conductive film 16 by 50 nm. The thickness is formed. Thereafter, in order to alleviate damage to the dielectric film 17a received by sputtering, the dielectric film 17a is annealed, for example, in an oxygen atmosphere at 550 ° C. for 60 minutes.

  Thereafter, as shown in FIG. 5, the first conductive film 16 is patterned to form the lower electrode 16a. The first capacitor protection insulating film 19 is patterned together with the first conductive film 16.

  Thereby, the ferroelectric capacitor 20 is comprised by the upper electrode 18a, the dielectric film 17a, and the lower electrode 16a. Subsequently, the ferroelectric capacitor 20 is annealed in an oxygen atmosphere at 650 ° C. for 30 minutes.

  Next, steps required until a structure shown in FIG.

First, a second interlayer insulating film 21 is formed on the entire surface of the ferroelectric capacitor 20 and the SiO ₂ film 15. The second interlayer insulating film 21 is first formed into a two-layer structure of an insulating film having a thickness of about 480 nm formed using TEOS and an SOG film having a thickness of about 90 nm formed thereon. Thereafter, the second interlayer insulating film 21 is etched back to a thickness of about 300 nm to a thickness of about 270 nm.

After that, plasma annealing is performed on the second interlayer insulating film 21 and various films below it using N ₂ O gas at a temperature of 350 ° C. In this plasma annealing, a silicon substrate 1 is placed in a chamber of a plasma generator, N ₂ O gas is introduced into the chamber at a flow rate of 700 sccm, and N ₂ gas is introduced at a flow rate of 200 sccm. The second interlayer insulating film 21 and various films below it are exposed to plasma in a time of 1 minute or longer. As a result, nitrogen enters deeply from the surface of the second interlayer insulating film 21 to prevent moisture from entering. Hereinafter, this processing is referred to as N ₂ O plasma processing. In this embodiment, for example, 350 ° C. and 2 minutes are selected as the heating temperature and the heating time.

  Next, steps required until a structure shown in FIG.

  First, the first contact hole 21a is formed on the upper electrode 16a of the ferroelectric capacitor 20 in the second interlayer insulating film 21 by photolithography. At the same time, a contact hole (not shown) is also formed on the contact region of the lower electrode 16a arranged in the direction perpendicular to the drawing. Thereafter, recovery annealing is performed on the dielectric film 17a. Specifically, heating is performed at a temperature of 550 ° C. for 60 minutes in an oxygen atmosphere.

Next, the second interlayer insulating film 21, the SiO ₂ film 15, and the SiON film 14 are patterned by a photolithography method so as to be placed on the second conductive plugs 13 b near both ends of the p well 3 in the memory cell region A. A second contact hole 21b is formed to expose the second conductive plug 13b. Then, a 125 nm-thick TiN film is formed on the second interlayer insulating film 21 and in the contact holes 21a and 21b by sputtering. Subsequently, the TiN film is patterned by photolithography to electrically connect the second conductive plug 18b and the upper electrode 18a of the ferroelectric capacitor 20 through the contact holes 21a and 21b in the memory cell region A. For this purpose, a local wiring 22a is formed. Thereafter, the second interlayer insulating film 21 is heated in a nitrogen (N ₂ ) atmosphere at 350 ° C. for 30 minutes.

  Further, a second capacitor protection insulating film 23 made of aluminum oxide is formed to a thickness of 20 nm on the local wiring 22a and the second interlayer insulating film 21 by sputtering.

Subsequently, a silicon oxide film is formed to a thickness of about 300 nm by plasma CVD using TEOS gas on the local wiring 22a and the second interlayer insulating film 21, and this silicon oxide film is formed on the third interlayer film. The insulating film 24 is used. Thereafter, the third interlayer insulating film 24 is modified by N ₂ O plasma treatment. Conditions of the N ₂ O plasma treatment, the same as the conditions of the N ₂ O plasma treatment to the second interlayer insulating film 21.

  Next, steps required until a structure shown in FIG.

  First, the pattern from the third interlayer insulating film 24 in the memory cell region A to the SiON film 14 below the third interlayer insulating film 24 is patterned by photolithography to contact the first conductive plug 13a at the center position of the p well 3. Hole 24a is formed. At the same time, contact holes 24c to 24e are formed on the conductive plugs 13c to 13e in the peripheral circuit region B.

  Furthermore, a Ti film having a thickness of 20 nm, a TiN film having a thickness of 50 nm, an Al—Cu film having a thickness of 600 nm, a Ti film having a thickness of 5 nm, and the third interlayer insulating film 24 and in the contact holes 24c to 24e, By sequentially laminating five layers of 150 nm thick TiN films and patterning these metal films, bit lines 25a are formed in the memory cell region A, and wirings 25b, 25c, and 25d are formed in the peripheral circuit region B. To do. Note that the Al—Cu film contains, for example, 0.5% of Cu. The bit line 25a and the wirings 25b, 25c, and 25d are first-layer aluminum wirings.

Next, a fourth interlayer insulating film (second insulating film) 26 made of SiO _{2 having} a thickness of about 2.3 μm is formed into a third interlayer insulating film 24 and a bit line 25a by plasma CVD using TEOS gas. And it forms on wiring 25b-25d.

Thereafter, in order to planarize the fourth interlayer insulating film 26, a process of polishing the upper surface by a CMP method is employed. The polishing amount is about 1.2 μm. Thereafter, the fourth interlayer insulating film 26 is modified by N ₂ O plasma treatment. Conditions of the N ₂ O plasma treatment, the same as the conditions of the N ₂ O plasma treatment to the second interlayer insulating film 21.

Next, as shown in FIG. 9, a redeposited interlayer insulating film 27 is formed on the interlayer insulating film 33 to a thickness of about 300 nm by plasma CVD using TEOS. Subsequently, the redeposited interlayer insulating film 27 is modified by N ₂ O plasma treatment. Conditions of the N ₂ O plasma treatment, the same as the conditions of the N ₂ O plasma treatment to the second interlayer insulating film 21.

  Next, steps required until a structure shown in FIG.

  First, the redeposited interlayer insulating film 27 and the fourth interlayer insulating film 26 are patterned by photolithography to form a via hole 26a reaching the first aluminum wiring, for example, the wiring 25c in the peripheral circuit region B.

Subsequently, a Ti film having a thickness of 20 nm and a TiN film having a thickness of 50 nm are sequentially formed on the inner surface of the via hole 26a and the upper surface of the redeposited interlayer insulating film 27 to form a glue layer 29a. Thereafter, a tungsten film 29b is formed on the glue layer 29a at a growth temperature of 370 ° C. using WF ₆ (tungsten hexafluoride) gas, SiH ₄ (silane) gas, and H ₂ (hydrogen).

  Subsequently, the tungsten film 29b is removed by etch back, and is left only in the via hole 26a. At this time, the glue layer 29a is not removed. Here, the tungsten film 29b remaining in the via hole 26a is used as the conductive plug 28c.

  Thereafter, an Al—Cu film 29c having a thickness of 600 nm and a TiN film 29d having a thickness of 150 nm are formed on the glue layer 29a and the conductive plug 28c. Here, the Al—Cu film 29c contains 3% of Cu.

  Next, a metal pattern 31 covering the plurality of ferroelectric capacitors 20 in the memory cell region A by patterning a multilayer metal film composed of the glue layer 29a, the Al—Cu film 29c and the TiN film 29d, and a peripheral circuit Metal wiring 30 is formed in region B. Thereafter, the silicon substrate 1 is fixed on a susceptor maintained at 350 ° C., annealed in an oxygen atmosphere of 2 Torr for 30 minutes, and then annealed at 350 ° C. in an atmosphere of 1 mTorr or less under reduced pressure from which oxygen is cut. For 90 minutes.

The metal pattern 31 is arranged so as to sufficiently cover the ferroelectric capacitor 20, and the occupied area varies depending on the size of the memory cell region A. Here, if the cell efficiency is defined as a percentage (S ₁ / S ₂ × 100%) obtained by dividing the area S ₁ of the memory cell region by the chip area S ₂ , for example, if the cell efficiency is 30%, metal The area of the pattern 31 is 30% or more of the chip area.

According to this, since the metal pattern 31 is arranged so as to always cover the entire memory cell region A, the ratio of the area of the metal pattern 31 to the chip area is a numerical value higher than the cell efficiency. The same applies to the second embodiment described later. The multilayer metal film stress of the Ti film, TiN film, Al—Cu film and TiN film constituting the metal pattern 31 and the metal wiring 30 is a weak tensile stress of 1 × 10 ⁸ dyne / cm ² immediately after the formation of the multilayer metal film ( However, when annealing is performed in a vacuum, the stress changes from 6 × 10 ⁹ dyne / cm ² to 1 × 10 ⁹ dyne / cm ² , and the stress is stronger in the tensile direction than immediately after film formation. The change in the stress gives a favorable stress to the lower ferroelectric capacitor 20, so that the ferroelectric characteristics of the ferroelectric capacitor 20 are improved.

  The TiN film and the TiN film 29d constituting the glue layer 29a have a compressive stress at the beginning of the film formation, the Al-Cu film 29c has a tensile stress, and the entire multilayer metal film has a slight tensile stress. .

  The specific resistance of the multilayer metal film increases by 5 to 10% by annealing.

  In the example described above, the multilayer metal film is annealed after patterning the multilayer metal film to form the metal pattern 31 and the metal wiring 30. However, even if the multilayer metal film is annealed immediately after the formation of the multilayer metal film under the above-described conditions, and then the metal pattern 31 and the metal wiring 30 are formed by patterning the multilayer metal film, the metal pattern 31 and the metal wiring 30 will eventually have the same stress effect. That is, the same effect can be expected even if the multilayer metal film is annealed at any stage as long as the treatment is not performed so as not to inhibit the stress of the metal film constituting the metal pattern 31 and the metal wiring 30. For example, it may be after the formation of the first cover film (third insulating film) 32 formed in the next step.

  The potential of the metal pattern 31 is a fixed potential or an electrically isolated floating potential.

Next, as shown in FIG. 11, a first cover film 32 made of silicon oxide having a thickness of 100 nm is formed on the metal pattern 31, the metal wiring 30, and the redeposited interlayer insulating film 27 by plasma CVD using TEOS gas. To form. Thereafter, the first cover film 32 is subjected to N ₂ O plasma treatment. The conditions of the N ₂ O plasma treatment, the same as the conditions of the N ₂ O plasma treatment to the second interlayer insulating film 21.

  Next, as shown in FIG. 12, a second cover film 33 made of silicon nitride having a thickness of 350 nm is formed on the first cover film 32 by the CVD method. Subsequently, in a region near the outermost periphery of the chip region (semiconductor device chip region) of the silicon substrate 1, the first and second cover films 32 and 33 are patterned by photolithography to form a second-layer aluminum wiring not shown. A hole (not shown) connected to is formed.

  Thereafter, as shown in FIG. 13, a polyimide resin 34 is applied on the second cover film 33 to prevent cracks during packaging, and a bonding opening (not shown) is formed in the polyimide resin 34. Thereafter, the polyimide resin 34 is cured at a temperature of 250 ° C. Thereby, FeRAM is completed.

  The planar structure of the semiconductor device shown in FIG. 13 is as shown in FIG. However, in FIG. 14, insulating films other than the element isolation insulating film 2 are omitted.

  In the embodiment described above, the tensile stress metal pattern 31 is formed on the redeposited interlayer insulating film 27 formed above the ferroelectric capacitor 20 and covering the entire memory cell region A. As a result, the force applied to the ferroelectric capacitor 20 by the interlayer insulating films 27, 26, 24 having the compressive stress and the cover films 32, 33 is relaxed by the metal pattern 31. In addition, unlike the insulating film, the metal pattern 31 does not release moisture, so the ferroelectric capacitor 20 is not deteriorated.

  By the way, about the yield of FeRAM formed through the process which anneals multilayer metal film 29a, 29c, 29d which comprises metal pattern 31 in oxygen atmosphere, and the yield of FeRAM formed without going through such an annealing process. As a result of the investigation, results as shown in FIG. 15 were obtained.

  In FIG. 15, PT1 indicates the yield with respect to the initial production amount investigated by measuring the characteristics of the ferroelectric capacitor in the initial stage of FeRAM formation, and PT2 indicates the ferroelectric capacitor obtained by heating FeRAM at 200 ° C. for 4 hours. It shows the yield with respect to the initial production amount by measuring the retention and imprint characteristics.

In FIG. 15, “O ₂ anneal” indicates FeRAM formed through a process of heating the multilayer metal film constituting the metal pattern 31 in an oxygen atmosphere, and “SiO ₂ present + O ₂ anneal” , FeRAM formed through a step of annealing the metal pattern 31 after forming an SiO ₂ film having a thickness of 80 nm as the first cover film 32 on the multilayer metal pattern 31, and “no annealing” The FeRAM formed without going through the step of annealing the multilayer metal film constituting the metal pattern 31 is shown.

  According to FIG. 15, there is no difference between PT1 and PT2 for FeRAM formed through the process of annealing the multilayer metal film constituting the metal pattern 31, and a good product immediately after the manufacture of FeRAM is at 200 ° C. for 4 hours. Even after heating, the memory cell characteristics could be maintained.

  On the other hand, for FeRAM formed without annealing the multilayer metal film, the yield of PT2 is lower than the yield of PT1, and it is found that FeRAM deteriorates by heating at 200 ° C. for 4 hours. It was.

  Next, when the switching charge Qsw and the accumulated charge saturation voltage V90 were examined for the ferroelectric capacitors immediately after the completion of the three types of FeRAMs used in FIG. 15, the results shown in FIG. 16 were obtained. The accumulated charge saturation voltage V90 is a voltage value at which the accumulated charge is 90% of the saturation value.

  According to FIG. 16, it can be seen that the ferroelectric capacitor characteristics are improved by annealing the metal film constituting the metal pattern 31.

Next, the stress variation due to annealing of the metal film was investigated. As an investigation sample, an Al—Cu film with a thickness of 500 nm and a TiN film with a thickness of 100 nm are formed as a metal film on a SiO ₂ film with a thickness of 100 nm covering the silicon substrate, and then the metal film is annealed. Then, when the fluctuation of stress was examined, the result shown in FIG. 17 was obtained. The annealing conditions were a temperature of 350 ° C. in an atmosphere of 2.2 Torr, an annealing time of 30 minutes, 60 minutes, and 120 minutes, and a gas introduced into the annealing atmosphere was either oxygen gas or nitrogen gas.

  In FIG. 17, the horizontal axis indicates the conditions for annealing. Further, in FIG. 17, ♦ indicates a state where annealing is not performed, and annealing is not performed under the conditions indicated by the horizontal axis.

  According to FIG. 17, it was found that when a metal film is annealed in a reduced pressure atmosphere into which oxygen or nitrogen is introduced, the tensile stress of the metal film including the aluminum film increases as the annealing time increases. That is, the tensile stress can be controlled by time, and an optimum value for the magnitude of the compressive stress of the interlayer insulating film can be selected.

By the way, in the above-described embodiment, the metal pattern covering the entire memory cell region A on the redeposited interlayer insulating film 27 is composed of a multilayer metal film including an Al—Cu film. May be. That is, the metal film constituting the metal pattern 31 may be a film of aluminum, copper, tungsten, titanium, or tantalum, or a film of an alloy or a mixture with any of these elements. When an aluminum film is formed, the thickness is preferably 250 nm or more. As an example of forming the metal pattern 31 from tungsten, for example, the tungsten film 29b for forming the conductive plug 28c is selectively left on the redeposited interlayer insulating film 27 in the memory cell region A to leave the metal pattern 31. It is good. The copper film has a compressive stress of −5 × 10 ¹⁰ dyne / cm ^{2 in} the initial stage of film formation, but when annealed at a temperature of, for example, 370 ° C. in an inert gas atmosphere, the copper film is 5 × 10 ¹⁰ dyne / cm ² . Changes to tensile stress.

  The annealing of the metal film constituting the metal pattern 31 may be performed in any of an oxygen atmosphere, an oxygen-containing atmosphere, an inert gas atmosphere, and an inert gas-containing atmosphere.

  Further, if the metal film is heated to the melting point or higher during the annealing, the metal film is melted and the metal film does not cause a desired stress. Therefore, the annealing temperature needs to be lower than the melting point of the metal film.

(Second Embodiment)
The present invention can also be applied to damascene processes. This will be described below. 18 to 32 are cross-sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. In this example, a stack type FeRAM will be described. However, the present embodiment is not limited to this, and can be applied to a planar type FeRAM.

  First, steps required until a sectional structure shown in FIG.

As shown in FIG. 18A, after an element isolation trench is formed around the transistor formation region of the n-type silicon (semiconductor) substrate 51 by photolithography, silicon oxide (SiO ₂ ) is embedded therein. Thus, an element isolation insulating film 52 for STI is formed. Note that an insulating film formed by the LOCOS method may be employed as the element isolation insulating film 52.

  Subsequently, a p-type impurity is selectively introduced into a predetermined transistor formation region of the silicon substrate 51 to form a p-well 53, and the surface of the p-well 53 of the silicon substrate 51 is thermally oxidized to form a gate insulating film. A silicon oxide film to be 54 is formed.

  Next, an amorphous or polycrystalline silicon film and a tungsten silicide film are sequentially formed on the entire upper surface of the silicon substrate 51. Thereafter, the silicon film and the tungsten silicide film are patterned by photolithography to leave the gate electrodes 56a and 56b on the gate insulating film 54. These gate electrodes 56a and 56b constitute part of the word line (WL).

Next, n-type impurities, for example phosphorus, are ion-implanted into the p-wells 53 on both sides of the gate electrodes 56a and 56b to form first to third n-type impurity diffusion regions 55a to 55c that serve as sources / drains. Furthermore, after an insulating film, for example, a silicon oxide (SiO ₂ ) film, is formed on the entire surface of the silicon substrate 51 by the CVD method, the insulating film is etched back to form insulating sidewalls 57 on both sides of the gate electrodes 56a and 56b. Leave as.

  Subsequently, n-type impurities are ion-implanted again into the first to third n-type impurity diffusion regions 55a to 55c using the gate electrodes 56a and 56b and the sidewalls 57 as a mask. As a result, high-concentration impurity regions are formed in the first to third n-type impurity diffusion regions 55a to 55c, respectively. The first to third n-type impurity diffusion regions 55a to 55c are formed by LDD (Lightly Doped Drain). It becomes a structure.

  Of the diffusion regions, the first and third n-type impurity diffusion regions 55a and 55c are electrically connected to a lower electrode of a capacitor described later, and the second n-type impurity diffusion region 55b is connected to a bit line described later. Electrically connected.

Through the above steps, two n-type MOS transistors T ₁ and T ₂ having gate electrodes 56a and 56b and n-type impurity diffusion regions 55a to 55c are shared by one n-type impurity diffusion region 55b on the p-well 53. It was formed.

Next, a silicon oxynitride (SiON) film having a thickness of about 200 nm is formed on the entire surface of the silicon substrate 51 as a cover insulating film 58 covering the MOS transistors T ₁ and T ₂ by plasma CVD. Thereafter, silicon oxide (SiO ₂ ) having a thickness of about 1.0 μm is formed on the cover insulating film 58 as the base insulating film 59 by plasma CVD using TEOS gas.

Subsequently, the upper surface of the base insulating film 59 is planarized by a chemical mechanical polishing (CMP) method. Thereafter, the base insulating film 59 is annealed in the N ₂ atmosphere at about 650 ° C. for about 30 minutes, so that the base insulating film 59 is densified and dehydrated.

  Next, steps required until a structure shown in FIG.

  First, the cover insulating film 58 and the base insulating film 59 are patterned by photolithography to form contact holes 59a to 59c having a depth reaching the first to third n-type impurity diffusion regions 55a to 55c.

Next, titanium (Ti) having a thickness of about 20 nm and titanium nitride (TiN) having a thickness of about 50 nm are formed in this order as a glue film 60 on the upper surface of the base insulating film 59 and the inner surfaces of the contact holes 59a to 59c in this order. . Further, a tungsten (W) film 61 is grown on the glue film 60 by a CVD method using tungsten hexafluoride (WF ₆ ) to completely fill the contact holes 59a to 59c.

  Next, as shown in FIG. 18C, the tungsten film 61 and the glue film 60 are selectively polished by the CMP method while using the base insulating film 59 as a polishing stopper film, so that the upper surface of the base insulating film 59 is formed. Remove from. As a result, the tungsten film 61 and the glue film 60 are left as the first conductive plugs 62a and 62c and the second conductive plug 62b in the contact holes 59a to 59c.

  Next, steps required until a sectional structure shown in FIG.

First, an Ir film is formed on the entire surface by sputtering to a thickness of about 200 to 400 nm, for example, 250 nm. Thereafter, a TiN film 63a is formed on the Ir film by sputtering to a thickness of about 200 to 400 nm, for example, 200 nm, and then a SiO ₂ film 63b is formed by plasma CVD using TEOS on the surface to a thickness of 800 to 400 nm. It is formed on the entire surface at about 900 nm, for example, 800 nm. Then, this on the SiO ₂ film 63b to form a resist pattern (not illustrated), and the resist pattern as an etching mask is patterned and a SiO ₂ film 63b and TiN film 63a, which is referred to as hard mask 63.

Thereafter, the silicon substrate 51 is placed on a lower electrode in an etching chamber (not shown), and a bias voltage is applied to the silicon substrate 51 by applying 700 W of bias high frequency power having a frequency of 600 kHz to the lower electrode. . Further, 800 W of high frequency power of 13.56 MHz is applied as antenna power to the coil provided around the chamber, and HBr, O ₂ , and C ₄ F ₈ are introduced into the chamber at flow rates of 10 sccm, 40 sccm, and 5 sccm, respectively. Then, the pressure in the chamber is maintained at 0.4 Pa, and the substrate temperature is set to 400 ° C. Thereby, the inside of the chamber becomes an etching atmosphere for Ir. The reason why C ₄ F ₈ is added to the etching atmosphere as described above is to stabilize the etching process.

  Since the hard mask 63 has etching resistance to the above etching atmosphere, the hard mask 63 functions as an etching mask, and the underlying Ir film is selectively etched and patterned. As a result, the conductive oxygen barrier films 64a and 64c made of an Ir film are selectively left on the first conductive plugs 62a and 62c.

  Since the conductive oxygen barrier films 64a and 64c are made of an Ir film excellent in oxygen permeation preventing ability, the first conductive plugs 62a and 62c therebelow are oxidized and contacted in various thermal processes performed later. It is possible to prevent the occurrence of defects.

  Next, steps required until a sectional structure shown in FIG.

First, an SiON film is formed as an anti-oxidation insulating film 65a on the entire surface to a thickness of about 100 nm by plasma CVD. Thereafter, a SiO ₂ film having a thickness of about 400 nm is formed as an insulating adhesive film 65b on the oxidation-preventing insulating film 65a by plasma CVD using TEOS.

Subsequently, polishing is performed from the upper surface of the insulating adhesive film 65b by the CMP method, and the polishing is stopped on the surface of the TiN film 63a. As a result, as shown in FIG. 19C, the SiO ₂ film 63b is removed and the surface of the TiN film 63a is exposed.

  Thereafter, by exposing the exposed TiN film 63a to an aqueous ammonia peroxide solution, the TiN film 63a is removed as shown in FIG.

  Subsequently, as shown in FIG. 20B, a resist is applied over the entire surface to a thickness of about 1000 nm as the sacrificial film 66. As such a resist, one having an etching rate substantially the same as that of the oxidation preventing insulating film 65a and the insulating adhesive film 65b is used. By etching back such a sacrificial film 66 by plasma etching, the surface to be etched is lowered and remains flat, and after the etch back is finished, as shown in FIG. The flat upper surface is transferred to the oxidation-preventing insulating film 65a and the insulating adhesive film 65b. Thereafter, the remaining antioxidant insulating film 65a and insulating adhesive film 65b are used as the insulating oxygen barrier film 65.

  The oxidation-preventing insulating film 65a in the insulating oxygen barrier film 65 is made of a SiON film as described above, and plays a role of preventing the underlying second conductive plug 62b from being oxidized by various thermal processes.

  Next, steps required until a sectional structure shown in FIG.

First, an Ir film and an IrO ₂ film are formed on the entire surface in this order by sputtering to a thickness of about 200 nm and about 30 nm, respectively, and these are used as an IrO ₂ / Ir film 67. Of the IrO ₂ / Ir film 67, the lowermost Ir film functions to prevent oxidation of the first conductive plug 62 a thereunder and to prevent contact characteristics from deteriorating.

Thereafter, a PtO film and a Pt film are formed on the IrO ₂ / Ir film 67 in this order by sputtering to a thickness of about 30 nm and about 50 nm, respectively, which are used as a Pt / PtO film 68. Of the Pt / PtO film 68, the Pt film plays a role in aligning the orientation of the ferroelectric film formed later on the Pt film.

The IrO ₂ / Ir film 67 and the Pt / PtO film 68 are used as the lower electrode conductive film 69.

  Note that before or after the formation of the lower electrode conductive film 69, the insulating adhesive film 65b may be annealed, for example, to prevent film peeling. As the annealing method, for example, RTA at 750 ° C. for 60 seconds in an argon atmosphere can be employed.

Next, a PZT film as a ferroelectric film 70 is formed on the lower electrode conductive film 69 to a thickness of about 180 nm by sputtering. As a method for forming the ferroelectric film 70, there are a MOD method, an MOCVD method, a sol-gel method and the like in addition to the sputtering method. In addition to PZT, the ferroelectric film 70 may be made of other PZT-based materials such as PLCSZT and PLZT, and Bi layers such as SrBi ₂ Ta ₂ O ₉ and SrBi ₂ (Ta, Nb) ₂ O _9. Structural compound materials and other metal oxide ferroelectrics may be employed. Further, when forming a DRAM, a high dielectric material such as (BaSr) TiO ₃ (BST) or strontium titanate (STO) may be used instead of the above ferroelectric material.

Next, the ferroelectric film 70 is crystallized by annealing in an oxygen-containing atmosphere. As the annealing, for example, a substrate temperature of 600 ° C. in a mixed gas atmosphere of Ar and O ₂ for a time of 90 seconds is a first step, and a substrate temperature of 750 ° C. in an oxygen atmosphere for a time of 60 seconds is a second step. A two-step RTA process is employed.

Subsequently, an IrO ₂ film having a thickness of, for example, 200 nm is formed on the ferroelectric film 70 as the upper electrode conductive film 71 by sputtering. Thereafter, annealing is performed for about 60 minutes in a furnace (not shown) in an oxygen atmosphere at 650 ° C. in order to recover the damage received by the ferroelectric film 70 when the upper electrode conductive film 71 is formed.

  Next, steps required until a sectional structure shown in FIG.

First, a TiN film 95 is formed on the upper electrode conductive film 71 by sputtering, and an SiO ₂ film 96 is further formed thereon by plasma CVD using TEOS. Thereafter, the TiN film 95 and the SiO ₂ film 96 are patterned into a capacitor shape by photolithography to form a hard mask 97.

Next, the silicon substrate 51 is placed on a lower electrode in an etching chamber (not shown), and a bias voltage is applied to the silicon substrate 51 by applying 700 W of bias high frequency power having a frequency of 600 kHz to the lower electrode. Further, 800 W of high frequency power of 13.56 MHz is applied as antenna power to a coil provided around the chamber, and HBr and O ₂ are introduced into the chamber at a flow rate of 10 sccm and 40 sccm, respectively, and the pressure in the chamber is adjusted. While holding at 0.4 Pa, the substrate temperature is set to 400 ° C. Thus, the etch chamber serves as an etching atmosphere for IrO _2, the upper electrode conductive layer 71 made of IrO ₂ is etched. Then, when the upper electrode conductive film 71 is overetched by 10%, the etching is terminated, whereby the upper electrode conductive film 71 is etched into the shape of the hard mask 97 to become the upper electrode 71a. Note that 10% overetching means that the upper electrode conductive film 71 is excessively etched by 10% of the film thickness of the upper electrode conductive film 71 of 200 nm, that is, 20 nm.

Subsequently, the bias power and the antenna power are left as they are, and the etching gas is changed to 40 sccm of Cl ₂ and 10 sccm of Ar, whereby the inside of the chamber is made an etching atmosphere for PZT, and the ferroelectric film 70 made of PZT is hard mask 97. Etching to shape. Then, the etching is stopped on the lower electrode conductive film 69 by monitoring the etching end point with the end point detector. As a result, the ferroelectric film 70 is etched to form a capacitor dielectric film 70a.

Next, the etching gas is again changed to 10 sccm of HBr and 40 sccm of O ₂ , and etching of the lower electrode conductive film 69 is started. When 10% overetching is achieved, the etching is terminated. As a result, the conductive film 69 for the lower electrode is etched into the shape of the hard mask 97 to become the lower electrode 69a.

  By this step, the ferroelectric capacitors Q1 and Q2 formed by laminating the lower electrode 69a, the ferroelectric film 70a, and the upper electrode 71a in this order are formed into the conductive oxygen barrier films 64a and 64c, the insulating oxygen barrier film 65, and the like. Thus, it is formed on the base insulating film 9. The ferroelectric capacitors Q1 and Q2 are electrically connected to the first diffusion region 55a and the third diffusion region 55c through the conductive oxygen barrier films 64a and 64c and the first conductive plugs 62a and 62c, respectively. Connected.

A part of the ferroelectric capacitors Q1 and Q2 is formed on the insulating oxygen barrier film 65. The uppermost layer of the insulating oxygen barrier film 65 is an insulating adhesive film 65b made of SiO _2. It is possible to prevent the lower electrodes 69a of the dielectric capacitors Q1 and Q2 from being peeled off from the insulating oxygen barrier film 65.

  Subsequently, recovery annealing is performed to recover damage to the dielectric film 70a due to etching. In this case, the recovery annealing is performed, for example, in a furnace containing oxygen at a substrate temperature of 650 ° C. for 60 minutes.

  Even if such recovery annealing is performed, the insulating oxygen barrier film 65 can prevent the second conductive plug 62b from being oxidized, and the conductive oxygen barrier films 64a and 64c can prevent the first conductive plugs 62a and 62c. Can be prevented from being oxidized. The hard mask 97 is removed after the ferroelectric capacitors Q1 and Q2 are formed.

  Next, as shown in FIG. 22A, alumina having a thickness of about 50 nm is formed on the ferroelectric capacitors Q1, Q2 and the insulating oxygen barrier film 65 as a first capacitor protective insulating film 73 by sputtering. Form. The first capacitor protection insulating film 73 protects the ferroelectric capacitors Q1 and Q2 from process damage, and may be made of PZT in addition to alumina.

Thereafter, a SiO ₂ film having a thickness of about 100 nm is formed on the first capacitor protection insulating film 73 as the second capacitor protection insulating film 72 by plasma CVD using TEOS.

Next, as shown in FIG. 22B, a first insulating film 74 made of SiO ₂ is deposited on the second capacitor insulating film 72 by about 1.5 μm by HDPCVD (High Density Plasma) using SiH ₄ . Form to thickness. In such an HDPCVD method, by applying a bias voltage to the silicon substrate 51, the first insulating film 74 having good embeddability is formed between the ferroelectric capacitors Q1 and Q2 having a high aspect ratio without generating voids. be able to.

However, since the HDPCVD method uses SiH ₄ having reducing hydrogen as a reactive gas, the dielectric film 70a may be deteriorated by the hydrogen. Therefore, by supplying O ₂ or 5 times the flow rate of SiH _4, then oxidized as possible hydrogen in the atmosphere as much as possible preferably prevent deterioration of the dielectric film 70a by hydrogen.

  Although the reason is unknown, when the second capacitor protective insulating film 72 is formed by the plasma CVD method using TEOS, the ferroelectric capacitor Q1, compared to the case where the first capacitor protective insulating film 73 is used as a single layer, The deterioration of Q2 can be prevented better.

Thereafter, as shown in FIG. 23A, a SiO ₂ film is formed on the first insulating film 74 as a sacrificial film 75 for CMP to a thickness of about 500 nm by a plasma CVD method using TEOS.

  Then, by polishing the sacrificial film 75 by CMP, the surface of the first insulating film 74 is planarized as shown in FIG. 23B, and the thickness of the first insulating film 74 on the upper electrode 71a is increased. About 500 nm.

  Next, as shown in FIG. 24A, a BN film (dielectric constant: about 2) is formed as a first low dielectric constant insulating film 76 on the planarized first insulating film 74 to a thickness of about 200 nm. Form.

Since the first low dielectric constant insulating film 76 is formed on the flattened first insulating film 74 having no wiring step, a film having a good embeddability, for example, applying a substrate bias is applied. There is no need to adopt the HDPCVD method. Therefore, the BN film can be formed without applying a bias voltage (non-bias) to the silicon substrate 51. For example, a non-bias plasma using B ₂ H ₆ and N ₂ as reaction gases. It can be formed by a CVD method.

  Since it is non-biased, hydrogen in the deposition gas is not drawn into the silicon substrate 51 by the bias voltage, and it is possible to prevent the ferroelectric capacitors Q1 and Q2 from being deteriorated by hydrogen.

As the low dielectric constant insulating film 76, a film formed by the SOL-GEL method may be used in addition to the BN film. In this case, a block film (not shown) that blocks degassing from the low dielectric constant film 76 is formed on the first insulating film 74, and the first low dielectric constant insulating film 76 is formed on the block film. Is preferred. Examples of such a block film include a SiN film, a SiO ₂ film, a SiC film, and a TiOx film formed by a Cat-CVD (Catalytic Chemical Vapor Deposition) method.

Subsequently, a SiO ₂ film having a thickness of 100 nm is formed as a first cap film 77 on the first low dielectric constant film 76 by a plasma CVD method using TEOS. The first cap film 77 serves to prevent the degassing from the first low dielectric constant film 76 from diffusing upward. As the first cap film 77, various films formed by the above-described Cat-CVD method may be used. Since the first cap film 77 is also formed on a flat surface, it is not necessary to form the film by the HDPCVD method.

  By this step, the first interlayer insulating film 118 composed of the insulating films 72 to 74 and 76 to 77 is formed so as to cover the ferroelectric capacitors Q1 and Q2.

  Next, steps required until a sectional structure shown in FIG.

  First, a photoresist is applied on the first cap film 77, and is exposed and developed to form a first resist pattern 78 having a hole-shaped resist opening 78a. Next, while using the first resist pattern 78 as an etching mask, the first cap film 77, the first low dielectric constant insulating film 76, the first insulating film 74, and the second capacitor protection insulating film 72 are etched, and each film is etched. First holes 72a, 74a, 76a, 77a are formed in the first and second holes 72a, 74a, 76a, 77a.

As an etching gas in this case, for example, a mixed gas of CF ₄ , C ₄ F ₈ , O ₂ , and Ar is used.

Since the etching selectivity between alumina and SiO ₂ in this etching is (alumina) :( SiO ₂ ) = 1: 2 to 3, the first capacitor protection insulating film 73 made of alumina serves as an etching stopper film in this etching. Fulfill.

  After this etching is completed, the first resist pattern 78 is removed by ashing with oxygen plasma.

  Next, steps required until a sectional structure shown in FIG.

First, a photoresist is applied to the entire surface, and is exposed and developed to form a second resist pattern 79 having a hole-shaped first resist opening 79a and a wiring-shaped second resist opening 79b. Next, using the second resist pattern 79 as an etching mask, the first cap film 77, the first low dielectric constant insulating film 76, the first insulating film 74, and the second capacitor protective insulating film under the first resist opening 79a. 72 is etched to form third holes 77c and 76c and second holes 74b and 72b in the respective films. As an etching gas in this etching, for example, a mixed gas of CF ₄ , C ₄ F ₈ , O ₂ , and Ar is used.

  It is possible to form these holes in the previous etching step (FIG. 24B), but the combined depth of these holes depends on the holes 72a and 74a on the ferroelectric capacitors Q1 and Q2. , 76a and 77a, the first capacitor protective insulating film 73 on the ferroelectric capacitors Q1 and Q2 is etched, and the ferroelectric capacitors Q1 and Q2 are exposed to the etching atmosphere for a long time, causing damage. There is a risk of receiving.

  Reference is again made to FIG. In the etching described above, the first cap film 77 and the first low dielectric constant insulating film 76 under the second resist opening 79b are also etched, and second holes 77b and 76b are formed in the respective films. The first wiring groove 80 is constituted by the second holes 77a and 76b.

  In this etching, the first capacitor protection insulating film 73 under the first hole 72a is etched, and the first hole 73a is formed there. As a result, a first contact hole 81 composed of the holes 72a to 74a is formed extending downward from the bottom of the first wiring groove 80, and the upper portions of the ferroelectric capacitors Q1 and Q2 are formed in the first contact hole 81. The electrode 71a is exposed.

  After this step is completed, the second resist pattern 79 is removed by ashing with oxygen plasma.

  Thereafter, oxygen annealing is performed for 60 minutes in an oxygen atmosphere at 550 ° C. in order to recover the damage received by the ferroelectric capacitors Q1 and Q2 in the steps up to here after the formation of the ferroelectric capacitors Q1 and Q2. At the time of this oxygen annealing, since the insulating oxygen barrier film 65 is formed on the second conductive plug 62b, oxidation of the second conductive plug 62b can be prevented.

  Next, steps required until a sectional structure shown in FIG.

  First, a photoresist is applied on the entire surface, and is exposed and developed to form a third resist pattern 82 having a wiring-shaped resist opening 82a.

Next, while using the third resist pattern 82 as an etching mask, the first cap film 77 and the first low dielectric constant insulating film 76 under the resist opening 82a are etched, and fourth holes 77d and 76d are formed in the respective films. These are used as the second wiring groove 83. As an etching gas in this etching, for example, a mixed gas of CF ₄ , C ₄ F ₈ , O ₂ , and Ar is used.

  In this etching, the first capacitor protective insulating film 73, the insulating adhesion film 65b, and the antioxidant insulating film 65a under the second hole 72b are also etched, and the second hole 73b and the first hole are formed in the respective films. 65d and 65c are formed. The holes 74b, 72b, 73b, 65d, and 65c are used as the second contact holes 84.

  After this process is completed, the third resist pattern 82 is removed by ashing with oxygen plasma.

  Next, steps required until a sectional structure shown in FIG.

  First, the upper surfaces of the upper electrode 71a and the second conductive plug 62b are etched by about 20 nm with Ar plasma to obtain clean surfaces. Thereafter, TaN is formed on the inner surfaces of the first and second contact holes 81 and 84 and the first and second wiring grooves 80 and 83 by sputtering as a first diffusion preventing film 85 for preventing copper diffusion. A thickness of about 50 nm is formed.

  Next, as shown in FIG. 26B, a Cu seed layer (not shown) is formed on the entire surface, and power is supplied to the Cu seed layer, so that the first and second contact holes 81 and 84 and the first and second wirings are supplied. A first copper film 86 having a thickness that completely fills the inner surfaces of the grooves 80 and 83 is formed by plating. In the plating method, in addition to copper sulfate, a plating solution to which an organic substance for improving copper embedding is added is used. In the plating method, since the substrate 51 is not heated, the thermal budget is lowered, and the ferroelectric capacitors Q1 and Q2 can be prevented from being damaged by heat.

Instead of the plating method, the first copper film 86 may be formed by a CVD method. In the CVD method, a silicon substrate 51 is mounted on a substrate mounting table 125 in a chamber 124 shown in FIG. 33, and Cl ₂ gas is introduced from above the chamber 124. Then, by supplying high frequency power of 13.56 MHz and power 3000 W generated by the high frequency power supply 128 to the coil 126, Cl plasma is generated in the chamber 124, and the Cl plasma is maintained at a temperature of about 300 ° C. It passes through the opening 127a of 127. As a result, the copper on the copper plate 127 is exposed to Cl plasma to produce copper chloride of Cu _x Cl _y , which adheres to the silicon substrate 51. Since the silicon substrate 51 is held at about 200 ° C., which is lower than that of the Cl plasma, Cl in Cu _x Cl _y is desorbed due to the temperature difference between the silicon substrate 51 and the plasma, and only Cu is deposited on the silicon substrate 51. As a result, the first copper film 86 is formed.

  When the first copper film 86 is formed by the CVD method in this way, in order to prevent a natural oxide film from being formed on the surface of the first copper film 86, it is exposed to the atmosphere after the first copper film 86 is formed. Should be avoided.

  Next, steps required until a sectional structure shown in FIG.

  First, the first copper film 86 and the first diffusion prevention film 85 above the first cap film 77 are removed by polishing by CMP, and the first copper film 86 and the first wiring grooves 80 and 83, and the first wiring grooves 80 and 83 are removed. The first and second copper wirings 86a and 86c and the first and second copper plugs 86b and 86d are left in the second contact holes 81 and 84, respectively. The first copper wiring 86a is electrically connected to the upper electrodes 71a of the ferroelectric capacitors Q1 and Q2 via the first copper plug 86b and functions as a plate line. Second copper interconnection 86c functions as a bit line, and is electrically connected to second n-type impurity diffusion region 55b through second copper plug 86d and second conductive plug 62b.

  Such a method for forming a copper wiring is called a dual damascene process.

  Next, a second diffusion preventing film 87 is formed on the entire surface in order to prevent copper from diffusing upward. As the second diffusion preventing film 87, for example, a SiN film having a thickness of 70 nm can be adopted. In order to avoid damage to the ferroelectric capacitors Q1 and Q2, the SiN film is formed by a non-biased plasma CVD method. Is preferred. Alternatively, a BN film, a SiC film, and an alumina film may be employed instead of the SiN film. Furthermore, instead of such an insulating film, a conductive film made of Ta, TaN, Ti, TiN or the like formed by sputtering may be adopted as the second diffusion preventing insulating film 87. When such a conductive film is used, in order to prevent the copper wirings 86a and 86c from being electrically connected, there is a step of patterning the conductive film into a shape of each copper wiring 86a and 86c after the conductive film is formed. Done.

  Next, steps required until a sectional structure shown in FIG.

First, an SiO ₂ film having a thickness of about 500 nm is formed on the second diffusion prevention film 87 as the second insulating film 88 by plasma CVD using TEOS. Thereafter, a non-biased plasma CVD method using B ₂ H ₆ and N ₂ as reaction gases is used to form a BN film as a second low dielectric constant insulating film 89 on the second insulating film 88 to a thickness of about 200 nm. Form. Subsequently, a SiO ₂ film having a thickness of 100 nm is formed as a second cap film 90 on the second low dielectric constant film 89 by a plasma CVD method using TEOS. The second cap film 90 functions to prevent the degassing from the second low dielectric constant film 89 from diffusing upward.

  Through the steps so far, the second interlayer insulating film 119 composed of the insulating films 87 to 90 is formed.

  Next, steps required until a sectional structure shown in FIG.

  First, a photoresist (not shown) is applied on the second cap film 90, and is exposed and developed to form a resist pattern (not shown) having a metal pattern-shaped opening. Next, using the resist pattern as an etching mask, the second cap film 90 and the second low dielectric constant insulating film 89 are etched to form the first holes 89a and 90a constituting the metal pattern groove 92 in these films. To form. The metal pattern groove 92 is formed above the capacitors Q1 and Q2 and the periphery thereof so as to cover the cell region including the capacitors Q1 and Q2.

  Next, as shown in FIG. 30, a TaN film having a thickness of about 30 nm is formed in the metal pattern groove 92 as the third diffusion prevention film 130, and further, by sputtering, or the plating method or the CVD method described above, A second copper film 131 is formed on the third diffusion barrier film 130. The thickness of the second copper film 131 is set to a depth that completely fills the metal pattern groove 92.

  Subsequently, as shown in FIG. 31, the third diffusion barrier film 130 and the second copper film 131 are polished by the CMP method. As a result, the third diffusion barrier film 130 and the second copper film 131 are removed from the upper surface of the second cap film 90 and are left in the metal pattern groove 92 to form the metal pattern 132. .

  The metal pattern 132 is formed wider than the cell region so as to sufficiently cover the ferroelectric capacitors Q1 and Q2. The potential of the metal pattern 132 is not limited and may be a fixed potential or an electrically isolated floating potential. Good.

Thereafter, the silicon substrate 51 is fixed on a susceptor maintained at 370 ° C., and the metal pattern 132 is annealed for 30 minutes in a reduced pressure atmosphere of inert gas, for example, in an N ₂ atmosphere at a pressure of 2 Torr.

Before this annealing, the second copper film 131 in the metal pattern 132 has a compressive stress of −5 × 10 ¹⁰ dyne / cm ² , but after this annealing, it changes to a tensile stress of 5 × 10 ¹⁰ dyne / cm ^2. . This stress change gives a favorable stress to the lower ferroelectric capacitors Q1 and Q2, so that the ferroelectric characteristics of the ferroelectric capacitors Q1 and Q2 are improved.

  In the above description, the metal pattern 132 is annealed after the metal film composed of the third diffusion barrier film 130 and the second copper film 131 is polished by CMP. However, the order of forming the metal pattern 132 and annealing is not limited. . For example, even if annealing is performed on the metal film before CMP under the above conditions, it can be expected that the same stress effect as described above is generated in the metal pattern 132. Furthermore, annealing may be performed after a fourth diffusion barrier film 100 described later is formed on the metal pattern 132.

  If the metal film is heated above its melting point in the annealing, the metal film melts and the metal film does not cause a desired stress. Therefore, the annealing temperature needs to be lower than the melting point of the metal film.

  Furthermore, this annealing may be performed not only in a reduced-pressure atmosphere of an inert gas but also in an oxygen atmosphere, an oxygen-containing atmosphere, or an inert gas-containing atmosphere.

  Next, steps required until a sectional structure shown in FIG.

  First, an alumina film or a Ta film having a thickness of about 70 nm is formed as a fourth diffusion prevention film 100 on the metal pattern 132 and the second cap film 90 by a sputtering method. By forming the fourth diffusion preventing film 100 by the sputtering method, the film formation atmosphere does not become a reducing atmosphere, so that the capacitors Q1 and Q2 can be prevented from being deteriorated by the reducing atmosphere.

  In the case where the Ta film is used as the fourth diffusion preventing film 100, in order to prevent the metal pattern 132 from being electrically connected to the wiring (not shown) in the same layer as that, after the Ta film is formed, It is patterned into the shape of the metal pattern 132.

Next, an SiO ₂ film having a thickness of about 100 nm is formed on the fourth diffusion barrier film 100 by a plasma CVD method using TEOS, and this is used as a third insulating film 101. Thereafter, a BN film having a thickness of about 200 nm is formed as a third low dielectric constant insulating film 102 on the third insulating film 101, and further a SiO ₂ film having a thickness of about 100 nm is formed thereon by plasma CVD using TEOS. Is formed as a third cap film 103.

  Subsequently, using a dual damascene process, a third copper plug 104 and a third copper are formed on the third diffusion barrier film 100, the third insulating film 101, the third low dielectric constant insulating film 102, and the third cap film 103. The wiring 105 is embedded. Each of the third copper plug 104 and the third copper wiring 105 has a two-layer structure of a TiN film and a copper film, and is electrically connected to the lower metal pattern 132.

  Here, when the metal pattern 132 is set to a floating potential, it is not necessary to connect the third copper plug 104 to the metal pattern 132. In this case, a hole may be formed in the metal pattern 132, and the third copper plug 104 may be formed so as to reach the first copper wiring 86a without touching the hole. In this case, a hole in which the third copper plug 104 is embedded is formed in each insulating film 87-90.

  Next, an alumina film or a Ta film having a thickness of about 70 nm is formed as a fifth diffusion prevention film 106 on the third copper wiring 105 and the third cap film 103 by sputtering. When the Ta film is used as the fifth diffusion preventing film 106, the Ta film is formed and then patterned into the shape of the third copper wiring 105.

Thereafter, a SiO ₂ film having a thickness of about 500 nm is formed on the fifth diffusion barrier film 106 as the fourth insulating film 107 by plasma CVD using TEOS. Further, a fourth low dielectric constant insulating film 108 such as a BN film is formed on the fourth insulating film 107 to a thickness of about 200 nm, and a SiO ₂ film is formed thereon by a plasma CVD method using TEOS, This is referred to as a fourth cap film 109.

  Then, the fourth copper wiring 110 is embedded in the fifth diffusion barrier film 106, the fourth insulating film 107, the fourth low dielectric constant insulating film 108, and the fourth cap film 109 by a dual damascene process. The fourth copper wiring 110 has a two-layer structure of a TiN film and a copper film, and is electrically connected to the third copper wiring 105 by a copper plug (not shown).

Subsequently, an alumina film or a Ta film is formed as a sixth diffusion prevention film 111 on the fourth copper wiring 110 and the fourth cap film 109 by a sputtering method to a thickness of about 70 nm. When the Ta film is used as the fourth diffusion preventing film 111, the Ta film is formed and then patterned into the shape of the sixth copper wiring 110. Thereafter, a SiO ₂ film having a thickness of about 500 nm is formed on the sixth diffusion prevention film 111 by plasma CVD using TEOS, and this is used as the fifth insulating film 112. Then, a hole is formed in the fifth insulating film 112 and the fourth diffusion prevention film 111 by photolithography, and a third conductive plug 113 is formed in the hole. The third conductive plug 113 has, for example, a structure in which a TaN film, a TiN film, and a tungsten film are stacked in order from the bottom.

  Thereafter, a multilayer metal film is formed on the third conductive plug 113 and the fifth insulating film 112. As the multilayer metal film, for example, a Ti film having a thickness of 60 nm, a TiN film having a thickness of 30 nm, an Al—Cu film having a thickness of 400 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 70 nm are sequentially formed by sputtering. Form. Then, the multilayer metal film is patterned by photolithography to form a final metal wiring 115.

Then, a SiO ₂ film having a thickness of about 1.5 μm is formed as the sixth insulating film 114 covering the final metal wiring 115 by plasma CVD using TEOS.

  Finally, a SiN film having a thickness of about 500 nm is formed as a surface protective film 116 for protecting the device surface. The SiN film is preferably formed by a non-biased plasma CVD method so as not to damage the capacitors Q1 and Q2.

  According to this embodiment described above, the metal pattern trench 92 is provided in the second interlayer insulating film 119, and the metal pattern 132 having tensile stress is formed there. Therefore, the compressive stress generated in the second insulating film 88 and the like in the second interlayer insulating film 119 is relieved by the metal pattern, and the net stress acting on the ferroelectric capacitors Q1 and Q2 is reduced, and the ferroelectric capacitor The ferroelectric characteristics of Q1 and Q2 are improved.

  In the above description, the second interlayer insulating film 119 is composed of a plurality of insulating films 88 to 90, but the second interlayer insulating film 119 may be formed of a single layer insulating film.

  Furthermore, in the above description, the metal pattern 132 is composed of the multilayer metal film of the third diffusion prevention film 130 and the second copper film 131, but it need not be a multilayer metal film. That is, it may be a film of any of aluminum, titanium, copper, tantalum, and tungsten, or a film of an alloy or a mixture with any of these elements.

FIG. 1 is a cross-sectional view (No. 1) showing a step of forming a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a sectional view (No. 2) showing a step of forming the semiconductor device according to the first embodiment of the invention. FIG. 3 is a sectional view (No. 3) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 4 is a sectional view (No. 4) showing a step of forming the semiconductor device according to the first embodiment of the invention. FIG. 5 is a sectional view (No. 5) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 6 is a sectional view (No. 6) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 7 is a sectional view (No. 7) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 8 is a sectional view (No. 8) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 9 is a sectional view (No. 9) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 10 is a sectional view (No. 10) showing a step of forming a semiconductor device according to the first embodiment of the invention. FIG. 11 is a sectional view (No. 11) showing a step of forming the semiconductor device according to the first embodiment of the invention. FIG. 12 is a sectional view (No. 12) showing a step of forming the semiconductor device according to the first embodiment of the invention. FIG. 13 is a sectional view (No. 13) showing a step of forming the semiconductor device according to the first embodiment of the invention. FIG. 14 is a plan view of the semiconductor device according to the first embodiment of the present invention. FIG. 15 is a diagram showing the yield of FeRAM according to the first embodiment of the present invention and the yield of FeRAM formed by the prior art. FIG. 16 is a diagram showing the characteristics of the ferroelectric capacitor in the FeRAM according to the first embodiment of the present invention and the characteristics of the ferroelectric capacitor in the FeRAM formed by the prior art. FIG. 17 is a diagram showing a change in stress due to annealing of the metal film. FIG. 18 is a cross-sectional view (No. 1) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 19 is a sectional view (No. 2) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 20 is a sectional view (No. 3) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 21 is a sectional view (No. 4) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 22 is a sectional view (No. 5) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 23 is a sectional view (No. 6) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 24 is a sectional view (No. 7) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 25 is a sectional view (No. 8) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 26 is a sectional view (No. 9) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 27 is a sectional view (No. 10) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 28 is a sectional view (No. 11) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 29 is a sectional view (No. 12) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 30 is a sectional view (No. 13) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 31 is a sectional view (No. 14) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 32 is a sectional view (No. 15) showing the step of forming the semiconductor device according to the second embodiment of the invention. FIG. 33 is a configuration diagram of a copper film forming apparatus used in the semiconductor device forming process according to the second embodiment of the present invention.

Explanation of symbols

A ... Memory cell region, B ... Peripheral circuit region, 1, 51 ... Silicon (semiconductor) substrate, 2, 52 ... Element isolation insulating film, 3a, 3b, 53 ... p well, 4 ... n well, 5, 54 ... gate Insulating films, 6a-6c, 56a, 56b ... gate electrodes, 7 ... extraction electrodes, 8a, 8b, 55a-55c ... n-type impurity diffusion regions, 9 ... p-type impurity diffusion regions, 10, 57 ... sidewalls, 11 ... Interlayer insulating film, 12a to 12e ... hole, 13a to 13e ... contact plug, 14 ... SiON film, 15 ... SiO2 film, 16 ... first conductive film, 16a ... lower electrode, 17 ... ferroelectric film, 17a ... dielectric Body film 18 ... second conductive film 18a ... upper electrode 19 ... first capacitor protective insulating film 20 ... capacitor 21 ... interlayer insulating film 22a ... local wiring 23 ... second capacitor protective insulating film 24 layers Edge film, 24a-24f ... hole, 25a ... bit line, 25b-25d ... wiring, 26 ... interlayer insulating film, 26c, 26e ... hole, 27 ... re-deposited interlayer insulating film, 28c ... conductive plug, 30 ... metal wiring , 31, 132 ... metal pattern, 32, 33 ... cover film, 58 ... cover insulating film, 59 ... base insulating film, 60 ... glue film, 61 ... tungsten film, 59a-59c ... contact hole, 62a, 62c ... first Conductive plug, 62b ... second conductive plug, 63a ... TiN film, 63b ... SiO ₂ film, 63 ... hard mask, 64a, 64b ... conductive oxygen barrier film, 65a ... antioxidation insulating film, 65b ... insulating adhesion 65, insulating oxygen barrier film, 66, 75 ... sacrificial film, 67 ... IrO ₂ / Ir film, 68 ... Pt / PtO film, 69 ... lower electrode conductive film, 69a ... lower electrode, 70 ... ferroelectric Membrane, 70 ... Dielectric film, 71 ... Upper electrode conductive film, 71a ... Upper electrode, 72 ... Second capacitor protective insulating film, 73 ... First capacitor protective insulating film, 74 ... First insulating film, 76 ... First low dielectric constant Insulating film, 77 ... first cap film, 78 ... first resist pattern, 72a, 74a, 76a, 77a ... first hole, 74b, 72b, 76b, 77b ... second hole, 76c, 77c ... third hole, 76d , 77d ... fourth hole, 78a ... resist pattern, 79 ... second resist pattern, 80 ... first wiring groove, 81 ... first contact hole, 82 ... third resist pattern, 83 ... second wiring groove, 84 ... first. 2 contact holes, 85 ... first diffusion prevention film, 86 ... first copper film, 86a ... first copper wiring, 86b ... first copper plug, 86c ... second copper wiring, 86d ... second copper plug, 87 ... first 2 expansion Preventing film, 88 ... second insulating layer, 89 ... second low dielectric constant insulating film, 90 ... second cap layer, 90a, 89a ... first hole, 92 ... metal pattern groove, 95 ... TiN film, 96 ... SiO _Two films, 97: Hard mask, 100: Fourth diffusion prevention film, 101: Third insulating film, 102: Third low dielectric constant insulating film, 103: Third cap film, 104: Third copper plug, 105: First 3 copper wirings 106... Fifth diffusion prevention film 107 107 fourth insulation film 108. Fourth low dielectric constant insulation film 109. Fourth cap film 110 110 fourth copper wiring 111 111 sixth diffusion prevention film , 112 ... fifth insulating film, 113 ... third conductive plug, 114 ... sixth insulating film, 115 ... final metal wiring, 116 ... surface protective film, 124 ... chamber, 125 ... substrate mounting table, 126 ... coil, 127 ... Copper plate, 127a ... Opening, 128 ... High frequency power supply, 13 ... third diffusion barrier layer, 131 ... second copper film.

Claims (7)

A semiconductor substrate;
A first insulating film formed above the semiconductor substrate;
A capacitor formed on the first insulating film and having a lower electrode, a dielectric film, and an upper electrode;
A first capacitor protective insulating film formed by sputtering over the capacitor;
A second capacitor protective insulating film formed on the first capacitor protective insulating film by a plasma CVD method;
A second insulating film formed on the second capacitor protective insulating film;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first capacitor protection insulating film is an alumina film. The semiconductor device according to claim 1, wherein the second capacitor protection insulating film is a SiO ₂ film. Forming a first insulating film above the semiconductor substrate;
Forming a capacitor having a lower electrode, a dielectric film and an upper electrode on the first insulating film;
Forming a first capacitor protective insulating film by sputtering over the capacitor;
Forming a second capacitor protective insulating film on the first capacitor protective insulating film by a plasma CVD method;
Forming a second insulating film on the second capacitor protection insulating film;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 4, wherein an alumina film is formed as the first capacitor protective insulating film. The method of manufacturing a semiconductor device according to claim 4, wherein an SiO ₂ film is formed as the second capacitor protective insulating film.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the second insulating film is formed by a plasma CVD method for applying a bias voltage to the semiconductor substrate.

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