JP2006284915A - Display device and array substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make electrostatic breakdown of an output control switch less likely to occur. <P>SOLUTION: A display device includes an insulating substrate SUB and a plurality of pixels PX arranged on the substrate. Each pixel PX includes a drive transistor DR connected between a first power terminal ND<SB>ps1</SB>and a first terminal ND1; an output control transistor SW1 connected between the first terminal ND1 and a second terminal ND2; a display element OLED connected between the second terminal ND2 and a second power terminal ND<SB>ps2</SB>; and a capacitor C2 connected between a gate of the output control transistor SW1 and the second terminal ND2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an active matrix display device and an array substrate used therefor.

  Patent Document 1 below describes an active matrix organic electroluminescence (EL) display device that employs a current copy type circuit as a pixel circuit. This current copy type pixel circuit includes an n-channel field effect transistor that is a drive control element, an organic EL element, a capacitor, an output control switch, a video signal supply control switch, and a diode connection switch.

  The source of the drive control element is connected to the first power supply line having a low potential, and the capacitor is connected between the gate of the drive control element and the first power supply line. The output control switch is connected between the drain of the drive control element and the cathode of the organic EL element, and the anode of the organic EL element is connected to a second power supply line having a higher potential. The video signal supply control switch is connected between the drain of the drive control element and the video signal line, and the diode connection switch is connected between the drain and gate of the drive control element. Note that a field effect transistor is usually used for each switch.

As typified by this current copy type circuit, in many pixel circuits of active matrix type organic EL display devices, a drive control element, an output control switch, and an organic EL element are connected between the first and second power supply terminals. They are connected in series in this order. When the present inventor makes the present invention, in the manufacture of an organic EL display device including such a pixel circuit, the output control switch is not changed between the formation of the pixel electrode and the completion of the organic EL element. It has been found that electrostatic damage is likely to occur.
US Pat. No. 6,373,454

  An object of the present invention is to make it difficult to cause electrostatic breakdown of an output control switch.

  According to a first aspect of the present invention, an insulating substrate and a plurality of pixels arranged on the insulating substrate are provided, and each of the plurality of pixels is connected between a first power supply terminal and a first terminal. A transistor, an output control transistor connected between the first terminal and the second terminal, a display element connected between the second terminal and a second power supply terminal, and a gate of the output control transistor; A display device including a capacitor connected to the second terminal is provided.

  According to a second aspect of the present invention, an insulating substrate, a plurality of pixels arranged thereon, a plurality of scanning signal lines arranged along a row formed by the plurality of pixels, and the plurality of pixels are formed. A plurality of video signal lines arranged along a column and a plurality of power supply lines, each of the plurality of pixels being connected between a first power supply terminal and a first terminal on the power supply line A transistor, an output control transistor connected between the first terminal and the second terminal, a pixel electrode connected to the second terminal, a counter electrode connected to the second power supply terminal, and an intervening therebetween A display element including the active layer, and when viewed from a direction perpendicular to the main surface of the insulating substrate, the pixel electrode in each of the plurality of pixels includes the plurality of scanning signal lines and the plurality of scanning signal lines. A plurality of video signal lines and the plurality of power supply lines The display device is provided, characterized in that the gate of the output control transistor to which the pixel includes are only overlapped connected the scanning signal lines.

  According to a third aspect of the present invention, there is provided an insulating substrate and a plurality of pixel circuits arranged thereon, and each of the plurality of pixel circuits is connected between a power supply terminal and a first terminal. A transistor; an output control transistor connected between the first terminal and the second terminal; a pixel electrode connected to the second terminal; and a gate of the output control transistor and the second terminal. An array substrate comprising a connected capacitor is provided.

  According to a fourth aspect of the present invention, an insulating substrate, a plurality of pixel circuits arranged thereon, a plurality of scanning signal lines arranged along a row formed by the plurality of pixel circuits, and the plurality of pixel circuits A plurality of video signal lines arranged along a column formed by the plurality of power supply lines arranged along the row or column, and each of the plurality of pixel circuits includes a power supply terminal on the power supply line. A drive transistor connected between the first terminal; an output control transistor connected between the first terminal and the second terminal; and a pixel electrode connected to the second terminal; When viewed from a direction perpendicular to the main surface of the substrate, in each of the plurality of pixel circuits, the pixel electrode includes the plurality of scanning signal lines, the plurality of video signal lines, and the plurality of power supply lines. The output control transistor included in the pixel circuit. Array substrate is provided, wherein a gate of Njisuta are only overlapped connected the scanning signal lines.

  According to the present invention, electrostatic breakdown of the output control switch is less likely to occur.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.

  FIG. 1 is a plan view schematically showing a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically showing an example of a structure that can be employed in the display device of FIG. FIG. 3 is an equivalent circuit diagram of a pixel included in the display device of FIG. FIG. 4 is a plan view schematically showing an example of a structure that can be employed in a pixel included in the display device of FIG.

  In FIG. 2, the display device is drawn such that its display surface, that is, the front surface or the light emitting surface faces downward, and the back surface faces upward. FIG. 4 shows a pixel structure viewed from the display surface side.

  This display device is a bottom emission type organic EL display device adopting an active matrix driving method. This organic EL display device includes, for example, an insulating substrate SUB such as a glass substrate.

On the substrate SUB, as shown in FIG. 2, for example, a SiN _x layer and a SiO _x layer are sequentially stacked as the undercoat layer UC.

  On the undercoat layer UC, for example, a gate insulating film GI that can be formed using a semiconductor layer SC which is a polysilicon layer in which a channel and a source / drain are formed, for example, TEOS (TetraEthyl OrthoSilicate), etc., and MoW, for example, The gates G are sequentially stacked, and they constitute a top gate type thin film transistor. In this example, these thin film transistors are p-channel thin film transistors, and are used as the drive control element DR and the switches SW1 to SW3 included in the pixel PX in FIGS.

  On the gate insulating film GI, scanning signal lines SL1 and SL2 shown in FIGS. 1, 3, and 4 and an electrode E1 shown in FIG. 4 are further arranged. The scanning signal lines SL1 and SL2 and the electrode E1 can be formed in the same process as the gate G.

  As shown in FIG. 1, the scanning signal lines SL1 and SL2 each extend in the row direction (X direction) of the pixels PX, and are alternately arranged in the column direction (Y direction) of the pixels PX. These scanning signal lines SL1 and SL2 are connected to the scanning signal line driver YDR. A part of the scanning signal line SL1 is used as one electrode of a capacitor C2 described later.

  The electrode E1 is connected to the gate G of the drive control element DR. The electrode E1 is used as one electrode of the capacitor C1 described later.

The gate insulating film GI, the gate G, the scanning signal lines SL1 and SL2, and the electrode E1 are covered with an interlayer insulating film II shown in FIG. The interlayer insulating film II is made of, for example, SiO _x formed by a plasma CVD method or the like. A portion of the interlayer insulating film II on the electrode E1 is used as a dielectric layer of the capacitor C1.

  On the interlayer insulating film II, the source electrode SE and the drain electrode DE shown in FIGS. 2 and 4, the video signal line DL and the power supply line PSL shown in FIGS. 1, 3 and 4, and the electrode shown in FIG. E2 is arranged. These can be formed in the same process and have, for example, a three-layer structure of Mo / Al / Mo.

  The source electrode SE and drain electrode DE are electrically connected to the source and drain of the thin film transistor through contact holes provided in the interlayer insulating film II.

  As shown in FIG. 1, each video signal line DL extends in the Y direction and is arranged in the X direction. These video signal lines DL are connected to a video signal line driver XDR.

  In this example, as shown in FIG. 4, the power supply lines PSL each extend in the Y direction and are arranged in the X direction.

  The electrode E2 is connected to the power supply line PSL. The electrode E2 is used as the other electrode of the capacitor C1.

The source electrode SE, the drain electrode DE, the video signal line DL, the power supply line PSL, and the electrode E2 are covered with the passivation film PS shown in FIG. The passivation film PS is made of, for example, SiN _x . A part of the interlayer insulating film II and the passivation film PS is used as a dielectric layer of the capacitor C2.

  On the passivation film PS, as shown in FIG. 2, light-transmitting first electrodes PE are juxtaposed apart from each other as a front electrode. Each first electrode PE is a pixel electrode, and is connected to the drain electrode DE of the switch SW1 through a through hole provided in the passivation film PS as shown in FIGS.

  The first electrode PE is an anode in this example. As a material of the first electrode PE, for example, a transparent conductive oxide such as ITO (Indium Tin Oxide) can be used. A portion of the first electrode PE facing the scanning signal line SL1 is used as the other electrode of the capacitor C2.

  A partition insulating layer PI shown in FIG. 2 is further disposed on the passivation film PS. In the partition insulating layer PI, a through hole is provided at a position corresponding to the first electrode PE, or a slit is provided at a position corresponding to a column or row formed by the first electrode PE. Here, as an example, the partition insulating layer PI is provided with a through hole at a position corresponding to the first electrode PE.

  The partition insulating layer PI is, for example, an organic insulating layer. The partition insulating layer PI can be formed using, for example, a photolithography technique.

  On the first electrode PE, an organic layer ORG including a light emitting layer is disposed as an active layer. The light emitting layer is, for example, a thin film containing a luminescent organic compound whose emission color is red, green, or blue. The organic layer ORG can further include a hole injection layer, a hole transport layer, a hole blocking layer, an electron transport layer, an electron injection layer, and the like in addition to the light emitting layer.

  The partition insulating layer PI and the organic layer ORG are covered with a second electrode CE that is a back electrode. The second electrode CE is a counter electrode connected to each other between the pixels PX, that is, a common electrode, and is a light-reflective cathode in this example. For example, the second electrode CE is electrically connected to an electrode wiring (not shown) formed on the same layer as the video signal line DL through a contact hole provided in the passivation film PS and the partition insulating layer PI. It is connected to the. Each organic EL element OLED includes a first electrode PE, an organic layer ORG, and a second electrode CE.

  In this example, the pixel circuit constituting each pixel PX includes an organic EL element OLED, a drive control element (drive transistor) DR, and an output control switch (output) as shown in FIGS. It includes a control transistor SW1, a video signal supply control switch (video signal supply control transistor) SW2, a diode connection switch (diode connection transistor) SW3, and capacitors C1 and C2. As described above, in this example, the drive control element DR and the switches SW1 to SW3 are p-channel thin film transistors. In this example, the video signal supply control switch SW2 and the diode connection switch SW3 are connected to each other in the connection state between the drain of the drive control element DR, the video signal line DL, and the gate of the drive control element DR. The switch group which switches between a 1st state and the 2nd state from which they were interrupted | blocked from each other is comprised.

The drive control element DR, the output control switch SW1, and the organic EL element OLED are connected in series between the first power supply terminal _NDps1 and the second power supply terminal _NDps2 in this order. In this example, the first power supply terminal ND _ps 1 is a high potential power supply terminal, and the second power supply terminal ND _ps 2 is a low potential power supply terminal. Hereinafter, the first power supply terminal ND _ps 1 and a second power supply terminal ND _ps 2 and nodes ND1 and ND2 conductive paths connecting each is referred to as a first and a second terminal.

  The gate of the output control switch SW1 is connected to the scanning signal line SL1. The video signal supply control switch SW2 is connected between the video signal line DL and the first terminal ND1, and its gate is connected to the scanning signal line SL2. The diode connection switch SW3 is connected between the gate of the drive control element DR and the first terminal ND1, and the gate thereof is connected to the scanning signal line SL2.

The capacitor C1 is connected between the gate of the drive control element DR and the constant potential terminal ND _cp . The capacitor C2 is connected between the gate of the output control switch SW1 and the second terminal ND2.

  A structure obtained by removing the second electrode CE and the organic layer ORG from the organic EL display device corresponds to an array substrate.

  When an image is displayed on this organic EL display device, for example, each of the scanning signal lines SL1 and SL2 is line-sequentially driven. In a writing period in which a video signal is written to a certain pixel PX, first, a scanning signal for opening the switch SW1 is output as a voltage signal from the scanning signal line driver YDR to the scanning signal line SL1 to which the previous pixel PX is connected. Subsequently, a scanning signal for closing the switches SW2 and SW3 is output as a voltage signal to the scanning signal line SL2 to which the previous pixel PX is connected. In this state, the video signal line driver XDR outputs the video signal as a current signal to the video signal line DL to which the previous pixel PX is connected, and the gate-source voltage of the drive control element DR is converted to the previous video signal. Set to the corresponding size. Thereafter, a scanning signal for opening the switches SW2 and SW3 is output as a voltage signal from the scanning signal line driver YDR to the scanning signal line SL2 to which the previous pixel PX is connected, and then the scanning signal to which the previous pixel PX is connected. A scanning signal for closing the switch SW1 is output as a voltage signal to the line SL1.

  In the effective display period in which the switch SW1 is closed, a drive current having a magnitude corresponding to the gate-source voltage of the drive control element DR flows through the organic EL element OLED. The organic EL element OLED emits light with a luminance corresponding to the magnitude of the drive current.

As described above, in the prior art, the electrostatic breakdown of the output control switch SW1 is likely to occur between the formation of the first electrode PE and the completion of the organic EL element OLED. The pixel PX in which the electrostatic breakdown of the output control switch SW1 has occurred may be visually recognized as a bright spot.
The inventor examined this phenomenon in detail. As a result, we found the following facts.

  From the formation of the first electrode PE to the completion of the organic EL element OLED, the first electrode PE is not covered with the second electrode CE. Therefore, the first electrode PE forms a capacitor when, for example, a metal mask for vapor deposition is brought close to the array substrate, and causes a potential change at the drain of the output control switch SW1. As a result, in the array substrate according to the prior art, a large voltage is applied between the drain of the output control switch SW1 and the scanning signal line SL1, and they are easily short-circuited.

  In this embodiment, one electrode of the capacitor C2 is connected to the output control switch SW1. Therefore, the above-described potential change hardly occurs. Moreover, in this embodiment, the other electrode of the capacitor C2 is connected to the gate of the output control switch SW1. Therefore, even if the drain potential of the output control switch SW1 changes, the gate potential of the output control switch SW1 changes in the same manner. Therefore, according to this aspect, it is possible to prevent a large voltage from being applied between the drain of the output control switch SW1 and the scanning signal line SL1. That is, it is possible to make the output control switch less susceptible to electrostatic breakdown.

  The capacitance of the capacitor C2 is, for example, in the range of 0.01 pF to 0.1 pF. When the capacitance of the capacitor C2 is small, the above-described effect may not be sufficiently obtained. When the capacitance of the capacitor C2 is large, the scanning signal may become dull.

  The first electrode PE typically has a scanning signal line SL2, a video signal line DL, a power supply line PSL, a drive control element DR, and switches SW1 to SW3 when viewed from a direction perpendicular to the main surface of the insulating substrate SUB. And so as not to overlap with the capacitor C1. In addition, the first electrode PE is arranged so as to overlap only the scan signal line SL1 to which the pixel PX including the first electrode PE is connected. This can prevent signal delay and does not adversely affect the operation of the transistor.

  The capacitor C2 may be formed using the first electrode PE and the scanning signal line SL1 as shown in FIG. 4, or may be composed of other members. For example, the drain electrode DE connecting the output control switch SW1 and the first electrode PE is designed to face the scanning signal line SL1, and the drain electrode DE and the scanning signal line SL1 are used as an electrode pair of the capacitor C2. Also good.

  In this embodiment, the organic EL display device is a bottom emission type, but may be a top emission type. In this aspect, the circuit of FIG. 3 is adopted for the pixel PX, but another circuit may be adopted for the pixel PX. For example, the pixel PX may employ a circuit that uses a voltage signal as a video signal instead of a circuit that uses a current signal as a video signal.

1 is a plan view schematically showing a display device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view schematically illustrating an example of a structure that can be employed in the display device of FIG. 1. FIG. 2 is an equivalent circuit diagram of a pixel included in the display device of FIG. 1. FIG. 2 is a plan view schematically showing an example of a structure that can be employed in a pixel included in the display device of FIG. 1.

Explanation of symbols

C1 ... capacitor, C2 ... capacitor, CE ... second electrode, DE ... drain electrode, DL ... video signal line, DR ... drive control element, E1 ... electrode, E2 ... electrode, G ... gate, GI ... gate insulating film, II ... Interlayer insulating film, ND1 ... first terminal, ND2 ... second terminal, ND _cp ... constant potential terminal, ND _ps 1 ... first power supply terminal, ND _ps 2 ... second power supply terminal, OLED ... organic EL element, ORG ... Organic layer, PE ... first electrode, PI ... partition insulating layer, PS ... passivation film, PSL ... power supply line, PX ... pixel, SC ... semiconductor layer, SE ... source electrode, SL1 ... scan signal line, SL2 ... scan signal line , SUB ... insulating substrate, SW1 ... output control switch, SW2 ... video signal supply control switch, SW3 ... diode connection switch, UC ... undercoat layer, XDR ... video signal line driver, YDR ... running Signal line driver.

Claims (5)

Comprising an insulating substrate and a plurality of pixels arranged thereon, each of the plurality of pixels comprising:
A drive transistor connected between the first power supply terminal and the first terminal;
An output control transistor connected between the first terminal and the second terminal;
A display element connected between the second terminal and a second power supply terminal;
A display device comprising a capacitor connected between the gate of the output control transistor and the second terminal. Insulating substrate, a plurality of pixels arranged thereon, a plurality of scanning signal lines arranged along a row formed by the plurality of pixels, and a plurality of images arranged along a column formed by the plurality of pixels Comprising a signal line and a plurality of power lines;
Each of the plurality of pixels includes a drive transistor connected between a first power supply terminal and a first terminal on the power supply line, and an output control transistor connected between the first terminal and the second terminal. A display element including a pixel electrode connected to the second terminal, a counter electrode connected to the second power supply terminal, and an active layer interposed therebetween,
When viewed from a direction perpendicular to the main surface of the insulating substrate, in each of the plurality of pixels, the pixel electrode includes the plurality of scanning signal lines, the plurality of video signal lines, and the plurality of power supply lines. Among these, the display device is characterized in that it overlaps only with the scanning signal line to which the gate of the output control transistor included in the pixel is connected.   The display device according to claim 1, wherein the display element is an organic EL element. An insulating substrate and a plurality of pixel circuits arranged thereon, each of the plurality of pixel circuits,
A drive transistor connected between the power supply terminal and the first terminal;
An output control transistor connected between the first terminal and the second terminal;
A pixel electrode connected to the second terminal;
An array substrate comprising a capacitor connected between a gate of the output control transistor and the second terminal. An insulating substrate, a plurality of pixel circuits arranged on the insulating substrate, a plurality of scanning signal lines arranged along a row formed by the plurality of pixel circuits, and a column formed by the plurality of pixel circuits. A plurality of video signal lines, and a plurality of power supply lines arranged along the row or column,
Each of the plurality of pixel circuits includes a drive transistor connected between a power supply terminal on the power supply line and a first terminal, an output control transistor connected between the first terminal and the second terminal, A pixel electrode connected to the second terminal,
When viewed from a direction perpendicular to the main surface of the insulating substrate, in each of the plurality of pixel circuits, the pixel electrode includes the plurality of scanning signal lines, the plurality of video signal lines, and the plurality of power supply lines. An array substrate characterized by overlapping only the scanning signal line to which the gate of the output control transistor included in the pixel circuit is connected.

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