JP2006283151A - Semiconductor manufacturing method, and semiconductor manufacturing equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method and semiconductor manufacturing equipment capable of obtaining satisfactory plating filling properties at the inside of a groove formed in a semiconductor substrate. <P>SOLUTION: The method includes: a process where a semiconductor substrate provided with a groove pattern and an insulating film in which an electrode layer to be a first electrode is formed at least on the inside of the groove pattern is introduced into a plating liquid in which a second electrode is installed; and a process where an a.c. electric field with the frequency of ≥100 Hz is superimposed on a d.c. electric field, and the same is applied between the first and second electrodes so as to form a metallic film on the metal layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a plating technique used in, for example, a Cu wiring forming process in a semiconductor device.

  In recent years, an electrolytic plating process has been used as a technique for forming a Cu wiring used in a semiconductor device (see, for example, Patent Document 1). As shown in FIG. 11, a semiconductor substrate 103 to be processed on which a wiring layer and a Cu layer serving as an electrode are formed is introduced into a plating tank 101 supplied with a plating solution, and an anode (Cu material 102). -A Cu plating film can be formed on the surface of the semiconductor substrate and in the groove by applying a DC electric field by the power source 104 between the cathodes (Cu layer in the semiconductor substrate 103 to be processed).

  At this time, an additive such as an accelerator router, a suppressor, or a leveler is added to the plating solution to selectively embed a plating film inside the groove (Gap fill).

  However, with the miniaturization of semiconductor elements, there is a problem that it is difficult to ensure embeddability.

As a monitoring means for such process management, current-voltage measurement during plating is performed. However, as the area to be processed increases due to the increase in the diameter of the semiconductor substrate, the plating solution interface resistance decreases, and resistance components that do not contribute to the formation of the plating film, such as contact resistance and the electrical resistance of the plating solution filter, increase. There is a problem that it is difficult to obtain good monitor sensitivity.
JP 2000-173949 A

  An object of this invention is to provide the semiconductor manufacturing method and semiconductor manufacturing apparatus which can obtain the favorable plating embedding property inside the groove | channel formed in the semiconductor substrate.

  According to one aspect of the present invention, a plating solution in which a second electrode is disposed on a semiconductor substrate serving as a first electrode that includes a groove pattern and an insulating film in which a metal layer is formed at least inside the groove pattern. And a step of forming a metal film on the metal layer by applying an AC electric field with a frequency of 100 Hz or more superimposed on a DC electric field between the first and second electrodes. A semiconductor manufacturing method is provided.

    According to another aspect of the present invention, a plating tank to which a plating solution and an additive are supplied, a groove pattern, and a first electrode including an insulating film having a metal layer formed at least inside the groove pattern; An AC electric field having a frequency of 100 Hz or more is superimposed on a DC electric field between the means for introducing the semiconductor substrate into the plating tank, the second electrode installed in the plating tank, and the first and second electrodes. Thus, a semiconductor manufacturing apparatus is provided.

  According to one embodiment of the present invention, it is possible to obtain a good plating embedding property inside a groove formed in a semiconductor substrate.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a conceptual diagram of a semiconductor manufacturing apparatus according to this embodiment. As shown in the figure, a plating tank 1 to which a plating solution and an additive are supplied, an anode electrode (Cu material) 2 at the bottom, a semiconductor substrate 3 to be processed on which a cathode electrode is formed facing the anode electrode, an anode An AC electric field in which a DC electric field is superimposed between the cathodes or a power supply 4 for applying a DC electric field in which the AC electric field is superimposed is installed. Further, substrate introduction means 5 for introducing a semiconductor substrate to be processed from above the plating tank is installed.

  Using such a semiconductor manufacturing apparatus, the semiconductor substrate 3 to be processed is subjected to Cu plating. As shown in FIG. 2, an insulating film 3a is previously formed on the substrate to be processed 3 as shown in FIG. 2, and a groove pattern 3b is formed on the insulating film 3a by RIE (Reactive Ion Etching). On the surface including the inside of the trench, a Ta film 3c and a Cu layer 3d serving as a cathode electrode are sequentially formed by a sputtering method to a thickness of 10 nm and 60 nm, respectively.

First, an alternating current of 0.3 A, in which a direct current of 3 A is superimposed, is applied between the anode and the cathode by the power source 4. And in the state to which the electric current was applied, using the board | substrate introduction means 5, the to-be-processed semiconductor substrate 3 was introduce | transduced into the plating tank 1 to which the plating liquid was supplied with the angle of 45 degrees with respect to the plating liquid surface, for example. Thereafter, the Cu plating process is performed horizontally in the plating solution. Additives such as accelerator routers, suppressors, and levelers are added as appropriate. At this time, as shown in Table 1, the Cu plating film is formed by changing the frequency. As a comparative example, a Cu plating film is formed only by a direct current of 3 A as in the conventional case.

  The cross sections of these samples 1 to 3 are observed by SEM (Scanning Electron Microscope), the result of sample 1 is shown in FIG. 3, the result of sample 2 is shown in FIG. 4, and the result of sample 3 is shown in FIG. In the sample 3 having only a DC electric field shown in FIG. 5, the void 6 is formed in the Cu plating film 3e formed in the groove of the insulating film 3a, whereas the AC electric field shown in FIGS. In Samples 1 and 2, it can be seen that a good Cu plating film 3e is formed with good embedding. This is considered due to the frequency dependence of the plating film formation mechanism. That is, it is possible to form a good Cu plating film by applying not only a conventional DC electric field but also an AC electric field of 100 Hz or higher, which is the rate limiting of the plating film formation.

(Embodiment 2)
In the present embodiment, as in the first embodiment, using the semiconductor manufacturing apparatus shown in FIG. 1, as in the first embodiment, a groove pattern is formed by RIE. A Cu plating process is performed on the semiconductor substrate to be processed on which the film is 10 nm and the Cu film is 60 nm. At this time, as shown in Table 2, the cathode electrode is 45 ° with respect to the anode electrode, and the electrolysis conditions are changed to form a Cu plating film.

  The cross sections of these samples 4 to 6 are observed by SEM, the result of sample 4 is shown in FIG. 5, the result of sample 5 is shown in FIG. 6, and the result of sample 6 is shown in FIG. As shown in FIGS. 6 and 7, in the sample 5 on which the low frequency (125 Hz) AC electric field is superimposed and the sample 6 only with the DC electric field, the void 6 is formed in the Cu plating film 3e formed in the groove of the insulating film 3a. In contrast, in the sample 4 on which the high frequency (10 kHz) AC electric field shown in FIG. 5 is superimposed, the anode-cathode angle is 45 °, although the vertical component of the electric field with respect to the substrate is small. It can be seen that a good Cu plating film 3e is formed with good embedding.

  Dominance of the directionality of the electric field in plating film formation tends to be suppressed on the high frequency side, and even if the anode-cathode angle fluctuates by superimposing a high frequency AC electric field of about 10 kHz or more on the DC electric field, it is good. A Cu plating film can be formed. Accordingly, even when the anode-cathode angle fluctuates when introducing the semiconductor substrate to be processed into the plating solution, a good Cu plating film is formed by superimposing a high-frequency AC electric field on the DC electric field. Is possible.

  In these embodiments, an alternating current of 0.3 A on which a direct current of 3 A is superimposed is applied, but the current (voltage) can be appropriately set depending on the area of the semiconductor substrate to be processed. In order to obtain better embedding controllability, the alternating current (voltage) is preferably about 2 to 20% of the superimposed direct current (voltage). Further, the frequency does not necessarily have to be fixed, and may be varied.

(Embodiment 3)
FIG. 9 shows a conceptual diagram of the semiconductor manufacturing apparatus of the present embodiment. The configuration is almost the same as that of the semiconductor manufacturing apparatus shown in FIG. 1, except that a phase difference measuring means 17 for measuring a current-voltage phase difference is provided. That is, a plating tank 11 to which a plating solution and an additive are supplied, an anode electrode (Cu material) 12 at the bottom, a semiconductor substrate 13 to be treated as a cathode electrode facing the anode electrode 12, and a DC electric field between the anode and the cathode A power source 14 for applying an AC electric field superimposed with a DC electric field or a DC electric field superimposed with an AC electric field, a substrate introducing unit 15 for introducing a semiconductor substrate to be processed from above the plating tank, and a phase difference measuring unit 17 for measuring a current-voltage phase difference. It becomes the structure where is installed.

  Using such a semiconductor manufacturing apparatus, the semiconductor substrate to be processed is subjected to Cu plating as in the first embodiment. As in the first embodiment, a groove pattern is formed in advance on the semiconductor film 13 to be processed by RIE on an insulating film formed on the semiconductor substrate, and a Ta film is formed on the surface including the inside of the groove by a sputtering method to a thickness of 10 nm. Cu film is formed to 60 nm.

First, a 0.3 A alternating current obtained by superimposing a 3 A direct current is applied between the anode and the cathode by the power source 14, and the phase difference measuring means 17 measures the current-voltage phase difference. Then, similarly to the first embodiment, the substrate introduction means 15 is used to apply the current to the semiconductor substrate 13 to be processed with respect to the plating liquid surface in the plating tank 11 supplied with the plating liquid. After introducing at an angle of 45 °, Cu plating is performed horizontally in the plating solution. Table 3 and FIG. 10 show the results of measuring the current-voltage phase difference while changing the electrolysis conditions (plating solution, frequency).

  From Table 3 and FIG. 10, when a plating solution containing an additive is used as in Samples 8 and 9, since the Cu plating film is preferentially formed inside the groove, the surface area to be treated changes sharply. . Therefore, the capacity of the electric double layer at the interface with the plating solution changes greatly, and this is detected as a steep change in the phase difference at the initial stage of plating. On the other hand, when no additive is contained as in Sample 7, the surface area change is small, so the phase difference gradually increases and no steep change at the initial stage of plating is observed.

  Therefore, it is possible to monitor the formation state of the plating film (groove filling state) by measuring the phase difference at the initial stage of plating, and the content of the additive (the presence or absence of inclusion) that governs this. Knowledge can be obtained. Further, by controlling plating conditions such as additives and electric field conditions based on these findings, it is possible to form a better Cu plating film.

  In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

1 is a conceptual diagram of a semiconductor manufacturing apparatus in one embodiment of the present invention. 4A and 4B are cross-sectional views of a semiconductor substrate in one embodiment of the present invention. FIG. 6 illustrates a cross section of a sample formed in one embodiment of the present invention. FIG. 6 illustrates a cross section of a sample formed in one embodiment of the present invention. FIG. 6 illustrates a cross section of a sample formed in one embodiment of the present invention. FIG. 6 illustrates a cross section of a sample formed in one embodiment of the present invention. FIG. 6 illustrates a cross section of a sample formed in one embodiment of the present invention. FIG. 6 illustrates a cross section of a sample formed in one embodiment of the present invention. 1 is a conceptual diagram of a semiconductor manufacturing apparatus in one embodiment of the present invention. FIG. 6 shows voltage-current phase differences in one embodiment of the present invention. The conceptual diagram of the conventional semiconductor manufacturing apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 11, 101 Plating tank 2, 12, 102 Cu material 3, 13, 103 Processed semiconductor substrate 4, 14, 104 Power supply 5, 15 Substrate introduction means 6 Void 17 Phase difference measurement means

Claims (5)

Introducing a semiconductor substrate to be a first electrode having a groove pattern and an insulating film having at least a metal layer formed in the groove pattern into a plating solution in which a second electrode is installed;
A method of manufacturing a semiconductor, comprising: applying a DC electric field superimposed on a DC electric field between the first and second electrodes to form a metal film on the metal layer.   The semiconductor manufacturing method according to claim 1, further comprising a step of monitoring a voltage-current phase difference between the first and second electrodes.   The semiconductor manufacturing method according to claim 1, wherein an additive is supplied into the plating solution. A plating tank to which a plating solution and additives are supplied;
Means for introducing a semiconductor substrate to be a first electrode provided with a groove pattern and an insulating film having at least a metal layer formed inside the groove pattern into the plating tank;
A second electrode installed in the plating tank;
A semiconductor manufacturing apparatus comprising means for applying an AC electric field having a frequency of 100 Hz or more superimposed on a DC electric field between the first and second electrodes.   5. The semiconductor manufacturing apparatus according to claim 4, further comprising means for monitoring a voltage-current phase difference between the first and second electrodes.