JP2006253639A - Optical semiconductor element and package thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical semiconductor element package in which characteristic impedance of a lead is reduced and control range of the characteristic impedance of the lead can be expanded. <P>SOLUTION: The optical semiconductor package has a disk-like stem 1, rod-like metal leads 3 and 13 protruding from a principal surface while penetrating the stem 1 in a thickness direction, and a mount 5 so provided as to vertically extend from the principal surface of the stem 1. The flat surface 51 of the mount 5 is so arranged as to face the leads 3 and 13. A dielectric substrate 6 is mounted on the flat surface 51, and an optical semiconductor chip 9 is mounted thereon. Two impedance-adjusting dielectric substrates 7 are extended in parallel to the leads 3 and 13, have a rectangular shape in a plane view, and are so arranged as to cover the top of the flat surface 51 facing the leads 3 and 13. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an optical semiconductor element package and an optical semiconductor element that accommodate an optical semiconductor chip, and more particularly, to an optical semiconductor element package and an optical semiconductor element in which a characteristic impedance of a lead is reduced.

  In recent years, in optical communication, the transmission speed tends to increase, and the transmission speed may be 10 Gbps or more. Therefore, not only an optical semiconductor chip but also an optical semiconductor element package that accommodates it is required to be relatively inexpensive and excellent in high-frequency characteristics.

  For example, Patent Document 1 discloses a stem-type optical semiconductor element package having a coaxial shape and a simple structure as a configuration that satisfies such a requirement.

  The stem type is a disc-shaped substrate called a stem, a plurality of leads that penetrate the stem in the thickness direction and protrude from the main surface, and a mount provided so as to extend vertically from the main surface of the stem And a ground potential pedestal called, and an optical semiconductor chip is mounted on the mount.

  In a stem type optical semiconductor device package, an optical semiconductor chip is not mounted directly on a mount, but mounted on a substrate called a submount provided so as to be in direct contact with the mount. The optical semiconductor chip is electrically connected by a wire.

  Here, the lead is covered with glass at the stem penetrating portion, but the portion protruding from the main surface of the stem is not covered for wire connection, and the characteristic impedance of the lead is increased as it is, Reflection due to the mismatch of characteristic impedance increases, the reflection characteristics deteriorate, and the transmission speed decreases.

  Therefore, Patent Document 1 discloses a configuration in which, for example, in FIG. 4, a dielectric plate is disposed on the surface of the mount facing the lead to lower the characteristic impedance of the lead.

Japanese Patent Laying-Open No. 2004-311923 (FIG. 4)

As described above, in the conventional stem type optical semiconductor element package, the characteristic impedance of the lead is lowered by inserting the dielectric plate between the lead and the mount.
However, the characteristic impedance in this case is defined by the distance between the lead and the mount and the dielectric constant of the dielectric plate, but the distance is determined by the manufacturing accuracy and the dielectric constant is determined by the material of the dielectric plate. There is a problem that the degree of freedom of impedance control is small and the control range of impedance is limited.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an optical semiconductor device package and an optical semiconductor device capable of reducing the characteristic impedance of the lead and widening the control range of the characteristic impedance of the lead. The purpose is to provide.

  An optical semiconductor device package according to claim 1 of the present invention is an optical semiconductor device package that accommodates an optical semiconductor chip, and includes a plate-like stem, the stem penetrating in a thickness direction, and from a main surface of the stem. Rod-shaped first and second leads projecting in parallel at intervals and supplying a driving current to the optical semiconductor chip, and provided so as to extend perpendicularly from the main surface of the stem, And at least a portion of the mounting table on which the optical semiconductor chip is mounted, and a portion facing the first and second leads on the planar portion of the mounting table. The first and second leads are disposed with a gap therebetween, and include an impedance adjusting dielectric substrate in which at least one conductor layer and a dielectric layer are laminated, and the mounting table has a ground potential. It is constant capable constructed.

  According to the optical semiconductor device package of the first aspect of the present invention, the conductor layer and the dielectric layer are disposed so as to cover at least the portions facing the first and second leads on the planar portion of the mounting table. Are provided with an impedance adjusting dielectric substrate in which at least one layer is laminated, thereby obtaining a configuration in which the distance between the first and second leads and the mounting table is substantially shortened or a configuration equivalent thereto. This can reduce the characteristic impedance at the projecting portion of the first and second leads from the stem main surface. In addition, since the characteristic impedance can be changed by changing the structure of the impedance adjusting dielectric substrate, the degree of freedom in controlling the characteristic impedance is increased and the control range of the characteristic impedance can be expanded.

  According to the optical semiconductor device of the eleventh aspect of the present invention, the characteristic impedance of the first and second leads protruding from the stem main surface can be reduced, and the structure of the impedance adjusting dielectric substrate is changed. By doing so, the characteristic impedance can be changed, the degree of freedom of control of the characteristic impedance is increased, and the control range of the characteristic impedance can be expanded.

<A. Embodiment 1>
A first embodiment of an optical semiconductor element package according to the present invention will be described with reference to FIGS.

<A-1. Overall system configuration>
FIG. 1 is a perspective view showing an overall configuration of an optical semiconductor element package 100 according to the first embodiment.

  An optical semiconductor element package 100 shown in FIG. 1 is an optical semiconductor element package called a so-called stem type, and is a disc-shaped stem 1 and a rod-shaped metal that penetrates the stem 1 in the thickness direction and protrudes from a main surface. Leads 3 and 13 (first and second leads) made of metal and a mount 5 provided so that the flat surface portion 51 extends vertically from the main surface of the stem 1 are provided.

  The mount 5 is a mounting table for the optical semiconductor chip 9 and is made of a metal having excellent electrical conductivity and thermal conductivity. For example, the mount 5 has a semi-cylindrical shape and is arranged so that the flat portion 51 faces the leads 3 and 13. It is installed. A dielectric substrate 6 as a submount is mounted on the flat portion 51, and an optical semiconductor chip 9 is mounted thereon.

  The leads 3 and 13 protrude from the main surface of the stem 1 in parallel with a gap therebetween, and the dielectric substrate 6 is disposed between the leads 3 and the leads 13. Leads 3 and 13 are electrically connected to conductor patterns 8 and 11 provided on the main surface of dielectric substrate 6 by a plurality of wires 4 and 12, respectively. The dielectric substrate 6 is made of a dielectric material such as alumina, and electrically separated conductor patterns 8 and 11 are formed on the surface thereof.

  The optical semiconductor chip 9 is a laser element, for example, and is mounted on the conductor pattern 8, and one of its main electrodes (not shown) is electrically connected to the conductor pattern 11 via the wire 10. The other main electrode of the optical semiconductor chip 9 is provided at a position facing the conductor pattern 8 and is electrically connected by being fixed on the conductor pattern 8 by soldering or the like.

  The stem 1 is made of a metal having excellent electrical and thermal conductivity, and the leads 3 and 13 are covered with a dielectric material 2 such as glass in the stem 1. The leads 3 and 13 also protrude from the main surface (back surface) of the stem 1 on the side opposite to the side on which the mount 5 is provided.

  The leads 3 and 13 supply driving current to the optical semiconductor chip 9 and are arranged so as to maintain a predetermined distance from the flat portion 51 of the mount 5 so as not to contact the mount 5 connected to the ground potential. It is installed. Two impedance adjusting dielectric substrates 7 having a rectangular shape in plan view extending in parallel with the leads 3 and 13 are disposed so as to cover the flat portion 51 facing the leads 3 and 13. The configuration of the impedance adjustment dielectric substrate 7 will be described later.

  FIG. 2 shows a plan view of the optical semiconductor element package 100 as viewed from above the optical semiconductor chip 9.

  As shown in FIG. 2, the size of the impedance adjustment dielectric substrate 7 in plan view is larger than that of the leads 3 and 13, and the leads 3 and 13 are disposed so as not to protrude from the impedance adjustment dielectric substrate 7. Is desirable. That is, the impedance adjusting dielectric substrate 7 is desirably provided in contact with the stem 1.

  However, in practice, the impedance adjustment dielectric substrate 7 is disposed with a predetermined gap from the stem 1 as shown in FIG. This is to prevent generation of stress on the stem 1 by separating the impedance adjusting dielectric substrate 7 from the stem 1. This also has an effect of preventing the stem 1 and the impedance adjusting dielectric substrate 7 from being short-circuited when the impedance adjusting dielectric substrate 7 is fixed to the mount 5 with solder or the like.

  The gap is desirably 0.1 mm or more, and the allowable range is 0.15 mm or less, and is set to 0.12 mm in FIG. If the gap is such a degree, it can be considered that the impedance adjusting dielectric substrate 7 substantially covers at least a portion of the flat portion 51 of the mount 5 facing the lead 3 or the lead 13.

  FIG. 3 is a plan view of the optical semiconductor element package 100 viewed from the main surface (back surface) opposite to the side on which the mount 5 of the stem 1 is provided. 13 indicates that the ground lead 18 protrudes. The ground lead 18 penetrates the stem 1 in the thickness direction and is connected to the mount 5 to fix the mount 5 to the ground potential. In addition, the stem 1 can also be fixed to the ground potential.

<A-2. Configuration and Effect of Impedance-Adjusting Dielectric Substrate>
Next, with reference to FIG. 1, the configuration and operational effects of the impedance adjusting dielectric substrate 7 will be described with reference to FIG. 4, which is a cross-sectional view taken along line AA in FIG. 2.

  As shown in FIG. 4, the impedance adjustment dielectric substrate 7 includes a dielectric layer 15 (first dielectric layer) in contact with the flat portion 51 of the mount 5 and a conductor layer 16 disposed on the dielectric layer 15. A dielectric layer 17 (second dielectric layer) disposed on the conductor layer 16 and a dielectric layer 15 penetrating the dielectric layer 15 in the thickness direction, and electrically connecting the conductor layer 16 and the mount 5 to each other. And a plurality of via contacts 14 to be connected to each other.

  The thickness of the impedance adjustment dielectric substrate 7 is set so that the upper surface of the impedance adjustment dielectric substrate 7, that is, the surface facing the leads 3 and 13 of the dielectric layer 17 does not contact the leads 3 and 13. .

  The dielectric layer 15 is made of alumina (relative dielectric constant εr = 9.4), and a through hole is formed in a portion where the via contact 14 is formed before being ceramicized by sintering, and a metal material is filled therein. Thus, the via contact 14 can be simultaneously formed by heat treatment during the sintering of alumina. The conductor layer 16 can be obtained by forming a metal film such as gold on the surface of the dielectric layer 15 by vacuum deposition.

  The dielectric layer 17 is made of alumina (relative dielectric constant εr = 9.4), and a contact filler material (wax) is used for the dielectric layer 15 on which the conductor layer 16 is formed. It is bonded by brazing or using a conductive adhesive. In this way, the impedance adjustment dielectric substrate 7 can be manufactured.

  Here, consider transmitting a high-frequency signal (current) at a transmission rate of 10 Gbps or more. A signal is input from the lead 13 and transmitted to the lead 3 via the optical semiconductor chip 9. When the signal is a high frequency signal of 10 GHz, the characteristic impedance of each part is as follows.

First, the portion of the lead 13 covered with the dielectric material 2 has the same structure as that of the coaxial cable, and the characteristic impedance Z ₀ (unit Ω) of the coaxial cable is expressed by the following formula (1). .

  In the above formula (1), a is the outer diameter of the inner conductor of the coaxial cable, b is the inner diameter of the outer conductor, and εr is the relative dielectric constant between the inner conductor and the outer conductor.

  On the other hand, since the portion of the lead 13 that protrudes from the main surface of the stem 1 is not covered with the dielectric material 2, the characteristic impedance is higher than that of the portion covered with the dielectric material 2. The same applies to the lead 3. If the characteristic impedance varies greatly depending on the location, impedance mismatching occurs, and the reflection of the high frequency signal increases at the boundary between the portions having different characteristic impedances, resulting in a decrease in transmission efficiency.

  Therefore, by disposing the impedance adjusting dielectric substrate 7 between the leads 3 and 13 and the mount 5, the characteristic impedance at the protruding portion of the leads 3 and 13 can be reduced.

  That is, the characteristic impedance of the signal line of the high-frequency signal varies depending on various elements, but the interval between the ground potential portion and the signal line is one of the elements, and when the interval between the ground potential portion and the signal line becomes small, The characteristic impedance tends to decrease.

  In the impedance adjusting dielectric substrate 7, the conductor layer 16 is electrically connected to the mount 5 through the plurality of via contacts 14, and the conductor layer 16 becomes the ground potential, so that the mount 5 is substantially close to the leads 3 and 13. The distance between 3 and 13 and the mount 5 is substantially shortened, and the characteristic impedance at the protruding portion of the leads 3 and 13 can be reduced.

  Here, an example of the calculation result of the characteristic impedance at the protruding portions of the leads 3 and 13 when the impedance adjusting dielectric substrate 7 is disposed when the high frequency signal is 10 GHz is shown.

  The diameters of the leads 3 and 13 are 0.35 mm, the dielectric material 2 is glass (relative permittivity εr = 5.6), the outer diameter is 0.7 mm, and the center of the leads 3 and 13 to the flat portion 51 of the mount 5 The shortest distance is 0.4 mm, and this will be based on this unless otherwise specified. The thickness of the dielectric layer 15 in the impedance adjusting dielectric substrate 7 is 0.139 mm, the thickness of the dielectric layer 17 is 0.060 mm, the thickness of the conductor layer 16 is 0.001 mm, and the diameter of the via contact 14 is 0.3 mm. When the height is 0.139 mm, the characteristic impedance at the protruding portions of the leads 3 and 13 is about 47Ω. This value is not obtained using mathematical formulas, but is obtained analytically by computer simulation.

  Of the leads 3 and 13, the characteristic impedance of the portion covered with the dielectric material 2, that is, the stem penetrating portion, is about 17Ω from Equation (1).

  Here, for comparison, in place of the impedance adjustment dielectric substrate 7, the lead 3 in the case where a dielectric plate (relative permittivity εr = 9.4) having the same thickness as the impedance adjustment dielectric substrate 7 is disposed and The characteristic impedance at the 13 protruding portion is about 61Ω when the high frequency signal is 10 GHz, and it can be seen that the characteristic impedance can be reduced by using the impedance adjusting dielectric substrate 7.

  The above-described characteristic impedance values of the leads 3 and 13 when using the impedance adjusting dielectric substrate 7 are values when the thicknesses of the respective layers are the above values, and the thicknesses and materials of the respective layers are changed, The characteristic impedance value can be changed by various combinations.

  In addition, the characteristic impedance of the leads 3 and 13 can be changed by changing the structure of the impedance adjusting dielectric substrate 7, and the characteristic impedance can be further reduced depending on the structure.

  This is because the characteristic impedance of the leads 3 and 13 is simply changed by replacing the impedance adjusting dielectric substrate 7 when the output impedance of the driver circuit changes with the change of the type of the driver circuit that drives the optical semiconductor chip 9. The characteristic impedance can be changed to a value close to the output impedance of the driver circuit to facilitate impedance matching. For this reason, even if the type of the driver circuit is changed, the design of the stem 1 is not changed, which is advantageous in terms of cost.

  Further, since the impedance adjustment dielectric substrate 7 is disposed only in the region facing the leads 3 and 13 on the flat portion 51 of the mount 5, basically, the external dimensions of the impedance adjustment dielectric substrate to be replaced are changed. If there is no change, there is no need to change the process (man-hours) in the assembly operation, which is advantageous in terms of cost, and the manufacturing accuracy can be easily maintained without change. Therefore, it is desirable to positively unify the external dimensions of the impedance adjustment dielectric substrate.

  Hereinafter, various modifications of the impedance adjustment dielectric substrate 7 will be described.

<A-3. Modification 1 of Impedance-Adjusting Dielectric Substrate>
In the optical semiconductor device package 100 described above, as shown in FIG. 4, the impedance adjusting dielectric substrate 7 having a three-layer structure in which the dielectric layer 15, the conductor layer 16, and the dielectric layer 17 are laminated is used. Although the characteristic impedance at the protruding portions of the leads 3 and 13 is reduced, the dielectric layer 17 may not be provided on the conductor layer 16.

  Also in this case, the characteristic impedance at the protruding portions of the leads 3 and 13 can be reduced.

  The optical semiconductor element package 100A shown in FIG. 5 is configured to reduce the characteristic impedance at the protruding portions of the leads 3 and 13 using the impedance adjusting dielectric substrate 7A.

  That is, the impedance adjusting dielectric substrate 7A includes a dielectric layer 15A (relative permittivity εr = 9.4) in contact with the flat portion 51 of the mount 5, a conductor layer 16 disposed on the dielectric layer 15A, a dielectric layer A plurality of via contacts 14 are provided so as to penetrate the body layer 15 </ b> A in the thickness direction and electrically connect the conductor layer 16 and the mount 5. In addition, the same code | symbol is attached | subjected about the structure same as the impedance adjustment dielectric substrate 7 shown in FIG. 4, and the overlapping description is abbreviate | omitted.

  Here, the thickness of the dielectric layer 15A is 0.199 mm, and by making it thicker than the dielectric layer 15 by the thickness of the dielectric layer 17, the entire thickness becomes the same as that of the impedance adjustment dielectric substrate 7. Is set to The thickness of the conductor layer 16 is 0.001 mm.

  In this case, the characteristic impedance at the protruding portions of the leads 3 and 13 is about 36Ω when the high-frequency signal is 10 GHz. This value is a value obtained by computer simulation.

  Since the conductor layer 16 is the uppermost layer in the impedance adjusting dielectric substrate 7A, it is needless to say that the overall thickness is set so as not to contact the leads 3 and 13, but when the thickness of the dielectric layer 15A is reduced, the characteristics Since the impedance reduction capability is lowered, when the characteristic impedance at the protruding portions of the leads 3 and 13 is desired to be as low as possible, the thickness of the dielectric layer 15A is made as large as possible and is not in contact with the leads 3 and 13. The entire thickness is set to.

<A-4. Modification Example 2 of Impedance-Adjusting Dielectric Substrate>
In the impedance adjustment dielectric substrates 7 and 7A described in the first embodiment and the first modification, the conductor layer 16 and the mount 5 are electrically connected by the plurality of via contacts 14. Alternatively, the configuration shown in FIG. 6 may be used.

  An optical semiconductor element package 100B shown in FIG. 6 has an impedance adjusting dielectric substrate 7B disposed on a flat portion 51 facing the leads 3 and 13, and the impedance adjusting dielectric substrate 7B is a flat portion of the mount 5. And a dielectric layer 17 disposed on the conductor layer 19. In addition, the same code | symbol is attached | subjected about the structure same as the impedance adjustment dielectric substrate 7 shown in FIG. 4, and the overlapping description is abbreviate | omitted.

  Here, the conductor layer 19 is made of, for example, metal and has a thickness of 0.140 mm. The dielectric layer 17 has a thickness of 0.060 mm, and the characteristic impedance at the protruding portions of the leads 3 and 13 is about 47Ω when the high-frequency signal is 10 GHz. This value is a value obtained by computer simulation.

  As described above, although the impedance adjustment dielectric substrate 7B has a simple configuration including only the conductor layer 19 and the dielectric layer 17, the effect of reducing the characteristic impedance at the protruding portions of the leads 3 and 13 is the impedance adjustment dielectric. It has an effect comparable to the body substrates 7 and 7A.

  In the impedance adjustment dielectric substrates 7 and 7A described in the first embodiment and the modification 1, the conductor layer 16 and the mount 5 are electrically connected. In the impedance adjustment dielectric substrate 7B described in the modification 2, By adopting a configuration in which the conductor layer 19 is in direct contact with the mount 5, the mount 5 is substantially brought close to the leads 3 and 13, and the effect of reducing the characteristic impedance at the protruding portion is obtained.

<A-5. Modified Example 3 of Impedance-Adjusting Dielectric Substrate>
An optical semiconductor element package 100C shown in FIG. 7 has an impedance adjustment dielectric substrate 7C disposed on a flat portion 51 facing the leads 3 and 13, and the impedance adjustment dielectric substrate 7C is a flat portion of the mount 5. 51, a dielectric layer 24 (first dielectric layer) in contact with 51, a conductor layer 22 (first conductor layer) disposed on the dielectric layer 24, and a dielectric disposed on the conductor layer 22 A layer 21 (second dielectric layer), a conductor layer 25 (second conductor layer) disposed on the dielectric layer 21, and a dielectric layer 26 (third layer) disposed on the conductor layer 25. And a plurality of via contacts 27 that are provided so as to penetrate the dielectric layer 21 in the thickness direction and electrically connect the conductor layer 25 and the conductor layer 22.

  The thickness of the impedance adjustment dielectric substrate 7C is set so that the upper surface of the impedance adjustment dielectric substrate 7C, that is, the surface facing the leads 3 and 13 of the dielectric layer 26 does not contact the leads 3 and 13. .

  The dielectric layers 21, 24, and 26 are all made of alumina (relative permittivity εr = 9.4), and in forming the dielectric layer 21, the via contact 27 is formed before being ceramicized by sintering. By forming a through hole in the portion and filling a metal material therein, the via contact 27 can be simultaneously formed by heat treatment during the sintering of alumina.

  The impedance adjusting dielectric substrate 7 </ b> C configured as described above functions as two capacitors connected in series provided between the leads 3 and 13 and the mount 5.

  FIG. 8 shows an equivalent circuit when the impedance adjusting dielectric substrate 7C is provided.

  As shown in FIG. 8, a capacitor C1 is formed between the lead 13 (same as the lead 3) and the conductor layer 25, a capacitor C2 is formed between the conductor layer 22 and the mount 5, and the capacitors C1 and C2 are The via contacts 27 are connected in series.

  When such a configuration is employed, a configuration equivalent to a configuration in which the distance between the lead 13 and the mount 5 is substantially shortened can be obtained by setting the capacitances of the capacitors C1 and C2 large, and the characteristic impedance is reduced. be able to.

  That is, the charge capacity C (unit F) of the parallel plate capacitor can be obtained by the following formula (2).

In the above equation (2), S is the electrode area, d is the distance between the electrodes, ε ₀ is the vacuum dielectric constant, and εr is the relative dielectric constant between the electrodes.

  As shown in Equation (2), by reducing the inter-electrode distance d, that is, the thickness of the dielectric, the charge capacity C of the capacitor is increased, and the characteristic impedance can be reduced.

  When the impedance adjusting dielectric substrate 7C is used, the capacitors C1 and C2 are connected in series, and the total charge capacity is halved compared to either one, but the dielectric layers 24 and 26 are made thinner. The thickness of the dielectric layers 24 and 26 is set so that the increase in capacitance due to exceeds the decrease in capacitance due to series connection.

  Specifically, the dielectric layers 24 and 26 have a thickness of 0.070 mm, the dielectric layer 21 has a thickness of 0.058 mm, the conductor layers 22 and 25 have a thickness of 0.001 mm, and the via contact 27 has a diameter of 0.1 mm. 3 mm, height is 0.058 mm, dielectric layers 21, 24 and 26 are made of alumina (relative permittivity εr = 9.4), and via contact 27 and conductor layers 22 and 25 are made of metal, The characteristic impedance at the protruding portions of the leads 3 and 13 is about 46Ω when the high-frequency signal is 10 GHz. This value is not obtained using mathematical formulas, but is obtained analytically by computer simulation.

  If the thickness of the dielectric layers 24 and 26 is further reduced to further increase the charge capacity, the characteristic impedance at the protruding portions of the leads 3 and 13 can be further reduced.

  For example, when the dielectric layers 24 and 26 have a thickness of 0.018 mm, the dielectric layer 21 has a thickness of 0.162 mm, and the conductor layers 22 and 25 have a thickness of 0.001 mm, the protruding portions of the leads 3 and 13 The characteristic impedance at is about 39Ω when the high-frequency signal is 10 GHz.

  Thus, by changing the thicknesses of the dielectric layers 24 and 26, the characteristic impedance at the protruding portions of the leads 3 and 13 can be changed, so that the characteristic impedance is output from the driver circuit of the optical semiconductor chip 9. It can be said that the configuration is suitable for impedance matching by changing to a value close to the impedance.

  The change range of the characteristic impedance value in the present invention is a combination of the conductor layer and the thickness of the dielectric layer constituting the impedance-adjusting dielectric substrate, and a usable dielectric material, that is, a manufacturing technique. It can be said that it is determined by factors based on.

  In addition, since there is no conductor in direct contact with the mount 5 in the impedance adjustment dielectric substrate 7C, it is possible to use a non-conductive adhesive when fixing the impedance adjustment dielectric substrate 7C on the mount 5. Thus, the selection range of the mounting method of the impedance adjustment dielectric substrate 7C is expanded, and flexible mounting becomes possible.

<A-6. Modification 4 of Impedance-Adjusting Dielectric Substrate>
As a configuration having the same effect as the impedance adjusting dielectric substrate 7C described above, a configuration as shown in FIG. 9 may be adopted.

  An optical semiconductor element package 100D shown in FIG. 9 has an impedance adjustment dielectric substrate 7D disposed on a flat portion 51 facing the leads 3 and 13, and the impedance adjustment dielectric substrate 7D is a flat portion of the mount 5. 51, a dielectric layer 24 in contact with the first dielectric layer (first dielectric layer), a conductor layer 28 disposed on the dielectric layer 24, and a dielectric layer 26 disposed on the conductor layer 28 (second dielectric layer). Body layer).

  In addition, the same code | symbol is attached | subjected about the structure same as the impedance adjustment dielectric substrate 7C shown in FIG. 7, and the overlapping description is abbreviate | omitted.

  In the impedance adjusting dielectric substrate 7D, a capacitor corresponding to the capacitor C1 (FIG. 8) is formed between the lead 13 (same as the lead 3) and the conductor layer 28, and a capacitor corresponding to the capacitor C2 (FIG. 8) is formed. It is formed between the conductor layer 28 and the mount 5.

  When such a configuration is adopted, the distance between the lead 13 (same as the lead 3) and the mount 5 is substantially shortened by setting the capacitance of the capacitor corresponding to the capacitors C1 and C2 large. An equivalent configuration is obtained, and the effect of reducing the characteristic impedance is obtained.

  When the impedance adjusting dielectric substrate 7D is used, two capacitors are connected in series, and the total charge capacity is halved compared to either one, but by making the dielectric layers 24 and 26 thinner. The thickness of the dielectric layers 24 and 26 is set so that the increase in capacitance exceeds the decrease in capacitance due to series connection.

  As a specific example, when the dielectric layers 24 and 26 have a thickness of 0.070 mm, the conductor layer 28 has a thickness of 0.060 mm, and the conductor layer 28 is made of metal, the characteristic impedance at the protruding portions of the leads 3 and 13 Is about 46Ω when the high-frequency signal is 10 GHz. This value is not obtained using mathematical formulas, but is obtained analytically by computer simulation.

  If the thickness of the dielectric layers 24 and 26 is further reduced to further increase the charge capacity, the characteristic impedance at the protruding portions of the leads 3 and 13 can be further reduced.

  For example, when the dielectric layers 24 and 26 have a thickness of 0.018 mm and the conductor layer 28 has a thickness of 0.164 mm, the characteristic impedance at the protruding portions of the leads 3 and 13 is 10 GHz when the high frequency signal is 10 GHz. About 39Ω.

  As described above, the impedance adjustment dielectric substrate 7D can not only reduce the characteristic impedance in the same manner as the impedance adjustment dielectric substrate 7C, but also has a simpler configuration than the impedance adjustment dielectric substrate 7C, which is advantageous in terms of cost. It can also be said that.

<B. Second Embodiment>
In the optical semiconductor element package 100 described in the first embodiment according to the present invention, as shown in FIG. 2, it extends in parallel with the leads 3 and 13 on the flat portion 51 of the mount 5 facing the leads 3 and 13. As shown, each of the impedance adjustment dielectric substrates 7 having a rectangular shape in plan view is disposed. The impedance adjustment dielectric substrates 7A to 7D in the first to fourth modifications also extend in parallel to the leads 3 and 13. Although described as existing, the shape of the impedance adjustment dielectric substrate in plan view is not limited to this.

<B-1. Overall system configuration>
Hereinafter, as a second embodiment of the present invention, the configuration of the optical semiconductor element package 200 will be described with reference to FIGS. 10 and 11. In addition, the same code | symbol is attached | subjected about the structure same as the optical semiconductor element package 100 shown in FIG. 1, and the overlapping description is abbreviate | omitted.

  In the optical semiconductor device package 200 shown in FIG. 10, the impedance adjustment having the functions of the dielectric substrate 6 and the impedance adjustment dielectric substrate 7 of the first embodiment so as to cover almost the entire flat surface 51 of the mount 5. A dielectric substrate 70 is mounted, and an optical semiconductor chip 9 is mounted thereon.

  Leads 3 and 13 are electrically connected to conductor patterns 8 and 11 provided on the main surface of impedance adjusting dielectric substrate 70 by a plurality of wires 4 and 12, respectively.

  FIG. 11 is a plan view of the optical semiconductor element package 200 as viewed from above the optical semiconductor chip 9.

  As shown in FIG. 11, the plan view shape of the impedance adjustment dielectric substrate 70 is the same as the plan view shape of the plane portion 51 of the mount 5, and the size of the impedance adjustment dielectric substrate 70 in plan view is The flat portion 51 of the mount 5 covers at least two regions facing the leads 3 and 13 and an arrangement region of the optical semiconductor chip 9 sandwiched between the two regions, and the leads 3 and 13 are impedance adjustment dielectrics. The size is set so as not to protrude from the body substrate 70.

<B-2. Configuration and Effect of Impedance-Adjusting Dielectric Substrate>
Here, the cross-sectional configuration of the impedance adjustment dielectric substrate 70 taken along the line BB in FIG. 11 is, for example, the impedance adjustment dielectric substrate 7 described with reference to FIG. 4 and FIGS. 5 to 7 and FIG. It is possible to use the same cross-sectional configuration as any of the impedance adjustment dielectric substrates 7A to 7D described above.

  That is, in adopting the configuration of the impedance adjusting dielectric substrates 7 and 7B, the dielectric layer 17 is provided as the uppermost layer. Therefore, the electrically isolated conductor patterns 8 and 11 are simply formed on the dielectric layer 17. Similarly, in the case of adopting the configuration of the impedance adjusting dielectric substrates 7C and 7D, the dielectric layer 26 is provided in the uppermost layer, so that the conductor patterns 8 and 11 are provided on the dielectric layer 26. become.

  In addition, the configuration of the impedance adjusting dielectric substrate 7A is realized by forming the conductor patterns 8 and 11 so as to be electrically separated from the conductor layer 16 on the dielectric layer 15A, for example. Is possible.

  The basic effect that the characteristic impedance at the protruding portions of the leads 3 and 13 can be changed by providing the impedance adjusting dielectric substrate 70 is the same as that of the first embodiment and the first to fourth modifications thereof. Depending on which of the cross-sectional configurations of the impedance adjustment dielectric substrate 7 and 7A to 7D is adopted, the respective specific effects can be obtained.

  Further, as a special effect compared with the impedance adjustment dielectric substrates 7 and 7A to 7D, there is an effect that the number of parts can be reduced.

  That is, when using the impedance adjustment dielectric substrates 7 and 7A to 7D, two of the impedance adjustment dielectric substrates 7 and 7A to 7D are prepared, and the optical semiconductor chip 9 is mounted on the mount 5 One dielectric substrate 6 is required. However, when the impedance adjustment dielectric substrate 70 is used, since only one impedance adjustment dielectric substrate 70 is prepared, the number of components is small, and the optical semiconductor element package 200 is provided. Easy to assemble.

  In the first and second embodiments according to the present invention described above, an optical semiconductor element package on which an optical semiconductor chip is mainly mounted has been described. The optical semiconductor element package further protects and seals the optical semiconductor chip. The optical semiconductor device is completed by fixing the cap and the stem to each other. In addition, it goes without saying that the cap has a light transmission window (including a lens) made of glass or the like, and other configurations of the cap are well known to those skilled in the art. Omitted.

  In the above description, the use of the laser element as the optical semiconductor chip 9 is limited. However, the present invention is not limited to this, and the configuration having the photodiode as the optical semiconductor chip 9, the laser element, and the photodiode. Needless to say, the present invention can be applied to the configuration having the above.

  Further, the present invention is effective for a configuration in which the transmission line (lead) and the grounding portion face each other and the transmission line is not covered with a dielectric.

  In the description of each embodiment, the thickness of the impedance adjustment dielectric substrate is set so as not to contact the lead, but the uppermost layer is not a conductor layer (impedance adjustment dielectric substrates 7 and 7B to 7D). ), The impedance adjustment dielectric substrate and the lead may be in contact with each other by making the thickness of the impedance adjustment dielectric substrate the same as the distance between the lead and the mount.

It is a perspective view explaining the structure of Embodiment 1 of the optical semiconductor element package which concerns on this invention. It is a top view explaining the structure of Embodiment 1 of the optical semiconductor element package which concerns on this invention. It is a top view explaining the structure which looked at the optical semiconductor element package concerning this invention from the back surface of the stem. It is sectional drawing explaining the structure of Embodiment 1 of the optical semiconductor element package which concerns on this invention. It is sectional drawing explaining the structure of the modification 1 of Embodiment 1 of the optical semiconductor element package which concerns on this invention. It is sectional drawing explaining the structure of the modification 2 of Embodiment 1 of the optical semiconductor element package which concerns on this invention. It is sectional drawing explaining the structure of the modification 3 of Embodiment 1 of the optical semiconductor element package which concerns on this invention. It is a figure explaining the equivalent circuit of the capacitor connected in series between the lead and the mount. It is sectional drawing explaining the structure of the modification 4 of Embodiment 1 of the optical semiconductor element package which concerns on this invention. It is a perspective view explaining the structure of Embodiment 2 of the optical semiconductor element package which concerns on this invention. It is a top view explaining the structure of Embodiment 2 of the optical semiconductor element package which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Stem, 3,13 Lead, 5 Mount, 6 Dielectric substrate, 7, 7A-7D, 70 Impedance adjustment dielectric substrate, 9 Optical semiconductor chip.

Claims (11)

An optical semiconductor element package for accommodating an optical semiconductor chip,
A plate-shaped stem;
Rod-shaped first and second leads that penetrate the stem in the thickness direction, protrude in parallel from the main surface of the stem at a distance, and supply a driving current to the optical semiconductor chip;
A mounting table provided so as to extend perpendicularly from the main surface of the stem, having a flat surface facing the first and second leads, and mounting the optical semiconductor chip;
Covering at least portions of the mounting table facing the first and second leads on the plane portion, the first and second leads being spaced apart from each other, and a conductor layer and a dielectric layer being provided An impedance adjustment dielectric substrate laminated at least one layer;
The mounting table is an optical semiconductor device package configured to be fixable to a ground potential.   The optical semiconductor device package according to claim 1, wherein the conductor layer of the impedance adjusting dielectric substrate is electrically connected to the mounting table. The dielectric layer of the impedance adjustment dielectric substrate is
A first dielectric layer disposed under the conductor layer;
A second dielectric layer disposed on top of the conductor layer,
The optical semiconductor element package according to claim 2, wherein the conductor layer is electrically connected to the mounting table by a via contact provided so as to penetrate the first dielectric layer in the thickness direction. The dielectric layer of the impedance adjustment dielectric substrate is disposed under the conductor layer,
The optical semiconductor element package according to claim 2, wherein the conductor layer is electrically connected to the mounting table by a via contact provided so as to penetrate the dielectric layer in a thickness direction. The dielectric layer of the impedance adjusting dielectric substrate is disposed on the conductor layer;
The optical semiconductor element package according to claim 2, wherein the conductor layer is disposed so as to be in contact with the planar portion of the mounting table.   The impedance adjusting dielectric substrate has a configuration in which two capacitors connected in series are formed between the first and second leads and the mounting table, respectively, using the dielectric layer as a dielectric material. Item 5. The optical semiconductor device package according to Item 1. The dielectric layer of the impedance adjustment dielectric substrate includes first to third dielectric layers,
The conductor layer includes first and second conductor layers;
The first dielectric layer is disposed so as to contact the flat portion of the mounting table,
The first conductor layer, the second dielectric layer, the second conductor layer, and the third dielectric layer are sequentially stacked on the first dielectric layer,
The optical semiconductor device package according to claim 6, wherein the first and second conductor layers are electrically connected to each other by a via contact provided so as to penetrate the second dielectric layer in the thickness direction. The dielectric layer of the impedance adjustment dielectric substrate is
A first dielectric layer disposed under the conductor layer;
A second dielectric layer disposed on top of the conductor layer,
The optical semiconductor device package according to claim 6, wherein the first dielectric layer is disposed so as to be in contact with the planar portion of the mounting table. The impedance adjusting dielectric substrate is
2. The first and second leads, respectively, on the flat surface portion of the mounting table facing the first and second leads so as to extend in parallel with the first and second leads, respectively. Optical semiconductor device package. The impedance adjusting dielectric substrate is
Arranged to cover two regions facing the first and second leads on the planar portion of the mounting table and a mounting region of the optical semiconductor chip sandwiched between the two regions, The optical semiconductor device package according to claim 1, wherein the optical semiconductor chip is disposed on the impedance adjusting dielectric substrate. An optical semiconductor element package according to any one of claims 1 to 10,
An optical semiconductor device comprising: a cap provided to seal the optical semiconductor chip housed in the optical semiconductor device package.

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