JP2006135397A - Data transfer controller and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer controller and electronic equipment by which power-saving of a physical layer circuit can be realized. <P>SOLUTION: The data transfer controller includes a transaction controller 84 which executes transaction processing and instructs the transmission of a packet constituting a transaction, and a packet generation circuit 86 for generating the packet whose transmission is instructed by the transaction controller 84, and outputting transmission data for allowing a transmission circuit 40 to transmit the generated packet. The transaction controller 84 makes the enable control signal of a current source 42 used by the transmission circuit 40 for packet transmission active at timing before the transmission start timing of starting the packet transmission by the transmission circuit 40. The transaction controller 84 recognizes a type of transaction executed by a bus on the basis of the analysis results obtained with a packet analysis circuit 82, and controls the enable control signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer control device and an electronic device.

  In recent years, high-speed serial interfaces such as USB 2.0 are in the spotlight. In USB 2.0, in addition to the FS (Full Speed) mode defined in the conventional USB 1.1, a transfer mode called HS (High Speed) mode is defined. Since data transfer is performed at 480 Mbps in the HS mode, data transfer can be performed at a much higher speed than the FS mode in which data transfer is performed at 12 Mbps.

  However, in this HS mode, the transmission circuit (HS transmission driver) drives the differential signal lines (DP, DM) using a current source, so that the power consumption is larger than that in the FS mode. For this reason, it has been difficult to incorporate a USB 2.0 data transfer control device into a mobile phone or the like that requires low power consumption.

As described above, in a high-speed serial interface such as USB 2.0, how to reduce the power consumption of a physical layer circuit such as a transmission circuit is a technical problem.
JP 2002-141911 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a data transfer control device and an electronic device that can realize power saving of a physical layer circuit. .

  The present invention is a data transfer control device for data transfer via a bus, which performs transaction processing and instructs transmission of a packet constituting a transaction, and transmits a packet instructed to be transmitted by the transaction controller. And a packet generation circuit that outputs transmission data for causing the transmission circuit to transmit the generated packet, and the transaction controller transmits an enable control signal for a current source used by the transmission circuit for packet transmission. The present invention relates to a data transfer control device that is activated at a timing before a transmission start timing at which a circuit starts packet transmission.

  According to the present invention, the enable control signal of the current source used for packet transmission is activated at a timing before the packet transmission start timing by the transmission circuit. Therefore, since the current of the current source can be enabled only when necessary, power saving can be achieved.

  Further, according to the present invention, the current source enable control is performed by the transaction controller of the transaction layer that can perform the transaction determination process. Therefore, it is possible to realize intelligent enable control according to the transaction type and the like.

  In the present invention, the enable controller signal may be activated at a timing between the timing when the transaction controller recognizes the type of transaction being performed on the bus and the transmission start timing.

  In this way, intelligent power saving control can be realized by performing enable control with a transaction controller that can recognize the type of transaction being performed on the bus.

  The present invention also includes a packet analysis circuit for analyzing a packet received via the bus, and the transaction controller recognizes the type of transaction being performed on the bus based on an analysis result in the packet analysis circuit. You may do it.

  In the present invention, when the bus is USB and the transaction controller is an IN transaction, the enable control is performed at a timing between an IN token packet reception completion timing and a data packet transmission start timing. The signal may be activated.

  Also, in the present invention, when the bus is USB and the transaction controller is an OUT transaction, the enable control signal is sent at a timing between a data packet reception completion timing and a handshake packet transmission start timing. May be activated.

  The present invention is also a data transfer control device for data transfer via USB, a packet analysis circuit for analyzing a packet received via USB, and a USB analysis based on the analysis result of the packet analysis circuit. The transaction controller that recognizes the type of transaction that is being performed in the transaction, sends a packet that is sent by the transaction controller, and sends a packet that is sent by the transaction controller. A packet generation circuit for outputting transmission data to be transmitted to the circuit, and when the transaction controller is an IN transaction, the transaction controller outputs an enable control signal of a current source used for packet transmission by the transmission circuit, IN token Relating to the data transfer control device to activate at a timing between the transmission start timing of the reception completion timing and the data packets of packets.

  According to the present invention, in the case of an IN transaction, the enable control signal becomes active at a timing between the reception completion timing of the IN token packet and the transmission start timing of the data packet. Therefore, since the enable control signal becomes active after it is determined that the transaction is an IN transaction, efficient power saving control can be realized.

  The present invention is also a data transfer control device for data transfer via USB, a packet analysis circuit for analyzing a packet received via USB, and a USB analysis based on the analysis result of the packet analysis circuit. The transaction controller that recognizes the type of transaction that is being performed in the transaction, sends a packet that is sent by the transaction controller, and sends a packet that is sent by the transaction controller. A packet generation circuit for outputting transmission data to be transmitted to the circuit, and when the transaction controller is an OUT transaction, the transaction controller outputs an enable control signal of a current source used for packet transmission by the transmission circuit, Data packet Relating to the data transfer control device to activate at a timing between the transmission start timing of the reception completion timing and handshake packet bets.

  According to the present invention, in the case of an OUT transaction, the enable control signal becomes active at a timing between the reception completion timing of the data packet and the transmission start timing of the handshake packet. Therefore, after it is determined that the transaction is an OUT transaction and a handshake packet must be returned, the enable control signal becomes active, so that efficient power saving control can be realized.

  Further, the present invention may include a transceiver having the transmission circuit.

In the present invention, the transmission circuit may include the current source provided between a first power source and a first node, and a first signal of a differential signal line constituting the bus with the first node. Between the first node and the second signal line of the differential signal line. The first transistor is provided between the first node and on / off controlled by a first transmission control signal. A second transistor that is on / off controlled by a second transmission control signal;
A third transistor provided between the first node and the second power supply and controlled to be turned on / off by a third transmission control signal may be included.

  The present invention also relates to an electronic device including any of the data transfer control devices described above and a processing unit that controls the data transfer control device.

  Hereinafter, embodiments of the present invention will be described in detail. In addition, this embodiment demonstrated below does not unduly limit the content of this invention described in the claim. Further, not all of the configurations described in the present embodiment are essential as a solution means of the present invention.

1. USB
First, USB data transfer will be briefly described. In USB, end points (EP0 to EP15) as shown in FIG. 1A are prepared on the USB device side. By specifying the device address and the endpoint number, the host can freely transmit data to the desired endpoint and receive data from the desired endpoint.

  In USB, control transfer, isochronous transfer, interrupt transfer, bulk transfer, and the like are defined as transfer types. Control transfer is a transfer mode for control performed between the host and the USB device (target) via the endpoint 0. Isochronous transfer is a transfer mode prepared for periodically transferring image and audio data. Interrupt transfer is a transfer mode prepared for periodically transferring a small amount of data at a relatively low transfer rate. Bulk transfer is a transfer mode prepared for transferring a large amount of data that occurs irregularly.

  Each of these transfers consists of a series of transactions. As shown in FIG. 1B, the transaction includes a token packet, an optional data packet, and an optional handshake packet.

  Here, the token packet is a packet used when the host requests reading or writing of the endpoint of the USB device. This token packet has fields of PID (packet ID of OUT, IN, SOF, SETUP, etc.), ADDR (device address), ENDP (endpoint number), and CRC (Cyclic Redundancy Check). The data packet is a packet for sending a data body, and has PID (DATA0, DATA1), DATA, and CRC fields. The handshake packet is a packet for the receiving side to tell the transmitting side whether or not the data reception is successful, and has a PID (ACK, NAK, STALL) field.

  In an OUT transaction (a transaction in which the host outputs information to the USB device), as shown in FIG. 1C, first, the host issues an OUT token (token packet) to the USB device. Next, the host transmits OUT data (data packet) to the USB device. If the USB device succeeds in receiving the OUT data, the USB device transmits an ACK (handshake packet) to the host. In this way, processing for the host to write data to the USB device is realized.

  On the other hand, in the IN transaction (transaction in which the host inputs information from the USB device), as shown in FIG. 1D, first, the host issues an IN token (token packet) to the USB device. Then, the USB device that has received the IN token transmits IN data (data packet) to the host. When the host succeeds in receiving the IN data, the host transmits ACK to the USB device. In this way, the host reads data from the USB device.

  In FIGS. 1C and 1D, “D ← H” means that information is transferred from the host to the USB device, and “D → H” means that the USB device is transferred to the host. Means that information is transferred.

2. Configuration of Data Transfer Control Device FIG. 2 shows a configuration example of the data transfer control device of this embodiment. The data transfer control device includes a transceiver 10, a transfer controller 70, and a data buffer (FIFO) 100. Note that some of these may be omitted. For example, the transceiver 10 and the data buffer 100 may not be included.

  The transceiver 10 is a circuit for transmitting / receiving USB (bus or serial bus in a broad sense) data using differential signal lines (DP, DM), and is a logic circuit that is a part of a USB logic layer circuit. 20 and an analog front end circuit 30 which is a physical layer circuit (PHY). Taking USB 2.0 as an example, a circuit compliant with the UTMI (USB 2.0 Transceiver Macrocell Interface) specification can be used as the transceiver 10.

  The logic circuit 20 included in the transceiver 10 includes EOP (End Of Packet) generation / deletion, SYNC (SYNChronization) generation / deletion, NRZI encoding (encoding), NRZI decoding (decoding), bit stuffing (bit insertion), Bit unstuffing (bit deletion), serial / parallel conversion, parallel / serial conversion, and generation / detection of differential signal line states (J, K, SE0, etc.).

  The analog front end circuit 30 (transmission / reception circuit) included in the transceiver 10 includes a transmission circuit 40 and a reception circuit 50. It also includes an analog circuit that detects the validity / invalidity of the differential signal data, detects the connection of the differential signal line, and controls the pull-up of the differential signal line.

  The transmission circuit 40 is a circuit for transmitting a packet via the USB. Specifically, the packet is transmitted by driving the USB differential signal line using the current source 42. More specifically, the differential signal lines (DP, DM) are driven with a constant current value using the current source 42 to generate a J state and a K state and transmit a packet (serial data). . The receiving circuit 40 is a circuit for receiving a packet transferred via the USB. Specifically, the packet (serial data) is received by detecting the above-described J state and K state.

  In USB, data is transmitted and received by differential signals using DP (Data +) and DM (Data-). In USB 2.0, the HS mode (first transfer mode in a broad sense) and the FS mode (second transfer mode in a broad sense) are defined as transfer modes. The HS mode is a transfer mode newly defined by USB 2.0. The FS mode is a transfer mode already defined in the conventional USB 1.1, and the transceiver 10 can transmit and receive data in both of these transfer modes.

  The transfer controller 70 is a controller for controlling data transfer via USB (serial bus). More specifically, protocol layer data transfer control such as a packet layer or a transaction layer is performed. The transfer controller 70 can be configured by a logic circuit or the like. A part of the function of the transfer controller 70 may be realized by firmware (software) operating on the CPU.

  An SIE (Serial Interface Engine) 80 included in the transfer controller 70 performs packet processing such as packet generation and packet handle, transaction processing such as transaction control and transaction management, and suspend / resume control processing. The SIE 80 includes a packet analysis circuit 82, a transaction controller 84, and a packet generation circuit 86.

  The packet analysis circuit 82 analyzes (decodes) the packet received by the reception circuit 50 via the USB (bus). Specifically, the packet is separated into a header and data, the header is analyzed, and the analysis results (packet analysis information, transaction analysis information) are output (stored in a register, memory, etc.). The analysis result may be information (analysis information) output from the packet analysis circuit 82 itself, or this information may be used by firmware that operates on the processing unit (CPU) or firmware that implements the transaction controller 84. The result obtained by analyzing may be sufficient.

  The transaction controller 84 performs transaction processing and gives an instruction to transmit a packet constituting the transaction. More specifically, the type of transaction (IN transaction, OUT transaction, etc.) being performed on the bus is recognized and recognized based on the analysis result (result interpreted by the processing unit) in the packet analysis circuit 82. A transmission instruction (transmission start instruction, packet information instruction) of a packet (data packet, handshake packet such as ACK, NAK, NYET, etc.) constituting the type of transaction is performed. More specifically, it is determined whether to switch the transaction phase (token phase, data phase, handshake), and when switching to a phase that requires packet transmission, the transmission of the packet in that phase is instructed.

  That is, the transaction controller 84 monitors a transaction (transaction phase switching) issued by the host. This monitoring can be performed based on the analysis result. Then, when a transaction is issued by the host, in response to the transaction, a transaction process for executing the transaction is performed.

  For example, when the host issues an IN transaction with an IN token packet, the transaction controller 84 performs a transaction process for executing the IN transaction. That is, if it is determined that the token phase is switched to the data phase after receiving the IN token, the transaction controller 84 instructs the packet generation circuit 86 to generate and transmit a data packet. It then monitors the return of handshake packets such as ACK from the host.

  When the host issues an OUT transaction using the OUT token packet, the transaction controller 84 performs a transaction process for executing the OUT transaction. That is, the transaction controller 84 monitors the transmission of a data packet from the host. When the data packet is received and it is determined that the data phase is switched to the handshake, the packet generation circuit 86 is instructed to generate and transmit a handshake packet such as an ACK.

  The packet generation circuit 86 generates a packet instructed to be transmitted by the transaction controller 84, and outputs (generates) transmission data for causing the transmission circuit 40 to transmit the generated packet. More specifically, a packet is assembled based on the header set by the processing unit (CPU) and the data from the data buffer 100. Each byte data (digital data) constituting the packet is output to the transceiver 10 (transmission circuit 40) as transmission data.

  The buffer controller 90 included in the transfer controller 70 performs an area securing process of the data buffer 100, an access (write, read) process to the data buffer 100, and the like. More specifically, an endpoint area (buffer area) is secured in the data buffer 100, endpoint numbers are managed and identified, and FIFO control of the endpoint area is performed.

  The data buffer 100 (FIFO, packet buffer) is for temporarily storing (buffering) data (transmission data, reception data, and packets) transferred via a USB (serial bus). The data buffer 100 can be realized by a memory such as a RAM (Random Access Memory).

3. Transmission Circuit FIG. 3 shows a configuration example of the transmission circuit 40. As shown in the figure, the transmission circuit 40 includes a current source 42 and a transmission driver 44 (HS current driver). Also included is a transmission control circuit 46 that generates transmission control signals GC1, GC2, and GC3 and outputs them to the transmission driver 44. The configuration of the transmission circuit 40 is not limited to the configuration shown in FIG. 3. For example, some of the components (transmission control circuit, etc.) in the same drawing may be omitted or other components may be added.

  As shown in FIG. 3, the current source 42 (constant current source) is provided between VDD (first power source) and the first node N1. The transmission driver 44 includes transistors TE1, TE1, and TE3 (first to third transistors) that function as switching elements. The transistor TE1 is provided between the plus signal line DP (first signal line) of the differential signal line constituting the USB (bus) and the node N1. The transistor TE2 is provided between the negative signal line DM (second signal line) of the differential signal line and the node N1. The transistor TE3 is provided between the node N1 and GND (second power supply).

  As shown in FIG. 3, one end of a device-side termination resistor RP1 and a host-side termination resistor RP2 is connected to the plus-side signal line DP of the USB differential signal line. Also, one end of a device-side termination resistor RM1 and a host-side termination resistor RM2 is connected to the minus-side signal line DM. The other end of the device-side termination resistors RP1 and RM1 is connected to the output of the device-side FS transmission driver, which will be described later, and the output of the device-side FS transmission driver becomes the GND level (0 V) in the HS mode. Thus, the other ends of RP1 and RM1 are connected to GND (second power supply). Similarly, the output of the FS transmission driver on the host side is connected to the other end of the termination resistors RP2 and RM2. When the output of the FS transmission driver on the host side becomes the GND level in the HS mode, the output of the RP2 and RM2 The other end is connected to GND. Note that a resistor RC1 having the same resistance value as that of RP1 and RM1 is provided between the transistors TE3 and GND.

  FIG. 4A shows signal waveform examples of the first, second, and third transmission control signals GC1, GC2, and GC3 output from the transmission control circuit 46. FIG. The signals GC1 and GC2 are non-overlapping signals in which one of them is active (for example, high level) and the other is inactive (for example, low level). The signal GC3 is a signal that becomes inactive during the transmission period and becomes active during a period other than the transmission period.

  When the signal GC1 becomes active, the transistor TE1 is turned on, and the current (constant current) from the current source 42 flows to the signal line DP side through the transistor TE1. On the other hand, when the signal GC2 becomes active, the transistor TE2 is turned on, and the current from the current source 42 flows to the signal line DM via the transistor TE2. At this time, the termination resistors RP1, RM1, RP2, and RM2 are connected to the signal lines DP and DM as described above. Accordingly, when the signal GC1 is activated and the signal GC2 is deactivated, a J state is generated in which the DP voltage is 400 mV and the DM voltage is 0V. When the signal GC1 is deactivated and the signal GC2 is activated, a K state is generated in which the DP voltage is 0V and the DM voltage is 400 mV. By controlling the signals GC1 and GC2 in this way to change the USB bus state to the J state or the K state, HS transmission of serial data (packets) via the USB becomes possible.

  As shown in FIG. 4A, in a period other than the transmission (HS transmission) period, the signal GC3 becomes active, so that the current (constant current) from the current source 42 is connected to the GND (analog) via the transistor TE3. GND, analog VSS) side. That is, the current from the current source 42 is discarded. In this way, even during a period other than the transmission period, the potential of the node N1 can be stabilized by continuously flowing the current from the current source 42 to the GND side via the transistor TE3. Then, immediately after the start of transmission, a stable current from the current source 42 can be passed through the signal line DP or DM via the transistor TE1 or TE2, and the response of the transmission circuit 40 can be improved.

4). Current Source Enable Control As described above, the transmission circuit 40 of this embodiment performs packet (serial data) transmission using the current source 42. In order to stabilize the potential of the node N1 and increase the response of the transmission circuit 40, the current from the current source 42 is supplied to the GND side via the transistor TE3 and the resistor RC1 even in a period other than the transmission period.

  However, the value of the current flowing from the current source 42 is as large as 17.78 mA, for example. Therefore, even during a period other than the transmission period, if the current from the current source 42 flows into the GND, the power consumption of the transmission circuit 40 increases. This has hindered the incorporation of USB 2.0 data transfer control devices such as mobile phones that are strongly required to have low power consumption.

  Therefore, in this embodiment, as shown in FIG. 4B, the enable control signal of the current source 42 is activated at the timing indicated by C2 before the transmission start timing indicated by C1 at which the packet is transmitted on the USB. . That is, the enable control signal is activated at a timing (C2) that is earlier than the transmission start timing (C1) of the packet by the transmission waiting period TS.

  In this way, proper packet transmission using the current of the current source 42 can be performed during the packet transmission period, and a situation where a wasteful current flows into the GND during a period other than the transmission period can be prevented. Thereby, it is possible to save power of an electronic device in which the data transfer control device is incorporated. In addition, by setting the length of the transmission standby period TS to a length sufficient for stabilizing the current of the current source 42 and the potential of the node N1 (for example, 100 ns or more), the current source is immediately Stable current from 42 can be supplied to DP and DM via TE1 and TE2, and the high response performance of the transmission circuit 40 can be maintained.

  The present embodiment is characterized in that this enable control signal is controlled (generated and output) by the transaction controller 84 which is a transaction layer.

  For example, as a comparative example of the present embodiment, a method in which the control of the enable control signal is performed by a circuit in the packet layer (or a layer below it) such as the packet generation circuit 86 can be considered. However, the packet layer circuit is completely unaware of the transactions that are taking place on the bus. Therefore, the method of this comparative example cannot realize intelligent control such as changing the signal change timing of the enable control signal according to the type of transaction being executed.

  Further, in order to guarantee the stable operation of the transmission circuit 40 at the start of transmission, the transmission standby period TS of FIG. 4B, which is a period from when the enable control signal becomes active until packet transmission starts, is necessary. Become. However, since the packet layer circuit does not recognize the transaction at all, if the packet layer circuit controls the enable control signal, a sufficiently long transmission waiting period TS cannot be secured. That is, if the enable control signal is activated after the packet layer circuit determines that the packet is to be transmitted, the transmission standby period TS becomes too short. For this reason, in the method of the comparative example, there is a possibility that a situation occurs in which packet transmission starts before the current of the current source 42 is stabilized.

  On the other hand, in this embodiment, the transaction controller 84 that recognizes the transaction (transaction phase switching timing) controls the enable control signal. Therefore, control according to the transaction performed on the bus is possible, and intelligent control such as changing the signal change timing of the enable control signal according to the type of transaction being executed can be realized. Specifically, when the transaction type is an IN transaction, the enable control signal can be controlled to become active at a timing between the IN token packet reception completion timing and the data packet transmission start timing. In addition, when the transaction type is an OUT transaction, it is possible to control to enable the enable control signal at a timing between the reception completion timing of the data packet and the transmission start timing of the handshake packet.

  In the present embodiment, since the transaction controller 84 that recognizes the transaction controls the enable control signal, the transmission waiting time TS in FIG. 4B can be set to a sufficiently long length. That is, the transaction controller 84 is an upper layer circuit of the packet layer circuit (packet generation circuit 86). Therefore, after the enable control signal is activated, a transmission instruction is sent to the packet layer (or lower layer) circuit after waiting for a predetermined period, so that the transmission waiting time TS of FIG. It can be secured. As a result, after the current flowing through the current source 42 is stabilized, packet transmission by the transmission circuit 40 can be started, and a stable transmission operation can be realized.

  The enable control signal may be a signal for enabling control of current of at least the current source 42. That is, it may be a signal instructing to enable the current source 42 or a signal instructing to disable the current source 42. For example, an enable control signal may be used as the signal GC3 for controlling the transistor TE3. The enable control signal may be output directly from the transaction controller 84 to the transmission circuit 40 or may be output to the transmission circuit 40 via another circuit such as a register.

5. Operation Next, the operation of this embodiment will be described with reference to FIGS. FIG. 5 is an example of a signal waveform for explaining the operation in the IN transaction.

  First, as indicated by E1 in FIG. 5, the host transmits an IN token packet via the USB, and an IN transaction starts. Then, the received IN token packet is received by the receiving circuit 50 of FIG. 4, and the packet analyzing circuit 82 analyzes (decodes) the received packet. When the reception of the IN token packet is completed as indicated by E2 in FIG. 5, the analysis result for the packet or transaction is output (stored in a register or the like) as indicated by E3.

  Next, the transaction controller 84 recognizes (determines) the type of transaction being performed on the bus and the switching of the transaction phase based on the analysis result. Then, processing according to the recognized transaction type and phase is performed. That is, the enable control signal is activated, or a transmission instruction of a packet (a packet necessary for the recognized phase) constituting the recognized type transaction is performed.

  For example, in FIG. 5, since it is determined that the transaction being performed on the bus is an IN transaction, the transaction controller 84 sends the enable control signal at the timing E4 in FIG. 5, which is the timing before the transmission start timing of the data packet. Activate. In addition, at the timing of E5, an instruction to transmit a data packet constituting the IN transaction is issued. That is, a transmission instruction signal (transmission start signal) and packet information are output to the packet generation circuit 86. Here, the packet information includes information such as the type and data size of a packet for instructing transmission.

  The packet generation circuit 86 generates a packet instructed to be transmitted by the transaction controller 84. Then, as shown by E6 in FIG. 5, transmission data for causing the transmission circuit 40 to transmit the generated packet is output. As a result, the transmission circuit 40 performs transmission processing based on the transmission data, and a data packet is transmitted via the USB as indicated by E7.

  When the transmission of the data packet is completed as indicated by E8 in FIG. 5, the transaction controller 84 deactivates the enable control signal and the transmission instruction signal as indicated by E9 and E10. Then, as shown in E11, when a handshake packet such as ACK (ACKnowledgment) is returned from the host, the IN transaction ends.

  FIG. 6 is a signal waveform example for explaining the operation in the OUT transaction. First, as shown by F1 in FIG. 6, the host transmits an OUT token packet, and an OUT transaction starts. Then, the reception circuit 50 receives the transmitted OUT token packet, and the packet analysis circuit 82 analyzes the received packet. When the reception of the OUT token packet is completed as indicated by F2, the analysis result is output as indicated by F3.

  Next, the transaction controller 84 recognizes (determines) the type of transaction being performed on the bus based on the analysis result. For example, in FIG. 6, it is determined that the transaction being performed on the bus is an OUT transaction.

  Next, as indicated by F4 in FIG. 6, the host transmits a data packet, and the data transfer control device receives the data packet. When reception of the data packet is completed as indicated by F5, the transaction controller 84 activates the enable control signal at the timing indicated by F6, which is the timing before the transmission start timing of the ACK packet (handshake packet in a broad sense). To do. At the timing indicated by F7, an instruction to transmit an ACK packet that constitutes an OUT transaction is issued.

  The packet generation circuit 86 generates a packet instructed to be transmitted by the transaction controller 84. Then, as shown at F8 in FIG. 6, transmission data for causing the transmission circuit 40 to transmit the generated packet is output. As a result, the transmission circuit 40 transmits an ACK packet via the USB as indicated by F9. When the transmission of the ACK packet is completed as indicated by F10, the transaction controller 84 deactivates the enable control signal and the transmission instruction signal as indicated by F11 and F12.

6). In this embodiment, as shown in FIG. 5, in this embodiment, the transaction controller 84 activates the enable control signal at the timing E4 before the timing E7 at which the transmission of the data packet is started. Specifically, the enable control signal is activated at the timing of E4 between the timing of E3 that recognizes the type (phase) of the transaction being performed on the bus and the timing of E7 that starts transmission of the data packet. .

  Further, as shown in FIG. 6, the transaction controller 84 activates the enable control signal at the timing of F6 before the timing of F9 at which the transmission of the ACK packet is started. Specifically, the enable control signal is activated at the timing of F6 between the timing of F3 that recognizes the type (phase) of the transaction being performed on the bus and the timing of F9 that starts transmission of the ACK packet. .

  As described above, if the enable control signal is activated at the timing of E4 in FIG. 5 or F6 in FIG. 6, the current of the current source 42 can be enabled at the timing immediately before the transmission of the data packet or the ACK packet. Accordingly, it is possible to prevent a situation in which the current of the current source 42 is wasted in the period before this timing, and to realize power saving. In addition, if the enable control signal is activated at such timing, it is possible to secure the transmission standby period TS of FIGS. 5 and 6 to a sufficient length. Accordingly, packet transmission can be started after the current of the current source 42 is stabilized, and a stable transmission operation can be realized.

  In USB, the time interval of the gap period TG between packets is standardized. Therefore, the transaction controller 84 performs a wait process for complying with the standard of the gap period TG. The timings indicated by E4 and E5 in FIG. 5 and F6 and F7 in FIG. 6 can be generated using this wait process. Specifically, the transmission instruction timing of E5 in FIG. 5 or F7 in FIG. 6 is controlled so that the gap period TG is a time interval within the standard. The enable control signal is activated at the timing of E4 and F6 before the transmission instruction timing of E5 and F7.

  For example, in the method of the above-described comparative example in which the packet layer circuit controls the enable control signal, after the wait period for complying with the standard of the gap period TG has elapsed and the transmission disclosure instruction has been issued, the enable control signal Will be activated. However, in this method, since time has already been spent in the elapse of the wait period, there is a problem that the transmission standby period TS of FIGS. 4 and 5 cannot be secured to a sufficient length. According to this embodiment, such a problem can be solved.

  In this embodiment, since the transaction controller 84 that recognizes the transaction generates the enable control signal, an optimum enable control signal corresponding to the transaction being performed on the bus can be realized.

  For example, when the transaction type is an IN transaction as shown in FIG. 5, the transaction controller 84 sends E4 between the timing E2 when the reception of the IN token packet is completed and the timing E7 when the transmission of the data packet starts. At this timing, the enable control signal is activated.

  On the other hand, when the transaction type is an OUT transaction as shown in FIG. 6, the timing of F6 between the timing of F5 when the reception of the data packet is completed and the timing of F9 when the transmission of the ACK (handshake) packet starts. The transaction controller 84 activates the enable control signal.

  As described above, in this embodiment, since the timing for activating the enable control signal can be changed according to the type of transaction, intelligent control can be performed as compared with the method of the comparative example described above. Thereby, the optimal power saving according to the transaction type can be realized.

  Note that the control method of the enable control signal is not limited to the method of FIGS. 5 and 6, and various modifications as shown in FIGS. 7A to 8B are possible.

  For example, when there is no data to be transmitted to the host in the IN transaction, the enable control signal may be controlled as shown in FIG. That is, when an IN token is received from the host and there is no data to be returned to the IN token on the device side and a NAK (Negative Acknowledgement) packet is returned, the transaction is performed at the timing before the transmission start timing of the NAK packet. Controller 84 activates the enable control signal. Then, after the transmission of the NAK packet is completed, the enable control signal is deactivated. Further, the handshake packet returned to the host side in the OUT transaction is not limited to the ACK packet in FIG. 6, and may be a NAK packet or a NYET packet. The ACK packet is a packet for notifying the success of reception, and the NAK packet is a packet for notifying the reception failure. The NYET packet is a packet for notifying that preparation for reception is not completed.

  In USB, a setup transaction is executed at the beginning of control transfer. In the case of this setup transaction, the enable control signal may be controlled as shown in FIG. That is, first, the host transmits a SETUP packet. Next, the host transmits a data packet such as a device request. Then, as shown in FIG. 7B, the transaction controller 84 activates the enable control signal at a timing before the transmission start timing of the ACK packet. Then, after the transmission of the ACK packet is completed, the enable control signal is deactivated.

  In USB, a PING transaction is defined in which a host sends a PING packet to a device before sending an OUT data packet. This PING transaction is for preventing a situation in which retransmission of a large OUT data packet is repeated by sending a NAK response from the device after transmitting a large OUT data packet. In the case of this PING transaction, the enable control signal may be controlled as shown in FIG. That is, first, the host transmits a PING packet. Then, the transaction controller 84 activates the enable control signal at a timing before the transmission start timing of the ACK (NAK) packet. Then, after the transmission of the ACK packet is completed, the enable control signal is deactivated.

  Further, the case where the data transfer control device is on the device side has been mainly described above, but the method of the present embodiment can also be applied when the data transfer control device is on the host side. For example, FIG. 8A shows an example in which the data transfer control device is the host side and the transaction type is an IN transaction. In this case, the transaction controller included in the data transfer control device on the host side activates the enable control signal at a timing before the transmission start timing of the IN token packet. Then, after the transmission of the IN token packet is completed, the enable control signal is deactivated. Next, the enable control signal is made active again at a timing between the reception completion timing of the data packet from the device side and the transmission start timing of the ACK packet (handshake packet). Then, after the transmission of the ACK packet is completed, the enable control signal is deactivated.

  FIG. 8B shows an example in which the data transfer control device is the host side and the transaction type is an OUT transaction. In this case, the transaction controller included in the data transfer control device on the host side activates the enable control signal at a timing before the transmission start timing of the OUT token packet. Then, after the transmission of the OUT token packet is completed and the transmission of the data packet is completed, the enable control signal is deactivated. Then, an ACK packet (handshake packet) is received from the device side.

7). Current Source FIG. 9 shows a configuration example of the current source 42 included in the transmission circuit 40. As shown in FIG. 9, the current source 42 includes P-type transistors TE <b> 5 to TE <b> 10 and a bias current source 43. The transistor TE5 is provided between VDD (first power supply) and the node N2, and an enable control signal is input to the gate electrode thereof. The transistor TE6 is provided between VDD and the node N3, and an enable control signal is input to its gate electrode. The transistors TE7 and TE8 are provided in series between VDD and the node N3, and the nodes N2 and N3 are connected to the gate electrodes, respectively. The bias current source 43 is provided between the node N3 and GND (second power supply). The transistors TE9 and TE10 are provided between VDD and the node N1, and nodes N2 and N3 are connected to the gate electrodes, respectively.

  When the enable control signal is active (high level), the transistors TE5 and TE6 are turned off. Therefore, the current flowing through the bias current source 42 is copied by the current mirror circuit formed by the transistors TE7 to TE10 and flows to the node N1. Thereby, normal packet transmission using the transmission driver 44 becomes possible.

  On the other hand, when the enable control signal becomes inactive (low level), the transistors TE5 and TE6 are turned on. As a result, the voltage levels of the nodes N2 and N3 become the VDD level, and the transistors TE7 to TE10 are turned off. Thereby, the current flowing through the current source 42 is turned off, and the power saving mode is realized. The configuration of the current source 42 is not limited to the configuration of FIG. 9, and various modifications can be made.

8). Transceiver FIG. 10 shows a configuration example of the transceiver 10. The transceiver 10 is not limited to the configuration shown in FIG. 10, and some of the components shown in FIG. 10 may be omitted or other components may be added.

  The transceiver 10 includes an HS transmission circuit 40, a reception circuit 50, and a detection circuit 54 (squelch circuit). In addition, a transmission circuit 60 and a reception circuit 66 for FS are included. Further, it includes a pull-up resistor Rpu and a pull-up switch SWU. SWD and Rpu 'are dummy switches and dummy resistors.

  The transmission circuit 40 is a circuit that performs transmission processing in the USB HS mode, and includes a current source 42, a transmission driver 44, and a transmission control circuit 46. The transmission driver 44 transmits serial data by current-driving the differential signal lines DP and DM based on the transmission control signal from the transmission control circuit 46 and the current from the current source 42.

  The reception circuit 50 is a circuit that performs reception processing in the USB HS mode, and includes a differential receiver 52. The differential receiver 52 differentially amplifies a differential signal (differential voltage) input via the differential signal lines DP and DM, and outputs the obtained reception data to the subsequent logic circuit 20.

  The detection circuit 54 (squelch circuit) is a circuit for distinguishing whether a signal on the USB is valid data or noise. More specifically, the detection circuit 54 holds the peak value of the USB signal and detects the amplitude of the signal by detecting the envelope of the signal. For example, if the detected amplitude is 100 mV or less, the signal is determined to be noise, and if the detected amplitude is 150 mV or more, it is determined to be valid data. If it is determined that the data is valid, the received data output from the receiving circuit 50 is determined to be valid data.

  The transmission circuit 60 is a circuit that performs transmission processing in the USB FS mode, and includes a transmission driver 62 and a transmission control circuit 64. The transmission driver 62 transmits serial data by voltage-driving the differential signal lines DP and DM based on the transmission control signal from the transmission control circuit 64. Resistors RP1 and RM1 are connected to the positive and negative outputs (differential outputs) of the transmission driver 62, respectively. In the HS mode, the outputs on the plus side and the minus side of the transmission driver 62 are set to 0 V (GND), so that the resistors RP1 and RM1 function as termination resistors for HS.

  The reception circuit 66 is a circuit that performs reception processing in the USB FS mode, and includes a differential receiver 67 for receiving serial data, and single-ended receivers 68 and 69 for detecting a line state and the like.

9. Electronic Device FIG. 11 shows a configuration example of an electronic device in which the data transfer control device of this embodiment is incorporated. The electronic device 300 includes the data transfer control device 310 described in the present embodiment, an application layer device 320 including an ASIC, a processing unit 330 (CPU), a ROM 340, a RAM 350, a display unit 360, and an operation unit 370. Note that some of these components may be omitted.

  Here, the application layer device 320 is, for example, a device that realizes an application engine of a mobile phone, a device that controls a drive of an information storage medium (hard disk, optical disk), a device that controls a printer, an MPEG encoder, an MPEG decoder, or the like Including the device. The processing unit 330 (CPU) controls the data transfer control device 310 and the entire electronic device. The ROM 340 stores control programs and various data. The RAM 350 functions as a work area and a data storage area for the processing unit 330 and the data transfer control device 310. The display unit 360 displays various information to the user. The operation unit 370 is for the user to operate the electronic device.

  In FIG. 11, the DMA bus and the CPU bus are separated, but they may be shared. Further, a processing unit that controls the data transfer control device 310 and a processing unit that controls the electronic apparatus may be provided separately.

  As electronic devices to which the present embodiment can be applied, mobile phones, audio devices (portable audio devices), video devices (portable video devices), hard disk drives, optical disk drives (CD-ROM, DVD), magneto-optical disk drives There are various types such as (MO), personal computers, electronic notebooks, and portable information devices.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention. For example, terms (USB, HS mode, FS mode) cited as broad or synonymous terms (bus or serial bus, first transfer mode, second transfer mode, handshake packet, etc.) in the description or drawings. ACK packet, etc.) can be replaced with broad or synonymous terms in other descriptions in the specification or drawings.

  The configurations of the data transfer control device and the electronic device of the present invention are not limited to the configurations described with reference to FIGS. 2, 3, 9 to 11 and the like, and various modifications can be made. For example, some of the components in these drawings may be omitted or the connection relationship may be changed.

  In the present embodiment, the application example to the data transfer of the USB standard has been described. However, the present invention can also be applied to data transfer based on a standard based on the same idea as USB, a standard developed from USB, or a standard other than USB (for example, a high-speed serial interface such as IEEE 1394).

1A, 1B, 1C, and 1D are explanatory diagrams of USB data transfer. 1 is a configuration example of a data transfer control device according to the present embodiment. A detailed configuration example of a transmission circuit and the like. 4A and 4B are signal waveform diagrams of transmission control signals. The signal waveform figure at the time of IN transaction. The signal waveform figure at the time of OUT transaction. 7A, 7B, and 7C are explanatory diagrams of a control method of the enable control signal. 8A and 8B are explanatory diagrams of the control method of the enable control signal. An example of the configuration of a current source. Example of transceiver configuration. Configuration example of an electronic device.

Explanation of symbols

10 transceivers, 20 logic circuits, 30 analog front-end circuits,
40 transmission circuit, 42 current source, 44 transmission driver, 46 transmission control circuit,
50 receiving circuit, 52 differential receiver, 54 detecting circuit, 60 transmitting circuit,
62 transmission driver, 64 transmission control circuit, 66 reception circuit,
67 differential receiver, 68, 69 single-ended receiver,
70 transfer controller, 80 SIE, 82 packet analysis circuit,
84 transaction controller, 90 buffer controller,
100 data buffer, 300 electronic equipment, 310 data transfer control device,
320 application layer device, 330 processing unit, 340 ROM,
350 RAM, 360 display unit, 370 operation unit,

Claims (10)

A data transfer control device for data transfer via a bus,
A transaction controller for performing transaction processing and instructing transmission of packets constituting the transaction;
A packet generation circuit that generates a packet instructed to be transmitted by the transaction controller and outputs transmission data for causing the transmission circuit to transmit the generated packet;
The transaction controller is
A data transfer control device, wherein an enable control signal of a current source used for packet transmission by the transmission circuit is activated at a timing before a transmission start timing at which the transmission circuit starts packet transmission. In claim 1,
The transaction controller is
A data transfer control device, wherein the enable control signal is activated at a timing between a timing at which a type of transaction being performed on a bus is recognized and the transmission start timing. In claim 2,
Includes a packet analysis circuit that analyzes packets received via the bus,
The transaction controller is
A data transfer control device for recognizing a type of a transaction performed on a bus based on an analysis result in the packet analysis circuit. In any one of Claims 1 thru | or 3,
The bus is USB;
The transaction controller is
A data transfer control device, wherein when the transaction type is an IN transaction, the enable control signal is activated at a timing between an IN token packet reception completion timing and a data packet transmission start timing. In any one of Claims 1 thru | or 4,
The bus is USB;
The transaction controller is
When the transaction type is an OUT transaction, the enable control signal is activated at a timing between a data packet reception completion timing and a handshake packet transmission start timing. A data transfer control device for data transfer via USB,
A packet analysis circuit for analyzing a packet received via USB;
A transaction controller for recognizing the type of transaction being performed on the USB based on the analysis result in the packet analysis circuit and instructing transmission of a packet constituting the recognized type of transaction;
A packet generation circuit that generates a packet instructed to be transmitted by the transaction controller and outputs transmission data for causing the transmission circuit to transmit the generated packet;
The transaction controller is
When the transaction type is an IN transaction, the enable control signal of the current source used by the transmission circuit for packet transmission is activated at a timing between the reception completion timing of the IN token packet and the transmission start timing of the data packet. A data transfer control device. A data transfer control device for data transfer via USB,
A packet analysis circuit for analyzing a packet received via USB;
A transaction controller for recognizing the type of transaction being performed on the USB based on the analysis result in the packet analysis circuit and instructing transmission of a packet constituting the recognized type of transaction;
A packet generation circuit that generates a packet instructed to be transmitted by the transaction controller and outputs transmission data for causing the transmission circuit to transmit the generated packet;
The transaction controller is
When the transaction type is an OUT transaction, the transmission circuit activates the enable control signal of the current source used for packet transmission at a timing between the reception completion timing of the data packet and the transmission start timing of the handshake packet. A data transfer control device. In any one of Claims 1 thru | or 7,
A data transfer control device comprising a transceiver having the transmission circuit. In claim 8,
The transmission circuit is
The current source provided between a first power source and a first node;
A first transistor provided between the first node and a first signal line of a differential signal line constituting a bus and controlled to be turned on / off by a first transmission control signal;
A second transistor provided between the first node and the second signal line of the differential signal line and controlled to be turned on / off by a second transmission control signal;
A data transfer control device comprising a third transistor provided between the first node and a second power supply and controlled to be turned on / off by a third transmission control signal. A data transfer control device according to any one of claims 1 to 9,
A processing unit for controlling the data transfer control device;
An electronic device comprising:

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