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JP2006128606A - Mounted structure for semiconductor component and method for manufacturing mounted substrate to be used therefor - Google Patents

Mounted structure for semiconductor component and method for manufacturing mounted substrate to be used therefor Download PDF

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Publication number
JP2006128606A
JP2006128606A JP2005118432A JP2005118432A JP2006128606A JP 2006128606 A JP2006128606 A JP 2006128606A JP 2005118432 A JP2005118432 A JP 2005118432A JP 2005118432 A JP2005118432 A JP 2005118432A JP 2006128606 A JP2006128606 A JP 2006128606A
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Prior art keywords
semiconductor component
mounting structure
land portion
land
upper layer
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JP2005118432A
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Japanese (ja)
Inventor
Shinji Murata
眞司 村田
Masayoshi Takeuchi
正宜 竹内
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP2005118432A priority Critical patent/JP2006128606A/en
Priority to US11/385,582 priority patent/US7456493B2/en
Priority to CNB2006100753321A priority patent/CN100416814C/en
Publication of JP2006128606A publication Critical patent/JP2006128606A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features

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Abstract

<P>PROBLEM TO BE SOLVED: To provide the mounted structure of a highly productive semiconductor component where peeling between a bump and a land can be prevented and a method for manufacturing a mounted substrate to be used for this. <P>SOLUTION: The mounted structure of a semiconductor component is provided with a mounted substrate 1 having an insulating substrate 2 on which a wiring pattern 3 and a land 4 are formed, a semiconductor component 5 mounted on the mounted substrate 1 through a bump 7 in the land 4, and an underfill 8 held between the semiconductor component 5 and an insulating substrate 2. An undercut 4c is formed on the end face 4a of the land 4 where the bump 7 is positioned so as to be inversely tapered from the insulating substrate 2 side to the top face of the land 4, and the bump is made to dig into the undercut 4c so that the connection of the bump 7 to the land 4 can be made strong, and when the underfill 8 is expanded and contracted, peeling can be prevented between the bump 7 and the land 4. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

本発明は種々の電子機器や電子回路ユニット等に適用して好適な半導体部品の実装構造、及びそれに使用される実装基板の製造方法に関する。   The present invention relates to a mounting structure for semiconductor components suitable for application to various electronic devices, electronic circuit units, and the like, and a method for manufacturing a mounting substrate used therefor.

従来の半導体部品の実装構造に係る図面を説明すると、図１５は従来の半導体部品の実装構造に係る要部拡大断面図、図１６は従来の半導体部品の実装構造に係り、ランド部の構成を示す実装基板の要部の平面図である。   FIG. 15 is an enlarged cross-sectional view of a main part related to a conventional semiconductor component mounting structure, and FIG. 16 relates to the conventional semiconductor component mounting structure. It is a top view of the principal part of the mounting board | substrate shown.

次に、従来の半導体部品の実装構造に係る構成を図１５，図１６に基づいて説明すると、実装基板５１は、絶縁基板５２と、この絶縁基板５２上に設けられた配線パターン５３と、この配線パターン５３の端部に設けられたランド部５４とで形成されている。   Next, a configuration related to a conventional semiconductor component mounting structure will be described with reference to FIGS. 15 and 16. The mounting substrate 51 includes an insulating substrate 52, a wiring pattern 53 provided on the insulating substrate 52, and A land portion 54 provided at an end of the wiring pattern 53 is formed.

そして、配線パターン５３とランド部５４は、金属膜をエッチングすることによって形成されると共に、ランド部５４は、複数個が点在する島状部５４ａで形成され、この島状部５４ａの端面は、絶縁基板５２側から島状部の上面に向かって垂直な面となっている。   The wiring pattern 53 and the land portion 54 are formed by etching a metal film, and the land portion 54 is formed by a plurality of island-like portions 54a, and an end surface of the island-like portion 54a is The surface is vertical from the insulating substrate 52 side toward the upper surface of the island portion.

半導体部品５５は、下面に複数の電極５６が設けられ、この電極５６には、バンプ５７が付着されていると共に、電極５６に付着したバンプ５７は、ランド部５４上に熱圧着されて、半導体部品５５が実装基板５１に実装されている。   A plurality of electrodes 56 are provided on the lower surface of the semiconductor component 55, and bumps 57 are attached to the electrodes 56, and the bumps 57 attached to the electrodes 56 are thermocompression-bonded on the land portions 54, thereby forming a semiconductor. A component 55 is mounted on the mounting substrate 51.

また、半導体部品５５の下面と絶縁基板５２の上面との間には、アンダーフィル５８を介在させて、半導体部品５５の取付を強固にすることによって、従来の半導体部品の実装構造が構成されている。（例えば、特許文献１参照）   In addition, an underfill 58 is interposed between the lower surface of the semiconductor component 55 and the upper surface of the insulating substrate 52 to strengthen the mounting of the semiconductor component 55, thereby forming a conventional semiconductor component mounting structure. Yes. (For example, see Patent Document 1)

しかし、従来の半導体部品の実装構造は、ランド部５４の島状部５４ａの端面が垂直面となした状態で、バンプ５７がランド部５４に付着するため、アンダーフィル５８が膨張、収縮した際、バンプ５７とランド部５４間の付着が剥がれる。   However, in the conventional semiconductor component mounting structure, when the underfill 58 expands and contracts because the bump 57 adheres to the land portion 54 with the end surface of the island-shaped portion 54a of the land portion 54 being a vertical surface. The adhesion between the bump 57 and the land portion 54 is peeled off.

また、従来の実装基板５１の製造方法は、絶縁基板５２上に設けられた金属膜をエッチングすることによって、配線パターン５３とランド部５４が形成されるため、ランド部５４の島状部５４ａの端面が垂直面となし、このため、バンプ５７がランド部５４に付着した状態で、アンダーフィル５８が膨張、収縮した際、バンプ５７とランド部５４間の付着が剥がれる。   Further, in the conventional method of manufacturing the mounting substrate 51, the wiring film 53 and the land portion 54 are formed by etching the metal film provided on the insulating substrate 52. Therefore, the island-shaped portion 54a of the land portion 54 is formed. The end surface is a vertical surface. Therefore, when the underfill 58 expands and contracts with the bump 57 attached to the land portion 54, the adhesion between the bump 57 and the land portion 54 is peeled off.

特開平１１−４０９４０号公報Japanese Patent Laid-Open No. 11-40940

従来の半導体部品の実装構造は、ランド部５４の島状部５４ａの端面が垂直面となした状態で、バンプ５７がランド部５４に付着するため、アンダーフィル５８が膨張、収縮した際、バンプ５７とランド部５４間の付着が剥がれるという問題がある。   In the conventional semiconductor component mounting structure, the bump 57 adheres to the land portion 54 with the end surface of the island-shaped portion 54a of the land portion 54 being a vertical surface. There is a problem that the adhesion between 57 and the land portion 54 is peeled off.

従来の実装基板５１の製造方法は、絶縁基板５２上に設けられた金属膜をエッチングすることによって、配線パターン５３とランド部５４が形成されるため、ランド部５４の島状部５４ａの端面が垂直面となし、このため、バンプ５７がランド部５４に付着した状態で、アンダーフィル５８が膨張、収縮した際、バンプ５７とランド部５４間の付着が剥がれるという問題がある。   In the conventional manufacturing method of the mounting substrate 51, the wiring pattern 53 and the land portion 54 are formed by etching the metal film provided on the insulating substrate 52. Therefore, the end surface of the island-shaped portion 54a of the land portion 54 is Therefore, when the underfill 58 expands and contracts with the bump 57 attached to the land portion 54, the adhesion between the bump 57 and the land portion 54 is peeled off.

そこで、本発明はバンプとランド部と間の剥がれが無く、生産性の良い半導体部品の実装構造、及びそれに使用される実装基板の製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor component mounting structure with good productivity and a manufacturing method of a mounting substrate used therefor, in which there is no peeling between the bump and the land portion.

上記課題を解決するための第１の解決手段として、配線パターンとランド部が設けられた絶縁基板を有する実装基板と、前記ランド部にバンプを介して前記実装基板に実装された半導体部品と、前記半導体部品と前記絶縁基板との間に介在したアンダーフィルとを備え、前記バンプが位置する前記ランド部の端面には、前記絶縁基板側から前記ランド部の上面に向かって逆テーパー状となるようなアンダーカット部が設けられ、前記アンダーカット部に前記バンプを食い込ませた構成とした。   As a first means for solving the above problems, a mounting substrate having an insulating substrate provided with a wiring pattern and a land portion, a semiconductor component mounted on the mounting substrate via a bump on the land portion, An underfill interposed between the semiconductor component and the insulating substrate is provided, and an end surface of the land portion where the bump is located has a reverse taper shape from the insulating substrate side toward the upper surface of the land portion. Such an undercut part was provided, and it was set as the structure which made the said bump cut into the said undercut part.

また、第２の解決手段として、前記ランド部は、互いに間隔を置いて対向する少なくとも一対の前記端面を有し、この一対の前記端面に設けられた前記アンダーカット部には、前記バンプを食い込ませた構成とした。
また、第３の解決手段として、前記ランド部は、互いに間隔を置いて対向する少なくとも一対の前記端面と、この一対の端面間に設けられ、前記ランド部が削除された溝部と、この溝部の少なくとも一端側に設けられた開放部を有し、前記溝部に介在した前記アンダーフィルが前記開放部を通って流出するようにした構成とした。 As a second solution, the land portion has at least a pair of end surfaces facing each other at an interval, and the bumps are bited into the undercut portions provided on the pair of end surfaces. The configuration was
Further, as a third solving means, the land portion is provided with at least a pair of the end surfaces facing each other with a space therebetween, a groove portion provided between the pair of end surfaces, the land portion being deleted, and the groove portion It has an open portion provided on at least one end side, and the underfill interposed in the groove portion flows out through the open portion.

また、第４の解決手段として、前記バンプが金材で形成された構成とした。
また、第５に解決手段として、前記ランド部は、前記絶縁基板上に設けられた導電率の高い金属からなる下地層と、この下地層上に設けられ、前記下地層よりも硬い金属からなる第１の上部層と、この第１の上部層上に設けられた金材からなる第２の上部層で形成された構成とした。
また、第６の解決手段として、前記下地層は、銅、又は銅を主成分とする合金、又は銀、又は銀を主成分とする合金で形成されると共に、前記第１の上部層がニッケルで形成された構成とした。 As a fourth solution, the bumps are made of a gold material.
As a fifth solution, the land portion is made of a metal having a high conductivity provided on the insulating substrate and a metal harder than the base layer provided on the base layer. The first upper layer and a second upper layer made of a gold material provided on the first upper layer are used.
As a sixth solution, the underlayer is formed of copper, an alloy containing copper as a main component, silver, or an alloy containing silver as a main component, and the first upper layer is formed of nickel. It was set as the structure formed by.

また、第７の解決手段として、請求項１から６の何れかに記載の半導体部品の実装構造を備え、前記実装基板は、前記絶縁基板上に金属性の下地層を形成する工程と、この下地層上に現像可能なレジストを形成する工程と、前記レジストを現像して、前記配線パターンと前記ランド部となる箇所に溝部を有した所望のパターン形状にするための工程と、前記レジストを加熱して、前記レジストの上部の角部を丸める工程と、前記下地層に付着した状態で、前記溝部内に金属性の上部層を形成する工程と、前記レジストを除去する工程と、前記上部層が位置する前記下地層部分を除く前記下地層を除去する工程によって製造されて、前記配線パターンと前記ランド部が前記下地層と前記上部層とで形成されると共に、前記レジストの除去工程、及び前記上部層が位置する前記下地層部分を除く前記下地層の除去工程によって前記アンダーカット部が形成された製造方法とした。   Further, as a seventh solving means, the semiconductor component mounting structure according to any one of claims 1 to 6 is provided, and the mounting substrate includes a step of forming a metallic underlayer on the insulating substrate, Forming a developable resist on an underlayer; developing the resist to form a desired pattern shape having a groove in the wiring pattern and the land portion; and Heating, rounding the upper corners of the resist, forming a metallic upper layer in the groove in a state of adhering to the underlayer, removing the resist, and the upper Manufactured by a step of removing the underlayer excluding the underlayer portion where the layer is located, and the wiring pattern and the land portion are formed of the underlayer and the upper layer, and the resist removing step, The step of removing the underlying layer, excluding the base layer portion microcrystalline the upper layer is positioned to the manufacturing method of the undercut portion is formed.

また、第８の解決手段として、前記上部層がメッキによって形成されると共に、前記下地層の除去がエッチングによって行われる製造方法とした。   As an eighth solution, the manufacturing method is such that the upper layer is formed by plating and the underlayer is removed by etching.

本発明の半導体部品の実装構造は、配線パターンとランド部が設けられた絶縁基板を有する実装基板と、ランド部にバンプを介して実装基板に実装された半導体部品と、半導体部品と絶縁基板との間に介在したアンダーフィルとを備え、バンプが位置するランド部の端面には、絶縁基板側からランド部の上面に向かって逆テーパー状となるようなアンダーカット部が設けられ、アンダーカット部にバンプを食い込ませたため、バンプのランド部への結合は、アンダーカット部にバンプを食い込ませることによって強固となり、アンダーフィルが膨張、収縮した際、バンプとランド部間の剥がれの無いものが得られる。   A mounting structure of a semiconductor component of the present invention includes a mounting substrate having an insulating substrate provided with a wiring pattern and a land portion, a semiconductor component mounted on the mounting substrate via a bump on the land portion, and a semiconductor component and an insulating substrate. And an undercut portion that is reversely tapered from the insulating substrate side toward the top surface of the land portion on the end surface of the land portion where the bump is located. Since the bumps are digged into the bump, the bonding of the bumps to the land is strengthened by the digging of the bumps into the undercut part. It is done.

また、ランド部は、互いに間隔を置いて対向する少なくとも一対の端面を有し、この一対の端面に設けられたアンダーカット部には、バンプを食い込ませたため、バンプとランド部間の結合は、一層強固となり、バンプとランド部間の剥がれの無いものが得られる。   In addition, the land portion has at least a pair of end surfaces facing each other with a space therebetween, and the undercut portions provided on the pair of end surfaces have the bumps bitten, so the coupling between the bump and the land portion is It becomes stronger, and a product with no separation between the bump and the land can be obtained.

また、ランド部は、互いに間隔を置いて対向する少なくとも一対の端面と、この一対の端面間に設けられ、ランド部が削除された溝部と、この溝部の少なくとも一端側に設けられた開放部を有し、溝部に介在したアンダーフィルが開放部を通って流出するようにしたため、溝部内からのアンダーフィルの流出が良好に出来る。   The land portion includes at least a pair of end surfaces facing each other at an interval, a groove portion provided between the pair of end surfaces, the land portion being deleted, and an open portion provided on at least one end side of the groove portion. Since the underfill interposed in the groove portion flows out through the open portion, the underfill outflow from the groove portion can be favorably performed.

また、バンプが金材で形成されたため、バンプとランド部間の導通が一層良くなると共に、アンダーカット部へのバンプの食い込みの良好なものが得られる。   In addition, since the bumps are formed of a gold material, the conduction between the bumps and the land portions is further improved, and the bumps that bite into the undercut portions can be obtained.

また、ランド部は、絶縁基板上に設けられた導電率の高い金属からなる下地層と、この下地層上に設けられ、下地層よりも硬い金属からなる第１の上部層と、この第１の上部層上に設けられた金材からなる第２の上部層で形成されたため、バンプの食い込み時の力による第１の上部層の変形が少なく、アンダーカット部へのバンプの食い込みを確実に出来る。   The land portion includes a base layer made of a metal having high conductivity provided on the insulating substrate, a first upper layer provided on the base layer and made of metal harder than the base layer, and the first layer. Since the second upper layer made of a gold material is provided on the upper layer of the first bump, the deformation of the first upper layer due to the force of the bump biting is small, and the bite of the bump into the undercut portion is ensured. I can do it.

また、下地層を銅、又は銅を主成分とする合金、又は銀、又は銀を主成分とする合金で形成することによって電導性を高めることが出来ると共に、第１の上部層をニッケルで形成することによって、第１の上部層を硬くできて、バンプの食い込み時の力による第１の上部層の変形が少なく、アンダーカット部へのバンプの食い込みを確実に出来る。   In addition, the conductivity can be improved by forming the underlayer from copper, an alloy containing copper as a main component, silver, or an alloy containing silver as a main component, and the first upper layer is formed from nickel. By doing so, the first upper layer can be hardened, and the deformation of the first upper layer due to the force at the time of biting of the bump is small, and the biting of the bump into the undercut portion can be ensured.

また、半導体部品の実装構造に使用される実装基板の製造方法は、半導体部品の実装構造を備え、実装基板は、絶縁基板上に金属性の下地層を形成する工程と、この下地層上に現像可能なレジストを形成する工程と、レジストを現像して、配線パターンとランド部となる箇所に溝部を有した所望のパターン形状にするための工程と、レジストを加熱して、レジストの上部の角部を丸める工程と、下地層に付着した状態で、溝部内に金属性の上部層を形成する工程と、レジストを除去する工程と、上部層が位置する下地層部分を除く下地層を除去する工程によって製造されて、配線パターンとランド部が下地層と上部層とで形成されると共に、レジストの除去工程、及び上部層が位置する下地層部分を除く下地層の除去工程によってアンダーカット部が形成された製造方法としたため、ランド部の端面におけるアンダーカット部の形成が確実で、生産性の良好なものが得られる。   A method of manufacturing a mounting substrate used for a semiconductor component mounting structure includes a semiconductor component mounting structure. The mounting substrate includes a step of forming a metallic base layer on an insulating substrate, and the base layer on the base layer. A step of forming a developable resist, a step of developing the resist to form a desired pattern shape having a groove portion at a portion to be a wiring pattern and a land portion, and heating the resist, The process of rounding corners, the process of forming a metallic upper layer in the groove while attached to the base layer, the process of removing the resist, and the base layer excluding the base layer portion where the upper layer is located are removed. The wiring pattern and the land portion are formed of the underlayer and the upper layer, and the undercover is removed by the resist removal step and the underlayer removal step excluding the underlayer portion where the upper layer is located. Since was prepared how isolation portion is formed, the formation of the undercut in the end face of the land portion is a reliable, having good productivity can be obtained.

また、上部層がメッキによって形成されると共に、下地層の除去がエッチングによって行われるため、その作業が容易で、生産性の良好なものが得られる。   Further, since the upper layer is formed by plating and the underlayer is removed by etching, the work is easy and a product with good productivity can be obtained.

本発明の半導体部品の実装構造、及びそれに使用される実装基板の製造方法に係る図面を説明すると、図１は本発明の半導体部品の実装構造の第１実施例に係る要部拡大断面図、図２は本発明の半導体部品の実装構造の第１実施例に係り、ランド部の構成を示す実装基板の要部の平面図、図３は本発明の半導体部品の実装構造の第２実施例に係り、ランド部の構成を示す実装基板の要部の平面図、図４は図３の４−４線における断面図、図５は本発明の半導体部品の実装構造の第３実施例に係り、ランド部の構成を示す実装基板の要部の平面図、図６は本発明の半導体部品の実装構造の第４実施例に係り、ランド部の構成を示す実装基板の要部の平面図、図７は本発明の半導体部品の実装構造の第５実施例に係り、ランド部の構成を示す実装基板の要部の平面図である。   BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view of an essential part of a semiconductor component mounting structure according to a first embodiment of the present invention; FIG. 2 relates to a first embodiment of a semiconductor component mounting structure according to the present invention. FIG. 3 is a plan view of an essential part of a mounting board showing the structure of a land portion, and FIG. 3 shows a second embodiment of a semiconductor component mounting structure according to the present invention. FIG. 4 is a sectional view taken along line 4-4 of FIG. 3, and FIG. 5 is a semiconductor component mounting structure according to a third embodiment of the present invention. FIG. 6 is a plan view of the main part of the mounting board showing the configuration of the land part according to the fourth embodiment of the semiconductor component mounting structure of the present invention, FIG. 7 relates to a fifth embodiment of the semiconductor component mounting structure according to the present invention, and shows the configuration of the land portion. It is a plan view of a main part of the plate.

また、図８は本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第１工程を示す説明図、図９は本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第２工程を示す説明図、図１０は本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第３工程を示す説明図、図１１は本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第４工程を示す説明図、図１２は本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第５工程を示す説明図、図１３は本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第６工程を示す説明図、図１４は本発明の半導体部品の実装構造の第６実施例に係る要部拡大断面図である。   FIG. 8 is an explanatory view showing a first step according to the method of manufacturing a mounting board used in the semiconductor component mounting structure of the present invention, and FIG. 9 shows the mounting board used in the semiconductor component mounting structure of the present invention. FIG. 10 is an explanatory view showing a second step according to the manufacturing method, FIG. 10 is an explanatory view showing a third step according to the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of the present invention, and FIG. 11 is a semiconductor component of the present invention. Explanatory drawing which shows the 4th process which concerns on the manufacturing method of the mounting substrate used for the mounting structure of FIG. 12, FIG. 12 is 5th description which concerns on the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of this invention. FIG. 13, FIG. 13 is an explanatory view showing a sixth step according to the method of manufacturing a mounting substrate used in the semiconductor component mounting structure of the present invention, and FIG. 14 relates to a sixth embodiment of the semiconductor component mounting structure of the present invention. It is a principal part expanded sectional view.

次に、本発明の半導体部品の実装構造の第１実施例に係る構成を図１，図２に基づいて説明すると、実装基板１は、絶縁基板２と、この絶縁基板２上に設けられた配線パターン３と、この配線パターン３の端部等に設けられたランド部４とで形成されている。   Next, the structure according to the first embodiment of the semiconductor component mounting structure of the present invention will be described with reference to FIGS. 1 and 2. The mounting substrate 1 is provided on the insulating substrate 2 and the insulating substrate 2. The wiring pattern 3 and the land portion 4 provided at the end of the wiring pattern 3 are formed.

また、ランド部４は、互いに間隔を置いて対向する少なくとも一対の端面４ａ、４ｂと、この端面４ａ、４ｂに設けられ、絶縁基板２側からランド部４の上面に向かって逆テーパー状となるようなアンダーカット部４ｃを有する。
即ち、アンダーカット部４ｃは、絶縁基板２側からランド部４の上面に向かって、ランド部４の上面面積が広くなるように傾斜状に形成されると共に、この第１実施例では、ランド部４が間隔を置いて配置された二つのランド部４で形成されている。
また、ランド部４には、一対の端面４ａ、４ｂ間に設けられ、ランド部４の削除部である溝部４ｄが設けられ、この溝部４ｄの少なくとも一端部は、ランド部４を除去して開放された開放部４ｅが設けられている。 The land portion 4 is provided on at least a pair of end surfaces 4a and 4b facing each other with a space therebetween and on the end surfaces 4a and 4b, and has a reverse taper shape from the insulating substrate 2 side toward the upper surface of the land portion 4. It has such an undercut part 4c.
That is, the undercut portion 4c is formed in an inclined shape so that the upper surface area of the land portion 4 increases from the insulating substrate 2 side toward the upper surface of the land portion 4, and in the first embodiment, the land portion 4 is formed by two land portions 4 arranged at intervals.
Further, the land portion 4 is provided with a groove portion 4d which is provided between the pair of end surfaces 4a and 4b and is a deletion portion of the land portion 4, and at least one end portion of the groove portion 4d is opened by removing the land portion 4. An open portion 4e is provided.

半導体チップ等からなる半導体部品５は、下面に複数の電極６が設けられ、この電極６には、金材等からなるバンプ７が付着されていると共に、電極６に付着したバンプ７は、ランド部４上に熱圧着されて、半導体部品５が実装基板１に実装されている。
この時、バンプ７は、ランド部４の端面４ａ、４ｂに形成された逆テーパー状のアンダーカット部４ｃに食い込んだ状態で、ランド部４に接合している。 A semiconductor component 5 made of a semiconductor chip or the like is provided with a plurality of electrodes 6 on the lower surface, and bumps 7 made of a gold material or the like are attached to the electrodes 6, and the bumps 7 attached to the electrodes 6 The semiconductor component 5 is mounted on the mounting substrate 1 by thermocompression bonding on the part 4.
At this time, the bump 7 is joined to the land portion 4 in a state of being bitten into the reverse tapered undercut portion 4c formed on the end surfaces 4a and 4b of the land portion 4.

また、半導体部品５の下面と絶縁基板２の上面との間には、アンダーフィル８を介在させて、半導体部品５の取付を強固にすると共に、溝部４ｄに介在したアンダーフィル８は、溝部４ｄ内に溜まることなく、開放部４ｅを通って溝部４ｄ外に流出するようになって、本発明の半導体部品の実装構造が構成されている。   In addition, an underfill 8 is interposed between the lower surface of the semiconductor component 5 and the upper surface of the insulating substrate 2 to strengthen the mounting of the semiconductor component 5, and the underfill 8 interposed in the groove portion 4 d has the groove portion 4 d. The semiconductor component mounting structure of the present invention is configured to flow out of the groove portion 4d through the open portion 4e without accumulating inside.

また、図３，図４は本発明の半導体部品の実装構造の第２実施例を示し、この第２実施例は、ランド部４の一端部をＵ字状に形成し、互いに間隔を置いて対向する一対の端面４ａ、４ｂには、絶縁基板２側からランド部４の上面に向かって逆テーパー状となるようなアンダーカット部４ｃを設けたものである。   3 and 4 show a second embodiment of the semiconductor component mounting structure of the present invention. In the second embodiment, one end of the land portion 4 is formed in a U-shape and spaced from each other. The pair of opposed end faces 4a and 4b are provided with undercut portions 4c that are reversely tapered from the insulating substrate 2 side toward the upper surface of the land portion 4.

なお、その他の構成は、上記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。   The other configurations are the same as those in the first embodiment, and the same parts are denoted by the same reference numerals, and the description thereof is omitted here.

また、図５は本発明の半導体部品の実装構造の第３実施例を示し、この第３実施例は、ランド部４の一部をＨ字状に形成し、互いに間隔を置いて対向する一対の端面４ａ、４ｂには、絶縁基板２側からランド部４の上面に向かって逆テーパー状となるようなアンダーカット部４ｃを設けたものである。   FIG. 5 shows a third embodiment of a semiconductor component mounting structure according to the present invention. In the third embodiment, a part of the land portion 4 is formed in an H shape and is opposed to each other with a space therebetween. The end surfaces 4a and 4b are provided with undercut portions 4c that are inversely tapered from the insulating substrate 2 side toward the upper surface of the land portion 4.

なお、その他の構成は、上記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。   The other configurations are the same as those in the first embodiment, and the same parts are denoted by the same reference numerals, and the description thereof is omitted here.

また、図６は本発明の半導体部品の実装構造の第４実施例を示し、この第４実施例は、ランド部４にＴ字状の溝部４ｄが形成され、互いに間隔を置いて対向する一対の端面４ａ、４ｂには、絶縁基板２側からランド部４の上面に向かって逆テーパー状となるようなアンダーカット部４ｃを設けたものである。   FIG. 6 shows a fourth embodiment of a semiconductor component mounting structure according to the present invention. In the fourth embodiment, a land portion 4 is formed with a T-shaped groove portion 4d and is opposed to each other with a gap therebetween. The end surfaces 4a and 4b are provided with undercut portions 4c that are inversely tapered from the insulating substrate 2 side toward the upper surface of the land portion 4.

なお、その他の構成は、上記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。   The other configurations are the same as those in the first embodiment, and the same parts are denoted by the same reference numerals, and the description thereof is omitted here.

また、図７は本発明の半導体部品の実装構造の第５実施例を示し、この第５実施例は、ランド部４の一部を十字状に形成し、互いに間隔を置いて対向する一対の端面４ａ、４ｂには、絶縁基板２側からランド部４の上面に向かって逆テーパー状となるようなアンダーカット部４ｃを設けたものである。   FIG. 7 shows a fifth embodiment of the semiconductor component mounting structure according to the present invention. In the fifth embodiment, a part of the land portion 4 is formed in a cross shape, and a pair of facing each other with a space therebetween. The end faces 4a and 4b are provided with undercut portions 4c that are reversely tapered from the insulating substrate 2 side toward the upper surface of the land portion 4.

なお、その他の構成は、上記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。   The other configurations are the same as those in the first embodiment, and the same parts are denoted by the same reference numerals, and the description thereof is omitted here.

次に、本発明の半導体部品の実装構造に使用される実装基板の製造方法を図８〜図１３に基づいて説明すると、先ず、図８に示すように、絶縁基板２上には、Ｔｉ層１１とＣｕ層１２の金属性の下地層１３を形成する工程を行う。
次に、この下地層１３上に現像可能なレジスト１４を形成する工程を行った後、図９に示すように、レジスト１４を現像して、配線パターン３とランド部４となる箇所に溝部１４ａを有した所望のパターン形状にするための工程を行う。 Next, a method for manufacturing a mounting substrate used in the semiconductor component mounting structure of the present invention will be described with reference to FIGS. 8 to 13. First, as shown in FIG. 8, a Ti layer is formed on the insulating substrate 2. 11 and a step of forming a metallic underlayer 13 of the Cu layer 12 are performed.
Next, after performing a step of forming a developable resist 14 on the base layer 13, the resist 14 is developed as shown in FIG. The process for making it into the desired pattern shape which has this is performed.

次に、図１０に示すように、レジスト１４を加熱（レジスト１４を焼き固める）して、レジスト１４の上部の角部を丸める（丸め部１４ｂを設ける）工程を行った後、図１１に示すように、下地層１３に付着した状態で、溝部１４ａ内には、メッキによってＣｕ層１５とＮｉ層１６の金属性の上部層１７を形成する工程を行う。   Next, as shown in FIG. 10, after the resist 14 is heated (resist 14 is baked and hardened), a corner of the upper portion of the resist 14 is rounded (rounded portion 14b is provided), and then shown in FIG. As described above, a process of forming the metallic upper layer 17 of the Cu layer 15 and the Ni layer 16 by plating is performed in the groove portion 14a while being attached to the base layer 13.

次に、図１２に示すように、レジスト１４を除去する工程を行った後、図１３に示すように、上部層１７が位置する下地層１３部分を除く下地層１３を除去する工程を行うと、本発明の実装基板１の製造が完了する。   Next, after performing the process of removing the resist 14 as shown in FIG. 12, the process of removing the base layer 13 excluding the part of the base layer 13 where the upper layer 17 is located is performed as shown in FIG. The manufacture of the mounting substrate 1 of the present invention is completed.

そして、図１３に示すように、配線パターン３とランド部４が下地層１３と上部層１７とで形成されると共に、レジスト１４の除去工程、及び上部層１７が位置する下地層１３部分を除く下地層１３の除去工程によってアンダーカット部４ｃが形成されるようになる。   Then, as shown in FIG. 13, the wiring pattern 3 and the land portion 4 are formed of the base layer 13 and the upper layer 17, and the resist 14 removal step and the base layer 13 portion where the upper layer 17 is located are excluded. The undercut portion 4c is formed by the removal process of the underlayer 13.

また、図１４は本発明の半導体部品の実装構造の第６実施例を示し、この第６実施例を説明すると、ランド部４は、絶縁基板２上に設けられた導電率の高い金属からなる下地層１８と、この下地層１８上に設けられ、下地層１８よりも硬い金属からなる第１の上部層１９と、この第１の上部層１９上に設けられた第２の上部層２０で形成されている。   FIG. 14 shows a sixth embodiment of the semiconductor component mounting structure according to the present invention. The sixth embodiment will be described. The land portion 4 is made of a metal with high conductivity provided on the insulating substrate 2. An underlayer 18, a first upper layer 19 provided on the underlayer 18 and made of a metal harder than the underlayer 18, and a second upper layer 20 provided on the first upper layer 19. Is formed.

そして、下地層１８は、１〜５μの厚みを有して、銅、又は銅を主成分とする合金、又は銀、又は銀を主成分とする合金で形成され、また、第１の上部層１９は、０．３〜３．０μの厚みを有して、ニッケルで形成されると共に、第２の上部層２０は、０．０３〜１．０μの厚みを有して、金によって形成されている。   The underlayer 18 has a thickness of 1 to 5 μm and is formed of copper, an alloy containing copper as a main component, silver, or an alloy containing silver as a main component, and the first upper layer. 19 has a thickness of 0.3 to 3.0 μm and is formed of nickel, and the second upper layer 20 has a thickness of 0.03 to 1.0 μm and is formed of gold. ing.

なお、その他の構成は、上記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。
また、この第５実施例における実装基板の製造方法は、上記で説明した製造方法とは下地層１８と上部１９，２０の材質が若干異なるが、上記製造方法と同様な工程で製造されるものである。 The other configurations are the same as those in the first embodiment, and the same parts are denoted by the same reference numerals, and the description thereof is omitted here.
Further, the manufacturing method of the mounting substrate in the fifth embodiment is manufactured in the same process as the manufacturing method described above, although the materials of the base layer 18 and the upper portions 19 and 20 are slightly different from the manufacturing method described above. It is.

本発明の半導体部品の実装構造の第１実施例に係る要部拡大断面図。The principal part expanded sectional view which concerns on 1st Example of the mounting structure of the semiconductor component of this invention. 本発明の半導体部品の実装構造の第１実施例に係り、ランド部の構成を示す実装基板の要部の平面図。The top view of the principal part of the mounting board which concerns on 1st Example of the mounting structure of the semiconductor component of this invention which shows the structure of a land part. 本発明の半導体部品の実装構造の第２実施例に係り、ランド部の構成を示す実装基板の要部の平面図。The top view of the principal part of the mounting board which concerns on 2nd Example of the mounting structure of the semiconductor component of this invention which shows the structure of a land part. 図３の４−４線における断面図。Sectional drawing in the 4-4 line | wire of FIG. 本発明の半導体部品の実装構造の第３実施例に係り、ランド部の構成を示す実装基板の要部の平面図。The top view of the principal part of the mounting board which concerns on 3rd Example of the mounting structure of the semiconductor component of this invention which shows the structure of a land part. 本発明の半導体部品の実装構造の第４実施例に係り、ランド部の構成を示す実装基板の要部の平面図。The top view of the principal part of the mounting board which concerns on 4th Example of the mounting structure of the semiconductor component of this invention which shows the structure of a land part. 本発明の半導体部品の実装構造の第５実施例に係り、ランド部の構成を示す実装基板の要部の平面図。The top view of the principal part of the mounting board which concerns on 5th Example of the mounting structure of the semiconductor component of this invention which shows the structure of a land part. 本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第１工程を示す説明図。Explanatory drawing which shows the 1st process which concerns on the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of this invention. 本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第２工程を示す説明図。Explanatory drawing which shows the 2nd process which concerns on the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of this invention. 本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第３工程を示す説明図。Explanatory drawing which shows the 3rd process which concerns on the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of this invention. 本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第４工程を示す説明図。Explanatory drawing which shows the 4th process which concerns on the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of this invention. 本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第５工程を示す説明図。Explanatory drawing which shows the 5th process which concerns on the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of this invention. 本発明の半導体部品の実装構造に使用される実装基板の製造方法に係る第６工程を示す説明図。Explanatory drawing which shows the 6th process which concerns on the manufacturing method of the mounting substrate used for the mounting structure of the semiconductor component of this invention. 本発明の半導体部品の実装構造の第６実施例に係る要部拡大断面図。The principal part expanded sectional view concerning 6th Example of the mounting structure of the semiconductor component of this invention. 従来の半導体部品の実装構造に係る要部拡大断面図。The principal part expanded sectional view which concerns on the mounting structure of the conventional semiconductor component. 従来の半導体部品の実装構造に係り、ランド部の構成を示す実装基板の要部の平面図。The top view of the principal part of the mounting board which concerns on the mounting structure of the conventional semiconductor component, and shows the structure of a land part.

符号の説明Explanation of symbols

１：実装基板
２：絶縁基板
３：配線パターン
４：ランド部
４ａ、４ｂ：端面
４ｃ：アンダーカット部
４ｄ：溝部
４ｅ：開放部
５：半導体部品
６：電極
７：バンプ
８：アンダーフィル
１１：Ｔｉ層
１２：Ｃｕ層
１３：下地層
１４：レジスト
１４ａ：溝部
１４ｂ：丸み部
１５：Ｃｕ層
１６：Ｎｉ層
１７：上部層
１８：下地層
１９：第１の上部層
２０：第２の上部層 1: Mounting board 2: Insulating board 3: Wiring pattern 4: Land part 4a, 4b: End face 4c: Undercut part 4d: Groove part 4e: Open part 5: Semiconductor component 6: Electrode 7: Bump 8: Underfill 11: Ti Layer 12: Cu layer 13: Underlayer 14: Resist 14a: Groove 14b: Round portion 15: Cu layer 16: Ni layer 17: Upper layer 18: Underlayer 19: First upper layer 20: Second upper layer

Claims (8)

配線パターンとランド部が設けられた絶縁基板を有する実装基板と、前記ランド部にバンプを介して前記実装基板に実装された半導体部品と、前記半導体部品と前記絶縁基板との間に介在したアンダーフィルとを備え、前記バンプが位置する前記ランド部の端面には、前記絶縁基板側から前記ランド部の上面に向かって逆テーパー状となるようなアンダーカット部が設けられ、前記アンダーカット部に前記バンプを食い込ませたことを特徴とする半導体部品の実装構造。 A mounting substrate having an insulating substrate provided with a wiring pattern and a land portion; a semiconductor component mounted on the mounting substrate via a bump on the land portion; and an underlayer interposed between the semiconductor component and the insulating substrate. An undercut portion having a reverse taper shape from the insulating substrate side toward the upper surface of the land portion is provided on the end surface of the land portion where the bump is located. A mounting structure of a semiconductor component, wherein the bump is bitten. 前記ランド部は、互いに間隔を置いて対向する少なくとも一対の前記端面を有し、この一対の前記端面に設けられた前記アンダーカット部には、前記バンプを食い込ませたことを特徴とする請求項１記載の半導体部品の実装構造。 The land portion has at least a pair of end surfaces facing each other with a space therebetween, and the bumps are bited into the undercut portions provided on the pair of end surfaces. 1. A mounting structure of a semiconductor component according to 1. 前記ランド部は、互いに間隔を置いて対向する少なくとも一対の前記端面と、この一対の端面間に設けられ、前記ランド部が削除された溝部と、この溝部の少なくとも一端側に設けられた開放部を有し、前記溝部に介在した前記アンダーフィルが前記開放部を通って流出するようにしたことを特徴とする請求項１、又は２記載の半導体部品の実装構造。 The land portion includes at least a pair of end surfaces facing each other with a space therebetween, a groove portion provided between the pair of end surfaces, the land portion being deleted, and an open portion provided on at least one end side of the groove portion. 3. The semiconductor component mounting structure according to claim 1, wherein the underfill interposed in the groove portion flows out through the open portion. 前記バンプが金材で形成されたことを特徴とする請求項１から３の何れかに記載の半導体部品の実装構造。 4. The semiconductor component mounting structure according to claim 1, wherein the bump is made of a gold material. 前記ランド部は、前記絶縁基板上に設けられた導電率の高い金属からなる下地層と、この下地層上に設けられ、前記下地層よりも硬い金属からなる第１の上部層と、この第１の上部層上に設けられた金材からなる第２の上部層で形成されたことを特徴とする請求項１から４の何れかに記載の半導体部品の実装構造。 The land portion includes a base layer made of a metal having high conductivity provided on the insulating substrate, a first upper layer provided on the base layer and made of a metal harder than the base layer, and the first layer. 5. The semiconductor component mounting structure according to claim 1, wherein the semiconductor component mounting structure is formed of a second upper layer made of a gold material provided on the upper layer of 1. 前記下地層は、銅、又は銅を主成分とする合金、又は銀、又は銀を主成分とする合金で形成されると共に、前記第１の上部層がニッケルで形成されたことを特徴とする請求項５記載の半導体部品の実装構造。 The underlayer is formed of copper, an alloy containing copper as a main component, silver, or an alloy containing silver as a main component, and the first upper layer is formed of nickel. The semiconductor component mounting structure according to claim 5. 請求項１から６の何れかに記載の半導体部品の実装構造を備え、前記実装基板は、前記絶縁基板上に金属性の下地層を形成する工程と、この下地層上に現像可能なレジストを形成する工程と、前記レジストを現像して、前記配線パターンと前記ランド部となる箇所に溝部を有した所望のパターン形状にするための工程と、前記レジストを加熱して、前記レジストの上部の角部を丸める工程と、前記下地層に付着した状態で、前記溝部内に金属性の上部層を形成する工程と、前記レジストを除去する工程と、前記上部層が位置する前記下地層部分を除く前記下地層を除去する工程によって製造されて、前記配線パターンと前記ランド部が前記下地層と前記上部層とで形成されると共に、前記レジストの除去工程、及び前記上部層が位置する前記下地層部分を除く前記下地層の除去工程によって前記アンダーカット部が形成されたことを特徴とする半導体部品の実装構造に使用される実装基板の製造方法。 The semiconductor component mounting structure according to claim 1, wherein the mounting substrate includes a step of forming a metallic base layer on the insulating substrate, and a developable resist on the base layer. Forming the resist, developing the resist to form a desired pattern shape having a groove in the portion to be the wiring pattern and the land, and heating the resist to form an upper portion of the resist. A step of rounding corners, a step of forming a metallic upper layer in the groove in a state attached to the base layer, a step of removing the resist, and the base layer portion where the upper layer is located. The wiring pattern and the land portion are formed of the base layer and the upper layer, and the resist is removed and the upper layer is located. The underlying layer manufacturing method of the mounting substrate used in the mounting structure of the semiconductor component, wherein the undercut portion is formed by the removal step, except the formation portion. 前記上部層がメッキによって形成されると共に、前記下地層の除去がエッチングによって行われることを特徴とする請求項７記載の半導体部品の実装構造に使用される実装基板の製造方法。 8. The method of manufacturing a mounting board for use in a semiconductor component mounting structure according to claim 7, wherein the upper layer is formed by plating and the underlayer is removed by etching.
JP2005118432A 2004-09-29 2005-04-15 Mounted structure for semiconductor component and method for manufacturing mounted substrate to be used therefor Withdrawn JP2006128606A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210591A (en) * 2005-01-27 2006-08-10 Matsushita Electric Ind Co Ltd Semiconductor apparatus and its manufacturing method
JP2010118534A (en) * 2008-11-13 2010-05-27 Mitsubishi Electric Corp Semiconductor device and method of manufacturing same
JP2017069013A (en) * 2015-09-30 2017-04-06 ミネベアミツミ株式会社 Planar lighting device
WO2023053412A1 (en) * 2021-09-30 2023-04-06 株式会社メイコー Substrate having lands for soldering
JP7454345B2 (en) 2019-08-08 2024-03-22 ローム株式会社 Semiconductor devices and their manufacturing methods, and electronic equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006210591A (en) * 2005-01-27 2006-08-10 Matsushita Electric Ind Co Ltd Semiconductor apparatus and its manufacturing method
JP4573657B2 (en) * 2005-01-27 2010-11-04 パナソニック株式会社 Semiconductor device and manufacturing method thereof
JP2010118534A (en) * 2008-11-13 2010-05-27 Mitsubishi Electric Corp Semiconductor device and method of manufacturing same
JP2017069013A (en) * 2015-09-30 2017-04-06 ミネベアミツミ株式会社 Planar lighting device
JP7454345B2 (en) 2019-08-08 2024-03-22 ローム株式会社 Semiconductor devices and their manufacturing methods, and electronic equipment
WO2023053412A1 (en) * 2021-09-30 2023-04-06 株式会社メイコー Substrate having lands for soldering

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