JP2006126817A - Display device and manufacturing method of device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique in which a display device having high picture quality and high reliability can be manufactured at a low cost with good yield. <P>SOLUTION: In this invention, a spacer is provided on a pixel electrode layer in a pixel region and on an insulation layer which functions as a partition that covers the periphery of the pixel electrode layer. When a light emitting material is formed on the pixel electrode region, a mask, which is used for selective formation, is supported by the spacer and occurrence of the contact to the pixel electrode layer by twisting and bending of the mask is prevented by the spacer. Thus, no scratch is generated on the pixel electrode layer by the mask, no shape failure of the pixel electrode layer is generated and the display device, which can conduct highly delicate display and has high reliability, can be manufactured. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device and a method for manufacturing the display device.

    In a display device including an electroluminescence (hereinafter, also referred to as EL) element, a color light emitting element that emits color light is used for full color display. In order to form a color light emitting element, it is one of the important elements to form a light emitting material of each color in a fine pattern on an electrode.

    For the above purpose, a method of forming a fine pattern using a mask is generally used when a material is formed using a vapor deposition method or the like.

However, due to miniaturization of the pixel region accompanying high-definition and an increase in size of the substrate accompanying an increase in area, defects due to the accuracy and deflection of the mask used during vapor deposition have become problems. Research aimed at increasing the accuracy and reliability of the evaporation mask has been reported (for example, see Patent Document 1).
JP 2000-129419 A

    An object of the present invention is to provide a technique capable of manufacturing a display device having high sensitivity and high reliability with high yield without complicating processes and devices.

    The present invention includes spacers on the pixel electrode layer in the pixel region and on the insulating layer functioning as a partition covering the periphery of the pixel electrode layer. When the light emitting material is formed on the pixel electrode layer by this spacer, the mask for selective formation is supported and prevents the pixel electrode layer from coming into contact with the mask due to kinking or deflection. Therefore, the pixel electrode layer is not damaged by a mask or the like, and the pixel electrode layer does not have a defective shape. Therefore, a highly reliable display device that performs highly delicate display can be manufactured.

    A display device to which the present invention can be used includes a light-emitting element and a thin film transistor (hereinafter also referred to as TFT) in which a layer containing an organic substance that emits light called electroluminescence or a mixture of an organic substance and an inorganic substance is interposed between electrodes. And a light emitting display device connected to each other.

    One display device of the present invention includes a first spacer on a first electrode layer, an insulating layer (insulator) that covers an end portion of the first electrode layer, and a first spacer on the insulating layer. 2 spacers, an electroluminescent layer on the first electrode layer and the first spacer, and a second electrode layer on the electroluminescent layer.

    One display device of the present invention includes a first spacer on a first electrode layer, an insulating layer (insulator) that covers an end portion of the first electrode layer, and a first spacer on the insulating layer. Two spacers, an electroluminescent layer on the first electrode layer and the first spacer, a second electrode layer on the electroluminescent layer, and the insulating layer and the first spacer are made of the same material Consists of.

    One display device of the present invention includes a first spacer on a first electrode layer, an insulating layer (insulator) that covers an end portion of the first electrode layer, and a first spacer on the insulating layer. 2 spacers, an electroluminescent layer on the first electrode layer and the first spacer, a second electrode layer on the electroluminescent layer, the first spacer and the second spacer are Made of the same material.

    In the above configuration, the first spacer and the insulating layer may be separated as shown in FIGS. 25 and 30, or may be continuously connected as shown in FIGS. Similarly, the first spacer and the second spacer may be separated or may be continuously connected. When the electroluminescent layer is formed on the first electrode layer functioning as the pixel electrode layer, the first spacer and the second spacer not only serve as a spacer for the mask to be used, but also form the electroluminescent layer, Even after sealing with a sealing substrate to complete a display device, the display device functions as a spacer that prevents damage and deformation due to external pressure and impact.

    One embodiment of a method for manufacturing a display device of the present invention is to form a first electrode layer, an insulating layer (insulator) that covers an end portion of the first electrode layer, and a first spacer on the first electrode layer. , A second spacer is formed on the insulating layer, an electroluminescent layer is formed on the first electrode layer and the first spacer, and a second electrode layer is formed on the electroluminescent layer.

    According to one embodiment of the method for manufacturing a display device of the present invention, a first electrode layer is formed, an insulating layer (insulator) covering an end portion of the first electrode layer, and a first spacer on the first electrode layer A mask is provided in contact with the second spacer, and an electroluminescent layer is selectively formed on the first electrode layer and the first spacer, and a second electrode layer is formed on the electroluminescent layer. .

    According to one method for manufacturing a display device of the present invention, a first electrode layer is formed, an insulating layer (insulator) that covers an end portion of the first electrode layer is formed, and the first electrode layer is formed over the first electrode layer. A second spacer is formed over the spacer and the insulating layer, an electroluminescent layer is formed over the first electrode layer and the first spacer, and a second electrode layer is formed over the electroluminescent layer.

    According to one method for manufacturing a display device of the present invention, a first electrode layer is formed, an insulating layer (insulator) edge covering an end portion of the first electrode layer is formed, the first electrode layer, An insulating film (insulating layer) is formed on the insulating layer, and the insulating film is processed to form a first spacer on the first electrode layer and a second spacer on the insulating layer, and the first electrode layer An electroluminescent layer is formed on the first spacer, and a second electrode layer is formed on the electroluminescent layer.

    According to one method for manufacturing a display device of the present invention, a first electrode layer is formed, an insulating layer (insulator) that covers an end portion of the first electrode layer is formed, and the first electrode layer is formed over the first electrode layer. A second spacer is formed over the spacer and the insulating layer, a mask is provided in contact with the second spacer, an electroluminescent layer is selectively formed over the first electrode layer and the first spacer, and an electric field is formed. A second electrode layer is formed on the light emitting layer.

    By using the present invention, a highly reliable display device can be manufactured through a simplified process. Therefore, a high-definition and high-quality display device can be manufactured at a low cost and with a high yield.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
A method for manufacturing the thin film transistor in this embodiment will be described in detail with reference to FIGS.

    FIG. 16A is a top view illustrating a structure of a display panel according to the present invention. A pixel portion 2701 in which pixels 2702 are arranged in a matrix over a substrate 2700 having an insulating surface, a scan line side input terminal 2703, a signal A line side input terminal 2704 is formed. The number of pixels may be provided in accordance with various standards. For XGA, 1024 × 768 × 3 (RGB), for UXGA, 1600 × 1200 × 3 (RGB), and for full specification high vision, 1920 × 1080. X3 (RGB) may be used.

    The pixels 2702 are arranged in a matrix by a scan line extending from the scan line side input terminal 2703 and a signal line extending from the signal line side input terminal 2704 intersecting. Each of the pixels 2702 includes a switching element and a pixel electrode layer connected to the switching element. A typical example of a switching element is a TFT. By connecting the gate electrode layer side of the TFT to a scanning line and the source or drain side to a signal line, each pixel can be controlled independently by a signal input from the outside. It is said.

    A TFT includes a semiconductor layer, a gate insulating layer, and a gate electrode layer as main components, and a wiring layer connected to a source region and a drain region formed in the semiconductor layer is attached to the TFT. Structurally, the top gate type in which the semiconductor layer, the gate insulating layer and the gate electrode layer are arranged from the substrate side, and the bottom gate type in which the gate electrode layer, the gate insulating layer and the semiconductor layer are arranged from the substrate side are representative. In the present invention, any of those structures may be used.

    FIG. 16A shows a structure of a display panel in which signals input to the scanning lines and the signal lines are controlled by an external driver circuit. As shown in FIG. 17A, a COG (Chip on The driver IC 2751 may be mounted on the substrate 2700 by the Glass method. As another mounting mode, a TAB (Tape Automated Bonding) method as shown in FIG. 17B may be used. The driver IC may be formed on a single crystal semiconductor substrate or may be a circuit in which a TFT is formed on a glass substrate. In FIG. 17, a driver IC 2751 is connected to an FPC (Flexible printed circuit) 2750.

    In the case where the TFT provided for the pixel is formed using a crystalline semiconductor, the scan line driver circuit 3702 can be formed over the substrate 3700 as shown in FIG. In FIG. 16B, the pixel portion 3701 is controlled by an external driver circuit as in FIG. 16A connected to the signal line side input terminal 3704. In the case where a TFT provided for a pixel is formed using a polycrystalline (microcrystalline) semiconductor, a single crystal semiconductor, or the like with high mobility, FIG. 16C illustrates a pixel portion 4701, a scan line driver circuit 4702, and a signal line driver circuit. 4704 can be integrally formed on the substrate 4700.

    Silicon nitride oxide by a sputtering method, a PVD method (Physical Vapor Deposition), a low pressure CVD method (LPCVD method), or a CVD method (Chemical Vapor Deposition) such as a plasma CVD method as a base film on the substrate 100 having an insulating surface A base film 101a is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm) using a film (SiNO), and a base film 101b is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm) using a silicon oxynitride film (SiON). . In this embodiment, the base film 101a and the base film 101b are formed by a plasma CVD method. As the substrate 100, a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used, or a flexible substrate such as a film may be used. As the plastic substrate, a substrate made of PET (polyethylene terephthalate), PEN (polyethylene naphthalate) or PES (polyethersulfone) can be used, and as the flexible substrate, a synthetic resin such as acrylic can be used.

As the base film, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used, and a single layer or a laminated structure of two layers or three layers may be used. Note that in this specification, silicon oxynitride is a substance in which the oxygen composition ratio is higher than the nitrogen composition ratio, and can also be referred to as silicon oxide containing nitrogen. Similarly, silicon nitride oxide is a substance in which the composition ratio of nitrogen is higher than the composition ratio of oxygen, and can be said to be silicon nitride containing oxygen. In this embodiment, a silicon nitride oxide film having a thickness of 50 nm is formed on a substrate using SiH ₄ , NH ₃ , N ₂ O, N _2, and H ₂ as reactive gases, and oxidized using SiH ₄ and N ₂ O as reactive gases. A silicon nitride film is formed with a thickness of 100 nm. The thickness of the silicon nitride oxide film may be 140 nm, and the thickness of the stacked silicon oxynitride film may be 100 nm.

    A silicon nitride film or a silicon nitride oxide film with a thickness of 0.3 nm to 5 nm is preferably formed as the uppermost layer of the base film in contact with the semiconductor layer. In this embodiment mode, a metal element that promotes crystallization (nickel is used in this embodiment mode) is added to the semiconductor layer, and then gettering treatment is performed for removal. Although the interface state between the silicon oxide film and the silicon film is good, a metal element in the silicon film reacts with oxygen in the silicon oxide at the interface to react with a metal oxide (in this embodiment, nickel oxide (NiOx)). In some cases, the metal element is difficult to getter. Further, the silicon nitride film may adversely affect the interface state with the semiconductor layer due to the stress of the silicon nitride film and the influence of traps. Therefore, a silicon nitride film or a silicon nitride oxide film with a thickness of 0.3 to 5 nm is formed as the uppermost layer of the insulating layer in contact with the semiconductor layer. In this embodiment, after a silicon nitride oxide film and a silicon oxynitride film are stacked over the substrate 100, a silicon nitride oxide film with a thickness of 0.3 nm to 5 nm is formed over the silicon oxynitride film, and three layers are stacked. Structure. With such a structure, the gettering efficiency of the metal element in the semiconductor layer is increased, and the adverse effect of the silicon nitride film on the semiconductor layer can be reduced. The insulating layer to be stacked is preferably formed continuously while switching the reaction gas at the same temperature without breaking the vacuum in the same chamber. If formed continuously without breaking the vacuum, it is possible to prevent the interface between the stacked films from being contaminated.

    Next, a semiconductor film is formed over the base film. The semiconductor film may be formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) with a thickness of 25 to 200 nm (preferably 30 to 150 nm). In this embodiment mode, it is preferable to use a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film by laser crystallization.

    As a material for forming the semiconductor film, an amorphous semiconductor (hereinafter also referred to as “amorphous semiconductor: AS”) manufactured by a vapor deposition method or a sputtering method using a semiconductor material gas typified by silane or germane is used. A polycrystalline semiconductor obtained by crystallizing a crystalline semiconductor using light energy or thermal energy, or a semi-amorphous (also referred to as microcrystal or microcrystal; hereinafter, also referred to as “SAS”) semiconductor can be used.

SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is the main component, the Raman spectrum shifts to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. The SAS is formed by glow discharge decomposition (plasma CVD) of a silicide gas. As the silicide gas, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, F ₂ and GeF ₄ may be mixed. This silicide gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times, the pressure is in the range of approximately 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature is preferably 300 ° C. or lower, and can be formed even at a substrate heating temperature of 100 to 200 ° C. Here, as an impurity element mainly taken in at the time of film formation, it is desirable that impurities derived from atmospheric components such as oxygen, nitrogen, and carbon be 1 × 10 ²⁰ cm ⁻³ or less, and in particular, the oxygen concentration is 5 × 10 5. It is preferable to be ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. Further, by adding a rare gas element such as helium, argon, krypton, or neon to further promote lattice distortion, stability is improved and a favorable SAS can be obtained. Alternatively, a SAS layer formed of a silicide gas containing hydrogen may be stacked on a SAS layer formed of a silicide gas containing fluorine as a semiconductor film.

    A typical example of an amorphous semiconductor is hydrogenated amorphous silicon, and a typical example of a crystalline semiconductor is polysilicon. Polysilicon (polycrystalline silicon) is mainly made of so-called high-temperature polysilicon using polysilicon formed through a process temperature of 800 ° C. or higher as a main material, or polysilicon formed at a process temperature of 600 ° C. or lower. And so-called low-temperature polysilicon, and polysilicon crystallized by adding an element that promotes crystallization. Needless to say, as described above, a semi-amorphous semiconductor or a semiconductor containing a crystal phase in part of a semiconductor film can also be used.

  When a large substrate such as 30 inches or 40 inches is used, if an amorphous semiconductor such as amorphous silicon is used, the process is not complicated and the productivity is good.

In the case where a crystalline semiconductor film is used as the semiconductor film, a method for manufacturing the crystalline semiconductor film can be a known method (laser crystallization method, thermal crystallization method, or heat using an element that promotes crystallization such as nickel. A crystallization method or the like may be used. In addition, a microcrystalline semiconductor that is a SAS can be crystallized by laser irradiation to improve crystallinity. In the case where an element for promoting crystallization is not introduced, the concentration of hydrogen contained in the amorphous semiconductor film is set to 1 × by heating at 500 ° C. for 1 hour in a nitrogen atmosphere before irradiating the amorphous semiconductor film with laser light. Release to 10 ²⁰ atoms / cm ³ or less. This is because when an amorphous semiconductor film containing a large amount of hydrogen is irradiated with laser light, the amorphous semiconductor film is destroyed. As the heat treatment for crystallization, a heating furnace, laser irradiation, irradiation with light emitted from a lamp (also referred to as lamp annealing), or the like can be used. As a heating method, there are RTA methods such as a GRTA (Gas Rapid Thermal Anneal) method and an LRTA (Lamp Rapid Thermal Anneal) method.

    The method of introducing the metal element into the amorphous semiconductor film is not particularly limited as long as the metal element can be present on the surface of the amorphous semiconductor film or inside the amorphous semiconductor film. For example, sputtering, CVD, A plasma treatment method (including a plasma CVD method), an adsorption method, or a method of applying a metal salt solution can be used. Among these, the method using a solution is simple and useful in that the concentration of the metal element can be easily adjusted. At this time, in order to improve the wettability of the surface of the amorphous semiconductor film and to spread the aqueous solution over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, hydroxy radical It is desirable to form an oxide film by treatment with ozone water or hydrogen peroxide.

By using a solid-state laser capable of continuous oscillation and irradiating laser light of the second to fourth harmonics of the fundamental wave, a crystal having a large grain size can be obtained. For example, typically, it is desirable to use the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm). Specifically, laser light emitted from a continuous wave YVO ₄ laser is converted into a harmonic by a non-linear optical element to obtain laser light having an output number of W or more. Then, it is preferably formed into a rectangular or elliptical laser beam on the irradiation surface by an optical system and irradiated onto the semiconductor film. At this time, the energy density of about 0.001~100MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 0.5 to 2000 cm / sec (preferably 10 to 200 cm / sec).

    The laser beam shape is preferably linear. As a result, throughput can be improved. Further, the laser may be irradiated with an incident angle θ (0 <θ <90 degrees) with respect to the semiconductor film. This is because laser interference can be prevented.

    Laser irradiation can be performed by relatively scanning such a laser and the semiconductor film. In laser irradiation, a marker can be formed in order to superimpose beams with high accuracy and to control the laser irradiation start position and laser irradiation end position. The marker may be formed on the substrate simultaneously with the amorphous semiconductor film.

As the laser, a continuous wave or pulsed gas laser, solid state laser, copper vapor laser, gold vapor laser, or the like can be used. Examples of gas lasers include excimer lasers, Ar lasers, Kr lasers, and He-Cd lasers. Solid state lasers include YAG lasers, YVO ₄ lasers, YLF lasers, YAlO ₃ lasers, Y ₂ O ₃ lasers, glass lasers, and ruby lasers. Alexandrite laser, Ti: sapphire laser, and the like.

    Further, the laser crystallization may be performed using a frequency band significantly higher than a frequency band of several tens to several hundreds Hz that is usually used with an oscillation frequency of pulsed laser light of 0.5 MHz or more. It is said that the time from irradiating a semiconductor film with laser light by pulse oscillation until the semiconductor film is completely solidified is several tens to several hundreds nsec. Therefore, by using the above frequency band, it is possible to irradiate the next pulse of laser light from when the semiconductor film is melted by the laser light to solidification. Accordingly, since the solid-liquid interface can be continuously moved in the semiconductor film, a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, a semiconductor film having almost no crystal grain boundary at least in the channel direction of the thin film transistor can be formed.

    Further, laser light may be irradiated in an inert gas atmosphere such as a rare gas or nitrogen. Accordingly, the surface roughness of the semiconductor can be suppressed by laser light irradiation, and variations in threshold values caused by variations in interface state density can be suppressed.

    Crystallization of the amorphous semiconductor film may be a combination of heat treatment and crystallization by laser light irradiation, or may be performed multiple times by heat treatment or laser light irradiation alone.

In this embodiment, an amorphous semiconductor film is formed over the base film 101b, and the crystalline semiconductor film is formed by crystallizing the amorphous semiconductor film. As the amorphous semiconductor film, amorphous silicon formed using a reaction gas of SiH ₄ and H ₂ is used. In this embodiment mode, the base film 101a, the base film 101b, and the amorphous semiconductor film are formed continuously while switching the reaction gas at the same temperature of 330 ° C. without breaking the vacuum in the same chamber.

    After removing the oxide film formed on the amorphous semiconductor film, the oxide film is made 1 by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydrogen radicals or hydrogen peroxide, and the like. Form ~ 5 nm. In this embodiment mode, Ni is used as an element for promoting crystallization. An aqueous solution containing 10 ppm of Ni acetate is applied by spin coating.

    In this embodiment, after heat treatment is performed at 650 ° C. for 6 minutes by an RTA method, an oxide film formed over the semiconductor film is removed and laser light is irradiated. The amorphous semiconductor film is crystallized by the above crystallization treatment and formed as a crystalline semiconductor film.

    When crystallization using a metal element is performed, a gettering step is performed in order to reduce or remove the metal element. In this embodiment mode, a metal element is captured using an amorphous semiconductor film as a gettering sink. First, an oxide film is formed over the crystalline semiconductor film by irradiation with UV light in an oxygen atmosphere, a thermal oxidation method, treatment with ozone water containing hydroxyl radicals or hydrogen peroxide, and the like. The oxide film is preferably thickened by heat treatment. In this embodiment, after the oxide film is formed, the oxide film is thickened by performing heat treatment at 650 ° C. for 6 minutes by the RTA method. Next, an amorphous semiconductor film is formed to a thickness of 30 nm by a plasma CVD method (conditions 350 W and 35 Pa in this embodiment).

  Thereafter, heat treatment is performed at 650 ° C. for 6 minutes by the RTA method to reduce or remove the metal element. The heat treatment may be performed in a nitrogen atmosphere. Then, the amorphous semiconductor film serving as the gettering sink and the oxide film formed over the amorphous semiconductor film are removed by hydrofluoric acid or the like, and the crystalline semiconductor film 102 in which the metal element is reduced or removed is removed. Can be obtained (see FIG. 2A). In this embodiment mode, the amorphous semiconductor film serving as a gettering sink is removed using TMAH (Tetramethyl ammonium hydroxide).

    In order to control the threshold voltage of the thin film transistor, the semiconductor film thus obtained may be doped with a trace amount of impurity element (boron or phosphorus). This doping of the impurity element may be performed on the amorphous semiconductor film before the crystallization step. When the impurity element is doped in the state of the amorphous semiconductor film, the impurity can be activated by heat treatment for subsequent crystallization. In addition, defects and the like generated during doping can be improved.

    Next, the crystalline semiconductor film 102 is processed into a desired shape using a mask. In this embodiment mode, after the oxide film formed over the crystalline semiconductor film 102 is removed, a new oxide film is formed. Then, a photomask is manufactured, and the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, and the semiconductor layer 106 are formed by etching processing using a photolithography method.

As the etching process, either plasma etching (dry etching) or wet etching may be employed, but plasma etching is suitable for processing a large area substrate. As an etching gas, a gas containing fluorine such as CF ₄ or NF ₃ or a gas containing chlorine such as Cl ₂ or BCl ₃ may be used, and an inert gas such as He or Ar may be added as appropriate. Further, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    In the present invention, a conductive layer for forming a wiring layer or an electrode layer, a mask layer for forming a predetermined pattern, or the like may be formed by a method capable of selectively forming a pattern such as a droplet discharge method. . A droplet discharge (ejection) method (also called an ink-jet method depending on the method) is a method in which a droplet of a composition prepared for a specific purpose is selectively ejected (ejection) to form a predetermined pattern (such as a conductive layer or a conductive layer). An insulating layer or the like can be formed. At this time, a process for controlling wettability and adhesion may be performed on the formation region. In addition, a method by which a pattern can be transferred or drawn, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) can be used.

  In this embodiment mode, a resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin is used as a mask to be used. Further, organic materials such as benzocyclobutene, parylene and polyimide, compound materials obtained by polymerization of siloxane polymers, composition materials containing water-soluble homopolymers and water-soluble copolymers, and the like can also be used. Alternatively, a commercially available resist material containing a photosensitizer may be used. For example, a novolak resin that is a typical positive resist and a naphthoquinonediazide compound that is a photosensitizer, a base resin that is a negative resist, diphenylsilanediol, and An acid generator or the like may be used. When using the droplet discharge method, regardless of which material is used, the surface tension and viscosity are appropriately adjusted by adjusting the concentration of the solvent or adding a surfactant or the like.

    The oxide film over the semiconductor layer is removed, and a gate insulating layer 107 is formed to cover the semiconductor layer 103, the semiconductor layer 104, the semiconductor layer 105, and the semiconductor layer 106. The gate insulating layer 107 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm using a plasma CVD method, a sputtering method, or the like. The gate insulating layer 107 may be formed using a known material such as silicon nitride, silicon oxide, silicon oxynitride, or silicon oxide or nitride material typified by silicon nitride oxide, and may be a stacked layer or a single layer. . In this embodiment, the gate insulating layer is a three-layer stack including a silicon nitride film, a silicon oxide film, and a silicon nitride film. Alternatively, a single layer or a double layer of silicon oxynitride film may be used. A silicon nitride film having a dense film quality is preferably used. Further, a thin silicon oxide film with a thickness of 1 to 100 nm, preferably 1 to 10 nm, more preferably 2 to 5 nm may be formed between the semiconductor layer and the gate insulating layer. As a method for forming a thin silicon oxide film, a thin silicon oxide film can be formed by oxidizing the surface of the semiconductor region using a GRTA method, an LRTA method, or the like to form a thermal oxide film. Note that in order to form a dense insulating film with low gate leakage current at a low deposition temperature, a rare gas element such as argon is preferably contained in the reaction gas and mixed into the formed insulating film.

    Next, a first conductive film 108 with a thickness of 20 to 100 nm and a second conductive film 109 with a thickness of 100 to 400 nm used as a gate electrode layer are stacked over the gate insulating layer 107 (FIG. 2 ( See B). The first conductive film 108 and the second conductive film 109 can be formed by a known method such as a sputtering method, an evaporation method, or a CVD method. The first conductive film 108 and the second conductive film 109 are tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), neodymium. An element selected from (Nd) or an alloy material or compound material containing the element as a main component may be used. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film 108 and the second conductive film 109. The structure is not limited to a two-layer structure. For example, a tungsten film with a thickness of 50 nm is used as the first conductive film, an aluminum-silicon alloy (Al-Si) film with a thickness of 500 nm is used as the second conductive film, The conductive film may have a three-layer structure in which titanium nitride films with a thickness of 30 nm are sequentially stacked. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient. In this embodiment, tantalum nitride (TaN) is formed to a thickness of 30 nm as the first conductive film 108 and tungsten (W) is formed to a thickness of 370 nm as the second conductive film 109.

Next, a resist mask 110a, a mask 110b, a mask 110c, a mask 110d, and a mask 110f are formed by photolithography, and the first conductive film 108 and the second conductive film 108 are processed into desired shapes. The first gate electrode layer 121, the first gate electrode layer 122, the conductive layer 123, the first gate electrode layer 124, the first gate electrode layer 125, the first gate electrode layer 126, and the conductive layer 111, a conductive layer 112, a conductive layer 113, a conductive layer 114, a conductive layer 115, and a conductive layer 116 are formed (see FIG. 2C). Using ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode layer, amount of power applied to electrode layer on substrate side, electrode temperature on substrate side, etc.) By appropriately adjusting the first gate electrode layer 121, the first gate electrode layer 122, the conductive layer 123, the first gate electrode layer 124, the first gate electrode layer 125, and the first gate electrode layer 126, and the conductive layer 111, the conductive layer 112, the conductive layer 113, the conductive layer 114, the conductive layer 115, and the conductive layer 116 can be etched to have a desired tapered shape. The taper shape can be controlled in angle and the like by the shapes of the mask 110a, the mask 110b, the mask 110c, the mask 110d, and the mask 110f. As the etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , CF ₅ , SF ₆ or NF _3, or O ₂ Can be used as appropriate. In this embodiment, the second conductive film 109 is etched using an etching gas composed of CF ₅ , Cl ₂ , and O ₂ , and then continuously etched using an etching gas composed of CF ₅ and Cl ₂ . The first conductive film 108 is etched.

Next, the conductive layer 111, the conductive layer 112, the conductive layer 113, the conductive layer 114, the conductive layer 115, and the conductive layer 116 are formed into desired shapes using the mask 110a, the mask 110b, the mask 110c, the mask 110d, and the mask 110f. To process. At this time, the conductive layer is etched under an etching condition with a high selection ratio between the second conductive film 109 that forms the conductive layer and the first conductive film 108 that forms the first gate electrode layer. By this etching, the conductive layer 111, the conductive layer 112, the conductive layer 113, the conductive layer 114, the conductive layer 115, and the conductive layer 116 are etched, and the second gate electrode layer 131, the second gate electrode layer 132, and the conductive layer are etched. 133, a second gate electrode layer 134, a second gate electrode layer 135, and a second gate electrode layer 136 are formed. In this embodiment mode, the third conductive layer also has a tapered shape, and the taper angles thereof are the first gate electrode layer 121, the first gate electrode layer 122, the conductive layer 123, and the first gate electrode. It is larger than the taper angle of the layer 124, the first gate electrode layer 125, and the first gate electrode layer 126. Note that the taper angle is an angle of a side surface with respect to the surfaces of the first gate electrode layer, the second gate electrode layer, and the conductive layer. Therefore, when the taper angle is increased and the angle is 90 degrees, the conductive layer has a vertical side surface and does not have a tapered shape. In this embodiment mode, Cl ₂ , SF ₆ , and O ₂ are used as etching gases for forming the second gate electrode layer.

    In this embodiment, since the first gate electrode layer, the conductive layer, and the second gate electrode layer are formed to have a tapered shape, both of the two gate electrode layers have a tapered shape. However, the present invention is not limited thereto, and only one gate electrode layer may have a tapered shape, and the other may have a vertical side surface by anisotropic etching. As in this embodiment, the taper angle may be different between the stacked gate electrode layers, or may be the same. By having a tapered shape, the coverage of a film stacked thereon is improved and defects are reduced, so that reliability is improved.

    Through the above steps, the peripheral driver circuit region 204 includes the gate electrode layer 117 including the first gate electrode layer 121 and the second gate electrode layer 131, and includes the first gate electrode layer 122 and the second gate electrode layer 132. The gate electrode layer 118 includes a gate electrode layer 127 including a first gate electrode layer 124 and a second gate electrode layer 134, and a gate electrode including a first gate electrode layer 125 and a second gate electrode layer 135. The gate electrode layer 129 including the layer 128, the first gate electrode layer 126 and the second gate electrode layer 136, and the conductive layer 130 including the conductive layer 123 and the conductive layer 133 can be formed in the connection region 205 (FIG. 2). (See (D).) In this embodiment mode, the gate electrode layer is formed by dry etching, but may be wet etching.

    The gate insulating layer 107 may be slightly etched by an etching process when forming the gate electrode layer, and the film thickness may be reduced (so-called film reduction).

    When forming the gate electrode layer, a thin film transistor capable of high-speed operation can be formed by reducing the width of the gate electrode layer. Two methods for forming the gate electrode layer with a narrow width in the channel direction are described below.

    In the first method, after a mask for the gate electrode layer is formed, the mask is thinned by etching, ashing, or the like in the width direction to form a mask having a narrower width. By using a mask formed in advance in a narrow shape, the gate electrode layer can also be formed in a narrow shape.

    Next, in the second method, a mask is formed, and a gate electrode layer is formed using the mask. Next, the obtained gate electrode layer is further thinned by side etching in the width direction. Therefore, a narrow gate electrode layer can be finally formed. Through the above steps, a thin film transistor with a short channel length can be formed later, and a thin film transistor capable of high-speed operation can be manufactured.

Next, an impurity element 151 imparting n-type conductivity is added using the gate electrode layer 117, the gate electrode layer 118, the gate electrode layer 127, the gate electrode layer 128, the gate electrode layer 129, and the conductive layer 130 as masks, n-type impurity region 140a, first n-type impurity region 140b, first n-type impurity region 141a, first n-type impurity region 141b, first n-type impurity region 142a, first n-type impurity region 142b A first n-type impurity region 142c, a first n-type impurity region 143a, and a first n-type impurity region 143b are formed (see FIG. 3A). In this embodiment, phosphine (PH ₃ ) (the doping gas is obtained by diluting PH ₃ with hydrogen (H ₂ ), and the ratio of PH _{3 in} the gas is 5%) is used as a doping gas containing an impurity element. Doping is performed at a gas flow rate of 80 sccm, a beam current of 54 μA / cm, an acceleration voltage of 50 kV, and an added dose of 7.0 × 10 ¹³ ions / cm ² . Here, the first n-type impurity region 140a, the first n-type impurity region 140b, the first n-type impurity region 141a, the first n-type impurity region 141b, the first n-type impurity region 142a, the first In the n-type impurity region 142b, the first n-type impurity region 142c, the first n-type impurity region 143a, and the first n-type impurity region 143b, an impurity element imparting n-type conductivity is 1 × 10 ^{17 to} 5 ×. Add so that it is contained at a concentration of about 10 ¹⁸ / cm ³ . In this embodiment mode, phosphorus (P) is used as the impurity element imparting n-type conductivity.

  In this embodiment, a region where the impurity region overlaps with the gate electrode layer through the gate insulating layer is referred to as a Lov region, and a region where the impurity region does not overlap with the gate electrode layer through the gate insulating layer is referred to as a Loff region. In FIG. 3, hatching and white background are shown in the impurity region, but this does not indicate that the impurity element is not added to the white background part, but the concentration distribution of the impurity element in this region is mask or doping. This is because it is possible to intuitively understand that the conditions are reflected. This also applies to other drawings in this specification.

Next, a mask 153a, a mask 153b, a mask 153c, and a mask 153d that cover the semiconductor layer 103, part of the semiconductor layer 105, and the semiconductor layer 106 are formed. An n-type impurity element 152 is added using the mask 153a, the mask 153b, the mask 153c, the mask 153d, and the second gate electrode layer 132 as a mask, and the second n-type impurity region 144a and the second n-type impurity region are added. 144b, a third n-type impurity region 145a, a third n-type impurity region 145b, a second n-type impurity region 147a, a second n-type impurity region 147b, a second n-type impurity region 147c, a third An n-type impurity region 148a, a third n-type impurity region 148b, a third n-type impurity region 148c, and a third n-type impurity region 148d are formed. In this embodiment, PH ₃ (doping gas is PH ₃ diluted with hydrogen (H ₂ ), and the ratio of PH _{3 in} the gas is 5%) is used as a doping gas containing an impurity element, and the gas flow rate is 80 sccm. The doping is performed at a beam current of 540 μA / cm, an acceleration voltage of 70 kV, and a dose of 5.0 × 10 ¹⁵ ions / cm ² to be added. Here, the second n-type impurity region 144a and the second n-type impurity region 144b are added so that the impurity element imparting n-type is included at a concentration of about 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. To do. The third n-type impurity region 145a and the third n-type impurity region 145b include a third n-type impurity region 148a, a third n-type impurity region 148b, a third n-type impurity region 148c, and a third n-type impurity region 148a. It is formed so as to contain an impurity element imparting n-type at a concentration similar to or slightly higher than that of the type impurity region 148d. In addition, a channel formation region 146 is formed in the semiconductor layer 104, and a channel formation region 149 a and a channel formation region 149 b are formed in the semiconductor layer 105.

    The second n-type impurity region 144a, the second n-type impurity region 144b, the second n-type impurity region 147a, the second n-type impurity region 147b, and the second n-type impurity region 147c are high-concentration n-type impurities. It is a region and functions as a source and a drain. On the other hand, a third n-type impurity region 145a, a third n-type impurity region 145b, a third n-type impurity region 148a, a third n-type impurity region 148b, a third n-type impurity region 148c, and a third The n-type impurity region 148d is a low concentration impurity region and becomes an LDD (Lightly Doped Drain) region. Since the n-type impurity region 145a and the n-type impurity region 145b are covered with the first gate electrode layer 122 through the gate insulating layer 107, they are Lov regions, which relieve an electric field in the vicinity of the drain and are caused by hot carriers. It is possible to suppress deterioration of on-current. As a result, a thin film transistor capable of high speed operation can be formed. On the other hand, the third n-type impurity region 148a, the third n-type impurity region 148b, the third n-type impurity region 148c, and the third n-type impurity region 148d are covered with the gate electrode layer 127 and the gate electrode layer 128. Therefore, the electric field in the vicinity of the drain is relaxed to prevent deterioration due to hot carrier injection and to reduce the off current. As a result, a highly reliable semiconductor device with low power consumption can be manufactured.

Next, the mask 153a, the mask 153b, the mask 153c, and the mask 153d are removed, and a mask 155a and a mask 155b that cover the semiconductor layer 103 and the semiconductor layer 105 are formed. An impurity element 154 imparting p-type conductivity is added using the mask 155a, the mask 155b, the gate electrode layer 117, and the gate electrode layer 129 as a mask, and the first p-type impurity region 160a, the first p-type impurity region 160b, and the first P-type impurity region 163a, first p-type impurity region 163b, second p-type impurity region 161a, second p-type impurity region 161b, second p-type impurity region 164a, and second p-type impurity region 164b is formed. In this embodiment, since boron (B) is used as the impurity element, diborane (B ₂ H ₆ ) (doping gas is obtained by diluting B ₂ H ₆ with hydrogen (H ₂ ) as a doping gas containing the impurity element. The B ₂ H ₆ ratio in the gas is 15%), and the doping is performed at a gas flow rate of 70 sccm, a beam current of 180 μA / cm, an acceleration voltage of 80 kV, and a dose of 2.0 × 10 ¹⁵ ions / cm ² to be added. Here, the first p-type impurity region 160a, the first p-type impurity region 160b, the first p-type impurity region 163a, the first p-type impurity region 163b, the second p-type impurity region 161a, and the second The p-type impurity region 161b, the second p-type impurity region 164a, and the second p-type impurity region 164b contain an impurity element imparting p-type at a concentration of about 1 × 10 ^{20 to} 5 × 10 ²¹ / cm ^3. Add as required. In this embodiment, the second p-type impurity region 161a, the second p-type impurity region 161b, the second p-type impurity region 164a, and the second p-type impurity region 164b include the gate electrode layer 117 and the gate electrode. Reflecting the shape of the layer 129, the concentration is lower than that of the first p-type impurity region 160a, the first p-type impurity region 160b, the first p-type impurity region 163a, and the first p-type impurity region 163b in a self-aligned manner. It forms so that it becomes. In addition, a channel formation region 162 is formed in the semiconductor layer 103, and a channel formation region 165 is formed in the semiconductor layer 106.

    The second n-type impurity region 144a, the second n-type impurity region 144b, the second n-type impurity region 147a, the second n-type impurity region 147b, and the second n-type impurity region 147c are high-concentration n-type impurities. It is a region and functions as a source and a drain. On the other hand, the second p-type impurity region 161a, the second p-type impurity region 161b, the second p-type impurity region 164a, and the second p-type impurity region 164b are low-concentration impurity regions, and are LDD (Lightly Doped Drain). It becomes an area. The second p-type impurity region 161a, the second p-type impurity region 161b, the second p-type impurity region 164a, and the second p-type impurity region 164b are connected to the first gate electrode through the gate insulating layer 107. Since it is covered with the layer 121 and the first gate electrode layer 126, it is a Lov region, and an electric field in the vicinity of the drain can be relaxed and deterioration of on-current due to hot carriers can be suppressed.

The masks 155a and 155b are removed by O ₂ ashing or resist stripping solution, and the oxide film is also removed. After that, an insulating film, so-called sidewall, may be formed so as to cover the side surface of the gate electrode layer. The sidewall can be formed using an insulating film containing silicon by a plasma CVD method or a low pressure CVD (LPCVD) method.

    In order to activate the impurity element, heat treatment, intense light irradiation, or laser light irradiation may be performed. Simultaneously with activation, plasma damage to the gate insulating layer and plasma damage to the interface between the gate insulating layer and the semiconductor layer can be recovered.

    Next, an interlayer insulating layer is formed to cover the gate electrode layer and the gate insulating layer. In this embodiment, a stacked structure of the insulating film 167 and the insulating film 168 is employed (see FIG. 4A). A silicon nitride oxide film having a thickness of 200 nm is formed as the insulating film 167, and an insulating film having a thickness of 800 nm is formed as the insulating film 168 to have a stacked structure. Further, a silicon oxynitride film is formed to a thickness of 30 nm, a silicon nitride oxide film is formed to a thickness of 140 nm, a silicon oxynitride film is formed to a thickness of 800 nm, and the three-layer stack is formed to cover the gate electrode layer and the gate insulating layer. It is good also as a structure. In this embodiment, the insulating film 167 and the insulating film 168 are continuously formed using a plasma CVD method as in the case of the base film. The insulating film 167 and the insulating film 168 are not limited to silicon nitride films, and may be a silicon nitride oxide film, a silicon oxynitride film, or a silicon oxide film formed by sputtering or plasma CVD. The film may be used as a single layer or a stacked structure of three or more layers.

    Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in a nitrogen atmosphere to perform a step of hydrogenating the semiconductor layer. Preferably, it carries out at 400-500 degreeC. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the insulating film 167 which is an interlayer insulating layer. In this embodiment, heat treatment is performed at 410 degrees (° C.).

    In addition, as the insulating films 167 and 168, aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide (AlNO) or aluminum oxide in which the nitrogen content is higher than the oxygen content, diamond like carbon (DLC) , A nitrogen-containing carbon film (CN), polysilazane, and other materials including inorganic insulating materials. A siloxane material (inorganic siloxane or organic siloxane) may also be used. Further, an organic insulating material may be used, and as the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, or benzocyclobutene can be used. A coating film formed by a coating method with good flatness may be used.

Next, contact holes (openings) reaching the semiconductor layers are formed in the insulating film 167, the insulating film 168, and the gate insulating layer 107 using a resist mask. Etching may be performed once or a plurality of times depending on the selection ratio of the material to be used. In this embodiment, the first etching is performed under a condition in which the insulating film 168 that is a silicon oxynitride film, the insulating film 167 that is a silicon nitride oxide film, and the gate insulating layer 107 have a selection ratio, and the insulating film 168 is formed. Remove. Next, the insulating film 167 and the gate insulating layer 107 are removed by second etching, and the first p-type impurity region 160a, the first p-type impurity region 160b, and the first p-type which are source regions or drain regions are removed. The impurity region 163a, the first p-type impurity region 163b, the second n-type impurity region 144a, the second n-type impurity region 144b, the second n-type impurity region 147a, and the second n-type impurity region 147b are reached. An opening is formed. In this embodiment mode, the first etching is performed by wet etching, and the second etching is performed by dry etching. As an etchant for wet etching, a hydrofluoric acid-based solution such as a mixed solution containing ammonium hydrogen fluoride and ammonium fluoride is preferably used. As the etching gas, a chlorine-based gas typified by Cl ₂ , BCl ₃ , SiCl ₄ or CCl ₄ , a fluorine-based gas typified by CF ₄ , SF ₆ or NF _3, or O ₂ is appropriately used. it can. Further, an inert gas may be added to the etching gas used. As the inert element to be added, one or more elements selected from He, Ne, Ar, Kr, and Xe can be used.

    A conductive film is formed so as to cover the opening, and the conductive film is etched to be electrically connected to a part of each source region or drain region, respectively, a source or drain electrode layer 169a, a source electrode layer or a drain electrode layer 169b, source / drain electrode layer 170a, source / drain electrode layer 170b, source / drain electrode layer 171a, source / drain electrode layer 171b, source / drain electrode layer 172a, source electrode layer Alternatively, the drain electrode layer 172b and the wiring layer 156 are formed. The source electrode layer or the drain electrode layer can be formed by forming a conductive film by a PVD method, a CVD method, an evaporation method, or the like and then etching the conductive film into a desired shape. Further, the conductive layer can be selectively formed at a predetermined place by a droplet discharge method, a printing method, an electroplating method, or the like. Furthermore, a reflow method or a damascene method may be used. The material of the source electrode layer or the drain electrode layer is Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, Al, Ta, Mo, Cd, Zn, Fe, Ti, Si, Ge, Zr, Ba Or a metal nitride thereof or a metal nitride thereof. Moreover, it is good also as these laminated structures. In this embodiment mode, titanium (Ti) is formed to a thickness of 100 nm, an alloy of aluminum and silicon (Al—Si) is formed to a thickness of 700 nm, and titanium (Ti) is formed to a thickness of 200 nm and processed into a desired shape. To do.

    Through the above steps, a p-channel thin film transistor 173 having a p-type impurity region in the Lov region in the peripheral driver circuit region 204, an n-channel thin film transistor 174 having an n-channel impurity region in the Lov region, and a conductive layer 177 in the connection region. An active matrix substrate having a multi-channel n-channel thin film transistor 175 having an n-type impurity region in a Loff region and a p-channel thin film transistor 176 having a p-type impurity region in a Lov region can be manufactured in the pixel region 206 ( (See FIG. 4B).

    The active matrix substrate can be used for a light emitting device having a self light emitting element, a liquid crystal display device having a liquid crystal element, and other display devices. Further, it can be used for various processors typified by a CPU (Central Processing Unit) and a semiconductor device such as a card equipped with an ID chip.

    Without being limited to this embodiment mode, the thin film transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. The thin film transistor in the peripheral driver circuit region may have a single gate structure, a double gate structure, or a triple gate structure.

    Note that, not limited to the method for manufacturing the thin film transistor described in this embodiment mode, a top gate type (planar type), a bottom gate type (reverse stagger type), or 2 arranged above and below a channel region with a gate insulating film interposed therebetween. The present invention can also be applied to a dual gate type or other structure having two gate electrode layers.

    Next, an insulating film 180 and an insulating film 181 are formed as a second interlayer insulating layer (see FIG. 5A). FIG. 5 shows a manufacturing process of a display device. A separation region 201 for separation by scribing, an external terminal connection region 202 as an FPC pasting portion, a wiring region 203 as a peripheral wiring region, They are a drive circuit area 204, a connection area 205, and a pixel area 206. The wiring region 203 is provided with wirings 179a and 179b, and the external terminal connection region 202 is provided with a terminal electrode layer 178 that is connected to an external terminal.

    As the insulating film 180 and the insulating film 181, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide having a nitrogen content higher than an oxygen content ( AlNO) or aluminum oxide, diamond-like carbon (DLC), nitrogen-containing carbon film (CN), PSG (phosphorus glass), BPSG (phosphorus boron glass), alumina film, polysilazane, and other substances including inorganic insulating materials It is possible to form with a material. A siloxane resin may also be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. An organic insulating material may be used, and the organic material may be either photosensitive or non-photosensitive, such as polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, and a low dielectric constant organic insulating material. Can be used.

    In this embodiment, a 200-nm-thick silicon oxynitride film is formed as the insulating film 180 by a CVD method. An interlayer insulating layer provided for planarization is required to have high heat resistance and high insulation and a high planarization rate. Therefore, a method for forming the insulating film 181 is represented by a spin coating method. It is preferable to use a coating method.

    In this embodiment, a coating film using a siloxane resin material is used as a material for the insulating film 181. The film after baking can be called a silicon oxide film (SiOx) containing alkyl groups (x, y = 1, 2,...). This silicon oxide film containing an alkyl group can withstand heat treatment at 300 ° C. or higher.

    For the insulating film 180 and the insulating film 181, dipping, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like can be employed. The insulating film 180 and the insulating film 181 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used.

    Next, as illustrated in FIG. 5B, openings are formed in the insulating film 180 and the insulating film 181 which are second interlayer insulating layers. The insulating film 180 and the insulating film 181 need to be etched over a wide area in the connection region 205, the wiring region 203, the external terminal connection region 202, the separation region 201, and the like. However, the opening area of the pixel region 206 is very small and fine compared to the opening area of the connection region 205 and the like. Therefore, by providing the photolithography process for forming the opening in the pixel region and the photolithography process for forming the opening in the connection region, the margin of the etching conditions can be further widened. As a result, the yield can be improved. Further, since the margin of the etching condition is widened, the contact hole formed in the pixel region can be formed with high accuracy.

    Specifically, wide-area openings are formed in the insulating film 180 and the insulating film 181 provided in part of the connection region 205, the wiring region 203, the external terminal connection region 202, the separation region 201, and the peripheral driver circuit region 204. To do. Therefore, a mask is formed so as to cover the insulating film 180 and the insulating film 181 in part of the pixel region 206, the connection region 205, and a part of the peripheral driver circuit region 204. For the etching, a parallel plate RIE apparatus or an ICP etching apparatus can be used. Note that the etching time is preferably set so that the wiring layer and the first interlayer insulating layer are over-etched. When the over-etching is performed as described above, it is possible to reduce the film thickness variation in the substrate and the etching rate variation. Thus, the opening 182 is formed in the connection region 205 and the opening 183 is formed in the external terminal connection region 202, respectively.

    After that, as illustrated in FIG. 5B, minute openings, that is, contact holes are formed in the insulating film 180 and the insulating film 181 in the pixel region 206 (see FIG. 5C). At this time, a mask is formed so as to cover the pixel region 206, a part of the connection region 205, the peripheral driver circuit region 204, and the pixel region 206. The mask is a mask for forming an opening in the pixel region 206, and a fine opening is provided at a predetermined location. As such a mask, for example, a resist mask can be used.

    Then, the insulating film 180 and the insulating film 181 are etched using a parallel plate RIE apparatus. Note that the etching time is preferably set so that the wiring layer and the first interlayer insulating layer are over-etched. When the over-etching is performed as described above, it is possible to reduce the film thickness variation in the substrate and the etching rate variation.

    An ICP apparatus may be used as the etching apparatus. Through the above steps, an opening 184 reaching the source or drain electrode layer 172a is formed in the pixel region 206. In the present invention, the source or drain electrode layer 172a covers the gate electrode layer 126 where the thin film is stacked in the thin film transistor 176 and the total film thickness is large via the insulating film 167 and the insulating film 168. Is formed. Therefore, since it is not necessary to open the opening 184 deeply, the opening process can be shortened and controllability is improved. In addition, since the electrode layer formed in the opening does not need to cover the opening having a large angle widely, it can be formed with good coverage and reliability is improved.

    In this embodiment mode, a mask that covers a part of the connection region 205, the wiring region 203, the external terminal connection region 202, the separation region 201, and the peripheral driver circuit region 204 and has a predetermined opening in the pixel region 206, Although the case where the insulating film 180 and the insulating film 181 are etched has been described, the present invention is not limited to this. For example, since the opening of the connection region 205 has a large area, the amount of etching is large. Such a wide-area opening may be etched a plurality of times. Further, in the case where a deep opening is formed as compared with other openings, etching may be performed a plurality of times in the same manner. Therefore, only a part of the insulating film 180 and the insulating film 181 in the wiring region 203, the external terminal connection region 202, the separation region 201, and the peripheral driver circuit region 204 are covered, and a predetermined opening is provided in the connection region 205 and the pixel region 206. The insulating film 180 and the insulating film 181 may be etched using the mask obtained. In the case of etching using such a mask, the insulating film 180 and the insulating film 181 in the connection region 205 are etched so as to increase in depth, and etching is performed until the insulating film 168 is exposed.

In this embodiment mode, the openings in the insulating film 180 and the insulating film 181 are formed in a plurality of times as shown in FIGS. 5B and 5C. However, the openings are formed by one etching process. You may do it. In this case, using an ICP apparatus, etching is performed with an ICP power of 7000 W, a bias power of 1000 W, a pressure of 0.8 Pascal (Pa), CF ₄ as an etching gas of 240 sccm, and O ₂ of 160 sccm. The bias power is preferably 1000 to 4000 W. Since the opening can be formed by one etching process, there is an advantage that the process is simplified.

Next, a first electrode layer 185 (also referred to as a pixel electrode layer) is formed so as to be in contact with the source or drain electrode layer 172a. The first electrode layer functions as an anode or a cathode, and an element selected from Ti, Ni, W, Cr, Pt, Zn, Sn, In, or Mo, TiN, TiSi _x N _y , WSi _x , WN _x WSi _x N _y , NbN, or a film mainly composed of an alloy material or compound material containing the above elements as a main component or a stacked film thereof may be used in a total film thickness range of 100 nm to 800 nm.

In this embodiment, a light-emitting element is used as a display element and light from the light-emitting element is extracted from the first electrode layer 185 side; thus, the first electrode layer 185 has a light-transmitting property. A transparent conductive film is formed as the first electrode layer 185, and the first electrode layer 185 is formed by etching into a desired shape. As the first electrode layer 185 used in the present invention, indium tin oxide containing silicon oxide (also referred to as indium tin oxide containing silicon oxide, hereinafter referred to as “ITSO”), zinc oxide, tin oxide, indium oxide, or the like is used. It may be used. In addition, a transparent conductive film such as an indium zinc oxide alloy in which 2 to 20 atomic% of zinc oxide (ZnO) is mixed with indium oxide can be used. In addition to the transparent conductive film, a titanium nitride film or a titanium film may be used as the first electrode layer 185. In this case, after forming the transparent conductive film, the titanium nitride film or the titanium film is formed with a thickness enough to transmit light (preferably, about 5 nm to 30 nm). In this embodiment, ITSO using indium tin oxide and silicon oxide is used for the first electrode layer 185. In this embodiment, the ITSO film is a target in which indium tin oxide is mixed with 1 to 10% silicon oxide (SiO ₂ ), the Ar gas flow rate is 120 sccm, the O ₂ gas flow rate is 5 sccm, and the pressure is A film having a film thickness of 185 nm is formed by sputtering at 0.25 Pa and power of 3.2 kW. The first electrode layer 185 may be wiped with a CMP method or a polyvinyl alcohol-based porous material and polished so that the surface thereof is planarized. Further, after polishing using the CMP method, the surface of the first electrode layer 185 may be subjected to ultraviolet irradiation, oxygen plasma treatment, or the like.

    Heat treatment may be performed after the first electrode layer 185 is formed. By this heat treatment, moisture contained in the first electrode layer 185 is released. Therefore, the first electrode layer 185 does not cause degassing. Therefore, even when a light-emitting material that is easily deteriorated by moisture is formed over the first electrode layer, the light-emitting material is not deteriorated and the display device has high reliability. Can be produced. In this embodiment mode, ITSO is used for the first electrode layer 185; therefore, even when baked, it does not crystallize like ITO (indium tin oxide alloy) and remains in an amorphous state. Therefore, ITSO has higher flatness than ITO, and even if the layer containing an organic compound is thin, short-circuiting with the cathode is unlikely to occur.

    Next, an insulator (insulating layer) 186 (referred to as a partition wall, a barrier, or the like) which covers the edge portion of the first electrode layer 185 and the source or drain electrode layer is formed (see FIG. 6B). In the same process, an insulator (insulating layer) 187 a and an insulator (insulating layer) 187 b are formed in the external terminal connection region 202.

In order to perform full color display, when the electroluminescent layer is formed on the first electrode layer, the electroluminescent layers that emit RGB light must be formed separately. Therefore, when the electroluminescent layer of another color is formed, the pixel electrode layer (first electrode layer) is covered with a mask. The mask can be in the form of a film made of a metal material or the like. At this time, the mask is provided and supported over the insulator 186 serving as a partition wall, but may be in contact with the pixel electrode layer due to bending or kinking, and the pixel electrode layer is damaged. When the pixel electrode layer has a shape defect due to scratches or the like, a light emission defect or a display defect is caused, and the image quality is deteriorated. Therefore, both reliability and performance are reduced.

    In this embodiment mode, the spacer 199 is formed with a thickness equivalent to that of the insulator 186 over the first electrode layer 185 which is a pixel electrode layer. The spacer 199 supports the mask used in the electroluminescent layer deposition, so that it does not come into contact with the first electrode layer. Therefore, a shape failure of the first electrode layer due to the mask is prevented, and the first electrode layer can be a highly reliable display device with high image quality without causing a light emission failure and a display failure.

    In this embodiment mode, the spacer 199 is formed using the same material and in the same step as the insulator 186 that is a partition; however, the spacer 199 may be formed in a separate step. The shape and size of the spacer are not limited, and may be set in consideration of the size of the pixel region, the aperture ratio, and the like. In this embodiment mode, a columnar shape as illustrated in FIG. 6B and a rounded upper portion such as a hemisphere are formed, and the height is 1 μm to 2 μm (preferably 1 μm to 1.5 μm).

    An example of the shape of the spacer will be described with reference to FIGS. As shown in FIGS. 28 and 31, an insulator (insulating layer) that is a partition wall and a spacer may be continuously connected. FIGS. 31A1, 31 </ b> B <b> 1, 28 </ b> A <b> 1, and 31 </ b> B <b> 1 are top views of a pixel region, and FIGS. It is sectional drawing of line | wire X1-Y1, X2-Y2, X3-Y3, X4-Y4 in (A1), (B1) and FIG. 28 (A1), (B1). 31A1 and 31A2, a pixel electrode layer is formed over the substrate 600, the base film 601a, the base film 601b, the gate insulating layer 602, the insulating film 603, the insulating film 604, the insulating film 605, and the insulating film 606. One electrode layer 607 is formed. An insulator (insulating layer) 608 which is a partition is formed so as to cover an end portion of the first electrode layer 607, and a spacer 609 is formed using the same material and the same process as the insulator 608.

    In FIGS. 31A1 and 31A2, the spacer 609 is formed so as to be in contact with the insulator 608 and continuously formed on the first electrode layer so as to cross the first electrode layer 607 diagonally. Has been. When the spacers 609 are continuously formed in this manner, the mask is always supported by the spacers 609 even during movement, so that the first electrode layer 607 is prevented from being in contact with the first electrode layer 607 and causing a shape defect. be able to.

    31B1 and 31B2, a pixel electrode layer is formed over the substrate 610, the base film 611a, the base film 611b, the gate insulating layer 612, the insulating film 613, the insulating film 614, the insulating film 615, and the insulating film 616. One electrode layer 617 is formed. An insulator (insulating layer) 618 that is a partition wall is formed so as to cover an end portion of the first electrode layer 617, and a spacer 619 is formed using the same material and the same process as the insulator 618.

    In FIGS. 31B1 and 31B, the spacer 619 is formed so as to be in contact with the insulator 618, and continuously over the first electrode layer so as to cross the short side direction of the first electrode layer 617. It is formed in two places. When the spacers 619 are continuously formed at a plurality of positions in this manner, the mask is always supported by the spacers 619 even during movement, and thus the first electrode layer 617 is brought into contact with the first electrode layer 617, causing a shape defect of the first electrode layer 617. Can be prevented.

    28A1 and 28A2, a pixel electrode layer is formed over the substrate 620, the base film 621a, the base film 621b, the gate insulating layer 622, the insulating film 623, the insulating film 624, the insulating film 625, and the insulating film 626. One electrode layer 627 is formed. An insulator (insulating layer) 628 that is a partition is formed so as to cover an end portion of the first electrode layer 627, and a spacer 629 is formed using the same material and the same process as the insulator 628.

    In FIGS. 28A1 and 28A2, the spacer 629 is formed so as to be in contact with the insulator 628 so as to cross over the first electrode layer in the long side direction and the short side direction of the first electrode layer 627. Are formed in a lattice shape. When the spacers 629 are continuously formed in a lattice shape in this manner, the mask is always supported by the spacers 629 even during movement, and thus the first electrode layer 627 is in contact with the first electrode layer 627, causing a shape defect of the first electrode layer 627. Can be prevented.

    28B1 and 28B2, a pixel electrode layer is formed over the substrate 630, the base film 631a, the base film 631b, the gate insulating layer 632, the insulating film 633, the insulating film 634, the insulating film 635, and the insulating film 636. One electrode layer 637 is formed. An insulator (insulating layer) 638 that is a partition is formed so as to cover an end portion of the first electrode layer 637, and a spacer 639 is formed using the same material and the same process as the insulator 638.

    28B1 and 28B2, the spacer 639 is formed so as to be in contact with the insulator 638, and is formed so as to cross the first electrode layer 637 several times obliquely with respect to the interface with the insulator 638. Has been. In this embodiment, the angle between the minor axis of the interface between the first electrode layer 637 and the insulator and the spacer 639 is 45 degrees. When the spacer 639 is continuously formed in this manner, the mask is always supported by the spacer 639 even during movement, so that it does not contact the first electrode layer 637 and cause a shape defect of the first electrode layer 637. be able to.

    As shown in FIG. 28A2, the spacer 629 has a tapered shape. As described above, the spacer may be a substantially rectangular parallelepiped as shown in FIGS. 31A2 and 28B2, and may have various shapes such as a cylinder, a prism, a cone, a pyramid, or a taper shape. Can do.

    In FIGS. 31 and 28, the spacer is formed in contact with an insulator (insulating layer) serving as a partition wall, but may be formed separately without being in contact therewith.

    The spacer is made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride or other inorganic insulating materials, or acrylic acid, methacrylic acid and derivatives thereof, polyimide, aromatic polyamide, It can be formed of a heat-resistant polymer such as polybenzoimidazole or an insulating material such as siloxane resin. In this embodiment mode, acrylic is used for the spacer 199.

    In this embodiment, acrylic is used for the insulator 186. In addition, when the same material as that of the insulating film 181 is used for the insulator 186 and formed in the same process, manufacturing cost can be reduced. In addition, the cost can be reduced by using a common apparatus such as a coating film forming apparatus or an etching apparatus.

    The insulator 186 includes silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and other inorganic insulating materials, or acrylic acid, methacrylic acid and derivatives thereof, polyimide, aromatic It can be formed of a heat-resistant polymer such as polyamide, polybenzimidazole, or an insulating material such as a siloxane resin. You may form using photosensitive and non-photosensitive materials, such as an acryl and a polyimide. The insulator 186 preferably has a shape in which the radius of curvature continuously changes, and the coverage of the electroluminescent layer 188 and the second electrode layer 189 formed thereon is improved.

    In the connection region 205, the insulator 186 is formed so as to cover the end portions of the insulating film 180 and the insulating film 181 on the side surface of the opening 182. The end portions of the insulating film 180 and the insulating film 181 processed to have a step by etching have a steep step, and thus the coverage of the second electrode layer 189 stacked thereover is poor. Therefore, as in the present invention, the step around the opening is covered with the insulator 186 and the step is smoothed, whereby the coverage of the second electrode layer 189 to be stacked can be improved. In the connection region 205, a wiring layer formed using the same process and material as the second electrode layer is electrically connected to the wiring layer 156. In this embodiment mode, the second electrode layer 189 is in direct contact with and electrically connected to the wiring layer 156; however, the second electrode layer 189 may be electrically connected through another wiring.

    In the present invention, the spacer 198 is formed over the insulator 186 functioning as a partition wall. Similarly to the spacer 199 formed on the pixel electrode layer, this spacer also supports the mask used in the electroluminescent layer deposition by the spacer 198, so that it does not come into contact with the first electrode layer. It is preferable that the spacer 198 formed over the insulator 186 avoid a defect such as electrostatic breakdown when the thin film transistor is avoided. Note that the spacer 199 formed over the pixel electrode layer can also be referred to as a first spacer, and the spacer 198 formed over the insulator 186 can also be referred to as a second spacer. Therefore, since the mask is supported by the first spacer and the second spacer, the shape defect to the first electrode layer by the mask is prevented, and the first electrode layer does not cause the light emission defect and the display defect. Therefore, a highly reliable display device with high image quality can be obtained.

    As the insulator 186, the spacer 199, and the spacer 198, dip, spray coating, doctor knife, roll coater, curtain coater, knife coater, CVD method, vapor deposition method, or the like can be employed. The insulator 186, the spacer 199, and the spacer 198 may be formed by a droplet discharge method. When the droplet discharge method is used, the material liquid can be saved. Further, a method capable of transferring or drawing a pattern, such as a droplet discharge method, for example, a printing method (a method for forming a pattern such as screen printing or offset printing) or the like can be used.

  In addition, after the insulator 186, the spacer 199, and the spacer 198 are formed, the surface may be flattened by pressing with pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-like object on the surface, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method.

    The spacer 198 may be formed of the same material and in the same process as the spacer 199, or may be formed in a separate process as in this embodiment. The shape and size of the spacer are not limited, and may be set in consideration of the size of the pixel region, the mask material, the film thickness, and the like. In this embodiment mode, a columnar shape as shown in FIG. 6B and a rounded upper part such as a hemisphere are formed, and the height is 1 μm to 3 μm (preferably 1.5 μm to 2 μm). In the case where the spacer 198 and the spacer 199 are formed using different materials and different processes, spacers having different shapes and film thicknesses can be freely formed. In this embodiment mode, the height of the spacer 198 and the upper surface of the spacer 199 from the substrate 100 is different. However, after the insulator 186 is formed, the spacer 198 and the spacer 199 are formed using a coating film having high flatness. For example, they can be formed with the same height. In such a case, since the support area by the mask spacer increases, the mask can be installed more stably.

    Since the insulating layer 186 and the spacer 198 are formed to have different shapes by stacking, it is preferable to use a material having a high selectivity in etching. For example, when an inorganic material is used for the insulating layer 186 and an organic material is used for the spacer 198, the insulating layer 186 can be processed into a favorable shape with a high selection ratio.

    In order to further improve the reliability, it is preferable to perform deaeration by performing vacuum heating before forming the electroluminescent layer (a layer containing an organic compound) 188. For example, before vapor deposition of the organic compound material, it is desirable to perform heat treatment at 200 to 400 ° C., preferably 250 to 350 ° C. in a reduced pressure atmosphere or an inert atmosphere in order to remove gas contained in the substrate. In addition, it is preferable to form the electroluminescent layer 188 by vacuum deposition or a droplet discharge method under reduced pressure without exposing it to the atmosphere. By this heat treatment, moisture contained in and adhering to the conductive film or insulating layer (partition wall) to be the first electrode layer can be released. This heat treatment can be combined with the previous heating step as long as the substrate can be transported in the vacuum chamber without breaking the vacuum, and the previous heating step may be performed once after the formation of the insulating layer (partition wall). . Here, if the interlayer insulating film and the insulator (partition wall) are formed of a material having high heat resistance, a heat treatment process for improving reliability can be sufficiently performed.

    An electroluminescent layer 188 is formed over the first electrode layer 185. Although only one pixel is shown in FIG. 1, field electrode layers corresponding to each color of R (red), G (green), and B (blue) are separately formed in this embodiment. In this embodiment mode, the electroluminescent layer 188 is formed by selectively forming materials that emit red (R), green (G), and blue (B) light by an evaporation method using an evaporation mask. 32 and FIG. 32 and 29 show a process of forming a material that emits red light. In this embodiment mode, a method is used in which each color is formed using different vapor deposition apparatuses and vapor deposition masks. However, three color light-emitting materials can be formed while moving one mask in the same chamber.

    FIG. 29A is a schematic diagram of a vapor deposition process, and FIG. 29B is a diagram of an element substrate and a vapor deposition mask viewed from the vapor deposition source 761 side. As shown in FIG. 29A, a magnetic body 765 that controls the position of a mask in a vapor deposition apparatus chamber 760 to be attached to and detached from the element substrate 764, an element substrate 764, a mask 763, a shutter 762, and a vapor deposition source 761. Is provided. The magnetic body 765 is moved in the direction of the arrow 770 by the control device 772, and is observed with the camera 771a and the camera 771b in order to align the element substrate 764 with the mask 763. In addition, the vapor deposition apparatus is provided with a heater for heating the vapor deposition source, a crystal resonator for controlling the film thickness, a controller for controlling the temperature and position in each part, and the like. The element substrate 764 is installed so that the element side faces downward toward the vapor deposition source 761, and close to the element substrate 764 toward the vapor deposition source 761 side, between the mask 763 and the mask 763 and the vapor deposition source 761. A shutter 762 for controlling the start and end of vapor deposition is provided. Since the mask 763 is made of a metal material and has magnetism, the vertical position control of the mask 763 in the direction of the arrow 770 is performed by a magnetic body 765 made of a magnetic material.

    FIG. 29B shows a mask 763 and an element substrate 764 viewed from the vapor deposition source 761 side, and the mask 763 is placed on the element side of the element substrate 764 so as to be in close contact with the magnetic force of the magnetic body 765. In addition, each pixel has a stripe arrangement in which pixels corresponding to red, green, and blue are arranged in a stripe pattern, a delta arrangement that is shifted by a half pitch for each line, and sub-pixels that correspond to red, green, and blue are slanted. Any arrangement method of the mosaic arrangement may be adopted. Since the stripe arrangement is suitable for displaying lines, figures, characters, and the like, it is preferably applied to a monitor. The mosaic arrangement is preferably applied to a television set or the like because a more natural image can be obtained than the stripe arrangement. In addition, since the delta arrangement can provide a natural image display, it is preferably applied to a television apparatus or the like.

    In this embodiment mode, a stripe arrangement is used as the arrangement of pixels. As shown in FIG. 29B, the mask 763 is a slit type having slit-like openings such as an opening 769a and an opening 769b. Use. The slit type is highly productive because each pixel can form all pixels emitting light of that color at once. In addition to the slit type, a slot type mask having an opening corresponding to each pixel and having a slot-like opening that does not have a continuous opening like the slit type is also used. Can do. The slot type pixel may require multiple times (two or more times) of vapor deposition for each color, but is suitable for a non-linear arrangement such as a delta arrangement. Because it is small, the mask has high rigidity.

    The element substrate 764 is provided with a pixel electrode layer 766a serving as a pixel for displaying red, a pixel electrode layer 766b serving as a pixel for displaying green, and a pixel electrode layer 766c serving as a pixel for displaying blue. Since FIG. 29 shows a case where a red light emitting material is formed, the mask 763 is provided so that the opening 769a and the opening 769b correspond to the pixel electrode layer that displays red.

    In the present invention, spacers are formed on the pixel electrode layer and on an insulator (insulating layer) that covers the edge of each pixel electrode layer and functions as a partition wall. Therefore, the spacer 767 and the spacer 768 are also provided over the pixel electrode layer and the insulator (insulating layer) illustrated in FIG. Since the mask 763 is supported by the spacer 767 and the spacer 768, even if the rigidity of the mask 763 is weak and kinking or deflection occurs due to a magnetic force, an attractive force, or the like, the mask 763 includes the pixel electrode layer 766 a, the pixel Contact with the electrode layer 766b and the pixel electrode layer 766c can be prevented. Therefore, no damage is caused to the pixel electrode layer, so that favorable light emission and display can be performed. Even if it becomes difficult to control the position of the mask accurately, the spacer becomes larger as the substrate becomes larger and more delicate, the mask opening becomes larger, and the shielding portion becomes thinner. Allows the mask to be supported and placed at the desired location.

    A detailed positional relationship between the element substrate and the mask will be described with reference to FIG. FIG. 32 is a cross-sectional view of the element substrate and mask during vapor deposition when the vapor deposition source is viewed from the top. Therefore, the element substrate shown in FIG. In FIG. 32, the thin film transistor 651a, the thin film transistor 651b, the thin film transistor 651c, and the thin film transistor 651d are connected to the first electrode layer 652a, the first electrode layer 652b, the first electrode layer 652c, and the first electrode layer 652d which are pixel electrode layers. is doing. The ends of the first electrode layer are covered with an insulator (insulating layer) 653a, an insulator (insulating layer) 653b, an insulator (insulating layer) 653c, and an insulator (insulating layer) 653d that function as partition walls. A spacer 654a, a spacer 654b, a spacer 654c, and a spacer 654d are formed over the first electrode layer. Similarly, a spacer 657a, a spacer 657b, a spacer 657c, and a spacer 657d are formed over the insulator (insulating layer). In FIG. 32, a spacer 654a, a spacer 654b, a spacer 654c, a spacer 654d, a spacer 657a, a spacer 657b, a spacer 657c, and a spacer 657d are formed using the same material after forming an insulator 653a, an insulator 653b, an insulator 653c, and an insulator 653d. An example of forming in the same process is shown.

    Since the spacers 654a to 654d, the spacers 657a, and the spacers 657b are formed by dry etching after forming a highly flat layer by a coating method, the height from the substrate is the same, and the column shape is used as a mask. The contacting upper surface is flat. When the mask is supported by a spacer having such a uniform height and a flat support surface, the mask support surface becomes larger and the mask is further stabilized. The insulators 653a to 653d each preferably has a gentle shape with a curved end in order to improve the coverage of the electroluminescent layer and the second electrode layer formed thereon. When the insulator and the spacer are formed in separate steps, each spacer can be formed in a free shape by using different materials and different steps. Therefore, a spacer suitable for the pixel layout and the evaporation mask can be provided. Of course, if the spacer on the pixel electrode layer and the insulator (insulating layer) are formed of the same material and in the same process, there is an advantage that the process can be shortened and the efficiency of the material can be improved. After forming the spacer on the pixel electrode layer and the insulator in the same material and the same step, another spacer can be formed again on the pixel electrode layer when the spacer on the insulator is formed.

    The first electrode layer 652 a and the first electrode layer 652 d are pixels that display red, and are disposed so as to correspond to the openings of the mask 656. Then, a red light-emitting material is formed as an electroluminescent layer over the first electrode layer 652a and the first electrode layer 652d. On the other hand, since the first electrode layer 652b is a pixel that displays green and the first electrode layer 652c is a pixel that displays blue, the first electrode layer 652b is installed to correspond to the shielding portion of the mask 656. Since the mask 656 is stably supported by spacers formed on the first electrode layer and the insulator, the mask 656 is in contact with the first electrode layer due to kinking or deflection, and the first electrode layer is shaped. There are no problems that cause defects. Therefore, the first electrode layer can produce a display device with high reliability and high quality without causing light emission failure and display failure.

    The spacer 654a provided over the pixel electrode layer 652a is not shielded by the mask when the electroluminescent layer is formed over the pixel electrode layer 652a. Therefore, the electroluminescent layer may be formed over the surface and the periphery of the spacer 654a. is there. On the other hand, since the insulator 653a, the insulator 653b, the spacer 657a, and the spacer 657b are substantially shielded by the mask 656, an electroluminescent layer can be formed only in a peripheral portion near the opening of the mask 656. When a plurality of spacers such as the spacer 657a provided over the insulator 653a and the spacer 654a provided over the pixel electrode layer 652a are provided as in this embodiment mode, the mask 656 is in contact with the electroluminescent layer deposition. There are spacers 657 a and spacers 654 a that do not contact the mask 656.

    Further, in the case where light emitting materials of each color are selectively formed using one mask 656, the mask 656 forms an electroluminescent layer on the first electrode layer 652a and the first electrode layer 652d, and then the direction of the arrow 655. And an electroluminescent layer can be formed on each first electrode layer.

Next, a second electrode layer 189 made of a conductive film is provided over the electroluminescent layer 188. As the second electrode layer 189, a material having a low work function (Al, Ag, Li, Ca, or an alloy or a compound thereof, MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used. Thus, a light-emitting element 190 including the first electrode layer 185, the electroluminescent layer 188, and the second electrode layer 189 is formed.

    In the display device of this embodiment mode illustrated in FIG. 1, light emitted from the light-emitting element 190 is transmitted through and emitted from the first electrode layer 185 side in the direction of the arrow in FIG.

    It is effective to provide a passivation film 191 so as to cover the second electrode layer 189. Examples of the passivation film 191 include silicon nitride, silicon oxide, silicon oxynitride (SiON), silicon nitride oxide (SiNO), aluminum nitride (AlN), aluminum oxynitride (AlON), and nitriding in which the nitrogen content is higher than the oxygen content. The insulating film includes aluminum oxide (AlNO) or aluminum oxide, diamond-like carbon (DLC), and a nitrogen-containing carbon film (CN), and a single layer or a combination of the insulating films can be used. A siloxane resin material may be used.

At this time, it is preferable to use a film with good coverage as the passivation film, and it is effective to use a carbon film, particularly a DLC film. Since the DLC film can be formed in a temperature range from room temperature to 100 ° C., it can be easily formed over the electroluminescent layer 119 having low heat resistance. The DLC film is formed by a plasma CVD method (typically, an RF plasma CVD method, a microwave CVD method, an electron cyclotron resonance (ECR) CVD method, a hot filament CVD method, etc.), a combustion flame method, a sputtering method, or an ion beam evaporation method. It can be formed by laser vapor deposition. The reaction gas used for film formation was hydrogen gas and a hydrocarbon-based gas (for example, CH ₄ , C ₂ H ₂ , C ₆ H _6, etc.), ionized by glow discharge, and negative self-bias was applied. Films are formed by accelerated collision of ions with the cathode. The CN film may be formed using C ₂ H ₄ gas and N ₂ gas as the reaction gas. The DLC film has a high blocking effect against oxygen and can suppress oxidation of the electroluminescent layer 188. Therefore, the problem that the electroluminescent layer 188 is oxidized during the subsequent sealing process can be prevented.

    FIG. 18 is a top view of a pixel region of the display device manufactured in this embodiment mode. In FIG. 18, the pixel 2702 includes a TFT 501, a TFT 502, a capacitor 504, a first electrode layer 185, a gate wiring layer 506, a source / drain wiring layer 505, and a power supply line 507. The display device of FIG. 18 is a drawing in which even the first electrode layer 185 is formed.

    Next, FIG. 30 illustrates a display device in which an insulator 186 functioning as a partition wall, a spacer 199, and a spacer 198 are formed so as to cover a peripheral end portion of the first electrode layer 185. In FIG. 30, a plurality of spacers 199 are provided on the first electrode layer, and a plurality of spacers 198 are provided on the insulator 186. The spacer 198 formed over the insulator 186 is preferably formed in a region where no thin film transistor is formed under the insulator 186 because defects such as electrostatic breakdown are unlikely to occur. Further, instead of the spacer 198 on the insulator, a mask provided with a recess at a location corresponding to the spacer 198 may be used. There may be a single spacer or a plurality of spacers. When there are a plurality of spacers, it is not necessary to have the same shape. Since the mask used in the step of forming the electroluminescent layer is supported by the spacer, the first electrode layer is not damaged by kinking or bending.

    The substrate 100 over which the light-emitting element 190 is formed in this manner and the sealing substrate 195 are fixed with a sealant 192 to seal the light-emitting element (see FIG. 1). In the display device of the present invention, the sealing material 192 and the insulator 186 are formed so as not to contact each other. When the sealing material and the insulator 186 are separated from each other in this manner, even when an insulating material using a highly hygroscopic organic material is used for the insulator 186, moisture hardly enters and deterioration of the light-emitting element can be prevented. This improves the reliability of the display device. As the sealant 192, it is typically preferable to use a visible light curable resin, an ultraviolet curable resin, or a thermosetting resin. For example, bisphenol A type liquid resin, bisphenol A type solid resin, bromine-containing epoxy resin, bisphenol F type resin, bisphenol AD type resin, phenol type resin, cresol type resin, novolac type resin, cyclic aliphatic epoxy resin, epibis type epoxy Epoxy resins such as resins, glycidyl ester resins, glycidylamine resins, heterocyclic epoxy resins, and modified epoxy resins can be used. Note that a region surrounded by the sealant may be filled with a filler 193, or nitrogen or the like may be sealed by sealing in a nitrogen atmosphere. Since this embodiment mode is a downward injection type, the filler 193 does not need to have a light-transmitting property. However, in the case of a structure in which light is extracted through the filler 193, the filler 193 needs to have a light-transmitting property. Typically, a visible light curable, ultraviolet curable, or thermosetting epoxy resin may be used. Through the above steps, a display device having a display function using a light-emitting element in this embodiment is completed. Further, the filler can be dropped in a liquid state and filled in the display device.

    A dropping injection method employing a dispenser method will be described with reference to FIG. In the dropping injection method of FIG. 19, the control device 40, the imaging means 42, the head 43, the filler 33, the marker 35, and the marker 45 are composed of the barrier layer 34, the sealing material 32, the TFT substrate 30, and the counter substrate 20. A closed loop is formed by the sealing material 32, and the filler 33 is dropped from the head 43 once or a plurality of times. When the viscosity of the filler material is high, the filler material is discharged continuously and adheres to the formation region while being connected. On the other hand, when the viscosity of the filler material is low, the filler material is intermittently discharged and the filler is dropped as shown in FIG. At that time, a barrier layer 34 may be provided to prevent the sealing material 32 and the filler 33 from reacting. Then, a board | substrate is bonded together in a vacuum, and ultraviolet curing is performed after that, and it is set as the state with which the filler was filled. When a hygroscopic substance such as a desiccant is used as the filler, a further water absorption effect can be obtained and deterioration of the element can be prevented.

    A desiccant is installed in the EL display panel in order to prevent deterioration of the element due to moisture. In this embodiment mode, the desiccant is provided in a recess formed in the sealing substrate so as to surround the pixel region, and the thickness is not hindered. Moreover, since the desiccant is formed also in the area | region corresponding to a gate wiring layer and the water absorption area is taken wide, the water absorption effect is high. Further, since the desiccant is formed on the gate wiring layer that does not emit light directly, the light extraction efficiency is not lowered.

    Note that in this embodiment mode, a case where a light-emitting element is sealed with a glass substrate is shown; however, the sealing process is a process for protecting the light-emitting element from moisture and is mechanically sealed with a cover material. Either a method, a method of encapsulating with a thermosetting resin or an ultraviolet light curable resin, or a method of encapsulating with a thin film having a high barrier ability such as a metal oxide or a nitride is used. As the cover material, glass, ceramics, plastic, or metal can be used. However, when light is emitted to the cover material side, it must be translucent. In addition, the cover material and the substrate on which the light emitting element is formed are bonded together using a sealing material such as a thermosetting resin or an ultraviolet light curable resin, and the resin is cured by heat treatment or ultraviolet light irradiation treatment to form a sealed space. Form. It is also effective to provide a hygroscopic material typified by barium oxide in this sealed space. This hygroscopic material may be provided in contact with the sealing material, or may be provided on the partition wall or in the peripheral portion so as not to block light from the light emitting element. Further, the space between the cover material and the substrate on which the light emitting element is formed can be filled with a thermosetting resin or an ultraviolet light curable resin. In this case, it is effective to add a moisture absorbing material typified by barium oxide in the thermosetting resin or the ultraviolet light curable resin.

    In this embodiment mode, the FPC 194 is connected to the terminal electrode layer 178 with the anisotropic conductive layer 196 in the external terminal connection region 202 so as to be electrically connected to the outside. As shown in FIG. 1A, which is a top view of the display device, the display device manufactured in this embodiment includes a scan line driver circuit in addition to the peripheral driver circuit region 204 having a signal line driver circuit. A peripheral drive circuit region 207a and a peripheral drive circuit region 207b are provided.

    In this embodiment mode, the circuit is formed as described above. However, the present invention is not limited to this, and an IC chip may be mounted as a peripheral driver circuit by the above-described COG method or TAB method. Further, the gate line driver circuit and the source line driver circuit may be plural or singular.

    In the display device of the present invention, the screen display driving method is not particularly limited. For example, a dot sequential driving method, a line sequential driving method, a surface sequential driving method, or the like may be used. Typically, a line sequential driving method is used, and a time-division gray scale driving method or an area gray scale driving method may be used as appropriate. The video signal input to the source line of the display device may be an analog signal or a digital signal, and a drive circuit or the like may be designed in accordance with the video signal as appropriate.

    Furthermore, in a display device in which a video signal is digital, there are a video signal input to a pixel having a constant voltage (CV) and a constant current (CC). A video signal having a constant voltage (CV) includes a constant voltage (CVCV) applied to the light emitting element and a constant current (CVCC) applied to the light emitting element. In addition, a video signal having a constant current (CC) includes a constant voltage (CCCV) applied to the light emitting element and a constant current (CCCC) applied to the light emitting element.

    By using the present invention, a highly reliable display device can be manufactured through a simplified process. Therefore, a high-definition and high-quality display device can be manufactured at a low cost and with a high yield.

(Embodiment 2)
An embodiment of the present invention will be described with reference to FIGS. This embodiment shows an example in which the second interlayer insulating layer is not formed in the display device manufactured in Embodiment 1. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    As described in Embodiment 1, the thin film transistor 173, the thin film transistor 174, the thin film transistor 175, the thin film transistor 176, and the conductive layer 177 are formed over the substrate 100, and the insulating film 168 and the insulating film 168 are formed. Each thin film transistor is provided with a source electrode layer or a drain electrode layer connected to a source region or a drain region of the semiconductor layer. A first electrode layer 395 is formed in contact with the source or drain electrode layer 172b in the thin film transistor 176 provided in the pixel region 206 (see FIG. 7A).

    The first electrode layer 395 functions as a pixel electrode and may be formed using a material and a process similar to those of the first electrode layer 185 in Embodiment 1. In this embodiment mode, as in Embodiment Mode 1, in order to pass light through the first electrode layer and extract it, ITSO, which is a transparent conductive film, is used for the first electrode layer 395 and processed into a desired shape. Form.

    A spacer 199 is formed over the insulator 186 and the pixel electrode layer so as to cover the end portion of the first electrode layer 395 and the thin film transistor. After the insulator 186 is formed, a spacer 198 is formed over the insulator 186 (see FIG. 7B). In this embodiment mode, acrylic is used for the insulator 186 and the spacer 199. In the present embodiment, the spacer 198 is columnar and has a shape with higher flatness on the upper surface. The spacer 198 and the spacer 199 support the mask for forming the electroluminescent layer, so that the pixel electrode layer is not damaged by the mask. Thus, a display device with high image quality and high reliability can be manufactured. Further, as in the present embodiment, when the convex portion is formed by the spacer 198 and the sealing substrate 195 is supported by the convex portion, the distance between the element substrate and the sealing substrate is controlled to be uniform. can do. When the interval is uniform, a good and high-quality display can be performed without causing a display defect such as interference of light emitted from the light emitting element.

    The electroluminescent layer 188 is formed over the first electrode layer, and the second electrode layer 189 is stacked, whereby the light emitting element 190 is formed. The second electrode layer 189 is electrically connected to the wiring layer 156 in the connection region 205, and the terminal electrode layer 178 is bonded to the FPC 194 through the anisotropic conductive layer 196 in the external terminal connection region 202. A passivation film 191 is formed so as to cover the second electrode layer 189. The substrate 100 is bonded to the sealing substrate 195 with a sealant 192, and the display device is filled with a filler 193 (see FIG. 8). In the display device of the present invention, the sealing material 192 and the insulator 186 are formed so as not to contact each other. When the sealing material and the insulator 186 are separated from each other in this manner, even when an insulating material using a highly hygroscopic organic material is used for the insulator 186, moisture hardly enters and deterioration of the light-emitting element can be prevented. This improves the reliability of the display device.

    In the display device in FIG. 9, the first electrode layer 395 can be selectively formed over the insulating film 168 before the source electrode layer or the drain electrode layer 172 b connected to the thin film transistor 176 is formed. In this case, the connection structure of the source or drain electrode layer 172b and the first electrode layer 395 is different from that in this embodiment, and the source or drain electrode layer 172b is stacked over the first electrode layer 395. It becomes a structure. When the first electrode layer 395 is formed before the source electrode layer or the drain electrode layer 172b, the first electrode layer 395 can be formed in a flat formation region. Therefore, the first electrode layer 395 can be formed in a flat formation region. There are advantages.

    By using the present invention, a highly reliable display device can be manufactured through a simplified process. Therefore, a high-definition and high-quality display device can be manufactured at a low cost and with a high yield.

(Embodiment 3)
An embodiment of the present invention will be described with reference to FIG. This embodiment shows an example in which the structure of the gate electrode layer of the thin film transistor is different in the display device manufactured in Embodiment 1. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    10A to 10C illustrate a display device in a manufacturing process, which corresponds to the display device in FIG. 4B described in Embodiment Mode 1.

    10A, a thin film transistor 273 and a thin film transistor 274 are provided in the peripheral driver circuit region 214, a conductive layer 277 is provided in the connection region, and a thin film transistor 275 and a thin film transistor 276 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10A includes a stack of two conductive films, and the upper gate electrode layer is processed to be narrower than the lower gate electrode layer. The lower gate electrode layer has a tapered shape, but the upper gate electrode layer does not have a tapered shape. As described above, the gate electrode layer may have a tapered shape, or may have a shape in which the side surface angle is nearly vertical, that is, a shape without a so-called tapered shape.

    10B, a thin film transistor 373 and a thin film transistor 374 are provided in the peripheral driver circuit region 214, a conductive layer 377 is provided in the connection region, and a thin film transistor 375 and a thin film transistor 376 are provided in the pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10B is also formed of a stack of two conductive films, but the upper gate electrode layer and the lower gate electrode layer have a continuous taper shape.

    10C, a thin film transistor 473 and a thin film transistor 474 are provided in the peripheral driver circuit region 214, a conductive layer 477 is provided in a connection region, and a thin film transistor 475 and a thin film transistor 476 are provided in a pixel region 216. The gate electrode layer of the thin film transistor in FIG. 10C has a single-layer structure and has a tapered shape. Thus, the gate electrode layer may have a single layer structure.

    As described above, the gate electrode layer can have various structures depending on its configuration and shape. Therefore, display devices manufactured also have various structures. When the impurity region in the semiconductor layer is formed in a self-aligned manner using the gate electrode layer as a mask, the structure and concentration distribution of the impurity region vary depending on the structure of the gate electrode layer. When designing is performed in consideration of the above, a thin film transistor having a desired function can be manufactured.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 and 2.

(Embodiment 4)
Although a display device having a light-emitting element can be formed by applying the present invention, light emitted from the light-emitting element performs any one of bottom emission, top emission, and dual emission. In this embodiment, examples of both injection molds and upper injection molds will be described with reference to FIGS.

    12 includes an element substrate 1300, a thin film transistor 1355, a thin film transistor 1365, a thin film transistor 1375, a first electrode layer 1317, an electroluminescent layer 1319, a second electrode layer 1320, a transparent conductive film 1321, a filler 1322, and a seal. Material 1325, gate insulating layer 1310, insulating film 1311, insulating film 1312, insulating film 1313, insulating film 1309, insulator (insulating layer) 1314, sealing substrate 1323, wiring layer 1380, terminal electrode layer 1381, anisotropic conductive The layer 1382, the FPC 1383, the spacer 1330, the spacer 1399a, and the spacer 1399b are included. As shown in FIG. 12, the spacers 1399a and 1399b on the insulator may be formed in a plurality of different shapes. The display device includes a separation region 221, an external terminal connection region 222, a wiring region 223, a peripheral driver circuit region 224, and a pixel region 226. The filler 1322 can be formed into a liquid composition by a dropping method as in the dropping method of FIG. The element substrate 1300 on which the filler is formed and the sealing substrate 1323 are attached to each other by a dropping method to seal the light-emitting display device.

    The display device in FIG. 12 is an emission type, and has a structure in which light is emitted from both the element substrate 1300 side and the sealing substrate 1323 side in the direction of the arrow. Note that in this embodiment, the first electrode layer 1317 is formed by forming a transparent conductive film and etching it into a desired shape. A transparent conductive film can be used as the first electrode layer 1317. In addition to the transparent conductive film, a titanium nitride film or a titanium film may be used as the first electrode layer 1317. In this case, after forming the transparent conductive film, the titanium nitride film or the titanium film is formed with a thickness enough to transmit light (preferably, about 5 nm to 30 nm). In this embodiment mode, ITSO is used as the first electrode layer 1317.

Next, a second electrode layer 1320 made of a conductive film is provided over the electroluminescent layer 1319. As the second electrode layer 1320, a material having a low work function (Al, Ag, Li, Ca, or an alloy or a compound thereof, MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used. In the display device in FIG. 6, a metal thin film (MgAg: film thickness of 10 nm) having a thin film thickness as the second electrode layer 1320 and an ITSO film with a film thickness of 100 nm are formed as the transparent conductive film 1321 so as to transmit light. Use lamination. As the transparent conductive film 1321, the same material as the above-described first electrode layer 1317 can be used.

    The display device of FIG. 11 is a one-side injection type, and has a structure in which upward injection is performed in the direction of the arrow. 11 includes an element substrate 1600, a thin film transistor 1655, a thin film transistor 1665, a thin film transistor 1675, a reflective metal layer 1624, a first electrode layer 1617, an electroluminescent layer 1619, a second electrode layer 1620, and a transparent conductive layer. Film 1621, filler 1622, sealant 1625, gate insulating layer 1610, insulating film 1611, insulating film 1612, insulating film 1613, insulating film 1609, insulator (insulating layer) 1614, sealing substrate 1623, wiring layer 1680, terminal The electrode layer 1681, the anisotropic conductive layer 1682, the FPC 1683, the spacer 1630, and the spacer 1699 are included. In the display device in FIG. 11, the insulating layer stacked over the terminal electrode layer 1681 is removed by etching. As described above, the reliability is further improved when the insulating layer having moisture permeability is not provided around the terminal electrode layer. In addition, the display device includes a separation region 231, an external terminal connection region 232, a wiring region 233, a peripheral driver circuit region 234, and a pixel region 236. In this case, a reflective metal layer 1624 is formed under the first electrode layer 1317 in the dual emission display device shown in FIG. A first electrode layer 1617 which is a transparent conductive film functioning as an anode is formed over the reflective metal layer 1624. As the metal layer 1624, it is only necessary to have reflectivity, so that Ta, W, Ti, Mo, Al, Cu, or the like may be used. Preferably, a substance having high reflectivity in the visible light region is used. In this embodiment, a TiN film is used.

A second electrode layer 1620 made of a conductive film is provided over the electroluminescent layer 1619. As the second electrode layer 1620, a material having a small work function (Al, Ag, Li, Ca, or an alloy or a compound thereof, MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) is used because it functions as a cathode. That's fine. In this embodiment mode, a stack of a thin metal film (MgAg: film thickness of 10 nm) as the second electrode layer 1620 and ITSO with a film thickness of 110 nm as the transparent conductive film 1621 so that light is transmitted is transmitted. Is used.

    A mode of a light-emitting element which can be applied in this embodiment mode is shown in FIG. The light-emitting element has a structure in which an electroluminescent layer 860 is sandwiched between a first electrode layer 870 and a second electrode layer 850. It is necessary to select materials for the first electrode layer and the second electrode layer in consideration of the work function, and the first electrode layer and the second electrode layer are both anodes or cathodes depending on the pixel configuration. sell. In this embodiment mode, when the polarity of the driving TFT is a p-channel type, the first electrode layer may be an anode and the second electrode layer may be a cathode. Further, since the polarity of the driving TFT is an N-channel type, it is preferable that the first electrode layer be a cathode and the second electrode layer be an anode.

    FIGS. 13A and 13B show the case where the first electrode layer 870 is an anode and the second electrode layer 850 is a cathode. The electroluminescent layer 860 is formed from the first electrode layer 870 side. , Buffer layer 804 composed of a stack of HIL (hole injection layer) and HTL (hole transport layer), EML (light emitting layer) 803, buffer layer composed of a stack of ETL (electron transport layer) and EIL (electron injection layer) It is preferable to stack 802 and the second electrode layer 850 in this order. FIG. 13A illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer 805 formed using a light-transmitting oxide conductive material, The electrode layer includes an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum from the electroluminescent layer 860 side. FIG. 13B illustrates a structure in which light is emitted from the second electrode layer 850. The first electrode layer is formed using a metal such as aluminum or titanium or nitrogen at a concentration equal to or lower than the stoichiometric composition ratio with the metal. An electrode layer 807 formed of a metal material containing silicon, and a second electrode layer 806 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%. The second electrode layer is composed of an electrode layer 801 containing an alkali metal or alkaline earth metal such as LiF or MgAg and an electrode layer 800 formed of a metal material such as aluminum from the electroluminescent layer 860 side. However, it is possible to emit light from the second electrode layer 850 by setting each layer to a thickness of 100 nm or less so that light can be transmitted.

    FIGS. 13C and 13D show the case where the first electrode layer 870 is a cathode and the second electrode layer 850 is an anode, and the electroluminescent layer 860 has an EIL (electron injection layer) from the cathode side. ) And ETL (electron transport layer), a buffer layer 802, an EML (light emitting layer) 803, a buffer layer 804 composed of a stack of HTL (hole transport layer) and HIL (hole injection layer), and a first anode. The two electrode layers 850 are preferably stacked in this order. FIG. 13C illustrates a structure in which light is emitted from the first electrode layer 870. The first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum, but each layer emits light from the first electrode layer 870 by setting the thickness to 100 nm or less so that light can be transmitted. It becomes possible to do. The second electrode layer includes, from the electroluminescent layer 860 side, a second electrode layer 806 formed of an oxide conductive material containing silicon oxide at a concentration of 1 to 15 atomic%, a metal such as aluminum or titanium, or the The electrode layer 807 is formed of a metal material containing nitrogen at a concentration equal to or lower than the stoichiometric composition ratio of metal. FIG. 13D illustrates a structure in which light is emitted from the second electrode layer 850, and the first electrode layer 870 includes an electrode layer containing an alkali metal or an alkaline earth metal such as LiF or MgAg from the electroluminescent layer 860 side. 801 and an electrode layer 800 formed of a metal material such as aluminum. The film thickness is large enough to reflect light emitted from the electroluminescent layer 860. The second electrode layer 850 includes an electrode layer 805 made of a light-transmitting oxide conductive material. Note that the electroluminescent layer can have a single-layer structure or a mixed structure in addition to the stacked structure.

    In addition, as the electroluminescent layer, materials that emit red (R), green (G), and blue (B) light are selectively formed by an evaporation method using an evaporation mask, respectively. A material that emits red (R), green (G), and blue (B) light can be formed by a droplet discharge method (such as a low-molecular or high-molecular material) in the same manner as a color filter. In this case, a mask is not used. Both are preferable because RGB can be separately applied.

In the case of a top emission type, when light-transmitting ITO or ITSO is used for the second electrode layer, BzOs—Li in which Li is added to a benzoxazole derivative (BzOs) or the like can be used. Further, for example, EML may be Alq ₃ doped with a dopant corresponding to each emission color of R, G, and B (DCM in the case of R, DMQD in the case of G).

    Note that the electroluminescent layer is not limited to the above materials. For example, instead of CuPc or PEDOT, an oxide such as molybdenum oxide (MoOx: x = 2 to 3) and α-NPD or rubrene can be co-evaporated to improve the hole injection property. The material of the electroluminescent layer can be used as an organic material (including a low molecule or a polymer), or a composite material of an organic material and an inorganic material. Hereinafter, materials for forming the light emitting element will be described in detail.

Among the charge injecting and transporting materials, materials having a particularly high electron transporting property include, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (5-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), Bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), quinoline skeleton or benzoquinoline Examples thereof include metal complexes having a skeleton. As a substance having a high hole-transport property, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, benzene ring-nitrogen) And a compound having a bond of

Among the charge injecting and transporting materials, materials having particularly high electron injecting properties include alkali metals or alkaline earths such as lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF ₂ ) and the like. Metal compounds can be mentioned. In addition, a mixture of a substance having a high electron transport property such as Alq ₃ and an alkaline earth metal such as magnesium (Mg) may be used.

Among the charge injecting and transporting materials, examples of the material having a high hole injecting property include molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), tungsten oxide (WOx), and manganese oxide. Examples thereof include metal oxides such as (MnOx). In addition, phthalocyanine compounds such as phthalocyanine (abbreviation: H ₂ Pc) and copper phthalocyanine (CuPc) can be given.

    The light emitting layer may be configured to perform color display by forming light emitting layers having different emission wavelength bands for each pixel. Typically, a light emitting layer corresponding to each color of R (red), G (green), and B (blue) is formed. In this case as well, it is possible to improve color purity and prevent mirror reflection (reflection) of the pixel portion by providing a filter that transmits light in the emission wavelength band on the light emission side of the pixel. Can do. By providing the filter, it is possible to omit a circularly polarized plate that has been conventionally required, and it is possible to eliminate the loss of light emitted from the light emitting layer. Furthermore, a change in color tone that occurs when the pixel portion (display screen) is viewed obliquely can be reduced.

There are various kinds of light emitting materials. As the low-molecular organic light-emitting material, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyl-9-julolidyl) ethenyl] -4H-pyran (abbreviation: DCJT), 4 -Dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJTB), perifrantene, 2,5 -Dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidin-9-yl) ethenyl] benzene, N, N'-dimethylquinacridone (abbreviation: DMQd), Coumarin 6, Coumarin 545T, Tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9,10-bis (2-naphthyl) anthrace (Abbreviation: DNA) or the like can be used. Other substances may also be used.

    On the other hand, the high molecular organic light emitting material has higher physical strength than the low molecular weight material, and the durability of the device is high. In addition, since the film can be formed by coating, the device can be manufactured relatively easily. The structure of the light emitting element using the high molecular weight organic light emitting material is basically the same as that when the low molecular weight organic light emitting material is used, and sequentially becomes a cathode, an organic light emitting layer, and an anode. However, when forming a light emitting layer using a high molecular weight organic light emitting material, it is difficult to form a laminated structure as in the case of using a low molecular weight organic light emitting material. . Specifically, the structure is a cathode, a light emitting layer, a hole transport layer, and an anode in this order.

    Since the light emission color is determined by the material for forming the light emitting layer, a light emitting element exhibiting desired light emission can be formed by selecting these materials. Examples of the polymer electroluminescent material that can be used for forming the light emitting layer include polyparaphenylene vinylene, polyparaphenylene, polythiophene, and polyfluorene.

    The polyparaphenylene vinylene system includes derivatives of poly (paraphenylene vinylene) [PPV], poly (2,5-dialkoxy-1,4-phenylene vinylene) [RO-PPV], poly (2- (2′- Ethyl-hexoxy) -5-methoxy-1,4-phenylenevinylene) [MEH-PPV], poly (2- (dialkoxyphenyl) -1,4-phenylenevinylene) [ROPh-PPV] and the like. The polyparaphenylene series includes derivatives of polyparaphenylene [PPP], poly (2,5-dialkoxy-1,4-phenylene) [RO-PPP], poly (2,5-dihexoxy-1,4-phenylene). ) And the like. The polythiophene series includes polythiophene [PT] derivatives, poly (3-alkylthiophene) [PAT], poly (3-hexylthiophene) [PHT], poly (3-cyclohexylthiophene) [PCHT], poly (3-cyclohexyl). -4-methylthiophene) [PCHMT], poly (3,4-dicyclohexylthiophene) [PDCHT], poly [3- (4-octylphenyl) -thiophene] [POPT], poly [3- (4-octylphenyl) -2,2 bithiophene] [PTOPT] and the like. Examples of the polyfluorene series include polyfluorene [PF] derivatives, poly (9,9-dialkylfluorene) [PDAF], poly (9,9-dioctylfluorene) [PDOF], and the like.

    Note that when a hole-transporting polymer-based organic light-emitting material is sandwiched between an anode and a light-emitting polymer-based organic light-emitting material, hole injection properties from the anode can be improved. In general, an acceptor material dissolved in water is applied by spin coating or the like. In addition, since it is insoluble in an organic solvent, it can be stacked with the above-described light-emitting organic light-emitting material. Examples of the hole-transporting polymer organic light emitting material include a mixture of PEDOT and camphor sulfonic acid (CSA) as an acceptor material, a mixture of polyaniline [PANI] and polystyrene sulfonic acid [PSS] as an acceptor material, and the like. .

    The light emitting layer can be configured to emit monochromatic or white light. In the case of using a white light emitting material, color display can be made possible by providing a filter (colored layer) that transmits light of a specific wavelength on the light emission side of the pixel.

To form a light emitting layer that emits white light, for _{example, Alq 3, Alq 3, Alq} 3 doped with Nile Red which is partly red light emitting pigment, p-EtTAZ, by TPD (aromatic diamine) evaporation A white color can be obtained by sequentially laminating. In the case where the EL is formed by a coating method using spin coating, it is preferable that baking is performed by vacuum heating after coating. For example, a poly (ethylenedioxythiophene) / poly (styrenesulfonic acid) aqueous solution (PEDOT / PSS) that acts as a hole injection layer is applied and baked on the entire surface, and then a luminescent center dye (1, 1,4,4-tetraphenyl-1,3-butadiene (TPB), 4-dicyanomethylene-2-methyl-6- (p-dimethylamino-styryl) -4H-pyran (DCM1), Nile Red, Coumarin 6 Etc.) A doped polyvinyl carbazole (PVK) solution may be applied to the entire surface and fired.

    The light emitting layer can also be formed as a single layer, and an electron transporting 1,3,4-oxadiazole derivative (PBD) may be dispersed in hole transporting polyvinyl carbazole (PVK). Further, white light emission can be obtained by dispersing 30 wt% PBD as an electron transporting agent and dispersing an appropriate amount of four kinds of dyes (TPB, coumarin 6, DCM1, Nile red). In addition to the light-emitting element that can emit white light as shown here, a light-emitting element that can obtain red light emission, green light emission, or blue light emission can be manufactured by appropriately selecting the material of the light-emitting layer.

    Furthermore, a triplet excitation material containing a metal complex or the like may be used for the light emitting layer in addition to a singlet excitation light emitting material. For example, among red light emitting pixels, green light emitting pixels, and blue light emitting pixels, a red light emitting pixel having a relatively short luminance half time is formed of a triplet excitation light emitting material, and the other A singlet excited light emitting material is used. The triplet excited luminescent material has a feature that the light emission efficiency is good, so that less power is required to obtain the same luminance. That is, when applied to a red pixel, the amount of current flowing through the light emitting element can be reduced, so that reliability can be improved. As a reduction in power consumption, a red light-emitting pixel and a green light-emitting pixel may be formed using a triplet excitation light-emitting material, and a blue light-emitting pixel may be formed using a singlet excitation light-emitting material. By forming a green light-emitting element having high human visibility with a triplet excited light-emitting material, power consumption can be further reduced.

    Examples of triplet excited luminescent materials include those using a metal complex as a dopant, and metal complexes having a third transition series element platinum as the central metal and metal complexes having iridium as the central metal are known. Yes. The triplet excited light-emitting material is not limited to these compounds, and a compound having the above structure and having an element belonging to group 8 to 10 in the periodic table as a central metal can also be used.

    The substances forming the light-emitting layer listed above are examples, and functionalities such as a hole injection transport layer, a hole transport layer, an electron injection transport layer, an electron transport layer, a light emission layer, an electron block layer, and a hole block layer are included. A light emitting element can be formed by appropriately stacking each layer. Moreover, you may form the mixed layer or mixed junction which combined these each layer. The layer structure of the light-emitting layer can be changed, and instead of having a specific electron injection region or light-emitting region, an electrode layer for this purpose is provided, or a light-emitting material is dispersed. Modifications can be made without departing from the spirit of the present invention.

    A light-emitting element formed using the above materials emits light by being forward-biased. A pixel of a display device formed using a light-emitting element can be driven by a simple matrix method or an active matrix method. In any case, each pixel emits light by applying a forward bias at a specific timing, but is in a non-light emitting state for a certain period. By applying a reverse bias during this non-light emitting time, the reliability of the light emitting element can be improved. The light emitting element has a degradation mode in which the light emission intensity decreases under a constant driving condition and a degradation mode in which the non-light emitting area is enlarged in the pixel and the luminance is apparently decreased. However, alternating current that applies a bias in the forward and reverse directions. By performing a typical drive, the progress of deterioration can be slowed and the reliability of the light emitting device can be improved. Further, either digital driving or analog driving can be applied.

    Therefore, a color filter (colored layer) may be formed on the sealing substrate. The color filter (colored layer) can be formed by an evaporation method or a droplet discharge method. When the color filter (colored layer) is used, high-definition display can be performed. This is because the color filter (colored layer) can correct a broad peak in each RGB emission spectrum to be a sharp peak.

    As described above, the case where a material that emits light of each RGB is formed has been described. However, full color display can be performed by forming a material that emits light of a single color and combining a color filter and a color conversion layer. The color filter (colored layer) and the color conversion layer may be formed, for example, on the second substrate (sealing substrate) and attached to the substrate.

    Of course, monochromatic light emission may be displayed. For example, an area color type display device may be formed using monochromatic light emission. As the area color type, a passive matrix type display unit is suitable, and characters and symbols can be mainly displayed.

    In the above configuration, a material having a small work function can be used as the cathode, and for example, Ca, Al, CaF, MgAg, AlLi, or the like is desirable. The electroluminescent layer may be any of a single layer type, a laminated type, and a mixed type having no layer interface. It is also formed from singlet materials, triplet materials, or combinations thereof, charge injection / transport materials containing organic compounds or inorganic compounds, and light-emitting materials, and low molecular organic compounds and medium molecular organic compounds (sublimation) based on the number of molecules. And an organic compound having a molecular number of 20 or less, or a chained molecule having a length of 10 μm or less), including one or more layers selected from macromolecular organic compounds, You may combine with the injection | pouring transport property or the hole injection transport property inorganic compound. The first electrode layer is formed using a transparent conductive film that transmits light. For example, in addition to ITO and ITSO, a transparent conductive film in which 2 to 20 atomic% of zinc oxide (ZnO) is mixed with indium oxide is used. Note that plasma treatment in an oxygen atmosphere or heat treatment in a vacuum atmosphere is preferably performed before forming the first electrode layer. A partition wall (also referred to as a bank) is formed using a material containing silicon, an organic material, and a compound material. A porous film may be used. However, it is preferable to use a photosensitive or non-photosensitive material such as acrylic or polyimide because the side surface has a shape in which the radius of curvature continuously changes and the upper thin film is formed without being cut off. This embodiment mode can be freely combined with the above embodiment modes.

    By using the present invention, a highly reliable display device can be manufactured through a simplified process. Therefore, a high-definition and high-quality display device can be manufactured at a low cost and with a high yield.

    This embodiment mode can be used in combination with each of Embodiment Modes 1 to 3.

(Embodiment 5)
One mode in which protective diodes are provided in the scanning line side input terminal portion and the signal line side input terminal portion will be described with reference to FIG. In FIG. 15, a pixel 2702 is provided with a TFT 501, a TFT 502, a capacitor 504, and a pixel electrode layer 503. This TFT has a configuration similar to that of the first embodiment. Spacers 510 a and 510 b are provided over the pixel electrode layer 503, and spacers 511 a and 511 b are provided over an insulator (not shown) that covers the periphery of the pixel electrode layer 503. Since this spacer supports a vapor deposition mask used for forming the electroluminescent layer on the pixel electrode layer 503, the spacer can prevent the mask from coming into contact with the pixel electrode layer 503 and causing damage.

    A protection diode 561 and a protection diode 562 are provided in the signal line side input terminal portion. This protection diode is manufactured in the same process as the TFT 501 or the TFT 502, and is operated as a diode by connecting the gate and one of the drain or the source. An equivalent circuit diagram of the top view shown in FIG. 15 is shown in FIG.

    The protection diode 561 includes a gate electrode layer, a semiconductor layer, and a wiring layer. The protective diode 562 has a similar structure. The common potential line 554 and the common potential line 555 connected to the protection diode are formed in the same layer as the gate electrode layer. Therefore, in order to electrically connect with the wiring layer, it is necessary to form a contact hole in the insulating layer.

    The contact hole to the insulating layer may be etched by forming a mask layer. In this case, if an atmospheric pressure discharge etching process is applied, a local electric discharge process is also possible, and it is not necessary to form a mask layer on the entire surface of the substrate.

    The signal wiring layer is formed of the same layer as the source and drain wiring layer 505 in the TFT 501, and has a structure in which the signal wiring layer connected thereto and the source or drain side are connected.

    The input terminal portion on the scanning signal line side has the same configuration. The protective diode 563 includes a gate electrode layer, a semiconductor layer, and a wiring layer. The protective diode 564 has a similar structure. The common potential line 556 and the common potential line 557 connected to the protection diode are formed in the same layer as the source and drain wiring layers. A protection diode provided in the input stage can be formed at the same time. Note that the position at which the protective diode is inserted is not limited to this embodiment mode, and can be provided between the driver circuit and the pixel.

(Embodiment 6)
A television device can be completed with the display device formed according to the present invention. In the display panel, only a pixel portion is formed as shown in FIG. 16A, and a scanning line side driver circuit and a signal line side driver circuit are mounted by a TAB method as shown in FIG. And a case where the TFT is formed by SAS as shown in FIG. 16B, and the pixel portion and the scanning line side driver circuit are integrated on the substrate. In some cases, the signal line side driver circuit is separately mounted as a driver IC, and the pixel portion, the signal line side driver circuit, and the scanning line side driver circuit are integrally formed over the substrate as shown in FIG. However, any form is acceptable.

    As other external circuit configurations, on the video signal input side, among the signals received by the tuner, the video signal amplification circuit that amplifies the video signal, and the signal output from it corresponds to each color of red, green, and blue And a control circuit for converting the video signal into the input specification of the driver IC. The control circuit outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit may be provided on the signal line side and an input digital signal may be divided into m pieces and supplied.

    Of the signals received by the tuner, the audio signal is sent to the audio signal amplifier circuit, and the output is supplied to the speaker via the audio signal processing circuit. The control circuit receives control information of the receiving station (reception frequency) and volume from the input unit, and sends a signal to the tuner and the audio signal processing circuit.

    As shown in FIGS. 20A and 20B, the display module can be incorporated into a housing to complete the television device. The display panel as shown in FIG. 1 attached up to the FPC is generally also referred to as an EL display module. Therefore, when an EL display module as shown in FIG. 1 is used, an EL television device can be completed. A main screen 2003 is formed by the display module, and a speaker portion 2009, operation switches, and the like are provided as other accessory equipment. Thus, a television device can be completed according to the present invention.

    Moreover, you may make it cut off the reflected light of the light which injects from the outside using a phase difference plate or a polarizing plate. In the case of a top emission display device, an insulating layer serving as a partition may be colored and used as a black matrix. This partition wall can also be formed by a droplet discharge method or the like. Carbon black or the like may be mixed with a pigment-based black resin or a resin material such as polyimide, or may be laminated. A different material may be discharged to the same region a plurality of times by a droplet discharge method to form a partition wall. As the retardation plate and retardation plate, a λ / 4 plate or a λ / 2 plate may be used and designed so that light can be controlled. As a configuration, a TFT element substrate, a light emitting element, a sealing substrate (sealing material), a phase difference plate, a phase difference plate (λ / 4 plate, λ / 2 plate), and a polarizing plate were sequentially emitted. The light passes through these and is emitted to the outside from the polarizing plate side. The retardation plate and the polarizing plate may be installed on the side from which light is emitted, and may be installed on both sides as long as the display is a double-sided emission type that emits light on both sides. Further, an antireflection film may be provided outside the polarizing plate. This makes it possible to display a higher-definition and precise image.

    As shown in FIG. 20A, a display panel 2002 using a display element is incorporated in a housing 2001, and reception of general television broadcasting is started by a receiver 2005, and a wired or wireless connection is made via a modem 2004. By connecting to a communication network, information communication in one direction (from the sender to the receiver) or in both directions (between the sender and the receiver or between the receivers) can be performed. The operation of the television device can be performed by a switch incorporated in the housing or a separate remote controller 2006, and this remote controller is also provided with a display unit 2007 for displaying information to be output. Also good.

    In addition, the television device may have a configuration in which a sub screen 2008 is formed using the second display panel in addition to the main screen 2003 to display channels, volume, and the like. In this configuration, the main screen 2003 may be formed using an EL display panel with an excellent viewing angle, and the sub screen may be formed using a liquid crystal display panel that can display with low power consumption. In order to prioritize the reduction in power consumption, the main screen 2003 may be formed using a liquid crystal display panel, the sub screen may be formed using an EL display panel, and the sub screen may blink. When the present invention is used, a highly reliable display device can be obtained even when such a large substrate is used and a large number of TFTs and electronic components are used.

    FIG. 20B illustrates a television device having a large display portion of 20 to 80 inches, for example, which includes a housing 2010, a keyboard portion 2012 that is an operation portion, a display portion 2011, a speaker portion 2013, and the like. The present invention is applied to manufacture of the display portion 2011. Since the display portion in FIG. 20B uses a bendable substance, the television set has a curved display portion. Since the shape of the display portion can be freely designed as described above, a television device having a desired shape can be manufactured.

    According to the present invention, since a display device can be formed through a simple process, cost reduction can be achieved. Therefore, a television device using the present invention can be formed at low cost even if it has a large screen display portion. Therefore, a high-performance and highly reliable television device can be manufactured with high yield.

    Of course, the present invention is not limited to a television device, but can be applied to various applications such as personal computer monitors, information display boards at railway stations and airports, and advertisement display boards on streets. can do.

(Embodiment 7)
Embodiments of the present invention will be described with reference to FIGS. 25, 26, 33 and 34. In this embodiment mode, an example of an active matrix display device using the present invention, which has different pixel arrangements and positions where spacers are provided, is shown. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    FIG. 25 is a top view of a pixel region in a stripe arrangement in which pixels are arranged in a stripe shape. A spacer 782 is formed over the first electrode layer 780 that is a pixel electrode layer, and a spacer 781 is formed over an insulator (insulating layer) 783 that functions as a partition wall that covers the end of the first electrode layer 780. Yes. The spacer 781 is formed via an insulator 783 on the intersection of the gate line and the source line. Since the mask is supported by the spacer 781 and the spacer 782 when the electroluminescent layer is formed, the mask does not damage the first electrode layer. Since a display defect or the like due to a shape defect of the first electrode layer does not occur, a display device with high image quality and high reliability can be manufactured.

    As the spacer, an inorganic insulating material or an organic insulating material can be used. In this embodiment, polyimide is used for the spacer 781 and the spacer 782, and the spacer 781 has a height of 1 to 1.5 μm (this embodiment 1.5 μm), and a bell-like shape having a tapered shape with a diameter increasing from the top surface to the bottom surface with a diameter of 10 μm to 15 μm (15 μm in this embodiment) in the top view. The spacer 781 is located between the power supply line and the source line and is provided in close contact with the pixel electrode layer, so that the mask for forming the electroluminescent layer can be supported more reliably and stably. Therefore, the pixel electrode layer can be protected from contact with the mask.

    FIG. 33 is a top view of a pixel region in a stripe arrangement in which pixels are arranged in a stripe shape. A spacer 582 is formed over the first electrode layer 580 that is a pixel electrode layer, and a spacer 581 is formed over an insulator (insulating layer) 583 that functions as a partition wall that covers the end of the first electrode layer 580. Yes. Since the mask is supported by the spacer 581 and the spacer 582 when the electroluminescent layer is formed, the first electrode layer is not damaged by the mask.

    As the spacer, an inorganic insulating material or an organic insulating material can be used. In this embodiment, acrylic is used for the spacer 581 and the spacer 582, and the spacer 581 has a height of 1 to 1.5 μm (this embodiment In this case, the shape is a bell shape having a tapered shape in which the diameter increases from the top surface to the bottom surface with a diameter of 5 μm in the top view. The spacer 781 is located between the power supply line and the source line and is provided in close contact with the pixel electrode layer, so that the mask for forming the electroluminescent layer can be supported more reliably and stably. Therefore, the pixel electrode layer can be protected from contact with the mask. Since a display defect or the like due to a shape defect of the first electrode layer does not occur, a display device with high image quality and high reliability can be manufactured.

    In the example shown in FIG. 25, the spacers on the insulator covering the periphery of the pixel electrode layer are provided along the gate line, corresponding to the intersection of the gate line and the source line, and along the source line in FIG. As shown in FIG. 34, an example of a display device having two types of spacers, a spacer 591a provided along a gate line and a spacer 591b provided along a source line, will be described.

    FIG. 34A is also a top view of a pixel region in a stripe arrangement in which pixels are arranged in a stripe pattern, as in FIGS. A spacer 592 is formed over the first electrode layer 590 which is a pixel electrode layer, and a spacer 591a and a spacer 591b are formed over an insulator (insulating layer) 593 functioning as a partition covering the end portion of the first electrode layer 590, respectively. Is formed. The spacer 591a is formed on the intersection of the gate line and the source line along the gate line with an insulator 593 interposed therebetween. The spacer 591b is formed through an insulator 593 along the source line.

    A cross-sectional view taken along line CD in FIG. 34A is illustrated in FIG. A gate line 597 is formed over the substrate 595, and a gate insulating layer 596 is formed. A spacer 591a and a spacer 591b are provided over the insulator 593 functioning as a partition wall. In this embodiment, the film thickness (height) of the spacer 591a, the spacer 591b, and the insulator 593 is 1.5 μm, and the total height of the insulator 593 and the spacer 591a or the spacer 591b is 3 μm. The spacer 591a has a bottom surface diameter of 10 μm to 15 μm (15 μm in this embodiment), and the spacer 591b has a bottom surface diameter of 5 μm. Both the spacer 591a and the spacer 591b have a tapered shape in which the diameter increases in the film thickness direction from the top surface to the bottom surface. Since the spacer is stable when it has an appropriate taper shape, the vapor deposition mask can also be supported stably. In addition, as shown in FIG. 34B, the spacer 591b has a rounded shape and a gentle shape having a curvature. Since the spacer 591b is located between the power supply line and the source line and is provided close to the pixel electrode layer, the mask for forming the electroluminescent layer can be supported more reliably and stably.

    Thus, by providing two or more types of spacers having different sizes and shapes, the mask for forming the electroluminescent layer can be more reliably and stably supported. Since the mask is supported by the spacer 592, the spacer 591a, and the spacer 591b when the electroluminescent layer is formed, the first electrode layer is not damaged by the mask. Since a display defect or the like due to a shape defect of the first electrode layer does not occur, a display device with high image quality and high reliability can be manufactured.

    FIG. 26 is a top view of a pixel region having a delta arrangement in which pixels are shifted by a half pitch for each line. A spacer 792 is formed over the first electrode layer 790 which is a pixel electrode layer, and a spacer 791 is formed over an insulator (insulating layer) 793 that functions as a partition wall covering the end portion of the first electrode layer 790. Yes. The spacer 782 over the first electrode layer 780 in FIG. 25 is formed without being in contact with the insulator 783, whereas the spacer 792 over the first electrode layer 790 in FIG. 26 is formed so as to be in contact with the insulator. The Thus, the shape of the spacer can be freely set. Since the mask is supported by the spacer 791 and the spacer 792 when the electroluminescent layer is formed, the mask does not damage the first electrode layer. Since a display defect or the like due to a shape defect of the first electrode layer does not occur, a display device with high image quality and high reliability can be manufactured.

(Embodiment 8)
An embodiment of the present invention will be described with reference to FIG. This embodiment mode shows an example of a passive display device using the present invention. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    27A is a top view of the passive display device, and FIG. 27B is a cross-sectional view taken along line AB in FIG. 27A. A first electrode layer 751 is formed over the substrate 750, and an insulator (insulating layer) 753 functioning as a spacer 752 and a partition is formed over the first electrode layer. A spacer 754 is formed over the insulator 753, and an electroluminescent layer 755 and a second electrode layer 756 are formed over the first electrode layer 751 to form a light emitting element. The spacer 752 and the spacer 754 support a mask when the electroluminescent layer 755 is deposited. Therefore, the first electrode layer is not damaged by the mask. Since a display defect or the like due to a shape defect of the first electrode layer does not occur, a high-quality and highly reliable passive display device can be manufactured with high yield.

(Embodiment 9)
An embodiment of the present invention will be described with reference to FIGS. In this embodiment, an example in which a channel-etched inverted staggered thin film transistor is used as the thin film transistor and the first interlayer insulating layer and the second interlayer insulating layer are not formed in the display device manufactured in Embodiment 1 is described. Therefore, repetitive description of the same portion or a portion having a similar function is omitted.

    The display device illustrated in FIG. 24 includes a substrate 700, a peripheral driver circuit region 255, an inverted staggered thin film transistor 701, an inverted staggered thin film transistor 702, a pixel region 256 having an inverted staggered thin film transistor 703, a first electrode layer 704, a spacer. 705a, spacer 705b, insulator (insulating layer) 709, electroluminescent layer 707, spacer 706, second electrode layer 708, filler 711, sealing substrate 710, sealing material 712 in the sealing region, terminal electrode layer 713, An anisotropic conductive layer 714, an FPC 715, a polarizing plate 717, and a protective film 716 serving as a passivation film are provided.

    The gate electrode layer, the source electrode layer, and the drain electrode layer of the inverted staggered thin film transistor 701, the inverted staggered thin film transistor 702, and the inverted staggered thin film transistor 703 which are manufactured in this embodiment are formed by a droplet discharge method. The droplet discharge method is a method in which a composition having a liquid conductive material is discharged and solidified by drying or baking to form a conductive layer or an electrode layer. An insulating layer can also be formed by discharging a composition containing an insulating material and solidifying it by drying or baking. Since a structure of the display device such as a conductive layer or an insulating layer can be formed selectively, the process can be simplified and material loss can be prevented, so that the display device can be manufactured with low cost and high productivity.

    The droplet discharge means used in the droplet discharge method is a general term for a device having means for discharging droplets such as a nozzle having a composition discharge port and a head having one or a plurality of nozzles. The diameter of the nozzle provided in the droplet discharge means is set to 0.02 to 100 μm (preferably 30 μm or less), and the discharge amount of the composition discharged from the nozzle is 0.001 pl to 100 pl (preferably 0). .1pl or more and 40pl or less, more preferably 10pl or less). The discharge amount increases in proportion to the size of the nozzle diameter. In addition, the distance between the object to be processed and the nozzle outlet is preferably as close as possible in order to drop it at a desired location, preferably about 0.1 to 3 mm (preferably about 1 mm or less). Set.

  A composition in which a conductive material is dissolved or dispersed in a solvent is used as the composition discharged from the discharge port. Conductive materials or materials that can be mixed with conductive materials include metals such as Ag, Au, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al, metal sulfides of Cd and Zn, Fe, Ti, It corresponds to fine particles or dispersible nanoparticles of materials such as oxides such as Si, Ge, Si, Zr and Ba, and silver halides. Further, it corresponds to indium tin oxide (ITO) used as a transparent conductive film, ITSO composed of indium tin oxide and silicon oxide, organic indium, organic tin, zinc oxide, titanium nitride, and the like. Moreover, you may use the said electroconductive material in mixture of multiple types. However, it is preferable to use a composition in which any of gold, silver and copper is dissolved or dispersed in a solvent in consideration of the specific resistance value, more preferably the composition discharged from the discharge port. It is preferable to use low resistance silver or copper. However, when silver or copper is used, a barrier film may be provided as a countermeasure against impurities. As the barrier film, a silicon nitride film or nickel boron (NiB) can be used.

  Alternatively, particles in which a conductive material is coated with another conductive material to form a plurality of layers may be used. For example, particles having a three-layer structure in which nickel boron (NiB) is coated around copper and silver is coated around it may be used. As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropyl alcohol and ethyl alcohol, organic solvents such as methyl ethyl ketone and acetone, water, and the like are used. The viscosity of the composition is preferably 20 mPa · s (cp) or less, in order to prevent the drying from occurring or to smoothly discharge the composition from the discharge port. The surface tension of the composition is preferably 40 mN / m or less. However, the viscosity and the like of the composition may be appropriately adjusted according to the solvent to be used and the application. As an example, the viscosity of a composition in which ITO, organic indium, or organic tin is dissolved or dispersed in a solvent is 5 to 20 mPa · s, the viscosity of a composition in which silver is dissolved or dispersed in a solvent is 5 to 20 mPa · s, The viscosity of the composition in which gold is dissolved or dispersed in a solvent is preferably set to 5 to 20 mPa · s.

  The conductive layer may be a stack of a plurality of conductive materials. Alternatively, first, silver may be used as a conductive material, and a conductive layer may be formed by a droplet discharge method, followed by plating with copper or the like. Plating may be performed by electroplating or chemical (electroless) plating. For plating, the substrate surface may be immersed in a container filled with a solution having a plating material, but the substrate is placed at an angle (or vertically) so that the solution having the material to be plated flows on the substrate surface. It may be applied. When plating is performed so that the solution is applied while standing the substrate, there is an advantage that the process apparatus is reduced in size.

  Although depending on the diameter of each nozzle and the desired pattern shape, the diameter of the conductor particles is preferably as small as possible for preventing nozzle clogging and producing a high-definition pattern. 1 μm or less is preferable. The composition is formed by a known method such as an electrolytic method, an atomizing method, or a wet reduction method, and its particle size is generally about 0.01 to 10 μm. However, when formed by a gas evaporation method, the nanomolecules protected by the dispersant are as fine as about 7 nm, and these nanoparticles are aggregated in the solvent when the surface of each particle is covered with a coating agent. And stably disperse at room temperature and shows almost the same behavior as liquid. Therefore, it is preferable to use a coating agent.

    Further, the step of discharging the composition may be performed under reduced pressure, and it is preferable to perform under reduced pressure because an oxide film or the like is not formed on the surface of the conductive layer. After discharging the composition, one or both steps of drying and baking are performed. The drying and firing steps are both heat treatment steps. For example, drying is performed at 100 degrees for 3 minutes, and firing is performed at 200 to 350 degrees for 15 minutes to 60 minutes. Time is different. The drying process and the firing process are performed under normal pressure or reduced pressure by laser light irradiation, rapid thermal annealing, a heating furnace, or the like. Note that the timing of performing this heat treatment and the number of heat treatments are not particularly limited. In order to satisfactorily perform the drying and firing steps, the substrate may be heated, and the temperature at that time depends on the material of the substrate or the like, but is generally 100 to 800 degrees (preferably 200). ~ 350 degrees). By this step, the solvent in the composition is volatilized or the dispersant is chemically removed, and the surrounding resin is cured and contracted to bring the nanoparticles into contact with each other, thereby accelerating fusion and fusion.

Irradiation with a laser beam used in the drying or baking process may be performed using a continuous wave or pulsed gas laser or solid state laser. Examples of the former gas laser include an excimer laser, a He—Cd laser, and an Ar laser. As the latter solid-state laser, crystals such as YAG, YVO ₄ , and GdVO ₄ doped with Cr, Nd, and the like are used. A laser etc. are mentioned. Note that it is preferable to use a continuous wave laser because of the absorption rate of the laser light. Further, a laser irradiation method combining pulse oscillation and continuous oscillation may be used. However, depending on the heat resistance of the substrate 700, the heat treatment by laser light irradiation may be performed instantaneously within a few microseconds to several tens of seconds so as not to destroy the substrate 700. Instantaneous thermal annealing (RTA) uses an infrared lamp or a halogen lamp that irradiates ultraviolet light or infrared light in an inert gas atmosphere, and rapidly raises the temperature for several minutes to several microseconds. This is done by applying heat instantaneously. Since this treatment is performed instantaneously, only the outermost thin film can be heated substantially without affecting the lower layer film. That is, it does not affect a substrate having low heat resistance such as a plastic substrate.

  In addition, after the conductive layer is formed, the surface may be pressed and flattened by pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-like object on the surface, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or melted with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

    In this embodiment mode, an amorphous semiconductor is used as a semiconductor layer, and a semiconductor layer having one conductivity type may be formed as needed. In this embodiment mode, an amorphous N-type semiconductor layer is stacked as a semiconductor layer and a semiconductor layer having one conductivity type. In addition, an N-type semiconductor layer is formed, and an NMOS structure of an N-channel TFT, a PMOS structure of a P-channel TFT having a P-type semiconductor layer, and a CMOS structure of an N-channel TFT and a P-channel TFT are manufactured. it can. In this embodiment mode, the inverted staggered thin film transistor 701 and the inverted staggered thin film transistor 703 are formed using N-channel TFTs, and the inverted staggered thin film transistor 702 is formed using P-channel TFTs. 701 and the inverted staggered thin film transistor 702 have a CMOS structure.

In order to impart conductivity, an element imparting conductivity is added by doping, and an impurity region is formed in the semiconductor layer, whereby an N-channel TFT or a P-channel TFT can be formed. Instead of forming the N-type semiconductor layer, conductivity may be imparted to the semiconductor layer by performing plasma treatment with a PH ₃ gas.

    Alternatively, an organic semiconductor material can be used as a semiconductor and can be formed by a printing method, a spray method, a spin coating method, a droplet discharge method, or the like. In this case, the number of processes can be reduced because the etching process is not necessary. As the organic semiconductor, a low molecular material, a polymer material, or the like is used, and materials such as an organic dye or a conductive polymer material can also be used. The organic semiconductor material used in the present invention is preferably a π-electron conjugated polymer material whose skeleton is composed of conjugated double bonds. Typically, a soluble polymer material such as polythiophene, polyfluorene, poly (3-alkylthiophene), a polythiophene derivative, or pentacene can be used.

    Since the mask for forming the electroluminescent layer is supported by the spacer 705a, the spacer 705b, and the spacer 706, the pixel electrode layer is not damaged by the mask. Thus, a display device with high image quality and high reliability can be manufactured.

  As a structure of the light-emitting element applicable to the present invention, the structure described in the above embodiment mode can be used. In addition, the structure of the light-emitting element in this embodiment described below can be used in combination with any of the above embodiments. A light-emitting element includes a plurality of layers sandwiched between a pair of electrodes, and at least one of them includes a layer containing a light-emitting substance (also referred to as an electroluminescent layer).

  An example of a suitable light-emitting element includes a layer containing a light-emitting substance and a mixed layer containing an inorganic substance and an organic substance at least one of the other layers. This mixed layer can be a hole injecting / transporting layer or an electron injecting / transporting layer depending on the selection of an inorganic substance and an organic substance.

  An example of a combination of hole injection / transport layers is as follows. Examples of the inorganic substance include molybdenum oxide (MoOx), vanadium oxide (VOx), ruthenium oxide (RuOx), tungsten oxide (WOx), and the like. In addition, indium tin oxide (ITO), zinc oxide (ZnO), and tin oxide (SnO) can be used. However, it is not limited to those shown here, and other substances may be used. The organic substance is a compound having a high hole transporting property, such as 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4. '-Bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) and 4,4', 4 ''-tris (N, N-diphenyl-amino) -triphenylamine (Abbreviation: TDATA), aromatic amine systems such as 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) (ie, Benzene ring-nitrogen bond). However, it is not limited to those shown here, and other substances may be used.

An example of a combination of electron injecting and transporting layers is as follows. The inorganic substance is one or more metals selected from lithium, cesium, magnesium, calcium, barium, erbium, and ytterbium, which exhibit electron donating properties. The organic substance is a substance having a high electron transporting property, and includes tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (5-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10− Hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), and other metals having a quinoline skeleton or a benzoquinoline skeleton It is a layer made of a complex or the like. In addition, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (abbreviation: Zn ( Metal complexes having an oxazole or thiazole ligand such as BTZ) ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5 -(P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5 (4-Biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2 , 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can also be used. However, it is not limited to those described in the present embodiment, and those described in the above embodiment and others may be used.

  A light-emitting element is formed by appropriately combining a layer containing a light-emitting substance and the above mixed layer. For example, a structure in which a hole injecting / transporting layer or an electron injecting / transporting layer is provided on one side of the layer containing a light-emitting substance can be employed. In addition, a structure in which a hole injecting / transporting layer is provided on one side and an electron injecting / transporting layer is provided on the other side with a layer containing a light-emitting substance interposed therebetween can be employed.

  Of the pair of electrodes, at least one or both of the electrodes are formed of indium oxide, tin oxide, zinc oxide, or a transparent conductive material in which at least a plurality of the oxides are mixed. For example, there are a mixture of indium oxide and tin oxide (also referred to as ITO), a mixture of indium oxide, indium oxide, and zinc oxide. Further, a transparent conductive material containing an appropriate amount of an oxide such as silicon oxide, titanium oxide, or molybdenum oxide may be used in order to suppress crystallization of these oxides and maintain surface smoothness. In addition, at least one of the pair of electrodes may be formed using a metal material containing aluminum, silver, titanium, tantalum, molybdenum, chromium, tungsten, or the like as a main component.

    The display device in FIG. 24 is a top emission display device in which light is extracted from the sealing substrate 710 side. The sealing substrate 710 includes a polarizing plate 716 and a protective film 716 on the element substrate side. The polarizing plate 716 is covered with the sealing substrate 710 and the protective film 716 and is protected from contamination and damage. In addition to the polarizing plate, a retardation plate (λ / 4 plate, λ / 2 plate) or an antireflection film may be provided. When a retardation plate or a polarizing plate is used, reflected light of light incident from the outside can be blocked, and a higher-definition and precise image can be displayed.

    FIG. 35 shows a dual emission type display device having a polarizing plate and a protective film. The display device of FIG. 35 is a dual emission type of the display device of FIG. 24. The same reference numerals are used in common between different drawings for the same parts or parts having the same functions as FIG. The repeated explanation is omitted. In FIG. 35, the protective film is provided as a protective film 726 on the side opposite to the element substrate of the sealing substrate. 35 is radiated from both the sealing substrate 710 side and the element substrate 700 side as indicated by an arrow in the drawing, and therefore, on the opposite side of the element substrate 700 from the element side, A polarizing plate 728 and a protective film 729 are provided. The protective films 726 and 729 protect the display device and the polarizing plate from contamination and damage, and increase the reliability of the display device. In addition to the polarizing plate, a retardation plate (λ / 4 plate, λ / 2 plate) or an antireflection film may be provided. When a retardation plate or a polarizing plate is used, reflected light of light incident from the outside can be blocked, and a higher-definition and precise image can be displayed.

As the protective film 716, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum nitride oxide (AlNO) in which the nitrogen content is higher than the oxygen content, or oxidation It can be formed of a material selected from materials including aluminum, diamond-like carbon (DLC), nitrogen-containing carbon film (CN), and other inorganic insulating materials. A siloxane resin may also be used. Moreover, an organic insulating material may be used, and as the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, or polysilazane can be used. A coating film formed by a coating method with good flatness may be used. In addition, a conductive material may be used if the design does not cause a failure in electrical characteristics such as a short circuit. In the display device of FIGS. 24 and 35, the protective film 716. Aluminum nitride oxide (AlN _X O _Y ) is used as the protective film 726 and the protective film 729, and the proportion of O in the composition in AlN _X O _Y is 0.1 to 30 atomic%. Since the AlN _X O _Y film has a thermal diffusion effect of diffusing heat, it can diffuse heat generated from the light emitting element, prevent deterioration of the light emitting element and the display device, and improve reliability. As shown in FIG. 24, when the protective film 716 is provided on the light emitting element side, it is closer to the light emitting element, so that the effect of thermal diffusion can be exerted greatly.

In this embodiment mode, as the filler 711, a liquid desiccant is injected dropwise and solidified. Therefore, since it is a substance including hygroscopicity, a water absorption effect can be obtained and deterioration of the element can be prevented. Further, as in the present embodiment, when the convex portion is formed by the spacer 198 and the sealing substrate 195 is supported by the convex portion, the distance between the element substrate and the sealing substrate is controlled to be uniform. can do. When the interval is uniform, the filler 711 is also uniformly filled, and a good and high-quality display can be performed without causing a display defect such as interference of light emitted from the light emitting element.
(Embodiment 10)

    This embodiment will be described with reference to FIG. In this embodiment, an example of a module using a panel including the display device manufactured in Embodiments 1 to 9 will be described.

    21A includes a controller 901, a central processing unit (CPU) 902, a memory 911, a power supply circuit 903, an audio processing circuit 929, a transmission / reception circuit 904, and other resistors. Elements such as a buffer and a capacitive element are mounted. Further, the panel 900 is connected to a printed wiring board 946 through a flexible wiring board (FPC) 908.

  The panel 900 includes a pixel portion 905 in which a light-emitting element is provided in each pixel, a first scanning line driver circuit 906 a that selects a pixel included in the pixel portion 905, and a second scanning line driver circuit 906 b. A signal line driver circuit 907 for supplying a video signal to the pixels is provided.

  Various control signals are input / output via an interface (I / F) unit 909 provided on the printed wiring board 946. An antenna port 910 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 946.

  Note that although the printed wiring board 946 is connected to the panel 900 through the FPC 908 in this embodiment mode, the present invention is not necessarily limited to this structure. The controller 901, the audio processing circuit 929, the memory 911, the CPU 902, or the power supply circuit 903 may be directly mounted on the panel 900 using a COG (Chip on Glass) method. In addition, the printed wiring board 946 is provided with various elements such as a capacitor element and a buffer to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

  FIG. 21B shows a block diagram of the module shown in FIG. The module 999 includes a VRAM 932, a DRAM 925, a flash memory 926, and the like as the memory 911. The VRAM 932 stores image data to be displayed on the panel, the DRAM 925 stores image data or audio data, and the flash memory stores various programs.

  In the power supply circuit 903, a power supply voltage to be supplied to the panel 900, the controller 901, the CPU 902, the sound processing circuit 929, the memory 911, and the transmission / reception circuit 931 is generated. Depending on the specifications of the panel, the power supply circuit 903 may be provided with a current source.

  The CPU 902 includes a control signal generation circuit 920, a decoder 921, a register 922, an arithmetic circuit 923, a RAM 924, an interface 935 for the CPU, and the like. Various signals input to the CPU 902 via the interface 935 are once held in the register 922 and then input to the arithmetic circuit 923, the decoder 921, and the like. The arithmetic circuit 923 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 921 is decoded and input to the control signal generation circuit 920. The control signal generation circuit 920 generates a signal including various instructions based on the input signal, and a location designated by the arithmetic circuit 923, specifically, a memory 911, a transmission / reception circuit 931, an audio processing circuit 929, a controller 901, and the like. Send to.

  The memory 911, the transmission / reception circuit 931, the sound processing circuit 929, and the controller 901 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 934 is sent to the CPU 902 mounted on the printed wiring board 946 via the interface 909. The control signal generation circuit 920 converts the image data stored in the VRAM 932 into a predetermined format in accordance with a signal sent from the input unit 934 such as a pointing device or a keyboard, and sends it to the controller 901.

  The controller 901 performs data processing on a signal including image data sent from the CPU 902 in accordance with the panel specifications, and supplies the processed signal to the panel 900. In addition, the controller 901 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply voltage 903 and various signals input from the CPU 902. Generated and supplied to the panel 900.

  In the transmission / reception circuit 904, signals transmitted / received as radio waves in the antenna 933 are processed. Specifically, high-frequency signals such as isolators, band-pass filters, VCOs (Voltage Controlled Oscillators), LPFs (Low Pass Filters), couplers, and baluns are used. Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 904 is sent to the audio processing circuit 929 in accordance with a command from the CPU 902.

  A signal including audio information sent in accordance with a command from the CPU 902 is demodulated into an audio signal by the audio processing circuit 929 and sent to the speaker 928. The audio signal sent from the microphone 927 is modulated by the audio processing circuit 929 and sent to the transmission / reception circuit 904 in accordance with a command from the CPU 902.

  The controller 901, the CPU 902, the power supply circuit 903, the sound processing circuit 929, and the memory 911 can be mounted as a package of this embodiment mode. The present embodiment can be applied to any circuit other than a high frequency circuit such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

  The display panel 900 includes a spacer on the pixel electrode or an insulator covering the periphery of the pixel electrode. Accordingly, the module including the display panel 900 supports the mask used when forming the electroluminescent layer so that it does not come into contact with the pixel electrode. Therefore, the pixel electrode can be prevented from being damaged, and high-quality display and high reliability can be achieved. Can play.

(Embodiment 11)
This embodiment will be described with reference to FIGS. FIG. 22 shows one mode of a portable small telephone (mobile phone) using radio including the module manufactured in the tenth embodiment. The display panel 900 can be incorporated in the housing 1001 in a detachable manner. The shape and size of the housing 1001 can be changed as appropriate in accordance with an electronic device to be incorporated.

  The housing 1001 to which the display panel 900 is fixed is fitted to the printed wiring board 946 and assembled as a module. On the printed wiring board 946, a controller, a CPU, a memory, a power supply circuit, a resistor, a buffer, a capacitor, and the like are mounted. Further, a signal processing circuit 993 such as an audio processing circuit including a microphone 995 and a speaker 995 and a transmission / reception circuit is provided. Panel 900 is connected to printed circuit board 946 through FPC 908.

  Such a module 999, input means 998, and battery 997 are housed in a housing 996. The pixel portion of the display panel 900 is arranged so as to be visible from an opening window formed in the housing 996.

  The display panel 900 includes a spacer on the pixel electrode or an insulator covering the periphery of the pixel electrode. Accordingly, the module including the display panel 900 supports the mask used when forming the electroluminescent layer so that it does not come into contact with the pixel electrode. Therefore, the pixel electrode can be prevented from being damaged, and high-quality display and high reliability can be achieved. Can play.

  A housing 996 illustrated in FIG. 22 illustrates an external shape of a telephone as an example. However, the electronic device according to this embodiment can be transformed into various modes depending on the function and application. An example of the aspect will be described in the embodiment described below.

(Embodiment 12)
Various display devices can be manufactured by applying the present invention. That is, the present invention can be applied to various electronic devices in which these display devices are incorporated in a display portion.

    Such electronic devices include cameras such as video cameras and digital cameras, projectors, head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, game machines, personal digital assistants (mobile computers, mobile phones or An electronic book), and an image reproducing apparatus (specifically, an apparatus having a display capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image). Examples thereof are shown in FIG.

    FIG. 23A illustrates a computer, which includes a main body 2101, a housing 2102, a display portion 2103, a keyboard 2104, an external connection port 2105, a pointing mouse 2106, and the like. By using the present invention, a computer that displays a high-quality image with high reliability even when the size is reduced and the pixels are miniaturized can be completed.

    FIG. 23B shows an image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2201, a housing 2202, a display portion A 2203, a display portion B 2204, and a recording medium (DVD etc.) reading portion 2205. , An operation key 2206, a speaker portion 2207, and the like. The display portion A2203 mainly displays image information, and the display portion B2204 mainly displays character information. By using the present invention, an image reproducing device that displays a high-quality image with high reliability even when the size is reduced and the pixel is miniaturized can be completed.

    FIG. 23C illustrates a mobile phone, which includes a main body 2301, an audio output portion 2302, an audio input portion 2303, a display portion 2304, operation switches 2305, an antenna 2306, and the like. By using the present invention, a mobile phone that displays a high-quality image with high reliability can be completed even if the device is downsized and pixels are miniaturized.

    FIG. 23D illustrates a video camera, which includes a main body 2401, a display portion 2402, a housing 2403, an external connection port 2404, a remote control reception portion 2405, an image receiving portion 2406, a battery 2407, an audio input portion 2408, an eyepiece portion 2409, and an operation. Key 2410 and the like. By using the present invention, a video camera that can display a high-quality image with high reliability even when the size is reduced and the pixel is miniaturized can be completed. This embodiment mode can be freely combined with the above embodiment modes.

6A and 6B illustrate a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 6A and 6B illustrate a display device of the present invention. 3A and 3B each illustrate a structure of a light-emitting element that can be applied to the present invention. FIG. 16 is an equivalent circuit diagram of the EL display device described in FIG. 15. FIG. 6 is a top view illustrating a display device of the present invention. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. The figure explaining the dripping injection method which can be applied to this invention. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. FIG. 11 illustrates an electronic device to which the present invention is applied. 6A and 6B illustrate a display device of the present invention. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. 6A and 6B illustrate a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. The top view of the display apparatus of this invention. 6A and 6B illustrate a display device of the present invention. 4A to 4D illustrate a method for manufacturing a display device of the present invention. The top view of the display apparatus of this invention. The top view of the display apparatus of this invention. 6A and 6B illustrate a display device of the present invention.

Claims (16)

Having a first spacer on the first electrode layer;
An insulating layer covering an end of the first electrode layer;
A second spacer on the insulating layer;
An electroluminescent layer on the first electrode layer and the first spacer;
A display device comprising a second electrode layer on the electroluminescent layer. Having a first spacer on the first electrode layer;
An insulating layer covering an end of the first electrode layer;
A second spacer on the insulating layer;
An electroluminescent layer on the first electrode layer and the first spacer;
A second electrode layer on the electroluminescent layer;
The display device, wherein the insulating layer and the first spacer are made of the same material. Having a first spacer on the first electrode layer;
An insulating layer covering an end of the first electrode layer;
A second spacer on the insulating layer;
An electroluminescent layer on the first electrode layer and the first spacer;
A second electrode layer on the electroluminescent layer;
The display device, wherein the first spacer and the second spacer are made of the same material.     4. The display device according to claim 1, wherein the first spacer and the second spacer are columnar.     5. The display device according to claim 1, wherein the first spacer and the insulating layer are separated from each other.     5. The display device according to claim 1, wherein the first spacer and the insulating layer are connected to each other.     5. The display device according to claim 1, wherein the first spacer and the second spacer are separated from each other.     5. The display device according to claim 1, wherein the first spacer and the second spacer are connected to each other. In any one of Claims 1 thru | or 8,
A thin film transistor including a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer;
The display device is characterized in that the source electrode layer or the drain electrode layer and the first electrode layer are electrically connected. Forming a first electrode layer;
Forming an insulating layer covering an end of the first electrode layer, and a first spacer on the first electrode layer;
Forming a second spacer on the insulating layer;
Forming an electroluminescent layer on the first electrode layer and the first spacer;
A method for manufacturing a display device, comprising forming a second electrode layer over the electroluminescent layer. Forming a first electrode layer;
Forming an insulating layer covering an end of the first electrode layer, and a first spacer on the first electrode layer;
Forming a second spacer on the insulating layer;
Providing a mask in contact with the second spacer, selectively forming an electroluminescent layer on the first electrode layer and the first spacer;
A method for manufacturing a display device, comprising forming a second electrode layer over the electroluminescent layer. Forming a first electrode layer;
Forming an insulating layer covering an end of the first electrode layer;
Forming a first spacer on the first electrode layer and a second spacer on the insulating layer;
Forming an electroluminescent layer on the first electrode layer and the first spacer;
A method for manufacturing a display device, comprising forming a second electrode layer over the electroluminescent layer. Forming a first electrode layer;
Forming an insulating layer covering an end of the first electrode layer;
Forming an insulating film on the first electrode layer and the insulating layer;
Processing the insulating film to form a first spacer on the first electrode layer and a second spacer on the insulating layer;
Forming an electroluminescent layer on the first electrode layer and the first spacer;
A method for manufacturing a display device, comprising forming a second electrode layer over the electroluminescent layer. Forming a first electrode layer;
Forming an insulating layer covering an end of the first electrode layer;
Forming a first spacer on the first electrode layer and a second spacer on the insulating layer;
Providing a mask in contact with the second spacer, selectively forming an electroluminescent layer on the first electrode layer and the first spacer;
A method for manufacturing a display device, comprising forming a second electrode layer over the electroluminescent layer. In any one of claims 10 to 14,
Forming a gate electrode layer;
Forming a gate insulating layer on the gate electrode layer;
Forming a semiconductor layer on the gate insulating layer;
A method for manufacturing a display device, comprising forming a source electrode layer and a drain electrode layer electrically connected to the first electrode layer over the semiconductor layer. In claim 15,
A method for manufacturing a display device, wherein the gate electrode layer, the source electrode layer, and the drain electrode layer are formed by discharging a composition containing a conductive material.