JP2006107659A - Optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital data reproducing device in which a PLL circuit capable of high speed frequency pulling in and phase pulling in suited for a PRML signal system is mounted having a circuit configuration considering characteristics of analog parts. <P>SOLUTION: In the digital data reproducing device for demodulating the digital data from an optical recording medium, switching a first frequency pulling in part for detecting synchronization pattern length, a synchronization pattern cycle and outputting the frequency error between oscillation frequency of an oscillation part and reproducing clock frequency, which the reproducing signal has, to a loop filter; a second frequency pulling in part for outputting the frequency error between wobble clock and the reproduction clock frequency, which the reproducing signal has, to the loop filter; and phase error of a phase comparison part by a switch part for outputting to the loop filter, so that the high-speed pulling in is made possible, the reproducing clock is generated, the digital data with multiple bits is outputted, and the data is reproduced by the PRML circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an apparatus for reproducing a signal from an optical disk, and in particular, extracts a synchronized clock signal and a multi-valued signal using a phase-locked loop such as a PLL (Phase-Locked Loop), and PRML (Partial Response Maximum Likelihood) The present invention relates to a device capable of reproducing a signal with a circuit.

In conventional optical disk playback devices, a multi-bit digital signal is sampled and PRML (Partial Response Maximum Likelihood) signal system that combines a partial response system and a Viterbi decoder that is one of the maximum likelihood decoding systems Has been proposed. This PRML signal system realizes a playback system that does not require high frequency components by intentionally adding waveform interference as the recording density in the linear recording direction increases, and by probability calculation considering waveform interference, This is a method for improving the quality of reproduced data (see Patent Document 1). In Patent Document 1, as a conventional example, a so-called wide capture method is described in which the VCO is controlled so that frequency control is performed up to a region where the reproduction clock and the reproduction digital signal can be synchronized. A sync pattern length in a specific period of one frame or more is detected, a cycle of the sync pattern is detected, and a frequency error amount for performing frequency control of the reproduction clock is detected.
JP 2003-36612 A (page 3, page 4, page 19, FIG. 14)

  First, the conventional wide capture method of Patent Document 1 has a problem that it takes a long time to lock the frequency.

  Here, in the case of CD, the “11T + 11T” pattern that appears once in 588T is a synchronization pattern, and in the case of DVD, “14T + 4T” that appears once in 1488T is a synchronization pattern.

  If these patterns are detected and the length of the synchronization pattern or the period of the synchronization pattern is measured, the frequency error can be detected. However, when this pattern is detected, it is determined whether or not the frequencies coincide with each other in each synchronization pattern cycle (one sync frame). The frequency error indicates whether the frequency of the VCO is faster or slower than the clock of the reproduction data. This signal controls the VCO through the loop filter and D / A.

  For example, when an image taken with a DVD camera is to be played back immediately, there is a demand for playback as early as 1 second during playback. Further, since the greatest feature of the optical disk apparatus is random access, it is necessary to speed up PLL synchronization at the time of high-speed seek.

  In the system disclosed in Patent Document 1, one A / D is used for the input stage, and two D / As are used for frequency control and phase control. When incorporated in an LSI, the circuit size of the analog component is significantly larger than that of a logic circuit. Especially high performance analog parts are particularly large. The component area directly determines the size of the LSI and affects the cost of the LSI. In addition, power consumption increases.

  At the present time, a 16-times DVD-RAM system has been studied, but the channel clock in this case is 466.88 MHz (1.times. Speed 29.18 MHz). Among analog parts, the AD converter can operate at a relatively high speed in terms of configuration, but the DA converter is difficult to increase in speed. In particular, there is generally no DA converter that can be built in an LSI that operates with a reproduction clock synchronized with the channel bit frequency of the 16-times DVD-RAM system. In addition, it is difficult to operate the DA converter with a 1/2 clock in the case of the 16-times DVD-RAM system.

  Secondly, there is a problem that when it is built in an LSI, it is necessary to reduce the circuit scale and power consumption as much as possible to reduce the cost, and to make the circuit configuration in consideration of the characteristics of the LSI process and analog parts.

  The present invention has been made to solve the above-described problems, and is equipped with a PLL circuit capable of high-speed frequency acquisition and phase acquisition adapted to the PRML signal system, thereby reducing the cost and consumption of the LSI. It is an object of the present invention to provide a digital data reproducing apparatus having a circuit configuration in consideration of power reduction and characteristics of analog parts.

  An object of the present invention is to extract a wobble signal corresponding to a wobbling recording guide groove wobbled periodically on a disc, and output a wobble signal as a binary signal synchronized with the wobble signal, and the optical disc An analog-to-digital conversion unit that samples the signal reproduced from the reproduction channel clock, an offset correction unit that corrects an offset of the sampled reproduction signal sampled by the analog-to-digital conversion unit, and the phase comparator The phase filter output for integrating and smoothing the obtained phase error output and the reproduction signal obtained by the offset correction unit are compared with the phase of the reproduction channel clock, and the sampling signal before and after the zero crossing is compared. The phase comparison unit for outputting the phase error to the loop filter and the output value of the loop filter And the oscillation frequency of the oscillation unit and the reproduction signal are detected by detecting the synchronization pattern length and the synchronization pattern period of the reproduction signal, so that the oscillation frequency of the oscillation unit approaches the reproduction clock frequency of the reproduction signal. A first frequency pull-in unit for outputting a frequency error from the reproduction clock frequency of the loop filter to the loop filter, and the wobble to bring the oscillation frequency of the oscillation unit close to the reproduction clock frequency of the reproduction signal at high speed. A frequency error between the wobble clock of the signal processing unit and the reproduction clock frequency of the reproduction signal, a second frequency pulling unit for outputting to the loop filter, a frequency error of the first frequency pulling unit, Switch unit for switching the frequency error of the second frequency pull-in unit and the phase error of the phase comparison unit to output to the loop filter The optical disk apparatus characterized by having, can be solved.

  The reproduction performance of digital data recorded on an optical disk medium is improved.

1. First Example FIG. 1 is a block diagram of a first example showing an embodiment of an optical disk apparatus of the present invention. Here, 1 is an optical disc such as a DVD-RAM in which prepit portions and data portions are alternately arranged, 2 is a spindle motor, 3 is an optical head (PU), 4 is an I / V converter, 5 is a Wobble processing portion, 6 is an RF data processing unit, 7 is an HPF, 8 is an A / D converter, 9 is a current controlled oscillator (ICO), 10 is a PLL unit that operates with a 1 / n clock of the channel bit rate, and 11 is a demodulated signal. Processing unit, 12 is a control unit, 13 is a host, 51 is a crystal oscillation unit (X'tal), 52 is a 1 / n frequency dividing unit that divides the Wobble clock or X'tal clock by 1 / n, and 61 is an auto gain Control (AGC) unit, 62 is a high-pass filter (HPF) unit, 63 is an equalizer (EQ) unit, 101 is a data serial / parallel conversion unit, 102 is an offset correction unit, 1030 is a first wide capture unit, and 1031 is a second Wide capture section, 104 is a phase comparator, 105 is a phase Switching unit for switching the period loop or frequency locked loop, 106 denotes a loop filter unit, 107 a D / A converter, respectively.

  The optical disk 1 is held and rotated by a spindle motor 2, and the optical head 3 forms a semiconductor laser that emits laser light for recording or reproducing information, and light from the semiconductor laser is formed as a light spot on the disk surface. And an optical detector for performing light spot control such as information reproduction and autofocus and track tracking using reflected light from the optical disk 1, and recording information on the optical disk 1, Information on the optical disc 1 is reproduced. The optical disk apparatus is connected to a host computer (hereinafter referred to as “host 13”) such as a personal computer or a workstation, and receives instructions and information data from the host 13 through a control unit 12 including a microcomputer or the like. Perform recording, playback, and seek operations (moving the head to the target track).

  Next, the operation of the reproduction process will be described. The host 13 issues a reproduction start instruction to the control unit 12, receives a signal from the optical head 3, and the I / V converter 4 converts the current / voltage converted reproduction signal into a wobble processing unit 5 and an RF data processing unit. 6 is output.

  The wobble signal processing unit 5 extracts a wobble signal corresponding to a wobbling recording guide groove wobbled periodically on the disk, and outputs a wobble clock as a binary signal synchronized with this signal. Further, it is possible to generate a clock obtained by dividing the clock of the crystal oscillation unit (X′tal) 51 by 1 / n.

  The RF data processing unit 6 includes an auto gain control (AGC) 61, a high pass filter (HPF) 62, an equalizer (EQ) 63, and the like. The AGC 61 controls the gain so that the amplitude of the signal from the I / V converter 4 becomes constant. The HPF 62 is provided to eliminate low-frequency DC fluctuations included in the reproduction signal. In the case of DVD-RAM, in order to reproduce the address of the header part, it is necessary to reduce the DC fluctuation of the header part, and a cutoff frequency (Fc) adjustment unit that switches the cutoff frequency of the HPF high is provided. The cut-off frequency is several kHz to several tens of kHz. Set the cut-off frequency at which the DC level after passing through the wound returns to normal.

  The EQ unit 63 corrects the attenuation of the high frequency component due to the optical characteristics. In the PRML system, the degree of influence on a plurality of bits is set to a value determined by the PR class, and the degree of interference between bits is controlled. For example, when PR (1, 2, 2, 1) is used, the characteristics of EQ 63 are corrected so as to be close to the frequency characteristics of PR (1, 2, 2, 1). In the case of DVD data modulated using PR (1, 2, 2, 1) and 8-16 modulated, the output sampled by the A / D converter described later is 0, 1, 3, 5, 6 Only the intermediate value of the five values is a possible value.

  Here, the input waveform of the A / D converter 8 will be described.

  A signal matching the input range of the A / D converter 8 is input to the A / D converter 8 from the RF data processing unit 6. For example, the standard input of the A / D converter 8 is about 1/2 to 3/4 of the input range.

FIG. 2 (a) shows PR (1, 2, 2, 1) waveform 3T-7T signals. Here, for example, a 4T signal is a signal in which a bit string written on a disk repeats 0000111100001111. When this signal is passed through PR (1, 2, 2, 1), the portion 1111 is output in the order of 1221 as shown below. That is,
01221
001221
0001221
00001221 sum,
013556510... Thus, only the five values 0, 1, 3, 5, 6 are possible values. It is necessary to input such an equivalent signal to the Viterbi complex in the demodulated signal processing unit 12. The equivalence may be performed by the EQ 63 of the RF data processing unit 6 or may be performed in the demodulated signal processing unit 11. In the 8-16 modulation method used in the DVD standard, a 3T to 14T signal is input from the analog front end unit (AFE) to the ADC. In FIG. 2A, the DC center is 3. The RF data processor 6 differentially inputs the center value 3 to the A / D converter so that the center value 3 becomes the center zero of the A / D converter output.

  FIG. 2B shows the output amplitude waveform of the A / D converter (when a 4T signal is input).

  A channel clock is generated by the PLL, and the A / D converter 8 samples the reproduction data using the channel clock. The sampling point takes a value between 0, 1, 3, 5, and 6 shown in FIG. In FIG. 2B, the center DC3 of 0 to 6 is represented as 0 (zero) of the output of the A / D converter, 3 or more is represented as +, and 3 or less is represented as-.

  The reason for taking the values between 0, 1, 3, 5, and 6 shown in FIG. 2 (a) is that the DPLL makes the clock phase so that the amplitude difference before and after the positive / negative switching point is zero by the phase comparator. It is for controlling. ● indicates data sampled with a clock of the channel frequency of the reproduced data (hereinafter referred to as channel clock).

  The center input DC value of the A / D converter is 0 at the output. In consideration of the input range of the A / D converter around this 0 (zero) center, the standard input to the A / D is determined. When the A / D converter is 7 bits, the A / D output takes values from −64 to +64 when expressed in two's complement.

  The PLL circuit 10 generates a reproduction clock for reproducing address data and user data from the RF signal that has passed through the RF data processing unit 6. The reproduction clock here is a channel bit rate clock (CK) for sampling data of the A / D converter 8 and a channel bit rate 1 / n clock for operating the digital circuit in the PLL 10. The channel bit rate clock (CK) is also used when the serial / parallel conversion unit 101 converts data from channel bit rate serial data to n parallel data. FIG. 3 shows a configuration outline of serial-parallel conversion when n = 4.

  The reproduced signal is reduced in offset by the HPF 7, sampled into a multi-bit digital signal by the A / D converter 8, further offset reduced by the offset correction circuit, and reproduced by the demodulated signal processing unit 11. The demodulated signal processing unit 11 is reproduced by a PRML signal method that combines a Viterbi decoder that is one of a partial response method and a maximum likelihood decoding method (maximum live-cliff).

  In the PRML signal system, since the sampled multi-bit digital signal value is meaningful in Viterbi decoding, it is important that the phase of the recovered clock is synchronized with the phase of the clock component of the recovered signal. In addition, it is necessary to output the reproduction clock stably without the PLL unit 10 being unlocked due to disturbances such as scratches and noise.

  Even if the RF data processor cannot detect a flaw, the flaw is detected (not shown), the output of the phase comparator is set to 0 so that the PLL unit 10 is not unlocked, and the integrator of the loop filter 106 Then, the output of the integrator of the offset correction unit 102 is held, and the oscillation frequency of the ICO unit 9 is held.

  The PLL circuit 10 that generates the reproduction clock is a digital PLL that controls the frequency of the oscillator by a digital value by the DA converter 10 7. From the signal corrected by the offset correction unit 102, a phase error before and after the zero cross point is extracted by the phase comparator 104, noise is removed by the loop filter 106, and the ICO 9 is oscillated via the DA converter 10 7. The sampling clock of the A / D converter and the 1 / n clock for data recovery are generated.

  Here, the offset correction unit 102 will be described. Offset correction is important for PLL circuits. If there is an offset in the input signal, the phase error signal is not correctly output and the worst lock occurs. Further, since it is impossible to detect a synchronization signal used in a wide capture described later, it is impossible to lock the frequency. The offset correction unit 102 is necessary to eliminate the DC offset as much as possible. The offset correction unit 102 is also referred to as duty feedback (DFB). The integrated signal, which is the output of the IIR filter, is subtracted from the output of the D / A converter and output to the demodulated signal processing unit 11 and the phase comparator 104 in the next stage. The offset correction unit 102 will be described. The signal input to the A / D converter is offset-corrected by the offset correction unit 102 so that the DSV (Digital Sum Value) becomes zero. DVD-RAM data is 8-16 modulated, and when data with 3 or 14 consecutive 0s or 1s restricted is reproduced on an ideal device, the DC average value of the playback signal is constant. It is always constant within the range. Such a signal is referred to herein as a DC-free signal. More specifically, DC free means that the DSV becomes 0 when the values are larger (+) and smaller (−) than the center value of the reproduction signal and are added for a certain period.

  Next, the phase comparator 104 will be described.

  For the output of the A / D converter 106, by subtracting the multiplication result of the sign bit and the data without the sign bit delayed by one clock from the multiplication result of the sign bit and the data without the sign bit delayed by one clock, The phase error can be expressed as an amplitude error (FIG. 2 (b)).

  It is sufficient if this calculation can be performed between channel clocks. When the channel clock is high speed, it is difficult to perform operations between the channel clocks, and thus parallel processing may be performed.

  FIG. 2B shows the 4T signal output of the A / D converter 8 and shows the operation of the phase comparator. If the phase is behind the playback data, the phase comparator output is negative. On the other hand, when the phase is ahead of the reproduction data, the phase comparator output is positive.

  Next, a circuit configuration for operating the PLL circuit at 1 / n in response to high speed will be described. First, the A / D converter 8 samples data with a channel clock. The A / D converter 8 needs to satisfy a high-speed specification that operates at a channel bit rate. The parallel conversion unit 101 converts sampling data from serial data to n parallel data. After conversion to parallel data, the PLL component is operated at 1 / n clock of the channel bit rate.

  When operating at 1 / n clock of the channel bit rate, the components whose circuit configuration is changed depending on the value of n require the phase comparator 104 that requires data before and after the zero cross point and data for each channel clock. This is an offset correction unit 102.

  On the other hand, when operated at a 1 / n clock of the channel bit rate, the circuit section that does not require a change in circuit configuration depending on the value of n uses an IIR filter that performs an integration operation, and is configured as a loop filter that operates at a low speed. Is an element.

  Without thinning out the A / D converter output data sampled with the channel clock, n phase comparators are used for parallel processing, the n data are added, latched, and output to the loop filter. As a result, the phase error before and after the zero cross point can be accurately output, and the PLL loop can be operated stably.

  In order to operate with a 1 / n clock, the following points should be noted.

  Operating with a 1 / n clock means that one FF operating with a channel clock is equivalent to n. When n is increased, the response of the PLL loop is deteriorated or the lock is not worst. Therefore, design is made with a circuit configuration that can maximize n by considering the response characteristics of the PLL loop from the maximum operating frequency, the number of bits of the A / D converter and D / A converter, the frequency sensitivity of the ICO, etc. According to the present invention, if n is less than or equal to n, a PLL circuit that operates any of several types of clocks can be created by controlling n via the host 13.

  Since the 1 / n clock is used for high-speed playback, power consumption can be reduced. Further, since sampled data is not thinned out, no error occurs and the quality of the reproduced signal does not deteriorate.

  Next, wide capture will be described.

  When the frequency of the clock component included in the reproduction signal is significantly different from the frequency of the reproduction clock generated by the PLL, the possibility of phase synchronization pull-in (cannot be locked) or pseudo-locking to a different frequency is performed. In order to avoid this, the clock generated by the PLL is brought close to the frequency of the clock component of the reproduction signal by wide capture so that the phase can be locked immediately after the frequency is locked.

  The first wide capture 1030 is a method of detecting a synchronization pattern as shown in the conventional wide capture method of Patent Document 1. Although there is no detailed description of the conventional example of Patent Document 1, it can be detected by the following method.

  Here, in the case of CD, the “11T + 11T” pattern that appears once in 588T is a synchronization pattern, and in the case of DVD, “14T + 4T” that appears once in 1488T is a synchronization pattern.

  By detecting these patterns and measuring the length of the synchronization pattern and the period of the synchronization pattern, the frequency error can be detected. When this pattern is detected, it is determined whether or not the frequencies are the same every cycle of the synchronization pattern (one sync frame). The frequency error indicates whether the frequency of the VCO is faster or slower than the clock of the reproduction data. This frequency error signal controls the ICO 9 via the loop filter 106 and the D / A 107.

  FIG. 4 shows a wide capture operation using a synchronization pattern. In the detection of the synchronization pattern, when frequency control is performed, since the frequencies do not match at first, one sync frame cannot be accurately counted. Therefore, a period called an interval period is determined, and synchronization detection is performed in the period. Specify the number of intervals as the number of lock-ins. Also specify the number of lockouts. FIG. 4A shows the operation when the number of intervals 4 and the number of lockouts 2 are specified. First, only the length of the synchronization pattern is determined for each interval. Since the synchronization pattern is the longest pattern included in the RF signal, the longest pattern of the interval period is stored, and the shortest pattern is regarded as the synchronization signal during the number of intervals.

  The numerical value of the frequency error output output after the channel clock is set from the host via the control unit. For example, if an integer value of 2 is set, -2 is output if the recovered clock is early. When the reproduction clock is slow, +2 is output. This value is input to the loop filter 106 via the switch 105, and the ICO 9 is controlled via the D / A 107. The length of the synchronization pattern is used for the lock-in function and the lock-out function for improving reliability.

  FIG. 4B shows a first wide capture sequence. In the case of DVD, the synchronization pattern length 14T can be detected, and after locking in, the synchronization pattern period is detected and a frequency error is output. By detecting the synchronization pattern period, the frequency error of the recovered clock can be made within 1%.

  FIG. 5 shows a configuration diagram of the first wide capture. Only the sign bit of the data sampled by AD is used. The sign bit indicates a binarized signal. The zero cross point is set as a slice level.

  The first wide capture 1030 is controlled by a switch 105 that selects a frequency loop and a phase loop so that a frequency error is output to the loop filter 106. After the frequency is pulled in (after the frequency lock), the switch 105 outputs not the frequency error but the phase error to the loop filter 106 by a signal indicating that the frequency has been pulled.

  The second wide capture 1031 compares the Wobble clock or X′tal clock output from the Wobble processing unit with the channel clock generated by the PLL. When operating at high speed, 1 / n clocks may be compared to reduce power consumption. Control is performed so that the channel clock frequency matches the reference frequency Wobble clock, and the PLL 10 is frequency-locked at high speed.

  As shown in FIG. 1, the second wide capture 1031 is controlled by a switch 105 that selects a frequency loop and a phase loop so that a frequency error is output to the loop filter 106. After the frequency is pulled in, the switch 105 outputs not the frequency error but the phase error to the loop filter 106 by a signal indicating that the frequency has been pulled. After locking the frequency, the phase comparator 104 locks the phase.

A schematic diagram of the second wide capture is shown in FIG. FIG. 8 shows the positioning of the second wide capture PLL circuit.
A count difference between the reproduction clock counter and a reference clock such as a Wobble clock is output as a frequency error. A clock obtained by dividing the Wobble clock can be used as a reference clock. For example, when using a Wobble clock, when using a Wobble clock divided by ¼, since n = 4, m = 25 (= 100/4) is set. When using the Wobble clock, since n = 1, m = 100 is set.

  The reference clock counter counts up to a value of m, and evaluates the frequency of whether the frequency of the recovered clock is faster or slower than the reference clock. The difference between the values of the reproduction clock counter is output as a frequency error. When it is within ± 1%, the frequency error output is 0 output. If the recovered clock is early, a negative value is output. When the reproduction clock is slow, a positive value is output. When the frequency difference is 2 to 1%, the frequency error output is ± 1, and when the frequency difference is 3 to 2%, the frequency error output is ± 2.

  In order to increase the reliability, the lock-in function assumes that the frequency error is within ± 1% if the frequency lock is continued for a predetermined number of times during frequency evaluation. Further, if the frequency error ± 1% does not continue for a predetermined number of times after locking by the lockout function, it is considered that the lockout has occurred.

  Whether the first wide capture or the second wide capture is used for the frequency pull-in is controlled by the switch 105 from the host 13 via the control unit 12.

  The first wide capture using the synchronization signal is used in the case of optical disc media (DVD-ROM, CD-ROM, etc.) that do not have Wobble. It is mainly used in a playback method in which the speed of the playback clock increases from the inner periphery to the outer periphery, as in CAV playback. If the recovered clock from the inner periphery to the outer periphery is constant during CLV playback, the frequency of the recovered clock is drawn in advance using the second wide capture by dividing or multiplying the X'tal clock. . Even with CAV playback, if the address is known in advance, it is possible to use a clock obtained by dividing or multiplying the X'tal clock.

Optical disk media (DVD ± R / RW, CD ± R / RW, etc.) on which Wobble exists draws the playback frequency with the Wobble clock by the second wide capture. When locked out, the frequency pull-in by the second wide capture is used again according to the synchronization pattern length detection result of the first wide capture.
FIG. 6 shows an auto wobble sequence using the first and second wide captures.
When the second wide capture is operating, and when the phase locked loop is operating instead of the frequency locked loop, the first wide capture does not output the frequency error to the loop filter 106, The length and appearance period of the synchronization signal are always detected. Therefore, it is used for detection that the PLL circuit 10 is unlocked when the preset number of times and the length of the synchronization signal is not 14T. For example, in the case of DVD, when the synchronization signal 14T is 15T, the frequency is shifted by 7%. Moreover, the case where the offset fluctuation | variation of an analog signal becomes large etc. can be considered. Since it is abnormal that the synchronization signal cannot be obtained several times, the frequency acquisition is performed again in the second wide capture. Since the frequency pull-in time is faster in the second wide capture than in the first wide capture, high-speed pull-in is possible. In the first wide capture, frequency evaluation is performed every sync frame (DVD: every 1488 channel clocks). On the other hand, the frequency of the second wide capture is evaluated every 100 channel clocks, and since an accurate frequency error amount can be output, the frequency pull-in of the second wide capture is better than the first wide capture. Is much faster.

  In addition, since the frequency-locked loop and the phase-locked loop are switched by the switch 105, it is possible to make a single system without using two loop filters and D / As as in Patent Document 1. Reduction, LSI cost reduction, and power consumption reduction.

2. Second Example Next, frequency pull-in during DVD-RAM playback will be described.

  FIG. 9A shows a DVD-RAM data format and timing signals.

  FIG. 9B shows a wide capture sequence when the second wide capture is used in the DVD-RAM mode.

  The DVD-RAM has a part in which an address is written in advance in the ID part and a partial data part having the same data format as the DVD-ROM. The ID unit synchronizes the frequency with the Wobble clock, and the data unit synchronizes the phase with the reproduction data. Alternatively, when data is not reproduced, it is possible to realize highly reliable data reproduction by synchronizing the frequency with the Wobble clock and synchronizing the phase with the reproduced data only when reproducing the data portion.

  Even when a DVD-RAM disk is used, since the frequency-locked loop and the phase-locked loop are switched by the switch 105, one system can be used without using two loop filters and D / A as in Patent Document 1. Therefore, it is possible to reduce circuit elements, reduce the cost of LSI, and reduce power consumption.

  Next, FIG. 10 shows a VFO wide capture configuration for capturing a VFO (Variable Frequency Oscillator) defined in the DVD-RAM standard. In the figure, VFO synchronous wide capture is used to widen the capture range when shifting from frequency synchronization synchronized with a wobble clock to phase synchronization synchronized with reproduction data. Thereby, even when the frequency of the wobble clock and the reproduction data is 1% or more apart, the phase can be drawn.

  Here, 4T-4T playback data continues in the DVD-RAM VFO period. That is, since the “rising edge” to “rising edge” of the data is 8T, the period from the “rising edge” to the “rising edge” of the reproduction data is measured, and the difference from 8T is obtained. When the period is longer than 8T, the value to speed up the recovered clock is output to the loop filter because the recovered clock is slow. When the period is shorter than 8T, the value to delay the recovered clock because the recovered clock is fast. Output to the filter. As a result, the capture range when shifting from frequency synchronization to phase synchronization can be expanded.

  In the above embodiment, a DVD disk has been described as an example. However, the scope of application of the present invention is not limited to a DVD-RAM, DVD ± R / RW, DVD-ROM, or the like. A similar PLL method can also be adopted in a recording / reproducing apparatus such as a blu-ray disc.

It is a figure which shows the 1st Example of the optical disk apparatus of this invention. FIG. 3 is a schematic diagram of a PR (1,2,2,1) pattern. It is a figure which shows serial parallel conversion (1/4 clock use). It is a figure which shows the operation | movement and sequence of a 1st frequency drawing-in part. It is a figure which shows the structure of a 1st frequency drawing-in part. It is a figure which shows the sequence of the 1st and 2nd frequency drawing-in part. It is a figure which shows a 2nd frequency drawing-in part. It is a figure which shows the structure of a 2nd frequency drawing-in part. It is a figure which shows the sequence of a DVD-RAM data format and a 2nd frequency drawing-in part. It is a figure which shows the example of arrangement | positioning of VFO synchronous wide capture.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Optical disk, 2 ... Spindle motor, 3 ... Optical head, 4 ... I / V converter, 5 ... Wobble processing part, 6 ... RF data processing part, 7 ... A / D converter, 8 ... 1 / n clock generation , 9... Current controlled oscillator (ICO), 10... PLL unit operating with 1 / n clock, 11... Demodulated signal processor, 12... Control unit, 13... Host computer, 51. ), 52... 1 / n divider, 61... Auto gain control (AGC), 62... High pass filter (HPF), 63. Equalizer (EQ), 101. , 1030... First wide capture unit, 1030... Second wide capture unit, 104... Phase comparator, 105... Switch unit for switching between phase locked loop or frequency locked loop, 10 6. D / A converter

Claims (4)

An optical disc apparatus for recording or reproducing information on an optical disc,
A wobble signal processing unit that extracts a wobble signal corresponding to a wobbled recording guide groove wobble of the disk and outputs a wobble clock as a binary signal synchronized with this signal;
An analog-to-digital converter that samples a signal reproduced from the optical disk based on a reproduction channel clock;
An offset correction unit that corrects an offset of the sampled reproduction signal sampled by the analog-digital conversion unit;
A loop filter unit for integrating and smoothing the phase error output obtained by the phase comparator;
A phase comparison unit for comparing the reproduction signal obtained by the offset correction unit and the phase of the reproduction channel clock, and outputting a phase error to the loop filter from sampling signals before and after zero crossing;
An oscillation unit whose oscillation frequency changes according to the output value of the loop filter;
In order to bring the oscillation frequency of the oscillation unit close to the reproduction clock frequency of the reproduction signal, the synchronization pattern length and the synchronization pattern period are detected from the sign bit information of the reproduction signal, and the oscillation frequency of the oscillation unit and the reproduction signal A first frequency pulling unit for outputting a frequency error with the reproduction clock frequency to the loop filter;
Output the frequency error between the wobble clock of the wobble signal processing unit and the reproduction clock frequency of the reproduction signal to the loop filter in order to bring the oscillation frequency of the oscillation unit close to the reproduction clock frequency of the reproduction signal at high speed. A second frequency pull-in section for
A switch unit for switching between a frequency error of the first frequency pull-in unit, a frequency error of the second frequency pull-in unit, and a phase error of the phase comparison unit and outputting to a loop filter is provided. Optical disk device. In claim 1,
The wobble clock of the wobble signal processing unit can be divided into 1 / n (n is a positive integer), and the 1 / n wobble clock is output.
The optical disk apparatus, wherein the second frequency pull-in unit synchronizes the reproduction channel clock with n times the reference frequency using the 1 / n wobble clock as a reference frequency. In claim 1,
The second frequency pull-in unit has a frequency pull-in completion output unit that performs frequency pull-in at high speed and outputs a signal indicating that the frequency pull-in is completed,
The change-over switch outputs a frequency error when performing the frequency pull-in by a frequency pull-in completion signal, and outputs a phase error output to the loop filter after the frequency pull-in is completed. . In claim 3,
The first frequency pull-in unit also reproduces the reproduced signal when the second frequency pull-in unit outputs a frequency error to the loop filter or a phase error to the loop filter by the switch. The sync pattern length and period included in the
When the phase error is output to the loop filter, if the synchronization pattern length cannot be obtained, the switch outputs the frequency error output of the second frequency acquisition unit to the loop filter instead of the phase error. Optical disk device to perform.