JP2006100387A - Field effect transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a Schottky transistor that controls the boundary shape of a source-drain and the height of a Schottky barrier as well as electrode specific resistance at the same time. <P>SOLUTION: An MIS field effect transistor is provided with: a semiconductor area 112 constituting a channel area; a gate electrode 114 formed on the semiconductor area 112 with a gate insulating film 113 in between; and a source-drain electrode formed on both sides of the semiconductor area 112 corresponding with the gate electrode 114. The source-drain electrode is formed by stacking in the direction of channel length a tunnel insulating film 116 that is formed with the semiconductor area 112 pinching in-between and of which thickness is made enough to be tunnelled by a carrier, a first metallic layer 117 that is formed in contact with the tunnel insulating film, and a second metallic layer 118 that is formed in contact with the first metallic layer 117 and has smaller specific resistance than the first metallic layer 117. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly, to a MIS field effect transistor with improved source / drain and a method for manufacturing the same.

  In order to improve the performance of a semiconductor integrated circuit, it is essential to improve the performance of a field effect transistor that is a component thereof. Up to now, improvement of device performance has been promoted by miniaturization of the device, but the limit of miniaturization has been pointed out in the future. In particular, formation of shallow junctions and reduction of parasitic resistance are considered to be serious problems. According to the international semiconductor roadmap, there is no solution for a 65 nm generation 10-20 nm junction (drain extension portion).

In recent years, MOSFETs (Schottky transistors) having a source / drain as a Schottky junction have been studied instead of the conventional pn junction (for example, see Non-Patent Document 1). In the Schottky transistor, diffusion of impurities is not used in the source / drain portion, and the source / drain is formed of metal, so that an extremely shallow junction is possible. In addition, since the resistance of the metal itself is extremely low, there are various advantages such as a reduction in electrode resistance, an elimination of the ion implantation process, and a simple process, and it is expected as a next-generation field effect transistor.
In this type of Schottky transistor, the Schottky junction of the source / drain portion determines its characteristics, and in order to achieve good characteristics, the metal Schottky barrier height used for the source / drain is used as a carrier. On the other hand, it is known that the following three conditions must be satisfied: reduction in size, formation of a flat interface shape, and low specific resistance of the metal itself. However, it has been difficult to satisfy all of these conditions.
JR Tucker et al, Appl. Phys. Lett., Vol. 65, no. 5, August 1994, pp. 618-620.

  As described above, Schottky transistors are conventionally effective for reducing parasitic resistance of the source / drain and suppressing the short channel effect. In this type of Schottky transistor, a metal Schottky barrier used for the source / drain is used. Three conditions must be satisfied: the height is made smaller than the carrier, the interface shape is formed flat, and the specific resistance of the metal itself is low. However, these three characteristics are essentially determined by the type of metal, and there is no means for arbitrarily controlling all these characteristics. To date, there has been no material that satisfactorily satisfies all these three characteristics for both nMOS and pMOS, and this has been one of the major factors hindering the practical application of Schottky transistors.

  The present invention has been made in consideration of the above circumstances, and the object of the present invention is to control the source / drain interface shape, Schottky barrier height, and electrode resistivity at the same time. An object of the present invention is to provide a MIS field effect transistor that can contribute to the realization of a Schottky transistor and a method for manufacturing the same.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, according to one embodiment of the present invention, a semiconductor region forming a channel region, a gate electrode formed over the semiconductor region with a gate insulating film interposed therebetween, and formed on both sides of the semiconductor region corresponding to the gate electrode MIS field effect transistor comprising a source / drain electrode formed, wherein the source / drain electrode is formed in contact with the semiconductor region on the source side and the drain side, respectively, and carriers can be tunneled A tunnel insulating film formed to a thickness, a first metal layer formed in contact with the tunnel insulating film, and a specific resistance formed in contact with the first metal layer and smaller than the metal layer. And a second metal layer having a layered structure in the channel length direction.

  Another embodiment of the present invention is a method for manufacturing a MIS field effect transistor, comprising: forming a semiconductor region constituting a channel region; and forming a gate electrode on the semiconductor region via a gate insulating film. Forming a tunnel insulating film with a thickness capable of tunneling carriers, sandwiching the semiconductor region from the channel length direction, and sandwiching the tunnel insulating film and the semiconductor region from the channel length direction. Forming a metal layer; forming a first metal layer, a tunnel insulating film, and a second metal layer having a specific resistance smaller than that of the metal layer by sandwiching the semiconductor region from the channel length direction; It is characterized by including.

  According to the present invention, by using the tunnel insulating film as a part of the source / drain electrode, the interface shape between the source / drain electrode and the channel region can be formed flat. In addition, since the portion in contact with the tunnel insulating film is the first metal layer and most of the other portions are the second metal layer, the Schottky barrier height can be set by selecting the first metal layer. The Schottky barrier height of the source / drain portion can be reduced with respect to the carrier. That is, the source / drain interface shape, the Schottky barrier height, and the electrode specific resistance can be controlled simultaneously, which contributes to the realization of a high-performance Schottky transistor.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a cross-sectional view showing an element structure of a MIS field effect transistor according to the first embodiment of the present invention.

  A buried insulating film 111 and a channel region 112 made of a silicon oxide film or the like are formed on the silicon substrate 110. A gate electrode 114 is formed on the channel region 112 via a gate insulating film 113, and a gate sidewall insulating film 115 is formed on the side surface of the gate electrode 114. A tunnel insulating film 116 is formed sandwiching the channel region 112 from the channel length direction, and a first metal layer 117 is formed on the outer side of the tunnel insulating film 116 in contact with the tunnel insulating film 116. Further, a second metal layer 118 is formed on the outside of the first metal layer 117 in contact with the metal layer 117. Here, the tunnel insulating film 116, the first metal layer 117, and the second metal layer 118 serve as source / drain electrodes.

  The feature of this embodiment is that the source / drain electrodes are not formed of a single layer of metal, but are formed of a tunnel insulating film 116 and first and second metal layers 117 and 118. Desirable requirements for these structures are as follows.

  The tunnel insulating film 116 is an insulating film of 2 nm or less so that carriers can sufficiently tunnel. Any material may be used, but silicon nitride, silicon oxide, silicon oxynitride, Hf (Si) O (N), etc. are desirable in consideration of consistency with the conventional process. The tunnel insulating film 116 can be formed by a thermal oxidation method, a CVD method, or the like, but its interface shape can be made extremely flat compared to a Schottky interface obtained by a normal silicide process. Also, by reducing the film thickness, carriers can easily tunnel through this film.

  The thickness of the first metal layer 117 may be equal to or greater than the Thomas Fermi shielding length (about 1 to 2 nm), and the material thereof may be a metal having a desired Schottky barrier (0.6 eV or less) against carriers. That's fine. Therefore, in addition to a single metal, not only a compound metal but also a metal whose work function is modulated by impurity doping may be used. A source / drain Schottky barrier is formed by the first metal layer 117.

  The second metal layer 118 is preferably a metal having a low specific resistance, and Co silicide, Ni silicide, Pa silicide, or the like is preferable in consideration of consistency with the conventional process. Due to the presence of the second metal layer 118, even if the specific resistance of the first metal layer 117 is high, the specific resistance of the entire device can be reduced.

  As described above, in this embodiment, the source / drain Schottky barrier height is controlled by the first metal layer 117, the interface shape is controlled by the tunnel insulating film 116, and the specific resistance is controlled by the second metal layer 118. It is a key transistor. This makes it possible to control each of the Schottky barrier height, interface shape, and resistivity of the Schottky transistor, which is usually difficult, to the desired state, thereby realizing a high-performance Schottky transistor. be able to.

  2 and 3 are cross-sectional views showing the manufacturing steps of the MIS field effect transistor of this embodiment.

  First, as shown in FIG. 2A, a buried insulating film 111 such as a silicon oxide film is formed on a silicon substrate 110 having a plane orientation (100) and a specific resistance of 2 to 6 Ωcm, and a silicon layer 112 is formed thereon. The prepared SOI substrate 100 is prepared. Then, on the SOI substrate 100, a polycrystalline silicon film to be an element isolation region (not shown), a gate oxide film (gate insulating film) 113, and a gate electrode is laminated by a known technique, and the polycrystalline silicon film is patterned. Thus, the gate electrode 114 is formed.

  Next, as shown in FIG. 2B, after depositing a silicon nitride film or the like by a low pressure chemical vapor deposition (LP-CVD) method or the like, the gate sidewall silicon nitride film 115 is etched back by an RIE method or the like. Form. Subsequently, the silicon layer 112 is selectively etched using the gate electrode 114 and the sidewall silicon nitride film 115 as a mask.

  Next, as shown in FIG. 2C, the silicon layer 112 is further slimmed by further etching. This slimmed region becomes a channel region. Subsequently, a tunnel insulating film 116 (SiN) is formed on the side surface of the channel region 112 by a known thermal oxidation method and oxide film nitridation method. That is, the tunnel insulating film 116 is formed so as to sandwich the channel region 112 from the channel length direction. At the same time, a silicon nitride film 121 is also formed on the gate electrode 114.

  Next, as shown in FIG. 2D, a polysilicon film 122 is deposited on the entire surface by LP-CVD or the like.

  Next, as shown in FIG. 3E, the polysilicon film 122 is etched back by the RIE method or the like to leave the polysilicon film 122 only on the side portion of the channel region 112. That is, the polysilicon film 122 is formed in contact with the tunnel insulating film 116 so as to sandwich the tunnel insulating film 116 and the channel region 112 from the channel length direction.

  Next, as shown in FIG. 3F, an aluminum film 123 is deposited to a thickness of 50 nm on the entire surface by sputtering or the like, and a Ni film 124 is deposited to a thickness of 150 nm thereon.

  Next, as shown in FIG. 3G, the upper portion is polished by CMP or the like until the gate electrode 114 is exposed.

  Next, for example, by performing heat treatment at 530 ° C. for 30 minutes, the first and second metal layers 117 and 118 are formed as shown in FIG. Specifically, when a thermal reaction occurs, an atomic exchange reaction occurs between the polysilicon film 122 and the aluminum film 123, and a first metal layer (Al) 117 is formed at the location where the polysilicon film 122 exists. The Further, the substituted silicon atom and the metal film 124 react to form a second metal layer (Ni silicide) 118 in contact with the first metal layer 117 so as to sandwich the first metal 117 from the channel length direction. Is done.

  Finally, by removing the unreacted Ni film 124, the structure as shown in FIG. 1 can be produced.

(Second Embodiment)
In the first embodiment, the first metal layer and the second metal layer are made of different metals. However, as described above, even if the Schottky barrier is adjusted to a desired value as the first metal layer. Therefore, the first metal layer and the second metal layer can be formed using the same metal material by introducing impurities into the interface.

  4 and 5 are sectional views showing the structure and manufacturing process of the MIS field effect transistor according to the second embodiment of the present invention based on such a viewpoint.

  First, as shown in FIG. 4A, an element isolation region (not shown) and a gate oxide film (gate insulation) are formed on an SOI substrate 200 including a silicon substrate 210, a buried insulating film 211, and a silicon layer 212 by a known technique. Film) 213 and gate electrode 214 are formed.

  Next, as shown in FIG. 4B, a silicon nitride film or the like is deposited by a low pressure chemical vapor deposition (LP-CVD) method or the like, and then etched back by an RIE method or the like to thereby form a gate sidewall silicon nitride film 215. Form. Subsequently, the silicon layer 212 is selectively etched using the gate electrode 214 and the sidewall silicon nitride film 215 as a mask. The basic process so far is the same as in the first embodiment.

  Next, as shown in FIG. 4C, the silicon layer 212 is further slimmed by further etching. This slimmed region becomes a channel region. Subsequently, a tunnel insulating film 216 (SiN) is formed on the side surface of the channel region 212 by a known thermal oxidation method and oxide film nitridation method. That is, the tunnel insulating film 216 is formed so as to sandwich the channel region 212 from the channel length direction. At the same time, a silicon nitride layer 221 is formed on the gate electrode 214.

  Next, as shown in FIG. 4D, a polysilicon film 222 is deposited on the entire surface by the LP-CVD method or the like. Unlike the first embodiment, this polysilicon film 222 is sufficiently thick, for example, formed to a thickness of 200 nm.

  Next, as shown in FIG. 5E, the upper portion is polished by CMP or the like until the gate electrode 214 is exposed.

  Next, as shown in FIG. 5F, impurities are ion-implanted into the polysilicon film 222 and activation annealing is performed to form a doping layer 223. More specifically, boron (B), for example, is implanted into the pMOS region, and phosphorus (P), for example, is implanted into the nMOS region, and spike annealing at about 1050 ° C. is performed.

  Next, as shown in FIG. 5G, a Ni film 224 is deposited to a thickness of about 25 nm by sputtering or the like.

  Next, for example, by performing heat treatment at 450 ° C. for 30 seconds, first and second metal layers 217 and 218 are formed as shown in FIG. Specifically, the Ni film 224 and Si of the polysilicon film 222 cause silicidation by heat treatment, and a NiSi film is formed. At this time, since impurities in the doping layer 223 gather at the reaction interface due to segregation, a first metal layer 217 containing impurities at a high concentration is formed in the vicinity of the tunnel insulating film 216 after the completion of silicidation. When the region becomes the second metal layer 218, the structure shown in FIG. 1 can be manufactured.

  Also in this embodiment, the interface shape can be flattened by the tunnel insulating film 216, the Schottky barrier height can be controlled by the first metal layer 217, and the low resistance of the source / drain can be achieved by the second metal layer 218. The same effects as those of the first embodiment can be obtained.

(Modification)
The present invention is not limited to the above-described embodiments. In the embodiment, an SOI substrate is used, but a bulk substrate can also be used. The substrate material is not necessarily limited to Si, and silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), and aluminum nitride (AlN) can be used. Furthermore, the plane orientation of the substrate material is not necessarily limited to the (100) plane, and the (110) plane or the (111) plane can be selected as appropriate.

  The essence of the present invention resides in the tunnel insulating film and the first and second metal layers constituting the source / drain electrodes. Therefore, the overlap or offset between the gate electrode and the source / drain electrode, the angle formed by the electrode with respect to the channel length direction, the position, etc. may be freely designed. Furthermore, the present invention includes three-dimensional types such as a Fin type structure and a double gate structure, and can be applied to all MIS type field effect transistors.

  In addition, various modifications can be made without departing from the scope of the present invention.

1 is a cross-sectional view showing an element structure of a MIS field effect transistor according to a first embodiment. Sectional drawing which shows the manufacturing process of the MIS type field effect transistor of 1st Embodiment. Sectional drawing which shows the manufacturing process of the MIS type field effect transistor of 1st Embodiment. Sectional drawing which shows the manufacturing process of the MIS type field effect transistor of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the MIS type field effect transistor of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100,200 ... SOI substrate 110,210 ... Silicon substrate 111,211 ... Embedded insulating film 112,212 ... Silicon layer (channel region)
113, 213 ... gate insulating film 114, 214 ... gate electrode 115, 215 ... gate sidewall insulating film 116, 216 ... tunnel insulating film 117, 217 ... first metal layer 118, 218 ... second metal layer 121, 221 ... Silicon nitride film 122, 222 ... Polysilicon film 123 ... Aluminum film 124 ... Ni film 223 ... Doping layer

Claims (8)

A semiconductor region constituting a channel region; a gate electrode formed on the semiconductor region via a gate insulating film; and source / drain electrodes formed on both sides of the semiconductor region corresponding to the gate electrode And
The source / drain electrodes are formed in contact with the semiconductor region on the source side and the drain side, respectively, and are formed in contact with the tunnel insulating film and a tunnel insulating film formed to a thickness capable of tunneling carriers. A first metal layer and a second metal layer formed in contact with the first metal layer and having a specific resistance smaller than that of the metal layer in the channel length direction. MIS type field effect transistor.   The tunnel insulating film is formed to sandwich the semiconductor region from the channel length direction, the first metal layer is formed to sandwich the tunnel insulating film and the semiconductor region from the channel length direction, and the second metal layer is 2. The MIS field effect transistor according to claim 1, wherein the MIS field effect transistor is formed by sandwiching the first metal layer, the tunnel insulating film, and the semiconductor region from the channel length direction.   3. The MIS field effect transistor according to claim 1, wherein the first metal layer is a metal that does not react with silicon, and the second metal layer is a metal silicide containing silicon.   The first metal layer is formed of the same material as the second metal layer, and the first metal layer contains an impurity that modulates a Schottky barrier, so that the first metal layer is different from the second metal layer. 3. The MIS type field effect transistor according to claim 1, further comprising a key barrier.   5. The MIS type field effect transistor according to claim 1, wherein the first and second metal layers are metal silicide containing silicon.   6. The impurity contained in the first metal layer is any one of B (boron), P (phosphorus), As (arsenic), indium, and antimony, or a plurality thereof. The MIS type field effect transistor as described.   2. The MIS field effect transistor according to claim 1, wherein the first metal layer is made of a metal having a Schottky barrier height of 0.6 eV or less. Forming a semiconductor region constituting a channel region;
Forming a gate electrode on the semiconductor region via a gate insulating film;
Sandwiching the semiconductor region from the channel length direction, forming a tunnel insulating film to a thickness that allows carriers to tunnel; and
Forming a first metal layer sandwiching the tunnel insulating film and the semiconductor region from the channel length direction;
Forming a second metal layer having a specific resistance smaller than that of the metal layer by sandwiching the first metal layer, the tunnel insulating film, and the semiconductor region from the channel length direction;
A method of manufacturing a MIS field effect transistor comprising:

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