JP2006196910A - In-situ cleaning method for semiconductor substrate, and manufacturing method of semiconductor element adopting the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an in-situ cleaning method for a semiconductor substrate, and a manufacturing method of a semiconductor element adopting it. <P>SOLUTION: A method for manufacturing an epitaxial layer includes a step for loading a substrate, having a semiconductor surface exposed into a reaction chamber. An oxide, existing on the exposed semiconductor surface, is decomposed, and the chamber in the process is excavated by a cleaning pressure so that a cleaning condition for deoxygenization is satisfied, so as to heat the substrate at a cleaning temperature. The cleaning condition is maintained during cleaning time so that the oxide is removed, a clean semiconductor surface is formed. The epitaxial layer is formed on the clean semiconductor surface. The substrate is unloaded from the reaction chamber. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for in-situ cleaning of a semiconductor substrate and a method for in-situ cleaning of semiconductors semiconductors and methods of manufacturing semiconductor semiconductors. Is.

  The manufacturing process of a semiconductor element includes forming a conductive or insulating thin film on a semiconductor substrate and patterning them. The quality of the thin film formed on the semiconductor substrate is greatly affected by the cleanliness of the process environment and the surface state of the semiconductor substrate on which the thin film is formed. The semiconductor substrate may be exposed to the atmosphere at any step during the manufacturing process of the semiconductor element. For example, the semiconductor substrate can be exposed to the atmosphere before being loaded into the process chamber. In this case, the surface of the semiconductor substrate can be contaminated by contaminants in the atmosphere. In particular, a natural oxide film formed on the surface of the semiconductor substrate with a non-stoichiometric composition can lower the electrical characteristics of the semiconductor element formed on the semiconductor substrate. Therefore, contaminants on the surface of the semiconductor substrate, especially the natural oxide film, should be removed through a separate cleaning process before each thin film forming process.

  Meanwhile, an epitaxial growth process is provided as an excellent means for forming a single crystal semiconductor layer on a single crystal semiconductor substrate. The epitaxial growth process was used to improve the operating characteristics of the bipolar transistor at an early stage, but has been widely used in the manufacture of CMOS direct circuits in recent years. For example, a selective epitaxial growth process (SEG process) is implemented to implement an elevated source / drain structure to improve the single channel effect and current driving capability of a MOS transistor. Has been applied. In addition, a hetero-epitaxial growth process is applied to form a strained channel for improving the carrier mobility of the MOS transistor.

  An epitaxial layer formed on the semiconductor substrate by the epitaxial growth process is grown along with the crystal structure of the semiconductor substrate. Therefore, the surface state of the semiconductor substrate greatly affects the quality of the epitaxial layer in the epitaxial growth step. As described above, the natural oxide film formed on the surface of the semiconductor substrate induces lattice defects such as slip or stacking fault in the epitaxial layer, so that it is preferably removed completely. For this, a cleaning process is performed before the semiconductor substrate for growing the epitaxial layer is loaded into the reaction chamber. The cleaning process is performed by a wet cleaning using an appropriate chemical solution or a chemical dry etching process. Furthermore, an in situ cleaning process is further performed after the cleaned semiconductor substrate is loaded into the reaction chamber. However, the in-situ cleaning process, which is also called a conventional hydrogen bake, is a high-temperature process that is usually performed in a hydrogen atmosphere at 850 ° C. to 1200 ° C. Therefore, the threshold voltage of the MOS transistor can be reduced by the diffusion of impurities doped in the semiconductor substrate during the in-situ cleaning process. In addition, when the semiconductor substrate is an SOI substrate, agglomeration of a top silicon layer may occur during the in-situ cleaning process.

  In conclusion, it is necessary to lower the temperature of the in-situ cleaning process in order to suppress the deterioration of the electrical characteristics of the semiconductor element in the epitaxial growth process.

  A technical problem to be solved by the present invention is a method for in-situ cleaning of a semiconductor substrate capable of effectively removing impurities such as a natural oxide film on the surface of the semiconductor substrate at a low temperature and a method for manufacturing an epitaxial layer employing the same. It is to provide.

  The present invention uses temperature that is substantially lower than that used during subsequent epitaxial deposition and that used in conventional cleaning methods, such as temperature related problems such as abnormal diffusion of impurities, autodoping ( Provided is an in-situ cleaning method capable of reducing auto doping, slip and stress problems and reducing the overall process time.

  Prior to forming the epitaxial layer, the low temperature used for cleaning and removing impurities from the silicon surface can reduce the thermal budget of the manufacturing process, and the CMOS device pre-formed on the substrate. Performance can be maintained

  The combination of temperature and pressure maintained in the reaction chamber sufficiently evaporates silicon oxide from the substrate surface. A carrier gas introduced into the pump and / or reaction chamber prevents exposure to equilibrium conditions by sufficiently removing silicon oxide vapor from the reaction chamber. In particular, the reaction chamber can be maintained in the reaction chamber such that the concentration of silicon oxide vapor is 50% or less, more preferably 10% or less of the equilibrium vapor pressure from the cleaning conditions. By reducing the partial pressure of the silicon oxide vapor in the reaction chamber, a reaction advantageous for the evaporation of the silicon oxide is promoted, and the evaporation rate of the silicon oxide can be increased.

  In an embodiment of the present invention, a substrate having an exposed semiconductor surface is loaded into a reaction chamber, and a cleaning condition is established in which oxygen present on the exposed semiconductor surface is decomposed to remove oxygen. The process chamber is evacuated with a cleaning pressure, the substrate is heated at a cleaning temperature, and the cleaning conditions are maintained during cleaning so that the oxide is removed, and a clean semiconductor surface ( forming a clean semiconductor surface, forming an epitaxial layer on the clean semiconductor surface, and unloading the substrate from the reaction chamber.

  By maintaining the cleaning pressure of about 50 mTorr or less and the cleaning temperature of about 800 ° C. or less with a cleaning time of about 200 seconds or less, the native oxide can be sufficiently removed from the semiconductor surface. Here, the term “about” is used to include deviations due to the performance of the apparatus and / or associated equipment used to adjust and / or measure one or more parameters to perform the method. For example, a heating facility set at 800 ° C. cannot generally maintain an accurate set temperature, and may show a deviation within an allowable range that is higher or lower than the set temperature. Thus, the use of the term “about” indicates that such a predictable deviation must be considered within the claimed parameters.

  A carrier gas, for example, a gas selected from the group consisting of hydrogen, argon, neon, krypton, and a mixed gas thereof is reacted at least at a certain time of the in situ cleaning process. It can be injected into the chamber. The reaction chamber is maintained in a vacuum condition during the in-situ cleaning process, and the carrier gas is injected into the reaction chamber, or the reaction chamber is maintained in a vacuum condition to supply the carrier gas to the reaction chamber. The partial pressure of the oxide vapor in the reaction chamber can be sufficiently reduced below the equilibrium condition for the temperature and pressure used. When the carrier gas is used, the carrier gas can be injected in a reaction chamber of substantially the same size at a flow rate that is less than that typically used in conventional hydrogen baking or etching processes. For example, when hydrogen is used, the flow rate of hydrogen may be about 25% or less, or about 10% or less, which is lower than the flow rate used in the conventional hydrogen baking process.

  Required to obtain a clean semiconductor surface by promoting the decomposition of the semiconductor oxide by reducing the partial pressure of the oxygen gas in the reaction chamber to about 50% or less, more preferably 10% or less of the equilibrium value. It is expected that process time can be shortened. In this case, in order to remove the oxide on the substrate without corrosion or damage to other structures, the vapor pressure of other materials exposed on the substrate must be taken into account, and the temperature in accordance with such considerations. And pressure conditions must be set.

  As will be described in detail below, the application of the in-situ cleaning process is not limited to the silicon surface, but other semiconductor surfaces, such as germanium, silicon / germanium, and binary compound semiconductors that are composed of two components. Materials (binary semiconductor materials), ternary compound semiconductor materials (tertiary semiconductor materials), quaternary compound semiconductor materials (quaternary semiconductor materials), and combinations of these semiconductor materials Can be done.

  An embodiment of the present invention processes a semiconductor substrate to form an intermediate device structure having an exposed semiconductor surface, and the intermediate device structure is loaded into a reaction chamber and is present on the exposed semiconductor surface. The process chamber is evacuated with a cleaning pressure and the substrate is heated at a cleaning temperature so that the oxide is decomposed and the cleaning condition for removing oxygen is established (establish) so that the oxide is removed. The cleaning conditions are maintained during a cleaning time to form a clean semiconductor surface, an epitaxial layer is formed on the clean semiconductor surface, and the semiconductor substrate is removed from the reaction chamber. A method of manufacturing a semiconductor device including loading is provided.

  The exposed semiconductor surface may include, for example, a source / drain region and / or a gate electrode surface. In addition, the structure of the epitaxial layer may include a single crystal structure, a polycrystalline structure, an amorphous structure, and a combination thereof.

  According to an embodiment of the present invention, a substrate having an exposed semiconductor surface is loaded in a reaction chamber, and oxides existing on the exposed semiconductor surface are decomposed and removed or converted into silicon by a reduction reaction. The cleaning conditions are maintained during the cleaning time so that the substrate is heated at the cleaning temperature by evacuating the process chamber with a cleaning pressure so that the oxides can be removed. Forming a clean semiconductor surface, forming an epitaxial layer on the clean semiconductor surface, and unloading the substrate from the reaction chamber. The manufacturing method of this is comprised.

  In some cases, the method of manufacturing the epitaxial layer may be performed in the process chamber so that a first cleaning condition is established in which an oxide existing on the exposed semiconductor surface is decomposed and removed (establish). The substrate is evacuated at a first cleaning pressure and the substrate is heated at a first cleaning temperature, so that a second cleaning condition is established in which oxide remaining on the exposed semiconductor surface is converted into silicon by a reduction reaction (establish). ) The process chamber is evacuated at a second cleaning pressure, the substrate is heated at a second cleaning temperature, and the second cleaning condition is maintained during the second cleaning time so that the remaining oxide is converted. Forming a clean semiconductor surface and epitaxially depositing on the clean semiconductor surface; Forming an epitaxial layer comprising forming a layer and unloading the substrate from the reaction chamber.

  According to an embodiment of the present invention, the process chamber is evacuated with a cleaning pressure so as to satisfy a cleaning condition in which an oxide existing on an exposed semiconductor surface is decomposed and removed (establish). A method for cleaning an exposed semiconductor surface, including heating at The decomposition step may be performed together with a reduction step that removes oxide remaining on the exposed semiconductor surface.

  According to the present invention, contaminants such as a natural oxide film on the surface of a semiconductor substrate can be effectively cleaned in situ at a low temperature. As a result, deterioration of the quality of the epitaxial layer can be prevented, and deterioration of the electrical characteristics of the semiconductor element can be minimized.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and can be embodied in other forms. Rather, the embodiments presented herein are provided so that the disclosed content will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout the specification.

  In order to grow an epitaxial silicon layer of excellent quality on the exposed silicon surface of the semiconductor substrate, the exposed silicon surface must be as perfect a crystal surface as possible. In particular, a process for removing contamination of the silicon surface must be performed, and the silicon surface has pits to prevent deterioration of the crystal lattice structure of the epitaxial layer formed during the subsequent epitaxial process. Or there should be no surface irregularities like other crystal defects. For example, contaminants such as oxides, metals and / or organics on the silicon surface can cause the formation of epitaxial layers having a variety of crystal defects.

  As is well known, an epitaxial layer having an irregular crystal lattice rather than a regular single crystal lattice reduces the yield, device characteristics and / or device reliability of the manufacturing process. For example, defects related to contamination lead to failure of in-line quality inspection during the manufacturing process, which lowers the wafer yield and increases the unit cost of the process. For example, device characteristics can be altered by unwanted mobile ionic contaminants that are incompatible with the device for the originally designed application and reduce the yield of the chip. Also, device reliability can be adversely affected by, for example, minute amounts of metal contaminants that move through the device structure and induce device failure. Therefore, in order to improve the quality of the epitaxial layer and reduce or prevent adverse effects on the yield, performance and reliability of the finally fabricated semiconductor device, contaminants and surface irregularities on the silicon surface It is important to remove

  Contaminant forms to be removed from the silicon surface include particulates, organic residues, and inorganic residues. The particulates include not only dust and smoke particles, but also other impurities commonly found in air and bacteria that have not grown and removed on the surface during wet processing. The organic residue may contain, for example, carbon, such as oil, a photoresist used during a photolithography process, or a compound contained within a chemical mechanical polishing (CMP) slurry composition. And a composition containing an organic compound. In addition, the inorganic residue includes carbon such as hydrochloric acid, hydrofluoric acid, or an oxide generated by exposing an unprotected silicon surface to an oxidizing atmosphere used in a previous step in the semiconductor manufacturing process. Related to compounds not included. As shown in the above-described example, the contamination source includes materials such as carbon and oxygen which are unavoidable from the environment as described above, and materials used or emitted in other steps in the semiconductor device manufacturing process. Including.

One method for cleaning the substrate surface prior to the epitaxial deposition process is to sequentially apply hydrochloric acid and ammonia hydroxide filled with peroxide. In this case, since the silicon surface is almost resistant to acids and bases, a very strong solvent can be used. However, as described above, the silicon surface reacts and bonds with impurities that are always present in the air or aqueous solution. On the other hand, a completely oxidized silicon surface such as silicon oxide (SiO ₂ ) is relatively inactive. Thus, silicon oxide and other residual contaminants should be removed from the silicon surface before the epitaxial process is performed.

  Since the in situ cleaning process is performed in the same chamber as the subsequent epitaxial process, it can provide a clean, non-oxidized silicon surface suitable for the epitaxial process. However, as described above, the conventional in-situ cleaning process involves heating the substrate to about 850 ° C. or higher, often 1200 ° C. While such a high temperature process can provide a clean surface, there is a risk of damage in the crystal structure and can increase the overall thermal budget of the final semiconductor device. Due to the continuous reduction of the dimensions of semiconductor devices, the manufacturing process of semiconductor devices must satisfy more stringent thermal budget requirements in order to prevent degradation of the electrical characteristics of the devices. In particular, the threshold voltage, which is the main device parameter, can be sensitively affected by excessive impurity diffusion due to excessive heating during the manufacturing process. .

<First embodiment>
Hereinafter, a semiconductor substrate having a silicon surface will be described. However, the present invention is not limited thereto, and various substrates such as a single crystal silicon substrate, an SOI substrate having single crystal silicon, and a single crystal silicon germanium are described. It can be applied to a substrate. In addition, the substrate applicable to the present invention is not limited to a single crystal germanium substrate and a single crystal silicon carbide substrate, but also various ternary compound semiconductor substrates, quaternary compound semiconductor substrates, and others known in this technical field. The semiconductor compound substrate can be included.

  The cleaning method according to the present invention can be used for a substrate that has not been processed and a substrate that has been processed after finishing some of the semiconductor manufacturing processes. The processed substrate may include circuit structures including wells, source / drain regions, junctions, gate electrode structures, various dielectrics and conductive films functionally associated with each other. Regardless of the progress of the process, the substrate may include at least a portion of the silicon surface exposed for epitaxial growth.

As shown in the flowchart of FIG. 1, first, a preliminary cleaning step (S3) is performed. The preliminary cleaning process (S3) is completed before the substrate is loaded into the reaction chamber. The preliminary cleaning process (S3) may be performed by a dry method and / or a wet method in order to remove bulk native oxide and other contaminants present on the substrate. In this case, an acidic solution applied to a normal RCA cleaning and / or piranha (H ₂ O ₂ / H ₂ SO ₄ ) wet cleaning process is used to remove organic and / or inorganic contaminants from the surface. be able to.

The RCA cleaning comprises (1) removing insoluble organic contaminants using a 5: 1: 1 H ₂ O: H ₂ O ₂ : NH ₄ OH solution, and (2) HF is against H ₂ O. Removing native oxide and metal contaminants using a 1:50 diluted solution, (3) ions and heavy metal atoms using a 6: 1: 1 H ₂ O: H ₂ O ₂ : HCl solution Removing the contaminants. As is well known, the specific steps in the wet process described above can be replaced or supplemented by a dry etching process. Also, a mechanical scrubber and / or rinse process can be applied to reduce particulates on the substrate surface. As mentioned above, most of the native oxide is removed in HF solution or buffered HF (BHF) solution, but the silicon surface with very high reactivity is a variety of chemicals applied to the surface. Can be at least partially oxidized during the rinsing and drying steps used to remove water. Therefore, it is necessary to perform in-situ cleaning before forming the epitaxial layer.

  As shown in FIGS. 1 and 2, after the substrate S is preliminarily cleaned, the substrate S is loaded into a reaction chamber 13 provided in the processing apparatus 11. (S5) The substrate S is positioned and supported on the chuck assembly 15 in the reaction chamber 13.

As shown in FIG. 2, the reaction chamber 13 is connected to one or more vacuum pumps. The vacuum pump removes a large volume of gas from the reaction chamber 13 and a high vacuum pump 17 such as a turbo molecular pump capable of reducing the pressure in the reaction chamber 13 to about 10 ⁻⁹ Torr, for example. A rough pump 19 that can reduce the pressure in the reaction chamber 13 to about 10 ⁻³ Torr can be included. Each pump can be connected to the reaction chamber 13 by an exhaust line regulated by one or more valves 21, 23.

  After the substrate S is positioned on the chuck assembly 15, which is also called a platen or a wafer support, a first purge process (S 7) is performed. The first purge step (S7) may include reducing the pressure in the reaction chamber 13 to about 100 Torr or less using the rough pump 19. Further, the first purge step (S7) may include injecting hydrogen gas into the reaction chamber 13 while evacuating the reaction chamber 13. Thus, during the first purge step (S7), the hydrogen gas is injected into the reaction chamber 13 while continuously removing the gas in the reaction chamber 13 using the rough pump 19. Residual nitrogen, residual oxygen and residual water vapor present in the reaction chamber 13 can be substantially removed. In more detail, during the first purge step (S7), after most of the oxidizing substances are removed from the reaction chamber 13 and the atmosphere in the reaction chamber 13 becomes a relatively pure hydrogen atmosphere, The reaction chamber 13 and the substrate S can be preheated at a temperature of about 300 ° C. to about 600 ° C.

When the first purge step (S7) is completed, the hydrogen gas is completely injected, and the pressure in the reaction chamber 13 is further reduced using the high vacuum pump 17. Accordingly, the pressure in the reaction chamber 13 is further reduced to about 10 ⁻¹ Torr or less, more specifically, about 10 ⁻⁹ Torr to less than the pressure maintained during the first purge (S7) process. The cleaning pressure is reduced to about 10 ⁻¹ Torr. (S9) Preferably, the pressure in the reaction chamber 13 can be reduced to 10 ⁻⁶ Torr to 10 ⁻³ Torr or 0.1 to 50 mTorr. The cleaning pressure is maintained during the in situ cleaning process using the rough pump 19 and the high vacuum pump 17.

  After the pressure in the reaction chamber 13 is maintained at the cleaning pressure, the substrate S is heated at a cleaning temperature of about 800 ° C. or less. (S11) According to the present invention, the pressure in the reaction chamber 13 is maintained at the cleaning pressure as described above. Therefore, the cleaning temperature of about 800 ° C. or less is sufficient to evaporate undesirable semiconductor oxide from the surface of the substrate S. Satisfactory results were also obtained when the cleaning temperature was about 600 ° C. to about 700 ° C., which was 800 ° C. or less.

  A carrier gas can be injected into the reaction chamber 13 at a relatively low flow rate of about 500 sccm or less during the heating of the substrate S at the cleaning temperature or until a subsequent cleaning process. In this case, the carrier gas may be hydrogen, argon, neon, xenon, an inert gas such as krypton, or a combination thereof. By selectively injecting the carrier gas into the reaction chamber 13, oxygen can be sufficiently removed from the oxide on the substrate S, which is preferable on a clean surface on the substrate S. No reaction can be suppressed. As described above, the oxygen gas concentration in the reaction chamber 13 is set to the saturation amount under the cleaning conditions set by injecting the selective carrier gas while evacuating the reaction chamber 13 at the cleaning pressure. It can be maintained at about 50% or less.

As described above, hydrogen can be used as a selective carrier gas, but in this case, the amount and temperature of the injected hydrogen are considered for reducing silicon dioxide (SiO ₂ ) in a conventional hydrogen baking process. It will be less than and less than the amount of hydrogen and temperature. For example, the flow rate of hydrogen injected as a carrier gas in a given reaction chamber can be about 10% or less, or even about 3% or less of the flow rate used in conventional hydrogen baking processes.

  Thereafter, the substrate S is maintained at the cleaning pressure and the cleaning temperature for an appropriate range of cleaning time. (S13) As a result, all the contaminants on the substrate S, for example, oxygen decomposed from the natural oxide film on the exposed silicon surface of the substrate S can be removed. The cleaning time varies within a range of about 10 seconds to about 500 seconds depending on the amount of exposed silicon surface and the cleaning temperature, the cleaning pressure, and the position of the substrate S to be cleaned, depending on the amount of exposed silicon surface and the degree of contamination by a natural oxide film. be able to. In one embodiment, the cleaning time can be about 30 seconds to 120 seconds, such as about 60 seconds, during which time sufficient cleaning can be performed.

  After the substrate S is cleaned while maintaining the cleaning temperature and the cleaning pressure during the cleaning time, hydrogen gas can be injected into the reaction chamber 13. (S15) or an inert gas other than the hydrogen gas may be injected. The hydrogen gas is injected to make the cleaned silicon surface more suitable for a subsequent silicon epitaxial process. Thereafter, the temperature of the substrate S can be adjusted as an epitaxial process temperature. In this case, after cleaning is completed, the cleaning temperature is preferably close to the temperature of the subsequent epitaxial process in order to minimize additional temperature increase and temperature adjustment at the epitaxial process temperature.

After adjusting the substrate S to a temperature suitable for the growth of the epitaxial layer, an epitaxial layer is grown on the exposed semiconductor surface. (S17) The epitaxial process for forming the epitaxial layer is performed in situ in the reaction chamber 13 in which the cleaning process is performed. More specifically, a reaction gas is injected into the reaction chamber 13. In this case, the reaction gas is determined by the type of epitaxial layer to be formed. For example, the reaction gas may be a silicon source gas such as SiH ₄ or SiH ₂ Cl ₂ . The reaction gas may be a germanium source gas such as GeH ₄ or GeH ₂ Cl. In addition, the reaction gas can be another semiconductor source gas.

  When a semiconductor manufacturing process for the substrate S is not performed in advance, that is, when a structure such as a conductive layer, an insulating layer, a semiconductor layer, or a pattern thereof is not formed on the substrate S, the epitaxial layer is formed on the substrate S. It can be formed on the entire surface. On the other hand, when a semiconductor manufacturing process for the substrate S is performed in advance before forming the epitaxial layer, the epitaxial layer is formed on the exposed silicon surface and / or the exposed polysilicon surface like a polysilicon gate electrode. Can only grow selectively.

  The epitaxial layer formed or grown on the exposed surface may not be the same material as the exposed surface. That is, an appropriate amount of another alloy element can be injected into the reaction chamber 13 together with the reaction gas to form an epitaxial layer having other characteristics physically or electrically. Such techniques can be used to form strained lattice layers and can be used to form ternary and quaternary compound semiconductor layers such as AlGaN, InGaN, AlInGaN, and AlPGaN. be able to.

  After performing the cleaning and epitaxial layer growth step as described above, the second purge step (S19) is performed. The second purge process (S19) is performed by injecting hydrogen gas or one or more inert gases into the reaction chamber 13. In addition, the substrate S can be cooled from the epitaxial deposition temperature while the second purge step (S19) is performed, and hydrogen gas or one or more injected during the second purge step (S19). The inert gas can suppress undesirable reactions that may occur during such a cooling process.

<Second embodiment>
3A to 3D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention.

  Referring to FIG. 3A, an isolation layer 102 that defines an active region is formed in a semiconductor substrate 100. The semiconductor substrate 100 may include silicon, silicon / germanium, silicon carbide, or germanium. A gate pattern 110 is formed on the active region. The gate pattern 110 includes a gate oxide layer 104 and a gate electrode 106 stacked on the semiconductor substrate 100. The gate electrode 106 may be a doped polysilicon or amorphous silicon layer. The gate electrode 106 may include a silicide layer to reduce resistance. In addition, the gate pattern 110 may include a capping layer 108 stacked on the gate electrode 106. The capping layer 108 is formed to protect the upper surface of the gate electrode 106 and may be formed on a silicon nitride film.

  Referring to FIG. 3B, after the gate pattern 110 is formed, an initial ion implantation process called LDD (lightly doped drain) ion implantation is performed to form a low concentration impurity region 118. That is, impurity ions are implanted into the active region using the gate pattern 110 as an ion implantation mask to form a low concentration impurity region 118. Next, an insulating film is formed on the semiconductor substrate 100 on which the low concentration impurity region 118 is formed. The insulating film can be formed by sequentially stacking a silicon oxide film and a silicon nitride film. Thereafter, the insulating film is anisotropically etched to form gate spacers 116 on the sidewalls of the gate pattern 110. In this case, the gate spacer 116 is formed to include an inner oxide spacer 112 and an outer nitride spacer 114.

  After the gate spacer 116 is formed, impurity ions are implanted into the active region using the gate pattern 110 and the gate spacer 116 as an ion implantation mask to form a source / drain region 120. The source / drain region 120 is formed to have a higher impurity concentration than the low concentration impurity region 118. After the ion implantation process for forming the source / drain region 120, a normal heat treatment is performed to activate the impurity ions in the source / drain region 120. Meanwhile, the impurity ion implantation process for forming the source / drain regions 120 can be performed after growing an epitaxial layer described later.

  Referring to FIG. 3C, an epitaxial layer 122 is grown on the exposed surface of the semiconductor substrate 100 having the gate pattern 110 and the source / drain regions 120. As described above, the step of growing the epitaxial layer 122 may include a pre-cleaning step (S3 in FIG. 1) performed before that. By performing the preliminary cleaning process, most contaminants present on the exposed surface of the semiconductor substrate 100 can be removed.

  After performing the preliminary cleaning step (S3 in FIG. 1), the semiconductor substrate 100 is loaded into the reaction chamber. (S5 in FIG. 1) Next, after performing the first purge process (S7 in FIG. 1), the in-situ cleaning process described with reference to FIGS. 1 and 2 is performed. (S9 to S15 in FIG. 1) As a result, after performing the preliminary cleaning, residual contaminants on the exposed surface of the semiconductor substrate 100, and before the atmosphere in the reaction chamber is established as an oxidizing atmosphere. The formed natural oxide film is effectively removed. The in-situ cleaning process uses a temperature lower than that used in the conventional hydrogen baking process. Even when hydrogen is used, it is used at a smaller flow rate than the conventional hydrogen baking process. In one embodiment, the in-situ cleaning process may be performed at a pressure of about 50 mTorr or less, such as 0.1 mTorr or less, and a temperature of about 650 ° C. to about 750 ° C., eg, about 700 ° C., for about 30 m. Second to about 180 seconds, such as 60 seconds.

  The time required for the in-situ cleaning process is applied to the exposed surface area of the semiconductor substrate, the pre-cleaning process, the method of handling the semiconductor substrate between the pre-cleaning process and the in-situ cleaning process, the volume of the reaction chamber and the in-situ cleaning process. Can be influenced by variables such as process conditions.

After performing the in-situ cleaning process, the conditions in the reaction chamber and the conditions of the semiconductor substrate 100, particularly the temperature, are set to be suitable for the growth of the epitaxial layer 122. Depending on the conditions for growing the epitaxial layer 122 and the state of the exposed semiconductor surface, the epitaxial layer 122 may be grown as a single crystal depending on the crystal direction of the exposed semiconductor surface, polycrystalline, amorphous, or these It can be grown to have a combined structure. The epitaxial layer 122 may be formed using a reactive gas such as SiH ₂ Cl ₂ and / or GeH ₂ Cl ₂ , a carrier gas such as hydrogen, and an etching gas such as HCl. Also, the semiconductor substrate 100 may be maintained at a temperature of about 750 ° C. to about 810 ° C., for example, 780 ° C. during the formation of the epitaxial layer 122.

  As shown in FIG. 3C, when the gate pattern 110 includes the capping layer 108, the epitaxial layer 122 is selectively formed on the exposed surface of the semiconductor substrate 100, that is, on the active region exposed by the gate pattern 116. It is formed. In contrast, when the gate pattern 110 does not include the capping layer 108 as shown in FIG. 3D, that is, when the surface of the gate electrode 106 is exposed, the gate pattern 106 is exposed on the exposed surface. An additional epitaxial layer 122 ′ can be formed simultaneously with the epitaxial layer 122. Since the additional epitaxial layer 122 ′ is formed on the gate electrode 106 having a polycrystalline structure, the additional epitaxial layer 122 ′ is not grown as a single crystal structure, but is grown so as to have a polycrystalline or amorphous structure depending on the growth conditions.

Depending on the underlying semiconductor substrate material, the epitaxial layer formed on the exposed semiconductor surface can have various components. For example, the epitaxial layer can be substantially pure silicon, germanium, silicon / germanium (Si _X Ge _1-X ), and / or silicon carbide (Si _X C _1-X ). The epitaxial layer may be a binary, ternary, or quaternary compound semiconductor. As described above, the epitaxial layer formed through the above-described process is injected with a suitable source gas into the reaction chamber during the formation, such as boron, phosphorous, or antimony. It is possible to dope into various impurity ions. In contrast, the epitaxial layer can be selectively doped by a subsequent diffusion or ion implantation process.

  After the epitaxial layer 122 is formed, a second purge process can be performed. (S19 in FIG. 1) In the second purge step, hydrogen, an inert gas, or a mixed gas thereof is injected into the reaction chamber to remove the source gas and etching gas remaining in the reaction chamber. This is done to prevent unwanted reactions during cooling.

<Comparative example>
Transistor samples were manufactured on silicon substrates prepared by substantially the same process by different epitaxial processes as shown in Table 1 below.

  After performing different epitaxial processes as shown in Table 1, a residual element manufacturing process was performed to manufacture a transistor for testing. FIG. 4 shows the test results of the transistor, in particular, the relationship between the channel length (L) and the threshold voltage (Vth). As shown in FIG. 4, the first sample transistor fabricated according to one embodiment of the present invention exhibits a high threshold voltage and a narrow channel length distribution. On the other hand, the transistors of the second sample and the third sample exhibit a low threshold voltage and a wide channel length distribution. As a result, the threshold voltage is reduced due to non-ideal diffusion of impurities during the in-situ cleaning of the first sample transistor formed in accordance with one embodiment of the present invention at a relatively low temperature. This is because it can be prevented.

  5A and 5B are a scanning electron microscope (SEM) image and a transmission electron microscope (TEM) image showing a silicon epitaxial layer selectively formed on the NMOS source / drain region, respectively, according to an embodiment of the present invention. It is. FIG. 5B shows a cut surface cut along the direction crossing the gate electrode 57 on the silicon epitaxial layer 55 of FIG. 5A. 6A and 6B are a scanning electron microscope (SEM) image and a transmission electron microscope (TEM) showing a silicon epitaxial layer selectively formed on a PMOS source / drain region according to an embodiment of the present invention, respectively. It is an image. FIG. 6A shows a cut surface cut along the direction crossing the gate electrode 67 on the silicon epitaxial layer 65 of FIG. 6B.

  As shown in FIG. 5A, the silicon epitaxial layer 55 formed on the NMOS source / drain region showed a flat surface morphology. Generally, when a contaminant such as a natural oxide film is not removed on the surface of a semiconductor substrate, the contaminant such as the natural oxide film affects the surface morphology of the epitaxial layer. That is, the presence of contaminants on the surface of the semiconductor substrate deteriorates the surface morphology of the epitaxial layer. The result of FIG. 5A shows that contaminants such as a natural oxide film on the source / drain regions can be effectively removed even when in-situ cleaning is performed at a low temperature as in the present invention. The result of FIG. 5B further confirms that the contaminants on the source / drain regions, that is, on the single crystal silicon substrate 51 are effectively removed. That is, as shown in FIG. 5B, the single crystal silicon substrate 51 and the silicon epitaxial layer 55 exhibit an interface state that is so good that they cannot be easily separated from each other. This is determined as the contaminants on the source / drain regions have been completely removed during the in situ cleaning.

  As shown in FIGS. 6A and 6B, the silicon epitaxial layer 65 formed on the PMOS source / drain region also has a flat surface morphology as described above, and the single crystal silicon substrate 61 and the silicon epitaxial layer 55 have the same surface morphology. Showed a good interface state.

3 is a process flowchart for explaining a method of forming an epitaxial layer according to an embodiment of the present invention. 1 is a schematic diagram of a reaction chamber that can be used in a method for forming an epitaxial layer according to an embodiment of the present invention. It is sectional drawing which shows the manufacturing process of the semiconductor element by one Example of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor element by one Example of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor element by one Example of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor element by one Example of this invention. 6 is a graph showing a relationship between a channel length and a threshold voltage of a transistor according to a comparative example with a transistor formed according to an embodiment of the present invention. 4 is a scanning electron microscope (SEM) image showing a silicon epitaxial layer selectively formed on NMOS source / drain regions according to an embodiment of the present invention. 2 is a transmission electron microscope (TEM) image showing a silicon epitaxial layer selectively formed on an NMOS source / drain region according to an embodiment of the present invention. 4 is a scanning electron microscope (SEM) image showing a silicon epitaxial layer selectively formed on a PMOS source / drain region according to an embodiment of the present invention. 3 is a transmission electron microscope (TEM) image showing a silicon epitaxial layer selectively formed on a PMOS source / drain region according to an embodiment of the present invention.

Explanation of symbols

11: Processing apparatus 13: Reaction chamber 15: Chuck assembly 17: High vacuum pump 19: Rough pump 21, 23: Valve 100: Semiconductor substrate 102: Element isolation film 104: Gate oxide film 106: Gate electrode 108: Capping layer 110: Gate pattern 112: Internal oxide film spacer 116: Gate spacer 118: Low-concentration impurity region 120: Source / drain region 122: Epitaxial layer

Claims (32)

Loading a substrate having an exposed semiconductor surface into a reaction chamber;
Evacuating the process chamber with a cleaning pressure and heating the substrate at a cleaning temperature so that a cleaning condition in which the oxide existing on the exposed semiconductor surface is decomposed and oxygen is removed is established;
Maintaining the cleaning conditions during a cleaning time so that the oxide is removed to form a clean semiconductor surface;
Forming an epitaxial layer on the clean semiconductor surface;
Unloading the substrate from the reaction chamber;
The manufacturing method of the epitaxial layer characterized by including.   The method for producing an epitaxial layer according to claim 1, wherein the cleaning pressure is about 1 mTorr or less, and the cleaning temperature is about 800 ° C or less.   The method of claim 1, further comprising pre-cleaning the exposed semiconductor surface before loading the substrate into the reaction chamber.   The method of claim 1, wherein the cleaning pressure is about 1 mTorr or less, the cleaning temperature is about 500 ° C to about 750 ° C, and the cleaning time is about 200 seconds or less.   The epitaxial layer of claim 1, wherein the cleaning pressure is about 0.1 mTorr or less, the cleaning temperature is about 730 ° C to about 790 ° C, and the cleaning time is about 120 seconds or less. Method.   The method of claim 1, further comprising injecting a carrier gas into the reaction chamber during the cleaning time.   The method for manufacturing an epitaxial layer according to claim 6, wherein the carrier gas is selected from the group consisting of hydrogen, argon, neon, krypton, and a mixed gas thereof.   8. The method of manufacturing an epitaxial layer according to claim 7, wherein the cleaning pressure is about 50 mTorr or less, the cleaning temperature is about 800 ° C. or less, and the cleaning time is about 200 seconds or less.   7. The method for producing an epitaxial layer according to claim 6, wherein the carrier gas is injected at a flow rate capable of maintaining oxygen gas in the reaction chamber at about 50% or less of a saturation amount as the cleaning condition.   10. The method of manufacturing a semiconductor device according to claim 9, wherein the carrier gas is injected at a flow rate of about 500 sccm or less.   7. The method for producing an epitaxial layer according to claim 6, wherein the carrier gas is injected at a flow rate capable of maintaining oxygen gas in the reaction chamber at about 10% or less of a saturation amount as the cleaning condition.   2. The method for producing an epitaxial layer according to claim 1, wherein the exposed semiconductor surface is selected from the group consisting of silicon, germanium, binary compound semiconductor, ternary compound semiconductor, quaternary compound semiconductor, and combinations thereof.   The method further includes maintaining the substrate as a cooling condition between the step of forming the epitaxial layer and the step of unloading the substrate from a reaction chamber, wherein the cooling condition is a condition that suppresses oxidation of the epitaxial layer. The method for producing an epitaxial layer according to claim 1.   The method of claim 13, further comprising injecting a cooling gas into the reaction chamber between forming the epitaxial layer and unloading the substrate from the reaction chamber. Production method.   15. The method for producing an epitaxial layer according to claim 14, wherein the cooling gas is selected from the group consisting of hydrogen, argon, neon, krypton, and a mixed gas thereof.   After loading the substrate into the reaction chamber and before reaching the cleaning conditions, the substrate further includes a step of maintaining the substrate in a temperature rising atmosphere, the temperature rising atmosphere comprising oxidizing the exposed semiconductor surface. The method for producing an epitaxial layer according to claim 1, wherein the atmosphere is suppressed.   The epitaxial layer manufacturing method according to claim 16, further comprising injecting a temperature rising gas into the reaction chamber after the substrate is loaded into the reaction chamber until the cleaning condition is reached. Method.   18. The method of manufacturing an epitaxial layer according to claim 17, wherein the temperature rise is selected from the group consisting of hydrogen, argon, neon, krypton, and a mixed gas thereof. Processing the semiconductor substrate to form an intermediate device structure having an exposed semiconductor surface;
Loading the intermediate element structure into a reaction chamber;
Evacuating the process chamber with a cleaning pressure and heating the substrate at a cleaning temperature so that a cleaning condition is established in which the oxide present on the exposed semiconductor surface is decomposed to remove oxygen; and
Maintaining the cleaning conditions during a cleaning time so that the oxide is removed to form a clean semiconductor surface;
Forming an epitaxial layer on the clean semiconductor surface;
Unloading the semiconductor substrate from the reaction chamber;
The manufacturing method of the semiconductor element characterized by the above-mentioned.   The method of claim 19, wherein the exposed semiconductor surface is a source / drain region.   20. The method of claim 19, wherein the exposed semiconductor surface is a source / drain region and a gate electrode surface.   The semiconductor device according to claim 19, wherein the epitaxial layer has one epitaxial layer structure selected from the group consisting of a single crystal semiconductor structure, a polycrystalline semiconductor structure, an amorphous semiconductor structure, and a combination thereof. Production method.   23. The method of manufacturing a semiconductor device according to claim 22, wherein one type of epitaxial layer structure is formed on the exposed semiconductor surface. Forming an intermediate device structure having an exposed semiconductor surface by treating the semiconductor substrate;
Defining an active region on the semiconductor substrate;
Forming a gate pattern on a first portion of the surface of the active region;
Exposing a second portion of the surface of the active region;
The method of manufacturing a semiconductor device according to claim 22, comprising: Forming an intermediate device structure having an exposed semiconductor surface by treating the semiconductor substrate;
Defining an active region on the semiconductor substrate;
Forming a gate pattern on a first portion of the surface of the active region;
Exposing a surface of the active region and a second portion of a semiconductor surface on the gate pattern;
The method of manufacturing a semiconductor device according to claim 22, comprising: Loading a substrate having an exposed semiconductor surface in a reaction chamber;
The process chamber is evacuated with a cleaning pressure so that a cleaning condition in which the oxide existing on the exposed semiconductor surface is decomposed and removed or converted into silicon by a reduction reaction is established, and the substrate is exhausted. Heating at a washing temperature;
Maintaining the cleaning conditions during a cleaning time so that the oxide is removed to form a clean semiconductor surface;
Forming an epitaxial layer on the clean semiconductor surface;
Unloading the substrate from the reaction chamber;
The manufacturing method of the epitaxial layer characterized by including. Loading a substrate having an exposed semiconductor surface in a reaction chamber;
The process chamber is evacuated at a first cleaning pressure and the substrate is heated at a first cleaning temperature so as to satisfy a first cleaning condition in which oxides present on the exposed semiconductor surface are decomposed and removed. And the stage of
The process chamber is evacuated at a second cleaning pressure so as to satisfy a second cleaning condition in which the oxide remaining on the exposed semiconductor surface is converted to silicon by a reduction reaction, and the substrate is discharged at a second cleaning temperature. Heating with
Maintaining the second cleaning conditions during a second cleaning time to convert the remaining oxide to form a clean semiconductor surface;
Forming an epitaxial layer on the clean semiconductor surface;
Unloading the substrate from the reaction chamber;
The manufacturing method of the epitaxial layer characterized by including.   And evacuating the reaction chamber with a cleaning pressure and heating the substrate at a cleaning temperature so as to satisfy a cleaning condition in which an oxide existing on an exposed semiconductor surface is decomposed and removed. A method for cleaning an exposed semiconductor surface.   29. The method of cleaning an exposed semiconductor surface according to claim 28, wherein removing the oxide further comprises removing oxide on the exposed semiconductor surface by a reduction reaction.   29. Cleaning the exposed semiconductor surface of claim 28, further comprising maintaining the reaction chamber at a cleaning pressure at which the oxygen gas partial pressure is about 50% or less of the equilibrium partial pressure at the cleaning temperature. Method.   29. The method of cleaning an exposed semiconductor surface according to claim 28, wherein the cleaning temperature is about 800 [deg.] C. or less.   The cleaning of the exposed semiconductor surface of claim 31, further comprising maintaining the reaction chamber at a cleaning pressure at which the partial pressure of oxygen gas is about 50% or less of the equilibrium partial pressure at the cleaning temperature. Method.