JP2006196181A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device suitable for high integration by reducing the circuit scale of a column system circuit by decreasing especially the number of sense amplifier circuits, data latch circuits, and verify-circuits. <P>SOLUTION: This device is provided with a memory cell array in which memory cells storing electrically rewritable (n) values (n is a natural number of 3 or more) are arranged in matrix, (m) pieces of data circuits holding data to be written in the memory cell, a write verify-means confirming whether a state after the write operation of the memory cell is a desired data storage state or not, and a data circuit contents batch updating means constituted of a data updating circuit (Qn5) updating contents of the data circuit so that re-writing is performed for only memory cells of insufficient writing based on contents of the data circuit and the state after the write operation of the memory cell, and the data updating circuit refers to contents of one data circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to a multi-value storage EEPROM that stores more than one bit of information in one memory cell.

  As one of the techniques for realizing the large capacity of the EEPROM, a multi-value storage EEPROM is known in which n (n ≧ 3) value information is stored in one memory cell. For example, in the quaternary storage type, each cell has one of four types of threshold voltages, which is (0, 0), (0, 1), (1, 0), (1, 1 ) And 2 bits of information.

  In order to read the data of the memory cell storing the n value, the data read from the cell is compared with (n−1) reference voltages. For this reason, conventionally, (n-1) sense amplifiers are required (for example, Japanese Patent Application Laid-Open No. 61-117796).

  In the four-value storage type EEPROM, the memory density of the memory cell is doubled and the area occupied by the memory cell is halved as compared to the EEPROM of the binary value storage type cell. Tripled, reducing the effect of densification. In particular, in an EEPROM of a type in which a sense amplifier is provided for each bit line for page reading, an increase in the number of sense amplifiers hinders an increase in capacity.

  On the other hand, Patent Document 2 discloses a read-only memory characterized in that the number of sense amplifiers is reduced by controlling the reference voltage of other sense amplifiers by the output of the sense amplifiers that have determined cell data. It is disclosed.

  On the other hand, in a multi-value storage EEPROM that stores n (n ≧ 3) types of threshold voltages in memory cells, it is necessary to distribute each threshold voltage in a narrower range when writing stored data. . Therefore, writing is performed in small increments, and it is checked whether or not each memory cell has been written within the target threshold range between writing, and if there is a cell with insufficient writing, only that cell is checked. Bit-by-bit verification is performed, in which additional writing is performed and control is performed so that optimum writing is performed for each memory cell. The bit-by-bit verification is disclosed in Patent Document 3.

  Further, bit-by-bit verification for a multi-level storage EEPROM is disclosed in Patent Document 4. However, the device disclosed in Patent Document 4 requires (n−1) sense amplifiers and verify circuits, respectively. Therefore, although a memory cell can store a large amount of data in a chip having the same area by storing a larger amount of data, a circuit for controlling data read / write becomes large-scale, There was a difficulty in high integration.

  Patent Document 5 discloses a nonvolatile semiconductor memory device that holds write data for memory cells that store ternary data in two flip-flops FF1 and FF2.

Further, at the time of verify read after writing, each detection voltage for detecting whether or not “2” state is reached or whether or not “1” or “2” is reached is applied to the gate electrode of the memory cell. Such a nonvolatile semiconductor memory device is described in Patent Document 4.
JP-A-61-117796 JP-A-62-54896 Japanese Patent Laid-Open No. 3-295098 JP-A-7-93979 JP-A-7-161852

  As described above, conventionally, a multi-value storage EEPROM having a verify function has required (n−1) verify circuits when the number of multi-value data is “n ≧ 3”. For this reason, (n−1) sense amplifiers and data latch circuits are required in accordance with the verify circuit.

  Due to the above circumstances, the circuit scale connected to the bit line, that is, the circuit scale of the column circuit, in particular, the number of sense amplifier circuits, data latch circuits, and verify circuits becomes enormous, which becomes a bottleneck for high integration. It has become.

  The present invention provides a nonvolatile semiconductor memory device suitable for high integration by reducing the circuit scale of a column circuit by reducing the number of sense amplifier circuits, data latch circuits, and verify circuits.

  The nonvolatile semiconductor memory device according to the first aspect of the present invention includes a memory cell array in which memory cells storing n values (n is a natural number of 3 or more) that can be electrically rewritten are arranged in a matrix, and the memory Threshold detecting means for charging the bit line connected to the cell through the memory cell and outputting the multi-value data of the memory cell as a multi-level potential to the bit line; and the threshold detecting means A sense amplifier that senses the charged multi-level bit line potential, first, second,..., M-th data circuits that hold data to be written to the memory cell, and a state after the write operation of the memory cell. Write verify means using the threshold value detection means for confirming whether or not a desired data storage state has been established, and the contents of the data circuit and the writing of the memory cell Data circuit content batch update means comprising a data update circuit for batch updating the contents of the data circuit so as to perform rewrite only to memory cells that are insufficiently written from the state after operation, the data update circuit comprising: The contents of one data circuit are referred to.

  A nonvolatile semiconductor memory device according to a second aspect of the present invention includes a memory cell array in which memory cells storing n values (n is a natural number of 3 or more) that can be electrically rewritten are arranged in a matrix, and the memory Threshold detecting means for charging the bit line connected to the cell through the memory cell and outputting the multi-value data of the memory cell as a multi-level potential to the bit line; and the threshold detecting means A sense amplifier that senses the bit line potential by comparing the charged multi-level bit line potential with a reference voltage, and first, second,..., M-th data circuits that hold data to be written to the memory cells. A write verifying means using the threshold value detecting means for confirming whether the state after the write operation of the memory cell is a desired data storage state; Data circuit content batch update means comprising a data update circuit for batch updating the data circuit contents so that rewriting is performed only on memory cells that are insufficiently written from the contents of the data circuit and the state after the memory cell write operation. And the data update circuit refers to the contents of one data circuit, and the data circuit contents batch update means is configured to sense and store the bit line potential as rewrite data after the write operation of the memory cell. The bit line from which the state is output and the reference potential are corrected according to the contents of the data circuit, and the data storage state of the data circuit is held until the bit line potential is corrected, and the corrected bit line potential is held. Keep the data circuit operating as a sense amplifier, update the contents of the data circuit at once, and write operations based on the contents of the data circuit Data circuit contents bulk update, electrically writing data by performing repeatedly until the memory cell reaches a predetermined write state.

A nonvolatile semiconductor memory device according to a third aspect of the present invention includes a memory cell array in which memory cells that store electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and the memory cells The first, second,..., ^M- th data circuit (m is a natural number satisfying 2 ^(m−1) <n ≦ 2 ^{m )} holding the data to be written, and the state of the memory cell after the write operation is desired Write verify means for confirming whether or not the data is in a storage state, and so that rewriting is performed only on memory cells that are insufficiently written from the contents of the data circuit and the state after the writing operation of the memory cells, And a data circuit content batch update means comprising a data update circuit for updating the content of the data circuit, wherein the data update circuit refers to the content of one data circuit.

  A nonvolatile semiconductor memory device according to a fourth aspect of the present invention includes a memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix, and the memory cells. M data circuits for holding data to be written; write verify means for confirming whether or not the state after the write operation of the memory cell is a storage state of desired data; the contents of the data circuit and the memory cell Data circuit contents batch update means comprising a data update circuit for updating the contents of the data circuit so as to perform rewriting only to memory cells that are insufficiently written from the state after the writing operation of the data updating circuit, Refers to the contents of one data circuit.

  According to the present invention, a non-volatile semiconductor memory device suitable for high integration can be provided by reducing the circuit scale of the column circuit by reducing the number of sense amplifier circuits, data latch circuits, and verify circuits. .

Embodiments of the present invention will be described below with reference to the drawings.

<Embodiment 1>
FIG. 1 is a configuration diagram showing the configuration of a multi-value storage NAND type EEPROM according to the first embodiment of the present invention.

As shown in FIG. 1, the multi-value storage NAND type EEPROM according to the first embodiment has a configuration called an open bit type. The open-bit type multi-value storage NAND type EEPROM includes a row system circuit 2A, 2B provided for each of the memory cell arrays 1A, 1B configured by arranging memory cells in a matrix, and each of the memory cell arrays 1A, 1B. And a column circuit 3 ^** used in common.

  The row-related circuits 2A and 2B receive the address signal output from the address input circuit (address buffer) 4 and, based on the received address signal, select a row decoder in the memory cell array and output the row decoder. Based on this, a word line driving circuit for driving the word lines of the memory cell array is included. In the case of a NAND type EEPROM, the word line indicates a selection gate SG (SGA, SGB) and a control gate CG (CGA, CGB). The word line driving circuit is read as a control gate / selection gate driving circuit.

A column circuit 3 ^** commonly used in each of the memory cell arrays 1A and 1B receives an address signal output from the address buffer 4 and selects a column of the memory cell array based on the received address signal. A column decoder and a column selection line driving circuit for driving a column selection line for selecting a column of the memory cell array based on the output of the column decoder are included.

Further, the column circuit 3 ^** includes a data circuit (bit line control circuit) for temporarily holding data to be written to the memory cell and reading data from the memory cell.

  The bit line control circuit is connected to a data input / output circuit (data input / output buffer) 5 through a data input / output line IO. The bit line control circuit is connected to the memory cell of the memory cell array 1A via the bit line BLa and to the memory cell of the memory cell array 1B via the bit line BLb.

  When writing data, the bit line control circuit receives write data from the data input / output buffer 5 and inputs the received write data to the memory cell. Further, when reading data, the bit line control circuit receives the read data from the memory cell and outputs the received read data to the data input / output buffer 5.

  The data input / output buffer 5 performs data input / output control. The data input / output buffer 5 guides write data input from the outside of the EEPROM to the memory core, and outputs read data read from the memory core to the outside of the EEPROM. To do.

  The write end detection circuit 18 detects whether or not the data write has ended based on the output of the bit line control circuit.

  FIG. 2 is a configuration diagram showing the configuration of the memory cell array and column system circuit shown in FIG. FIGS. 3A and 3B are diagrams showing when data is read from the memory cell shown in FIG. 2, FIG. 3A is a diagram showing a voltage input state, and FIG. 3B is a voltage input waveform and an output waveform appearing on a bit line. FIG.

  As shown in FIG. 2, memory cells MC are arranged in a matrix in each of the memory cell arrays 1A and 1B.

The column circuit 3 ^** includes m data circuits (bit line control circuits) 6 ^** . The bit line control circuit 6 ^** is connected to one bit line BLa and one bit line BLb.

  Further, as shown in FIG. 3A, in the NAND type EEPROM, one cell MC includes a plurality of memory cell transistors M1 to M4 connected in series with each other, and constitutes a NAND type cell MC. ing. One end of the cell MC is connected to the bit line BL via the selection transistor S1, and the other end is connected to the source line Vs via the selection transistor S2. A group of memory cell transistors M sharing the control gate CG forms a unit called “page”. Data writing and reading are performed simultaneously on the “page”. A group of memory cell transistors M connected to the four control gates CG1 to CG4 forms a unit called “block”. Each of “page” and “block” is selected by a control gate / select gate driving circuit.

  The memory cell transistor M stores multi-value data according to a threshold level. In the apparatus according to the present invention, the threshold level is read as shown in FIGS. 3 (a) and 3 (b). Here, the memory cell transistor M2 having the control gate CG2 is selected. As seen in FIG. 3A, a voltage is applied to each part, and the bit line BL is made floating. If the bit line BL is reset to 0V in advance, the bit line BL is charged through the NAND cell by the common source line Vs. The selection gate and control gate voltages are controlled so that the potential of the charged bit line BL is determined by the threshold value of the selected memory cell M2.

  In this example, the selection gates SG1 and 2, the control gates CG1 and CG3 to CG4 are set to 6V, the selected control gate CG2 is set to 2V, and the common source line Vs is set to 6V. The voltage waveform of each part is shown in FIG. For example, when the potential of the bit line BL is 0V, the threshold is 2V or more, and when the bit line potential is 3.5V, the threshold is −1.5V or less. However, in the following embodiment, in order to simplify the description, the expression “threshold value” is considered in consideration of the back bias.

  After electrons are emitted from the floating gate of the memory cell by the erase operation, electrons are injected into the floating gate by the write operation according to the write data.

  FIG. 4 is a diagram showing the relationship between the output voltage appearing on the bit line and the number of memory cells.

  When one memory cell has three states (data “0”, “1”, “2”), for example, the bit line output voltage at the time of reading is 3.5 to 4.5 V as shown in FIG. The state (about −2.5 V to −1.5 V at the threshold) is the data “0” (erased state), and the bit line output voltage is 1.5 to 2.5 V (the threshold is about − 0.5V to 0.5V) may be data “1”, and the bit line output voltage may be 0 to 0.5V (threshold value of about 1.5V to 2.5V) may be data “2”. .

  FIG. 5 is a circuit diagram of the data circuit shown in FIG. The data circuit shown in FIG. 5 is configured with ternary storage as an example.

  As shown in FIG. 5, flip-flop FF1 composed of n-channel MOS transistors Qn21, Qn22, Qn23 and p-channel MOS transistors Qp9, Qp10, Qp11, n-channel MOS transistors Qn29, Qn30, Qn31 and p-channel MOS transistor Qp16 , Qp17, Qp18, and write / read data are latched in FF2. These also operate as sense amplifiers.

  The flip-flop FF1 latches “0”, “1” or “2” write ”as write data information, and whether the memory cell holds“ 0 ”information, Alternatively, whether “1” information is held or “2” information is held ”is sensed and latched as read data information. The flip-flop FF2 latches “whether“ 1 ”or“ 2 ”is written” ”as write data information, and the memory cell holds“ 1 ”information or“ 2 ”. “Do you hold information?” Is sensed and latched as read data information.

  Data input / output lines IOA, IOB and flip-flop FF1 are connected via n-channel MOS transistors Qn28, Qn27. Data input / output lines IOC, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, IOD are also connected to data input / output buffer 5 in FIG.

  The gates of n-channel MOS transistors Qn27, Qn28, Qn35, Qn36 are connected to the output of a column address decoder composed of NAND logic circuit G2 and inverter I4. The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being “H”, respectively. N-channel MOS transistors Qn24 and Qn32 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd1. N-channel MOS transistors Qn25 and Qn33 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd2.

  The circuit constituted by the p-channel MOS transistors Qp12 and Qp13 changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1 by the activation signal VRFYBA. The circuit constituted by the p-channel MOS transistors Qp14 and Qp15 changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF1 by the activation signal VRFYBB. A circuit composed of n-channel MOS transistors Qn1 and Qn2 changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1. A circuit composed of n-channel MOS transistors Qn3 and Qn4 changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1.

  MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors, and are sufficiently smaller than the bit line capacitance. N channel MOS transistor Qn37 charges MOS capacitor Qd1 to voltage VA by signal PREA. N channel MOS transistor Qn38 charges MOS capacitor Qd2 to voltage VB by signal PREB. N-channel MOS transistors Qn39 and Qn40 control connection between the data circuit 3 and the bit lines BLa and BLb, respectively, by signals BLCA and BLCB. A circuit composed of n-channel MOS transistors Qn37 and Qn38 also serves as a bit line voltage control circuit. A circuit composed of p-channel MOS transistors Qp12 and Qp13, a circuit composed of p-channel MOS transistors Qp14 and Qp15, a circuit composed of n-channel MOS transistors Qn1 and Qn2, and composed of n-channel MOS transistors Qn3 and Qn4 This circuit is also a bit line voltage control circuit.

  Next, the operation of the thus configured EEPROM will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected is shown.

<Read operation>
FIG. 6 is an operation waveform diagram showing a read operation.

  As shown in FIG. 6, first, at time t1R, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is 2V, the non-selection control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A. Is set to 6V. The source potential of the memory cell is set to 6V. When the memory cell is “0”, the bit line BLa is 3.5 V or more. When “1”, the bit line BLa is 1.5 V or more and 2.5 V or less. 5V or less. The dummy bit line BLb is charged from VB to 3V. When the voltage drop corresponding to the threshold value of n channel MOS transistor Qn40 becomes a problem, signal BLCA may be boosted.

  At time t2R, the nodes N1 and N2 of the capacitors Qd1 and Qd2 are set to 1.5 V and then floated. At time t3R, BLCA and BLCB become VCC (for example, 5 V), and the potentials of the bit lines BLa and BLb are transferred to N1 and N2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. When the voltage drop corresponding to the threshold value of the n-channel MOS transistors Qn24 and Qn25 becomes a problem, the signals RV1A and RV1B may be boosted. At time t4R, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltages at the nodes N1 and N2 are sensed and latched. Thus, “whether the data in the memory cell is“ 0 ”,“ 1 ”or“ 2 ”” is sensed by the flip-flop FF1, and the information is latched.

  Next, it is sensed whether the memory cell is “1” or “2”.

  At time t5R, the dummy bit line BLb is charged from VB to 1V. At time t6R, the nodes N1 and N2 of the capacitors Qd1 and Qd2 are set to 1.5 V and then floated. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. At time t7R, the signals SAN2 and SAP2 again become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, whether the data in the memory cell is “1” or “2” is sensed by the flip-flop FF2, and the information is latched.

  FIG. 7 is a diagram showing read data sensed and latched by the flip-flops FF1 and FF2.

  The data in the flip-flops FF1 and FF2 at this time are as shown in FIG. 7, and read data is output to the data input / output lines IOA, IOB, IOC, and IOD.

  Output data to the outside of the chip may be converted by the input / output buffer 5 based on signals output to the data input lines IOA, IOB, IOC, and IOD.

<Write operation>
Prior to the write operation, the input 2-bit data is converted by the data input / output buffer 4 and input to the data circuit 6 ^** .

FIG. 8 is a diagram showing write data input to the data circuit 6 ^** and latched by the flip-flops FF1 and FF2. The relationship between the quaternary data and the data input / output lines IOA, IOB, IOC, and IOD is as shown in FIG.

  The converted ternary data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is “H”.

  FIG. 9 is an operation waveform diagram showing a write operation.

  At time t1w, the voltage VA becomes the bit line write control voltage 1V, and the bit line BLa is set to 1V. When a voltage drop corresponding to the threshold value of n channel MOS transistor Qn39 becomes a problem, signal BLCA may be boosted. Subsequently, the signal PRE becomes “L” and the bit line is floated. Next, the signal RV2A is set to 1.5 V at time t2w. As a result, the bit line control voltage 0 V is applied to the bit line in the column holding the data “2”. If the threshold value of the n-channel MOS transistor Qn32 is 1V, the n-channel MOS transistor Qn32 is “OFF” when “0” or “1” is written, and “ON” when “2” is written. Thereafter, VRFYBA becomes 0V at time t3w, and the bit line write control voltage VCC (for example, 5V) is output to the bit line from the data circuit in which the data “0” is held.

  As a result, the bit line for writing “0” becomes VCC, the bit line for writing “1” becomes 1V, and the bit line for writing “2” becomes 0V.

  At time t1w, the selection gate SG1A and the control gates CG1A to CG4A of the selected block become VCC by the control gate / selection gate drive circuit. The selection gate SG2A is 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become the VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “2”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 1 V and the VPP of the control gate, and the threshold value rises. The reason why the channel potential is set to 1 V is that the injection amount of electrons may be smaller than that of “2” data writing. In the memory cell corresponding to the data circuit holding data “0”, the potential difference between the channel potential and the VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During the write operation, the signals SAN1, SAN2, VRFYBB, PREB, and BLCB are “H”, the signals SAP1, SAP2, RV1A, RV1B, RV2B, ECH1, and ECH2 are “L”, and the voltage VB is 0V.

<Verify read operation>
FIG. 10 is an operation waveform diagram showing a verify read operation.

  First, at time t1RV, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 2V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to 6V. The source potential of the memory cell is set to 6V. In the case of writing “0”, the bit line BLa becomes 3.5V or more. When “1” writing is sufficient, the bit line BLa is 2.5 V or less, and when “1” writing is insufficient, it is 1.5 V or more. When “2” writing is sufficient, it is 0.5 V or less, and when “2” writing is insufficient, it is 0.5 V or more. The dummy bit line BLb is charged from VB to 2.5V. The reason why the potential of the dummy bit line BLb is made lower by 0.5 V than 3 V at the time of “1” reading is to sufficiently write the memory cells. If the voltage drop corresponding to the threshold value of n channel MOS transistor Qn40 becomes a problem, signal BLCA may be boosted.

  At time t2RV, the nodes N1 and N2 of the capacitors Qd1 and Qd2 are set to 1.5 V and then floated. At time t3RV, VRFYBB1 becomes “H”. At this time, as can be seen from FIG. 7, the node N6 is “H” only when “2” is written. Therefore, the dummy bit line BLb for writing “2” is changed from Vref to 0.5V. The reason why the potential of the dummy bit line BLb for “2” writing is made lower by 0.5V than 1V at the time of “2” reading is to sufficiently write the memory cells. In the case of writing “0” or “1”, since N6 is “L”, the n-channel MOS transistor Qn4 is turned off and the dummy bit line BLb is maintained at 2.5V.

  At time t4RV, BLCA and BLCB become VCC (for example, 5V), and the potentials of the bit lines BLa and BLb are transferred to N1 and N2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected.

  At time t5RV, RV1A becomes 1.5V. As a result, N1 is grounded in the column to which data “0” is written. If the threshold value of the n-channel MOS transistor Qn24 is 1V, the n-channel MOS transistor Qn24 is “OFF” when “1” or “2” is written, and “ON” when “0” is written.

  The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. When the voltage drop corresponding to the threshold value of the n-channel MOS transistors Qn24 and Qn25 becomes a problem, the signals RV1A and RV1B may be boosted. At time t4R, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltages at the nodes N1 and N2 are sensed and latched.

  As described above, in the data circuit holding “1” write data, it is detected whether or not the data in the corresponding memory cell is sufficiently in the “1” write state. If the data in the memory cell is “1”, the write data is changed to “1” by sensing and latching the voltage at the node N1 by the flip-flop FF1. If the data in the memory cell is not “1”, the write data is held at “1” by sensing and latching the voltage at the node N1 by the flip-flop FF1. In the data circuit holding “2” write data, it is detected whether or not the data in the corresponding memory cell is sufficiently in the “2” write state. If the data in the memory cell is “2”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flop FF1. If the data in the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage at the node N1 by the flip-flop FF1. The write data of the data circuit holding “0” write data is not changed.

  During the write verification, the signal VRFYBB is “H” and the voltage Vs is 0V.

If all the selected memory cells to be written “1” or “2” have reached a desired threshold value, all the nodes N4 of the data circuit become “L”. That "1" write or "2" when all of the memory cell selected for writing is written to enough, all of the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1 , 6 ^**- m, the node N3 becomes “H” and N4 becomes “L”. When this is detected, it can be determined whether or not all selected memory cells to be written “2” or “3” have reached a desired threshold value. For example, “2” and “3” write end collective detection transistors Qn5 may be used to detect the end of “2” write and “3” write as shown in FIG. After verify read, VRT is precharged to VCC, for example. If even one memory cell is insufficiently written “1” or “2”, the node N4 of the data circuit is “H”, so that the n-channel MOS transistor Qn5 is turned on and VRT is grounded. When all "1" or "2" memory cell to write is written to enough, the data circuit 6 ^** -0,6 ^** -1, ..., of 6 ^** -m-1, 6 ^** -m The node N4 becomes “L”. As a result, the n channel MOS transistors Qn5 in all the data circuits are turned off, so that VRT maintains the precharge potential.

  In the multi-value storage NAND type EEPROM according to the first embodiment, when writing data, the bit line is charged to a desired bit line write control voltage by at least one bit line voltage control circuit. With such a device, it is possible to realize a bit line voltage control circuit that has a simple circuit configuration and applies a bit line write control voltage corresponding to n (n ≧ 2) value write data to the bit line. .

  Therefore, the circuit scale of the column system circuit 3 is reduced especially by reducing the number of sense amplifier circuits, data latch circuits, and verify circuits, and a nonvolatile semiconductor memory device suitable for high integration can be obtained.

<Embodiment 2>
Next explained is a multi-value storage NAND type EEPROM according to the second embodiment of the invention.

  In the EEPROM according to the first embodiment, the example in which the number of multi-value data is ternary has been described. However, after the EEPROM according to the second embodiment, the number of multi-value data is quaternary. An example will be described.

  The EEPROM according to the second embodiment has a configuration similar to that shown in FIGS.

  FIG. 11 is a diagram showing the threshold distribution of the memory cell transistor at the time of four-value storage.

  When the EEPROM is of a four-value storage type, one memory cell transistor M is provided with four write states. The four write states are distinguished from each other by the threshold voltage of the memory cell transistor M.

  As shown in FIG. 11, in an EEPROM whose power supply voltage VCC is 3V, the state of data “0” is the same as the state after data erasure, and has a negative threshold value, for example. The data “1” state has a threshold value between 0.5 V and 0.8 V, for example. The data “2” state has a threshold value between 1.5V and 1.8V, for example. For the state of data “3”, for example, a threshold value between 2.5 V and 2.8 V is provided.

  When data is read from the memory cell transistor M, three read voltages VCG2R, VCG3R, and VCG1R are applied to the control gate CG in this order.

  First, the read voltage VCG2R is applied to the control gate CG. Thus, whether the stored data is “0”, “1”, “2”, “3” is detected depending on whether the memory cell transistor M is “ON” or “OFF”. The Subsequently, when the read voltage VCG3R is applied, whether the stored data is “2” or “3” is detected, and when the read voltage VCG1R is further applied, whether the data is “0”. , “1” is detected. One example of the read voltages VCG1R, VCG2R, and VCG3R is 0V, 1V, and 2V, respectively.

  Also, the voltages VCG1V, VCG2V, and VCG3V shown in FIG. 11 are called verify read voltages, and are read voltages used when checking whether data is sufficiently written (verify operation). The verify read voltage is applied to the control gate CG after writing data. When the verify read voltage is applied to the control gate CG, the threshold value of the memory cell transistor M is shifted to a range corresponding to the written data depending on whether the memory cell transistor M is “ON” or “OFF”. You can know if it is. Using this, it is checked whether or not sufficient writing has been performed. One example of the verify read voltages VCG1V, VCG2V, and VCG3V is 0.5V, 1.5V, and 2.5V, respectively.

  FIG. 12 is a circuit diagram of a data circuit included in the EEPROM according to the second embodiment of the present invention. The data circuit shown in FIG. 12 is configured with quaternary storage as an example.

  As shown in FIG. 12, flip-flop FF1 composed of n-channel MOS transistors Qn21, Qn22, Qn23 and p-channel MOS transistors Qp9, Qp10, Qp11, n-channel MOS transistors Qn29, Qn30, Qn31 and p-channel MOS transistor Qp16 , Qp17, Qp18, and write / read data are latched in FF2. These also operate as sense amplifiers.

  The flip-flops FF1 and FF2 latch “write as“ 0 ”,“ 1 ”,“ 2 ”write, or“ 3 ”write” as write data information, and the memory cell. Reads “data holding“ 0 ”,“ 1 ”holding,“ 2 ”holding,“ 3 ”holding”, etc. Sense and latch.

  Data input / output lines IOA, IOB and flip-flop FF1 are connected via n-channel MOS transistors Qn28, Qn27. Data input / output lines IOC, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, and IOD are also connected to data input / output buffer 5 shown in FIG.

  The gates of n-channel MOS transistors Qn27, Qn28, Qn35, Qn36 are connected to the output of a column address decoder composed of NAND logic circuit G2 and inverter I4. The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being “H”, respectively. N-channel MOS transistors Qn24 and Qn32 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd1. N-channel MOS transistors Qn25 and Qn33 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd2.

  The circuit constituted by the p-channel MOS transistors Qp12 and Qp13 changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1 by the activation signal VRFYBA. The circuit constituted by the p-channel MOS transistors Qp14 and Qp15 changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF1 by the activation signal VRFYBB. A circuit composed of n-channel MOS transistors Qn1 and Qn2 changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1. A circuit composed of n-channel MOS transistors Qn3 and Qn4 changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1.

  MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors, and are sufficiently smaller than the bit line capacitance. N channel MOS transistor Qn37 charges MOS capacitor Qd1 to voltage VA by signal PREA. N channel MOS transistor Qn38 charges MOS capacitor Qd2 to voltage VB by signal PREB. N-channel MOS transistors Qn39 and Qn40 control connection between the data circuit 3 and the bit lines BLa and BLb, respectively, by signals BLCA and BLCB. A circuit composed of n-channel MOS transistors Qn37 and Qn38 also serves as a bit line voltage control circuit. A circuit composed of p-channel MOS transistors Qp12 and Qp13, a circuit composed of p-channel MOS transistors Qp14 and Qp15, a circuit composed of n-channel MOS transistors Qn1 and Qn2, and composed of n-channel MOS transistors Qn3 and Qn4 This circuit is also a bit line voltage control circuit. Further, the circuit constituted by the flip-flop FF2 and the n-channel MOS transistors Qn32 and Qn33 also serves as a bit line voltage control circuit.

  Next, the operation of the thus configured EEPROM will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected is shown.

<Read operation>
FIG. 13 is an operation waveform diagram showing a read operation.

  As shown in FIG. 13, first, at time t1R, the voltages VA and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become “L”, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. Subsequently, at time t2R, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 1V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. If the threshold value of the selected memory cell is 1V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 1V or more, the bit line voltage remains 1.8V. Thereafter, at time t3R, the signals BLCA and BLCB become “H”, and the bit line data is transferred to the MOS capacitors Qd1 and Qd2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, the selected control gate is set to 2V. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. At time t4R, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltages at the nodes N1 and N2 are sensed and latched. Thus, “whether the data of the memory cell is“ 0 ”or“ 1 ”,“ 2 ”or“ 3 ”” is sensed by the flip-flop FF1, and the information is latched.

  Next, at time t5R, the signals PREA and PREB become “H”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 become 1.8V and 1.5V, respectively. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. If the threshold value of the selected memory cell is 2V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 2V or more, the bit line voltage remains 1.8V. Thereafter, the signals BLCA and BLCB are set to “H” at time t6R. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. At time t7R, the signals SAN2 and SAP2 again become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, whether or not the data in the memory cell is “3” is sensed by the flip-flop FF2, and the information is latched.

  FIG. 14 is a diagram illustrating read data sensed and latched by the flip-flops FF1 and FF2 at time t7R.

  Finally, it is sensed whether the data written in the memory cell is “0” or not. First, at time t8R, the bit lines BLa and BLb are charged to 1.8 V and 1.5 V, respectively, and then float. Further, the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are also in a floating state. Subsequently, at time t9R, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 0V, and the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. If the threshold value of the selected memory cell is 0V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0V or higher, the bit line voltage remains 1.8V. Thereafter, at time t10R, the signals BLCA and BLCB become “H”, and the bit line data is transferred to the MOS capacitors Qd1 and Qd2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Prior to sensing the data of the MOS capacitor, VRFYBA1 becomes VCC at time t11R. As can be seen from FIG. 14, the node N5 is “high level” only in the case of “3” data. Therefore, only in the case of “3” data, the n-channel MOS transistor Qn2 is turned on and the node N1 is grounded. Then, the signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. At time t12R, the signals SAN2 and SAP2 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, “whether the data in the memory cell is“ 0 ”or not” is sensed by the flip-flop FF2, and the information is latched.

  FIG. 15 is a diagram showing read data sensed and latched by the flip-flops FF1 and FF2.

  As a result of the above read operation, quaternary data is latched in the flip-flops FF1 and FF2 as shown in FIG.

  The threshold distribution of each data in the figure is as follows.

Data “0”: Threshold value: 0 V or less Data “1”: Threshold value 0.5 V or more and 0.8 V or less Data “2”: Threshold value 1.5 V or more and 1.8 V or less Data “3”... Threshold value 2.5 V or more and 2.8 V or less During reading, the signals VRFYBA and VRFYBB are “H”. The voltage Vs (Vsa, Vsb) is 0V.

  When the column activation signal CENB input to the column address decoder becomes “H”, the data held in the data circuit selected by the address signal is output to the data input / output lines IOA, IOB, IOC, IOD, and the data The data is output outside the EEPROM via the input / output buffer 5.

  The relationship among the data stored in the memory cell, the threshold value, and the level output after reading to the data input / output lines IOA, IOB, IOC, and IOD is as shown in FIG.

  Output data to the outside of the chip may be converted based on signals output to the data input lines IOA, IOB, IOC, and IOD by the data input / output buffer 5.

<Write operation>
FIG. 16 is a schematic diagram showing an outline of the write operation.

  As shown in FIG. 16, first, write data is loaded into the flip-flops FF1 and FF2. Thereafter, “2” data and “3” data are written almost simultaneously in the first program cycle. Then, a first verify read cycle is performed to check whether “2” data and “3” data are sufficiently written. If there is a memory cell that is insufficiently written, rewriting is performed. When all of the memory cells to be written “2” and “3” are sufficiently written, the memory cell to be written “1” next is written almost simultaneously (program second cycle). Then, a second verify read cycle for checking whether the “1” write has been sufficiently performed is performed. Rewriting is performed on a memory cell in which “1” is insufficiently written, and writing is completed when all the memory cells are sufficiently written.

  Hereinafter, the first program cycle, the first verify read cycle, the second program cycle, and the second verify read cycle will be described in detail.

(1) Program First Cycle Before the write operation, the input 2-bit data is converted by the data input / output buffer 4 and input to the data circuit 6 ^** .

FIG. 17 is a diagram showing write data input to the data circuit 6 ^** and latched by the flip-flops FF1 and FF2. The relationship between the quaternary data and the data input / output lines IOA, IOB, IOC, and IOD is as shown in FIG.

  The converted quaternary data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is “H”.

  FIG. 18 is an operation waveform diagram showing a write operation (program first cycle).

  At time t1w, the voltage VA becomes the bit line write control voltage 1V, and the bit line BLa is set to 1V. When a voltage drop corresponding to the threshold value of n channel MOS transistor Qn39 becomes a problem, signal BLCA may be boosted. Subsequently, the signal PRE becomes “L” and the bit line is floated. Next, the signal RV2A is set to 1.5 V at time t2w. As a result, the bit line control voltage 0 V is applied to the bit line in the column holding the data “1” or “3”. Assuming that the threshold value of the n-channel MOS transistor Qn32 is 1V, the n-channel MOS transistor Qn32 is “OFF” when “0” or “2” is written, and “ON” when “1” or “3” is written. Thereafter, VRFYBA becomes 0 V at time t3w, and the bit line write control voltage VCC is output to the bit line from the data circuit holding the data “0” or data “1”.

  As a result, the bit line for writing “0” or “1” becomes VCC, the bit line for writing “2” becomes 1V, and the bit line for writing “3” becomes 0V.

  At time t1w, the selection gate SG1A and the control gates CG1A to CG4A of the selected block become VCC by the control gate / selection gate drive circuit. The selection gate SG2A is 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become the VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “3”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding data “2”, electrons are injected into the floating gate due to the potential difference between the channel potential of 1 V and the VPP of the control gate, and the threshold value rises. The reason why the channel potential is set to 1 V is that the injection amount of electrons may be smaller than that of “3” data writing. In a memory cell corresponding to a data circuit holding data “0” or data “1”, the potential difference between the channel potential and the VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During the write operation, the signals SAN1, SAN2, VRFYBB, PREB, and BLCB are “H”, the signals SAP1, SAP2, RV1A, RV1B, RV2B, ECH1, and ECH2 are “L”, and the voltage VB is 0V.

(2) Verify Read First Cycle After the write operation, the threshold values of the memory cell for writing “2” and the memory cell for writing “3” are detected (write verify). If the desired threshold value is reached, the data in the data circuit is changed to “0”. If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The first write cycle and the first write verify cycle are repeated until all “2” -written memory cells and “3” -written memory cells reach a desired threshold value.

  FIG. 19 is an operation waveform diagram showing a verify read operation (verify read first cycle).

  First, at time t1v, the voltages VA and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become “L”, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. Subsequently, at time t2v, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 1.5V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. . If the threshold value of the selected memory cell is 1.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 1.5V or higher, the bit line voltage remains 1.8V. At time t3v, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. Thereafter, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, at time t4v, the signal RV2A is set to 1.5 V, for example, equal to or lower than VCC. When the threshold value of n channel MOS transistor Qn32 is 1V, in a data circuit holding “3” write data, n channel MOS transistor Qn32 is “ON” and node N1 is 0V. In the data circuit in which “2” write data is held and the memory cell is sufficiently written “2”, the n-channel MOS transistor Qn32 is “OFF” and the node N1 is kept at 1.5 V or higher. It is. When “2” writing is insufficient, the node N1 is 1.5V or less. During this time, the selected control gate is set to 2.5V. When the signal VRFYBA becomes “L” at time t5v, in the data circuit holding “0” or “1” write data, the p-channel MOS transistor Qp13 is “ON” and the node N1 becomes VCC. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. Again, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched at time t6v. Thus, only the data circuit holding “2” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “2” write state. If the data in the memory cell is “2”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flop FF1. If the data in the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage at the node N1 by the flip-flop FF1. The write data of the data circuit holding “0”, “1” or “3” write data is not changed.

  Next, since the selected control gate is set to 2.5V, if the threshold value of the selected memory cell is 2.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 2.5V or more, the bit line voltage remains 1.8V. Thereafter, at time t7v, the signals BLCA and BLCB are set to “H”, and the potentials of the bit lines are transferred to N1 and N2. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBC becomes “L”, in the data circuit in which “0” or “1” write data is held and the data circuit in which “2” write is sufficiently performed, the p-channel MOS transistor Qp12C “ON”, and the node N1 becomes VCC. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. Thereafter, at time t8v, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched.

  Thereafter, as shown in FIG. 19, conversion of write data is further performed. At time t9v, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBA1 becomes “H” at time t10v, in the data circuit in which “0” or “2” write data is held, the n-channel MOS transistor Qn2 is “ON” and the node N1 is connected to VCC. Become. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. Thereafter, at time t11v, the signals SAN2 and SAP2 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched.

  In the second embodiment, by setting VRFYBA1 to VCC at time t10v, the node N1 of the MOS capacitor Qd1 when “0” writing and “2” writing are performed from the potential (1.5 V) of the node N2. The battery is charged to be higher. RV2B may be set to 1.5 V, for example, at t10v. In this case, in the case of “0” write or “2” write, since the node N6 is 0V, the n-channel MOS transistor Qn33 is turned on, and N2 becomes 0V. On the other hand, when “1” or “3” is written, since the node N6 is VCC and N2 is 1.5V, the n-channel MOS transistor Qn33 is turned off and N2 is maintained at 1.5V. At time t10v, VRFYBA1 is set to VCC. When “0” writing and “2” writing are performed, charging to N1 only needs to be larger than the potential of N2 (0V). A low voltage is sufficient.

  As described above, only the data circuit holding the “3” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “3” write state. If the data in the memory cell is “3”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not “3”, the write data is held at “3” by sensing and latching the voltage at the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding “0”, “1” or “2” write data is not changed.

  During the write verification, the signal VRFYBB is “H” and the voltage Vs is 0V.

  FIG. 20 is a diagram showing data latched by the flip-flops FF1 and FF2 after “2” or “3” writing is sufficiently performed.

If all the selected memory cells to be written “2” or “3” have reached the desired threshold value, the data in the data circuit is as shown in FIG. That "2" writing or "3" When all the memory cells selected for writing is written to enough, all of the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1 , 6 ^**- m, the node N3 becomes “H” and N4 becomes “L”. When this is detected, it can be determined whether or not all selected memory cells to be written “2” or “3” have reached a desired threshold value.

  FIG. 21 is a circuit diagram of a data circuit having a write completion batch detection transistor.

For example, “2” and “3” write end collective detection transistors Qn5 as shown in FIG. 21 may be used to detect the end of “2” write and “3” write. VRT is precharged to, for example, VCC after the first verify read cycle. If even one memory cell is insufficiently written “2” or “3”, the node N4 of the data circuit is “H”, so that the n-channel MOS transistor Qn5 is turned on and VRT is grounded. When all "2" or "3" memory cell write is written to enough, the data circuit 6 ^** -0,6 ^** -1, ..., of 6 ^** -m-1, 6 ^** -m The node N4 becomes “L”. As a result, the n channel MOS transistors Qn5 in all the data circuits are turned off, and VRT maintains the precharge potential.

(3) Program Second Cycle After all “2” and “3” writes are completed, “1” write (program second cycle) is performed. FIG. 20 shows the node potential of the flip-flop when “1” is written. That is, in the case of “1” write, the node N5 becomes “L” and the write potential is applied to the bit line, and the node N5 becomes “H” except for “1” write, and the write non-selection potential is applied to the bit line. Applied.

  FIG. 22 is an operation waveform diagram showing a write operation (program second cycle).

  At time t1p, the voltage VRFYBA1 becomes “H”, and the bit line BLa on which “0”, “2” or “3” is written is charged to the write non-select voltage VCC. When a voltage drop corresponding to the threshold value of n channel MOS transistor Qn39 becomes a problem, signal BLCA may be boosted. Subsequently, the signal RV2A is set to VCC. As a result, the write non-select voltage VCC is applied to the bit line BLa from the data circuit holding the data “0”, “2” or “3”. A write bit line potential of 0 V is applied to the bit line BLa from the data circuit holding the data “1”.

  The selection gate SG1A and the control gates CG1A to CG4A of the selected block become VCC by the control gate / selection gate drive circuit. The selection gate SG2A is 0V. Next, the control gate CG2A selected at time t2p becomes the high voltage VPP (for example, 20V), and the non-selection control gates CG1A, CG3A, and CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the VPP of the control gate, and the threshold value rises. In a memory cell corresponding to a data circuit holding data “0”, “2”, or “3”, the potential difference between the channel potential and the VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. . Therefore, the threshold value of the memory cell does not change. During the write operation, the signals SAN1, SAN2, VRFYBB, PREB, and BLCB are “H”, the signals SAP1, SAP2, RV1A, RV1B, ECH1, and ECH2 are “L”, and the voltage VB is 0V.

(4) Second Verify Read Cycle After the second write cycle is completed, the threshold value of the memory cell to which “1” is written is detected (write verify second cycle). If the desired threshold value is reached, the data in the data circuit is changed to “0”. If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all memory cells to which “1” is written reach a desired threshold value.

  FIG. 23 is an operation waveform diagram showing a verify read operation (verify read second cycle).

  First, at time t1y, the voltages VA and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become “L”, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. Subsequently, at time t2y, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 0.5V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. . If the threshold value of the selected memory cell is 0.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0.5V or higher, the bit line voltage remains 1.8V. At time t3y, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. Thereafter, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBA1 becomes “H” at time t4y, in the data circuit holding “0”, “2” or “3” write data, the n-channel MOS transistor Qn2 is “ON” and the node N1 becomes VCC.

  The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. Again, the signals SAN2 and SAP2 become “H” and “L”, respectively, whereby the voltage at the node N1 is sensed and latched at time t5y. As a result, only the data circuit holding the “1” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “1” write state. If the data in the memory cell is “1”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flop FF2. If the data in the memory cell is not “1”, the write data is held at “1” by sensing and latching the voltage at the node N2 by the flip-flop FF1. Write data of the data circuit holding “0”, “2” or “3” write data is not changed.

  FIG. 24 is a diagram showing data latched by the flip-flops FF1 and FF2 after "1" is sufficiently written.

If all the selected memory cells to be written “1” have reached the desired threshold value, the data in the data circuit is as shown in FIG. That "1" when all of the memory cell write is written to enough, all of the data circuit 6 ^** -0,6 ^** -1, ..., of 6 ^** -m-1, 6 ^** -m node N5 becomes “H” and N6 becomes “L”. When this is detected, it can be determined whether or not all selected memory cells have reached a desired threshold value.

For example, a write end batch detection transistor Qn6 as shown in FIG. 21 may be used to detect the write end of the program cycle 2. VRED is precharged to, for example, VCC after the second verify read cycle. If even one memory cell is insufficiently written with “1”, the node N6 of the data circuit is “H”, so that the n-channel MOS transistor Qn6 is turned on and VRED is grounded. When all memory cells are written to enough, the data circuit 6 ^** -0,6 ^** -1, ..., the node N6 of 6 ^** -m-1, 6 ^** -m becomes "L". As a result, the n-channel MOS transistors Qn6 in all the data circuits are turned off, and VRED maintains the precharge potential.

  Although the EEPROM according to the second embodiment has been described above, other operations are possible for verify read, write, normal read, and the like.

  FIG. 25 is an operation waveform diagram showing another verify read operation (verify read first cycle).

  For example, the first verify read cycle may be operated as shown in the operation waveform diagram of FIG.

  In the first verify read cycle shown in FIG. 25, the operation up to time t7v is the same as the first verify read first cycle shown in FIG. 19, and the operations after time t7v are different.

  At time t7v, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. When the threshold voltage of the memory cell is 2.5V or more, the bit line BLa is 1.5V or more, and when it is 2.5V or less, the bit line BLb is 1.5V or less. Thereafter, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBA1 becomes “H” at time t8z, in the data circuit in which “0” or “2” write data is held, the n-channel MOS transistor Qn2 is “ON” and the node N1 is set to 1. 5V or more. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. Thereafter, at time t9z, the signals SAN2 and SAP2 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched.

  Thereafter, as shown in FIG. 25, the conversion of the write data is further performed. At time t10z, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBA becomes “L” at time t11z, the p-channel MOS is used in the data circuit in which “0” or “1” write data is held and the data circuit in which “2” write is sufficiently performed. The transistor Qp13 is “ON”, and the node N1 becomes VCC. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. After that, at time t12z, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched.

As described above, only the data circuit holding the “3” write data can detect whether or not the data in the corresponding memory cell is sufficiently in the “3” write state. If the data in the memory cell is “3”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not “3”, the write data is held at “3” by sensing and latching the voltage at the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding “0”, “1” or “2” write data is not changed. If all the selected memory cells to be written “2” or “3” have reached the desired threshold value, the data in the data circuit is as shown in FIG. That is, "2" written or "3" When all the memory cells selected for writing is written to enough, all of the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m- The node N3 of 1, 6 ^**- m becomes “H” and N4 becomes “L”. By detecting this, it can be determined whether or not all selected memory cells to be written “2” or “3” have reached a desired threshold value.

  Further, the circuit configuration of the data circuit is not limited to the circuit configurations shown in FIGS. 12 and 21 and may be other circuit configurations.

  FIG. 26 and FIG. 27 are other circuit diagrams of the data circuit, respectively.

  The operation timing of VRFYBA1 and VRFYBB1 of the data circuit shown in FIG. 26 is the same as the operation timing of the data circuit of FIG. 12 and FIG. 21 (operation waveform diagram; FIG. 13, FIG. 18, FIG. 19, FIG. 23 and 25), VCC may be set to 0V, and 0V to VCC. Note that the operation timings of VRFYBA and VRFYBB are the same as in the case of using the data circuit of FIGS.

  27, the operation timing of VRFYBA and VRFYBB of the data circuit shown in FIG. 27 is the same as that of the data circuit of FIG. 12 and FIG. 21 (operation waveform diagram; FIG. 13, FIG. 18, FIG. 22, FIG. 23, FIG. 25), VCC may be 0V, and 0V may be VCC. Note that the operation timings of VRFYBA1 and VRFYBB1 are the same as in the case of using the data circuit of FIGS.

  In the second embodiment, “2” and “3” data are written at the same time, and then “1” data is written next. However, the order of writing is highly arbitrary. For example, “3” may be written after writing “1” and “2”, or “2” may be written after writing “1” and “3”.

<Embodiment 3>
Next explained is a multi-value storage NAND type EEPROM according to the third embodiment of the invention.

  In the second embodiment, first, the “2” state and the “3” state are written almost simultaneously, and then the “1” state is written. However, in the third embodiment, “1” is written. The “state”, “2” state, and “3” state are written almost simultaneously.

  Note that the EEPROM according to the third embodiment has the same configuration as that shown in FIGS. 1 and 2, similarly to the EEPROM according to the second embodiment.

  FIG. 28 is a circuit diagram of a data circuit included in the EEPROM according to the third embodiment of the present invention. The data circuit shown in FIG. 28 is configured with quaternary storage as an example.

As shown in FIG. 28, memory cells M1 to M4 are connected in series to form a NAND type cell. Both ends thereof are connected to a bit line BL and a source line Vs through selection transistors S1 and S2, respectively. The memory cell M group sharing the control gate CG forms a unit called “page”, and data is written / read simultaneously. A block is formed by a group of memory cells connected to the four control gates CG1 to CG4. “Page” and “Block” are selected by a control gate / selection gate drive circuit. Each bit line BL0 to BLm, data circuits ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1,6 ** -m are connected, data to be written into the corresponding memory cell Or memorize it temporarily.

  The relationship between the write state of the memory cell and the threshold value is the same as that of the first embodiment, for example, as shown in FIG.

  As shown in FIG. 28, flip-flop FF1 composed of n-channel MOS transistors Qn21, Qn22, Qn23 and p-channel MOS transistors Qp9, Qp10, Qp11, n-channel MOS transistors Qn29, Qn30, Qn31 and p-channel MOS transistor Qp16 , Qp17, Qp18, and write / read data are latched in FF2. These also operate as sense amplifiers.

  The flip-flops FF1 and FF2 latch “write as“ 0 ”,“ 1 ”,“ 2 ”write, or“ 3 ”write” as write data information, and the memory cell. Reads “data holding“ 0 ”,“ 1 ”holding,“ 2 ”holding,“ 3 ”holding”, etc. Sense and latch.

  Data input / output lines IOA, IOB and flip-flop FF1 are connected via n-channel MOS transistors Qn28, Qn27. Data input / output lines IOC, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, and IOD are also connected to data input / output buffer 4 in FIG.

  The gates of n-channel MOS transistors Qn27, Qn28, Qn35, Qn36 are connected to the output of a column address decoder composed of NAND logic circuit G2 and inverter I4. The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being “H”, respectively. N-channel MOS transistors Qn24 and Qn32 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd1. N-channel MOS transistors Qn25 and Qn33 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd2.

  The circuit constituted by the p-channel MOS transistors Qp12C and Qp13C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1 by the activation signal VRFYBAC. The circuit constituted by the p-channel MOS transistors Qp14C and Qp15C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF1 by the activation signal VRFYBBC. A circuit formed of p-channel MOS transistors Qp12C, Qp19C, and Qp20C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flops FF1 and FF2 by the activation signal VRFYBA2C. A circuit composed of p-channel MOS transistors Qp14C, Qp21C, and Qp22C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flops FF1 and FF2 by the activation signal VRFYBB2C. A circuit composed of n-channel MOS transistors Qn1C and Qn2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1C. A circuit formed of n-channel MOS transistors Qn3C and Qn4C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1C.

  MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors, and are sufficiently smaller than the bit line capacitance. N channel MOS transistor Qn37 charges MOS capacitor Qd1 to voltage VA by signal PREA. N channel MOS transistor Qn38 charges MOS capacitor Qd2 to voltage VB by signal PREB. N-channel MOS transistors Qn39 and Qn40 control connection between the data circuit 3 and the bit lines BLa and BLb, respectively, by signals BLCA and BLCB. A circuit composed of n-channel MOS transistors Qn37 and Qn38 also serves as a bit line voltage control circuit.

  Next, the operation of the thus configured EEPROM will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected is shown.

<Read operation>
FIG. 29 is an operation waveform diagram showing a read operation.

  As shown in FIG. 29, first, the voltages VA and VB are 1.8V and 1.5V, respectively, and the bit lines BLa and BLb are 1.8V and 1.5V, respectively. At time t1RC, the signals BLCA and BLCB become “L”, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb become floating. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. Subsequently, at time t2RC, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 0 V, and the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. If the threshold value of the selected memory cell is 0V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0V or higher, the bit line voltage remains 1.8V. Thereafter, at time t3RC, the signals BLCA and BLCB become “H”, and the bit line data is transferred to the MOS capacitors Qd1 and Qd2. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, the selected control gate is set to 1V. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. At time t4RC, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, “whether the data in the memory cell is“ 0 ”,“ 1 ”,“ 2 ”or“ 3 ”) is sensed by the flip-flop FF1, and the information is latched.

  Next, since the selected control gate is 1V, if the threshold value of the selected memory cell is 1V or less, the bit line voltage becomes lower than 1.5V. If the threshold value of the selected memory cell is 1V or more, the bit line voltage remains 1.8V. At time t5RC, the signals PREA and PREB become “H”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 become 1.8V and 1.5V, respectively. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. Thereafter, the signals BLCA and BLCB are set to “H” at time t6RC. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. At time t7RC, the signals SAN2 and SAP2 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, “whether the data in the memory cell is“ 0 ”or“ 1 ”,“ 2 ”or“ 3 ”” is sensed by the flip-flop FF2, and the information is latched.

  FIG. 30 is a diagram illustrating read data sensed and latched by the flip-flops FF1 and FF2 at time t7RC. The potentials of the nodes N3C and N5C of the flip-flops FF1 and FF2 at this time are as shown in FIG.

  Finally, it is sensed whether the data written in the memory cell is “2” or “3”. The selected control gate is set to 2V. If the threshold value of the selected memory cell is 2V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 2V or more, the bit line voltage remains 1.8V. At time t8RC, the signals PREA and PREB become “H”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 become 1.8V and 1.5V, respectively. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. Thereafter, the signals BLCA and BLCB are set to “H” at time t10RC. Thereafter, the signals BLCA and BLCB again become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Prior to sensing the MOS capacitor data, VRFYBA2C becomes 0V at time t11RC. As can be seen from FIG. 22, the node N5C becomes “Low level” and the node N3C becomes “high level” (that is, the node N4C becomes “Low level”) only in the case of “1” data. Accordingly, only in the case of “1” data, the p-channel MOS transistors Qp12C, Qp19C, and Qp20C are turned on and the node N1 becomes VCC. Thereafter, the signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. At time t12RC, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, “whether the data in the memory cell is“ 2 ”or“ 3 ”” is sensed by the flip-flop FF1, and the information is latched.

  FIG. 31 is a diagram showing read data sensed and latched by the flip-flops FF1 and FF2.

  As a result of the above read operation, quaternary data is latched in the flip-flops FF1 and FF2 as shown in FIG. The threshold distribution of each data in the figure is as follows.

Data “0”: Threshold value: 0 V or less Data “1”: Threshold value 0.5 V or more and 0.8 V or less Data “2”: Threshold value 1.5 V or more and 1.8 V or less Data “3”... Threshold value 2.5 V or more and 2.8 V or less During reading, the signals VRFYBAC and VRFYBBC are “H”, and the signals VRFYBA1C and VRFYBB1C are “L”. The voltage Vs is 0V.

  When the column activation signal CENB input to the column address decoder becomes “H”, the data held in the data circuit selected by the address signal is output to the data input / output lines IOA, IOB, IOC, IOD, and the data The data is output outside the EEPROM via the input / output buffer 4.

  The relationship among the data stored in the memory cell, the threshold value, and the level output after reading to the data input / output lines IOA, IOB, IOC and IOD is as shown in FIG.

  Output data to the outside of the chip may be converted based on signals output to the data input lines IOA, IOB, IOC, and IOD by the data input / output buffer 5.

<Write operation>
First, write data is loaded into the flip-flops FF1 and FF2. Thereafter, “1” data, “2” data, and “3” data are written almost simultaneously. Then, verify read is performed to check whether “1” data, “2” data, and “3” data are sufficiently written. If there is an insufficiently written memory cell, rewrite is performed. Writing is completed when the writing end detection circuit detects that all the memory cells are sufficiently written.

  In the following, first, the program will be described, and then verify read will be described.

(1) Program Before the write operation, the input 2-bit data is converted by the data input / output buffer 5 and input to the data circuit 6 ^** .

FIG. 32 is a diagram showing write data input to the data circuit 6 ^** and latched by the flip-flops FF1 and FF2. The relationship between the quaternary data and the data input / output lines IOA, IOB, IOC, and IOD is as shown in FIG.

  The converted quaternary data is transferred to the data circuit at the column address designated by the address signal when the column activation signal CENB is “H”.

  FIG. 33 is an operation waveform diagram showing a write operation.

  First, at time t1s, the voltage VA becomes the bit line write control voltage 1V, and the bit line BLa is set to 1V. When a voltage drop corresponding to the threshold value of n channel MOS transistor Qn39 becomes a problem, signal BLCA may be boosted. Subsequently, the signal PRE becomes “L” and the bit line is floated. Next, the signal RV2A is set to 1.5 V at time t2s. As a result, since the data “1” or “3” is held, the bit line control voltage 0 V is applied to the bit line. Assuming that the threshold value of the n-channel MOS transistor Qn32 is 1V, the n-channel MOS transistor Qn32 is “OFF” when “0” or “2” is written, and “ON” when “1” or “3” is written. Thereafter, VRFYBAC becomes 0 V at time t3s, and the bit line write control voltage VCC is output to the bit line from the data circuit holding the data “0” or data “1”.

  At time t4s, VRFYBA2C becomes 0V, and the data line holding the data “1” outputs the bit line “1” write potential 2V to the bit line via V1.

  As a result, the bit line for writing "0" is VCC, the bit line for writing "1" is 2V, the bit line for writing "2" is 1V, and the bit line for writing "3" is 0V.

  At time t1s, the selection gate SG1A and the control gates CG1A to CG4A of the selected block become VCC by the control gate / selection gate drive circuit. The selection gate SG2A is 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become the VM (for example, 10V). In the memory cell corresponding to the data circuit holding data “3”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and the VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding data “2”, electrons are injected into the floating gate due to the potential difference between the channel potential of 1 V and the VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding data “1”, electrons are injected into the floating gate due to the potential difference between the channel potential of 2V and the VPP of the control gate, and the threshold value rises. The channel potential for “2” writing is set to 1 V, and the channel potential for “1” writing is set to 2 V. The electron injection amount is “3” data writing, “2” writing, “ This is to reduce the order in the case of 1 "writing. In the memory cell corresponding to the data circuit holding data “0”, the potential difference between the channel potential and the VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During the write operation, the signals SAN1, SAN2, PREB, and BLCB are “H”, the signals SAP1, SAP2, VRFYBA1C, RV1A, RV1B, RV2B, ECH1, and ECH2 are “L”, and the voltage VB is 0V.

(2) Verify read After the write operation, it is detected whether the write has been sufficiently performed (write verify). If the desired threshold value is reached, the data in the data circuit is changed to “0”. If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify are repeated until all the “1” -written memory cells, “2” -written memory cells, and “3” -written memory cells reach a desired threshold value.

  34 and 35 are operation waveform diagrams showing a verify read operation, respectively.

  Hereinafter, the write verify operation will be described with reference to FIG. 34 and FIG.

  First, it is detected whether the memory cell to which “1” is written has reached a predetermined threshold value.

  First, as shown in FIG. 34, at time t1yc, the voltages VA and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and BLb become 1.8V and 1.5V, respectively. The signals BLCA and BLCB become “L”, the bit line BLa and the MOS capacitor Qd1, the bit line BLb and the MOS capacitor Qd2 are disconnected, and the bit lines BLa and BLb are in a floating state. The signals PREA and PREB become “L”, and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are in a floating state. Subsequently, at time t2yc, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 0.5V, the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. . If the threshold value of the selected memory cell is 0.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0.5V or higher, the bit line voltage remains 1.8V. At time t3yc, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. Thereafter, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, at time t4yc, RV1A becomes 1.5V, and in the case of “2” writing and “3” writing, the node N1 is discharged to 0V. Thereafter, the selected control gate is set to 1.5V. When the signal VRFYBA1C becomes “H” at time t5yc, in the data circuit holding “0” or “2” write data, the n-channel MOS transistor Qn2 is “ON” and the node N1 becomes VCC. As a result, the node N1 becomes VCC when “0” or “2” is written, and becomes 0 V when “3” is written.

  The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. Again, when the signals SAN2 and SAP2 become “H” and “L”, respectively, the voltage at the node N1 is sensed and latched at time t6yc. As a result, only the data circuit holding the “1” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “1” write state. If the data in the memory cell is “1”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flop FF2. If the data in the memory cell is not “1”, the write data is held at “1” by sensing and latching the voltage at the node N2 by the flip-flop FF1. Write data of the data circuit holding “0”, “2” or “3” write data is not changed.

  Next, since the selected control gate is set to 1.5V, if the threshold value of the selected memory cell is 1.5V or less, the bit line voltage becomes lower than 1.5V. If the threshold value of the selected memory cell is 1.5V or higher, the bit line voltage remains 1.8V. At time t7yc, PREA and PREB become VCC, and after nodes N1 and N2 become 1.8V and 1.5V, they become floating. Thereafter, as shown in FIG. 35, at time t8yc, the signals BLCA and BLCB are set to “H”, and the potentials of the bit lines are transferred to N1 and N2. Thereafter, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, at time t9yc, the signal RV2A is set to 1.5 V, for example, equal to or lower than VCC. When the threshold value of n channel MOS transistor Qn32 is 1V, in a data circuit holding “3” write data, n channel MOS transistor Qn32 is “ON” and node N1 is 0V. In the data circuit in which “2” write data is held and the memory cell is sufficiently written “2”, the n-channel MOS transistor Qn32 is “OFF” and the node N1 is kept at 1.5 V or higher. It is. When “2” writing is insufficient, the node N1 is 1.5V or less. During this time, the selected control gate is set to 2.5V. When the signal VRFYBAC becomes “L” at time t10yc, in the data circuit holding “0” or “1” write data, the p-channel MOS transistor Qp13 is “ON” and the node N1 becomes VCC.

  The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. Again, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched at time t11yc. Thus, only the data circuit holding “2” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “2” write state. If the data in the memory cell is “2”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flop FF1. If the data in the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage at the node N1 by the flip-flop FF1. The write data of the data circuit holding “0”, “1” or “3” write data is not changed.

  Next, since the selected control gate is set to 2.5V, if the threshold value of the selected memory cell is 2.5V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 2.5V or more, the bit line voltage remains 1.8V. Thereafter, at time t12yc, the signals BLCA and BLCB are set to “H”, and the potentials of the bit lines are transferred to N1 and N2. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBAC becomes “L” at time t13yc, the p-channel MOS is used in the data circuit in which “0” or “1” write data is held and the data circuit in which “2” write is sufficiently performed. The transistor Qp13C is “ON”, and the node N1 becomes VCC. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. Thereafter, at time t14yc, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched.

  Thereafter, as shown in FIG. 35, the conversion of the write data is further performed. At time t15yc, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBA1C becomes “H” at time t16yc, the n-channel MOS transistor Qn2C is turned “ON” in the data circuit holding “0” or “2” write data and the data circuit sufficient for “1” write. ”And the node N1 becomes VCC. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. Thereafter, at time t17yc, the signals SAN2 and SAP2 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched.

  In the above embodiment, by setting VRFYBA1C to VCC at time t16yc, the node N1 of the MOS capacitor Qd1 when writing “0” and “2” is made higher than the potential (1.5 V) of the node N2. Is charging. RV2B may be set to 1.5 V at t16yc, for example. In this case, in the case of writing “0” or “2”, since the node N6C is 0V, the n-channel MOS transistor Qn33 is turned on and N2 becomes 0V. On the other hand, when “1” or “3” is written, since the node N6C is VCC and N2 is 1.5V, the n-channel MOS transistor Qn33 is turned off and N2 is kept at 1.5V. At time t16yc, VRFYBA1C is set to VCC. When “0” writing and “2” writing are performed, charging to N1 only needs to be larger than the potential of N2 (0V). A low voltage is sufficient.

  As described above, only the data circuit holding the “3” write data detects whether or not the data in the corresponding memory cell is sufficiently in the “3” write state. If the data in the memory cell is “3”, the write data is changed to “0” by sensing and latching the voltage at the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not “3”, the write data is held at “3” by sensing and latching the voltage at the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding “0”, “1” or “2” write data is not changed.

  During the write verification, the signal VRFYBBC is “H”, the signal VRFYBB1C is “L”, and the voltage Vs is 0V.

  If all the selected memory cells reach the desired threshold value, the data in the data circuit becomes “0” data. That is, when the writing is completed, the nodes N4C and N6C become “L”. By detecting this, it can be determined whether or not all selected memory cells have reached a desired threshold value.

  FIG. 28 is a circuit diagram of a data circuit having a write completion batch detection transistor.

For example, as shown in FIG. 28, the write end batch detection transistors Qn5C and Qn6C may be used to detect the end of writing. After the verify read, first, VRTC is precharged to VCC, for example. If even one memory cell is insufficiently written, at least one of the nodes N4C or N6C of the data circuit is “H”, so that at least one of the n-channel MOS transistors Qn5C and Qn6C is turned on, and the VRTC is precharged. Decrease from When all memory cells are written to enough, the data circuit ^{6 ** -0,6 ** -1, ...,} 6 ** -m-1 node N4C, N6C becomes "L". As a result, n-channel MOS transistors Qn5C and Qn6C in all data circuits are turned off, so that VRTC maintains the precharge potential.

  Although the EEPROM according to the third embodiment has been described above, other operations are possible for verify read, write, normal read, and the like.

  FIG. 36 is an operation waveform diagram showing another verify read operation.

  For example, the verify read may be operated as shown in the operation waveform diagram of FIG.

  In the verify read shown in FIG. 36, the operation up to time t12yc is the same as the verify read shown in FIG. 35, and the operation after time t12yc is different.

  At time t12yc, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. When the threshold voltage of the memory cell is 2.5V or more, the bit line BLa is 1.5V or more, and when it is 2.5V or less, the bit line BLb is 1.5V or less. Thereafter, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. Thereafter, when the signal VRFYBA1C becomes “H” at time t13zc, the n-channel MOS transistor Qn2 is turned “ON” in the data circuit holding “0” or “2” write data and the data circuit sufficient for “1” write. ", And the node N1 is 1.5 V or higher. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H”. Thereafter, at time t14zc, the signals SAN2 and SAP2 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched.

  Thereafter, as shown in FIG. 36, the conversion of the write data is further performed. At time t15zc, the signals BLCA and BLCB are set to “H”, and the potential of the bit line is transferred to N1 and N2. Again, the signals BLCA and BLCB become “L”, and the bit line BLa and the MOS capacitor Qd1, and the bit line BLb and the MOS capacitor Qd2 are disconnected. After that, when the signal VRFYBAC becomes “L” at time t16zc, the p-channel MOS is used in the data circuit in which “0” or “1” write data is held and the data circuit in which “2” write is sufficiently performed. The transistor Qp13 is “ON”, and the node N1 becomes VCC. The signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, the signals RV1A and RV1B become “H”. After that, at time t17zc, the signals SAN1 and SAP1 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Further, the circuit configuration of the data circuit is not limited to the circuit configuration shown in FIG. 20, and may be another circuit configuration.

  37, 38, 39, and 40 are other circuit diagrams of the data circuit, respectively.

  The operation timing of VRFYBA1C and VRFYBB1C of the data circuit shown in FIG. 37 is the same as that of the data circuit of FIG. 28 (operation waveform diagram: FIGS. 29, 33, 34, 35, and 36). VCC may be set to 0V and 0V to VCC. Note that the timings of VRFYBAC, VRFYBBC, VRFYBA2C, and VRFYBB2C are the same as when the data circuit of FIG. 28 is used.

  Further, the operation timing of VRFYBAC, VRFYBBC, VRFYBA2C, and VRFYBB2C in the data circuit shown in FIG. 38 is the case where the data circuit of FIG. 28 is used (operation waveform diagram; FIGS. 29, 33, 34, 3535, and 36). ), VCC may be set to 0V, and 0V may be set to VCC. The operation timing of VRFYBA1C and VRFYBB1C is the same as that when the data circuit of FIG. 28 is used.

  Further, the operation timing of VRFYBAC and VRFYBBC of the data circuit shown in FIG. 39 is obtained when VCC is used when the data circuit of FIG. 28 is used (operation waveform diagram: FIG. 29, FIG. 33, FIG. 34, FIG. 35, FIG. 36). What is necessary is just to make 0V and 0V into VCC. Note that the operation timings of VRFYBA1C, VRFYBB1C, VRFYBA2C, and VRFYBB2C are the same as those when the data circuit of FIG. 28 is used.

  In addition, the operation timing of VRFYBA2C and VRFYBB2C of the data circuit shown in FIG. 40 is obtained when VCC is used when the data circuit of FIG. 28 is used (operation waveform diagrams: FIGS. 29, 33, 34, 35, and 36). What is necessary is just to make 0V and 0V into VCC. Note that the operation timings of VRFYBA1C, VRFYBB1C, VRFYBAC, and VRFYBBC are the same as when the data circuit of FIG. 28 is used. Furthermore, when VRFYBA2C, VRFYBB2C, VRFYBA1C, and VRFYBB1C are set to VCC, VCC + Vth (Vth is a threshold voltage of an n-channel MOS transistor) or VCC + 2Vth may be used instead of VCC. In this case, the n-channel MOS transistor can transfer the potential without causing a substantial “threshold drop”.

  In the third embodiment, at the time of reading and verify reading, after precharging the bit line, the non-selected control gates CG1A, CG3A, and CG4A are set to VCC, so that CG1A, CG3A, and CG4A are used as gate electrodes. The memory cell to be turned on is turned on.

  For example, the non-selected control gates CG1A, CG3A, and CG4A may be set to VCC, then floated, and then the bit line may be precharged. Alternatively, after precharging the bit line, the non-selected control gate may be set to VCC, and then the non-selected control gate may be floated. In this case, the non-selected control gate is in a floating state while a read current flows from the bit line to the source line through the memory cell. While the read current flows, the channel of the memory cell having the non-selected control gate as the gate electrode increases from 0 V. As a result, the potential of the non-selected control gate is higher than VCC due to capacitive coupling between the channel and the non-selected control gate. growing. As described above, when the potential of the non-selected control gate becomes higher than VCC, the resistance of the memory cell having the non-selected control gate as the gate electrode is reduced, and as a result, the read current is increased, and the reading speed is increased.

<Embodiment 4>
Next explained is a multi-value storage NAND type EEPROM according to the fourth embodiment of the invention.

  Note that the EEPROM according to the fourth embodiment has the same configuration as that shown in FIGS. 1 and 2 as in the case of the EEPROM according to the second embodiment.

  FIG. 41 is a circuit diagram of a data circuit included in the EEPROM according to the fourth embodiment of the present invention. The data circuit shown in FIG. 41 is configured with quaternary storage as an example.

  The data circuit shown in FIG. 41 includes two latch circuits (a first latch circuit and a second latch circuit). At the time of writing, 2-bit write data is stored in these two latch circuits. At the time of reading, the read quaternary data is stored in these two latch circuits and then output to the outside of the chip via IOA to IOD.

  As shown in FIG. 41, n-channel MOS transistors Qn21, Qn22, Qn23 and p-channel MOS transistors Qp9, Qp10, Qp11, flip-flop FF1, n-channel MOS transistors Qn29, Qn30, Qn31 and p-channel MOS transistor Qp16, Write / read data is latched in FF2 constituted by Qp17 and Qp18. These also operate as sense amplifiers.

  The flip-flops FF1 and FF2 latch “write as“ 0 ”,“ 1 ”,“ 2 ”write, or“ 3 ”write” as write data information, and the memory cell. Reads “data holding“ 0 ”,“ 1 ”holding,“ 2 ”holding,“ 3 ”holding”, etc. Sense and latch.

  Data input / output lines IOA, IOB and flip-flop FF1 are connected via n-channel MOS transistors Qn28, Qn27. Data input / output lines IOC, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36. Data input / output lines IOA, IOB, IOC, IOD are also connected to data input / output buffer 5 shown in FIG. The gates of n-channel MOS transistors Qn27 and Qn28 are connected to the output of a column address decoder composed of NAND logic circuit G3 and inverter I5.

  The n-channel MOS transistors Qn26 and Qn34 equalize the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being “H”, respectively. N-channel MOS transistors Qn24 and Qn32 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd1. N-channel MOS transistors Qn25 and Qn33 control connection between flip-flops FF1 and FF2 and MOS capacitor Qd2.

  A circuit formed of n-channel MOS transistors Qn50C and Qn51C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1 by the activation signal VRFYBAC. A circuit composed of n-channel MOS transistors Qn52C and Qn53D changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF1 by the activation signal VRFYBBC. A circuit formed of n-channel MOS transistors Qn53C, Qn54C, and Qn55C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flops FF1 and FF2 by the activation signal VRFYBA2C. A circuit composed of n-channel MOS transistors Qn56C, Qn57C, and Qn58C changes the gate voltage of MOS capacitor Qd2 according to the data of flip-flops FF1 and FF2 by activation signal VRFYBB2C. A circuit composed of n-channel MOS transistors Qn1C and Qn2C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2 by the activation signal VRFYBA1C. A circuit formed of n-channel MOS transistors Qn3C and Qn4C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flop FF2 by the activation signal VRFYBB1C.

  MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors, and are sufficiently smaller than the bit line capacitance. N channel MOS transistor Qn37 charges MOS capacitor Qd1 to voltage VA by signal PREA. N channel MOS transistor Qn38 charges MOS capacitor Qd2 to voltage VB by signal PREB. N-channel MOS transistors Qn39 and Qn40 control connection between the data circuit 3 and the bit lines BLa and BLb, respectively, by signals BLCA and BLCB. A circuit composed of n-channel MOS transistors Qn37 and Qn38 also serves as a bit line voltage control circuit.

  Next, the operation of the thus configured EEPROM will be described with reference to an operation waveform diagram. Hereinafter, a case where the control gate CG2A is selected is shown.

<Read operation>
FIG. 42 is an operation waveform diagram showing a read operation.

  As shown in FIG. 42, first, at time tw1, the voltages VA and VB are 1.8V and 1.5V, respectively, and the bit lines BLa and BLb are 1.8V and 1.5V, respectively. Next, the signals PREA and PREB become “L”, and the bit lines BLa and BLb become floating. Subsequently, at time tw2, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit is set to 1V, and the non-selected control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. If the threshold value of the selected memory cell is 1V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 1V or more, the bit line voltage remains 1.8V. Thereafter, the signals SAN1 and SAP1 become “L” and “H”, respectively, to inactivate the flip-flop FF1, and the signal ECH1 becomes “H” and equalized. Thereafter, at time t3w, the signals RV1A and RV1B become “H”. At time tw4, the signals SAN1 and SAP1 again become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, “whether the data of the memory cell is“ 0 ”or“ 1 ”,“ 2 ”or“ 3 ”” is sensed by the flip-flop FF1, and the information is latched.

  Next, it is determined whether the threshold value of the memory cell is 0 V or higher or 0 V or lower. At time tw5, the bit line BLa is precharged to 1.8V and the dummy bit line BLb is precharged to 1.5V, and then floated. Thereafter, the control gate selected at time tw6 is set to 0V. If the threshold value of the selected memory cell is 0V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 0V or higher, the bit line voltage remains 1.8V. The signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, the signals RV2A and RV2B become “H” at time tw7. At time tw8, the signals SAN2 and SAP2 become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, “whether the data in the memory cell is“ 0 ”,“ 1 ”,“ 2 ”or“ 3 ”) is sensed by the flip-flop FF2, and the information is latched.

  FIG. 43 shows read data sensed and latched by the flip-flops FF1 and FF2 at time tw8. At this time, the potentials of the nodes N3C and N5C of the flip-flops FF1 and FF2 are as shown in FIG.

  Finally, it is sensed whether the data written in the memory cell is “0”, “1”, “2”, or “3”. At time tw9, the bit line BLa is precharged to 1.8V and the dummy bit line BLb is precharged to 1.5V, and then floated. Thereafter, the control gate selected at time tw10 is set to 2V. If the threshold value of the selected memory cell is 2V or less, the bit line voltage is lower than 1.5V. If the threshold value of the selected memory cell is 2V or more, the bit line voltage remains 1.8V. VRFYBA2C becomes VCC at time tw11.

  As can be seen from FIG. 43, the node N5C becomes “high level” and the node N3C becomes “Low level” (that is, the node N4C becomes “high level”) only in the case of “1” data. Therefore, only in the case of “1” data, the n-channel MOS transistors Qn54C, Qn55C, and Qn53C are turned on, and the node N1 becomes VCC. Thereafter, the signals SAN2 and SAP2 become “L” and “H”, respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes “H” and equalized. Thereafter, at time tw12, the signals RV2A and RV2B become “H”. At time tw13, the signals SAN2 and SAP2 again become “H” and “L”, respectively, so that the voltage at the node N1 is sensed and latched. Thus, “whether the data of the memory cell is“ 0 ”,“ 1 ”,“ 2 ”, or“ 3 ”” is sensed by the flip-flop FF2, and the information is latched.

  FIG. 44 is a diagram showing read data sensed and latched by the flip-flops FF1 and FF2.

  The 2-bit data held in the flip-flops FF1 and FF2 is output outside the chip when CENB is activated at time tw14.

  The write operation and the write verify read operation may be performed in substantially the same manner as in the third embodiment.

  In the fourth embodiment, the bit line and the dummy bit line are precharged every time before a predetermined read voltage (for example, 0V, 1V, 2V) is applied to the word line.

  On the other hand, in the third embodiment, at the time of reading and verify reading, the bit line and the dummy bit line are first precharged and then not precharged, and the read voltage of the word line is changed (for example, from 0V to 1V). 2V). Also in the third embodiment, every time a read voltage (for example, 0V, 1V, 2V) is applied to the word line at the time of reading or verify reading, the bit line as in the fourth embodiment. And the dummy bit line may be precharged.

  As mentioned above, although this invention was demonstrated by the 1st-4th embodiment, in the 1st-4th embodiment, the following further deformation | transformation is possible.

  FIG. 45 is a configuration diagram of an EEPROM having a modified column configuration.

In the first to fourth embodiments described above, one data circuit 6 ^** corresponds to one bit line BL on the left and right, but one data circuit on each bit line BL on the left and right sides. 6 ^** can be changed to a corresponding form.

As shown in FIG. 45, in an EEPROM having a modified column configuration, data is transferred to four bit lines BLai-1 to BLai-4 or BLbi-1 to BLbi-4 (i is 0 to 3). one of the circuits 6 ^** -0~6 ^** -m is provided.

  Hereinafter, the memory cell array 1A side will be described as an example.

For example, when BLai-1 is selected from the four bit lines BLai-1 to BLai-4, among the drive signals BLC1 to BLC4 for driving the transfer gate circuit 7 ^* A on the data circuit side, the signal BLC1 is set to “H”. The other signals BLC 2 to 4 are set to “L” level.

At the same time, among the drive signals BLC1D to BLC4D for driving the transfer gate circuit 7 ^** A on the non-selected bit line control circuit side, the signal BLC1D is set to “L” level, and the other signals BLC2D to 4D are set to “H”. “Level. Thus, only the bit lines BLi-1, which is selected is connected to the data circuit 6 ^** -0~6 ^** -m.

Thus, only the bit lines BLai-1 which is selected is connected to the data circuit 6 ^** -0~6 ^** -m, respectively the bit line BLai-2~BLai-4 that have not been selected, the unselected bit lines Connected to control circuits 20-0A to 20-mA. Unselected bit line control circuits 20-0A to 20-mA control the potentials of unselected bit lines BLai-2 to BLai-4.

  Further, the memory cells integrated in the memory cell arrays 1A and 1B are not limited to NAND type cells, and the present invention can be implemented with cells as described below.

  FIG. 46 is a diagram showing a memory cell array in which NOR type cells are integrated. The NOR type cell shown in FIG. 46 is connected to the bit line BL via a selection gate.

  FIG. 47 is a diagram showing a memory cell array in which other NOR type cells are integrated. The NOR type cell shown in FIG. 47 is directly connected to the bit line BL.

  FIG. 48 is a diagram showing a memory cell array in which ground array type cells are integrated. As shown in FIG. 48, the ground array type cell has a bit line BL and a source line Vs arranged in parallel. The ground array type cell is one of NOR type memories.

  FIG. 49 is a diagram showing a memory cell array in which other ground array type cells are integrated. The ground array type cell shown in FIG. 49 has an erase gate EG used when erasing data. Further, a part of the control gate CG is a so-called split channel type in which the channel of the memory cell transistor is overlapped.

  FIG. 50 is a diagram showing a memory cell array in which alternating ground array type cells are integrated. As shown in FIG. 50, the alternate ground array type cell matches the ground array type cell in that the bit line BL and the source line Vs are arranged in parallel, but the bit line BL and the source line Vs are alternated. The point that can be switched to is different.

  FIG. 51 shows a memory cell array in which other alternating ground array type cells are integrated. The alternating ground array type cell shown in FIG. 51 has the same configuration as the ground array type cell shown in FIG.

  FIG. 52 is a diagram showing a memory cell array in which DINOR (DIvided NOR) type cells are integrated. As shown in FIG. 52, the DINOR type cell is configured by connecting, for example, four memory cell transistors in parallel between a bit line BL and a source line Vs via a bit line side select transistor.

  FIG. 53 is a diagram showing a memory cell array in which AND-type cells are integrated. As shown in FIG. 53, in an AND type cell, for example, four memory cell transistors are connected in parallel between a bit line BL and a source line Vs via a bit line side selection transistor and a source line side selection transistor. Configured.

  According to the first to fourth embodiments, when data is written, the bit line is charged to a desired bit line write control voltage by at least one bit line voltage control circuit. Accordingly, a bit line voltage control circuit that applies a bit line write control voltage corresponding to n-value write data to the bit line can be realized with a simple circuit configuration. Therefore, the scale of the column circuit can be reduced, the chip size can be reduced, and a low-cost n-value storage EEPROM can be obtained.

For example, when the number of multivalued data is 2 ^m (m is a natural number of 2 or more) = n value, the flip-flop circuit latches write data to the memory cell and senses and latches read data from the memory cell. Therefore, the column scale of the column circuit can be reduced. And a determination circuit for determining whether or not to perform writing again during the verification. The determination circuit is updated to the data latch / sense amplifier circuit according to the verification read result during the verification. It is configured to be controlled by the write data being processed.

The number n of the multi-value data may be a natural number satisfying 2 ^(m−1) <n ≦ 2 ^m .

FIG. 1 is a configuration diagram showing the configuration of a multi-value storage NAND type EEPROM according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the memory cell array and column system circuit shown in FIG. FIG. 3 is a diagram showing when data is read from the memory cell shown in FIG. 2. FIG. 3A shows a voltage input state, and FIG. 3B shows a voltage input waveform and an output waveform appearing on a bit line. FIG. FIG. 4 is a diagram showing the relationship between the output voltage appearing on the bit line and the number of memory cells. FIG. 5 is a circuit diagram of the data circuit shown in FIG. FIG. 6 is an operation waveform diagram showing a read operation. FIG. 7 is a diagram showing read data sensed and latched by the flip-flop. FIG. 8 is a diagram showing write data latched by the flip-flop. FIG. 9 is an operation waveform diagram showing a write operation. FIG. 10 is an operation waveform diagram showing a verify read operation. FIG. 11 is a diagram showing a threshold distribution of memory cell transistors in the case of four-value storage. FIG. 12 is a circuit diagram of a data circuit included in an EEPROM according to the second embodiment of the present invention. FIG. 13 is an operation waveform diagram showing a read operation. FIG. 14 is a diagram showing read data sensed and latched by the flip-flop. FIG. 15 is a diagram showing read data sensed and latched by a flip-flop. FIG. 16 is a schematic diagram showing an outline of the write operation. FIG. 17 is a diagram showing write data latched by the flip-flop. FIG. 18 is an operation waveform diagram showing a write operation (program first cycle). FIG. 19 is an operation waveform diagram showing a verify read operation (verify read first cycle). FIG. 20 is a diagram showing data latched by a flip-flop. FIG. 21 is a circuit diagram of a data circuit having a write completion batch detection transistor. FIG. 22 is an operation waveform diagram showing a write operation (program second cycle). FIG. 23 is an operation waveform diagram showing a verify read operation (verify read second cycle). FIG. 24 is a diagram showing data latched by a flip-flop. FIG. 25 is an operation waveform diagram showing another verify read operation (verify read first cycle). FIG. 26 is another circuit diagram of the data circuit. FIG. 27 is another circuit diagram of the data circuit. FIG. 28 is a circuit diagram of a data circuit included in an EEPROM according to the third embodiment of the present invention. FIG. 29 is an operation waveform diagram showing a read operation. FIG. 30 is a diagram showing read data sensed and latched by the flip-flop. FIG. 31 is a diagram showing read data sensed and latched by a flip-flop. FIG. 32 is a diagram showing write data latched by the flip-flop. FIG. 33 is an operation waveform diagram showing a write operation. FIG. 34 is an operation waveform diagram showing a verify read operation. FIG. 35 is an operation waveform diagram showing a verify read operation. FIG. 36 is an operation waveform diagram showing another verify read operation. FIG. 37 is another circuit diagram of the data circuit. FIG. 38 is another circuit diagram of the data circuit. FIG. 39 is another circuit diagram of the data circuit. FIG. 40 is another circuit diagram of the data circuit. FIG. 41 is a circuit diagram of a data circuit included in an EEPROM according to the fourth embodiment of the invention. FIG. 42 is an operation waveform diagram showing a read operation. FIG. 43 is a diagram showing read data sensed and latched by the flip-flop. FIG. 44 is a diagram showing read data sensed and latched by a flip-flop. FIG. 45 is a configuration diagram of an EEPROM having a modified column configuration. FIG. 46 is a diagram showing a memory cell array in which NOR-type cells are integrated. FIG. 47 is a diagram showing a memory cell array in which other NOR type cells are integrated. FIG. 48 is a diagram showing a memory cell array in which ground array cells are integrated. FIG. 49 is a diagram showing a memory cell array in which other ground array type cells are integrated. FIG. 50 is a diagram showing a memory cell array in which alternating ground array type cells are integrated. FIG. 51 is a diagram showing a memory cell array in which other alternating ground array type cells are integrated. FIG. 52 is a diagram showing a memory cell array in which DINOR type cells are integrated. FIG. 53 shows a memory cell array in which AND-type cells are integrated.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row system circuit, 3 ... Column system circuit, 4 ... Address buffer, 5 ... Data input / output circuit, 6 ^** ... Data circuit, 7 ... Transfer gate circuit, MC ... Memory cell, M ... Memory Cell transistor, S ... select transistor, SG ... select gate, CG ... control gate, BL ... bit line, FF ... flip-flop circuit.

Claims (6)

A memory cell array in which memory cells storing n values (n is a natural number of 3 or more) that can be electrically rewritten are arranged in a matrix;
Threshold detecting means for charging the bit line connected to the memory cell through the memory cell and outputting the multi-value data of the memory cell as a multi-level potential to the bit line;
A sense amplifier that senses a multi-level bit line potential charged by the threshold detection means;
A first, second,..., Mth data circuit for holding data to be written to the memory cell;
A write verify unit that uses the threshold value detecting unit to confirm whether or not the state after the write operation of the memory cell is a storage state of desired data;
Batch update of data circuit contents comprising a data update circuit that batch updates the contents of the data circuit so that rewriting is performed only on memory cells that are insufficiently written from the contents of the data circuit and the state after the write operation of the memory cells. Means and
A nonvolatile semiconductor memory device, wherein the data update circuit refers to the contents of one data circuit. A memory cell array in which memory cells storing n values (n is a natural number of 3 or more) that can be electrically rewritten are arranged in a matrix;
Threshold detecting means for charging the bit line connected to the memory cell through the memory cell and outputting the multi-value data of the memory cell as a multi-level potential to the bit line;
A sense amplifier that senses the bit line potential by comparing the reference voltage to the multi-level bit line potential charged by the threshold detection means;
A first, second,..., Mth data circuit for holding data to be written to the memory cell;
A write verify unit that uses the threshold value detecting unit to confirm whether or not the state after the write operation of the memory cell is a storage state of desired data;
Batch update of data circuit contents comprising a data update circuit that batch updates the contents of the data circuit so that rewriting is performed only on memory cells that are insufficiently written from the contents of the data circuit and the state after the write operation of the memory cells. Means and
The data update circuit refers to the contents of one data circuit,
The data circuit content batch updating means determines the bit line to which the state after the write operation of the memory cell is output and the reference potential in accordance with the contents of the data circuit so that the bit line potential is sensed and stored as rewrite data. The data storage state of the data circuit is maintained until the bit line potential is corrected, the data circuit is operated as a sense amplifier while the corrected bit line potential is maintained, and the contents of the data circuit are collectively updated. ,
A nonvolatile semiconductor memory device, wherein data is electrically written by repeatedly performing a write operation based on the contents of a data circuit and a batch update of data circuit contents until a memory cell enters a predetermined write state. The memory cell is a NAND cell in which a plurality of memory cell transistors are connected in series, and one end of the NAND cell is connected to a bit line via a first selection gate, and the NAND cell The other end is connected to the source line via the second selection gate,
The threshold detection means transfers the source line voltage to the bit line via the NAND cell to charge the bit line,
The unselected control gate voltage and the first and second selection gate voltages are the voltages of the unselected memory cell and the first and second selection transistors so that the bit line voltage is determined by the threshold value of the selected memory cell. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is controlled so as to sufficiently increase a transfer capability. A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix;
First, a second, ..., (the m ^{2 (m-1)} <natural number satisfying n ≦ ^{2 m)} the m-th data circuit for holding data to be written into the memory cell,
A write verify means for confirming whether or not the state after the write operation of the memory cell is a storage state of desired data;
Data circuit contents batch updating means comprising a data updating circuit for updating the contents of the data circuit so as to perform rewriting only to the insufficiently written memory cells from the contents of the data circuit and the state after the writing operation of the memory cells. And
A nonvolatile semiconductor memory device, wherein the data update circuit refers to the contents of one data circuit.   The nonvolatile semiconductor memory device according to claim 1, wherein n is 4 or more. A memory cell array in which memory cells for storing electrically rewritable n values (n is a natural number of 3 or more) are arranged in a matrix;
M data circuits for holding data to be written in the memory cells;
A write verify means for confirming whether or not the state after the write operation of the memory cell is a storage state of desired data;
Data circuit contents batch updating means comprising a data updating circuit for updating the contents of the data circuit so as to perform rewriting only to the insufficiently written memory cells from the contents of the data circuit and the state after the writing operation of the memory cells. And
A nonvolatile semiconductor memory device, wherein the data update circuit refers to the contents of one data circuit.

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