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JP2006165109A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2006165109A
JP2006165109A JP2004351343A JP2004351343A JP2006165109A JP 2006165109 A JP2006165109 A JP 2006165109A JP 2004351343 A JP2004351343 A JP 2004351343A JP 2004351343 A JP2004351343 A JP 2004351343A JP 2006165109 A JP2006165109 A JP 2006165109A
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JP
Japan
Prior art keywords
semiconductor device
ground terminal
substrate
transfer mold
mold resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004351343A
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Japanese (ja)
Inventor
Satoo Yamanishi
学雄 山西
Atsunori Kajiki
篤典 加治木
Hiroyuki Takatsu
浩幸 高津
Takashi Tsubota
崇 坪田
Sadakazu Akaike
貞和 赤池
Akinobu Inoue
明宣 井上
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2004351343A priority Critical patent/JP2006165109A/en
Publication of JP2006165109A publication Critical patent/JP2006165109A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be made compact and can improve productivity, and its manufacturing method, in the semiconductor device which can protect electronic parts mounted to a substrate from electromagnetic waves, and to provide its manufacturing method. <P>SOLUTION: A ground terminal 57 is exposed, and a transfer mold resin 75 is provided to cover an individual part 67 as an electronic part and a semiconductor chip 70, and then a metal layer 77 is formed on the surface of the transfer mold resin 75 and it is electrically connected with the ground terminal 57. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置及びその製造方法に係り、特に基板上に実装された電子部品を電磁波から保護することのできる半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device capable of protecting an electronic component mounted on a substrate from electromagnetic waves and a manufacturing method thereof.

従来の半導体装置には、基板上に実装された電子部品を電磁波から保護するためのシールドケースを備えたものがある。図１及び図２は、シールドケースを備えた従来の半導体装置の断面図である。なお、図１において、Ｈ１はポッティング樹脂３５の高さ（以下、「高さＨ１」とする）、Ｈ２は半導体装置１０の高さ（以下、「高さＨ２」とする）、Ｃ１はポッティング樹脂３５とシールドケース３６との間の隙間（以下、「隙間Ｃ１」とする）をそれぞれ示している。また、図２において、Ｈ３は半導体装置４０の高さ（以下、「高さＨ３」とする）、Ｃ２はポッティング樹脂３５とシールドケース４４との間の隙間（以下、「隙間Ｃ２」とする）をそれぞれ示している。さらに、図２において、図１と同一構成部分には同一符号を付す。   Some conventional semiconductor devices include a shield case for protecting electronic components mounted on a substrate from electromagnetic waves. 1 and 2 are cross-sectional views of a conventional semiconductor device provided with a shield case. In FIG. 1, H1 is the height of the potting resin 35 (hereinafter referred to as “height H1”), H2 is the height of the semiconductor device 10 (hereinafter referred to as “height H2”), and C1 is the potting resin. A gap between the shield case 36 and the shield case 36 (hereinafter referred to as “gap C1”) is shown. In FIG. 2, H3 is the height of the semiconductor device 40 (hereinafter referred to as “height H3”), and C2 is a gap between the potting resin 35 and the shield case 44 (hereinafter referred to as “gap C2”). Respectively. Further, in FIG. 2, the same components as those in FIG.

図１に示すように、半導体装置１０は、大略すると、基板１１と、電子部品である個別部品２６及び半導体チップ３１と、ポッティング樹脂３５と、シールドケース３６とを有した構成とされている。基板１１は、大略すると基材１２と、貫通ビア１３と、接続部１４，１５と、グラウンド端子１６と、絶縁層１７と、配線２１と、ソルダーレジスト２３と、はんだボール２５とを有した構成とされている。貫通ビア１３は、基材１２を貫通するよう配設されている。貫通ビア１３は、接続部１４，１５と配線２１との間を電気的に接続するためのものである。   As shown in FIG. 1, the semiconductor device 10 generally includes a substrate 11, individual components 26 and semiconductor chips 31 that are electronic components, a potting resin 35, and a shield case 36. The substrate 11 generally includes a base material 12, a through via 13, connection portions 14 and 15, a ground terminal 16, an insulating layer 17, a wiring 21, a solder resist 23, and a solder ball 25. It is said that. The through via 13 is disposed so as to penetrate the base material 12. The through via 13 is for electrically connecting the connection portions 14 and 15 and the wiring 21.

接続部１４，１５は、基材１２の上面に設けられており、貫通ビア１３と電気的に接続されている。接続部１４は、金ワイヤ３４を介して半導体チップ３１と電気的に接続されている。接続部１５は、個別部品２６と電気的に接続されている。グラウンド端子１６は、個別部品２６及び半導体チップ３１が実装される領域よりも外側に位置する基材１２上に設けられている。グラウンド端子１６は、グラウンド電位とされた導体であり、シールドケース３６と電気的に接続されている。絶縁層１７は、接続部１４，１５間を隔てるよう基材１２の上面に設けられている。   The connection parts 14 and 15 are provided on the upper surface of the base material 12 and are electrically connected to the through via 13. The connection part 14 is electrically connected to the semiconductor chip 31 via a gold wire 34. The connection unit 15 is electrically connected to the individual component 26. The ground terminal 16 is provided on the base material 12 positioned outside the region where the individual component 26 and the semiconductor chip 31 are mounted. The ground terminal 16 is a conductor having a ground potential, and is electrically connected to the shield case 36. The insulating layer 17 is provided on the upper surface of the base material 12 so as to separate the connection portions 14 and 15.

配線２１は、はんだボール２５が接続される接続パッド２２を有した構成とされている。配線２１は、基材１２の下面に設けられており、貫通ビア１３と電気的に接続されている。ソルダーレジスト２３は、接続パッド２２を露出すると共に、接続パッド２２以外の配線２１を覆うよう基材１２の下面側に設けられている。はんだボール２５は、接続パッド２２と電気的に接続されている。はんだボール２５は、半導体装置１０をマザーボード等の他の基板に接続するための外部接続端子である。   The wiring 21 has a connection pad 22 to which the solder ball 25 is connected. The wiring 21 is provided on the lower surface of the substrate 12 and is electrically connected to the through via 13. The solder resist 23 is provided on the lower surface side of the substrate 12 so as to expose the connection pads 22 and cover the wirings 21 other than the connection pads 22. The solder ball 25 is electrically connected to the connection pad 22. The solder ball 25 is an external connection terminal for connecting the semiconductor device 10 to another substrate such as a mother board.

個別部品２６は、トランジスタ、ダイオード、抵抗、コンデンサ等の基本となる電気的素子の１つの機能が１つの部品となっているものである。個別部品２６は、はんだペースト２７により接続部１５と電気的に接続されている。   The individual component 26 is a component in which one function of basic electrical elements such as a transistor, a diode, a resistor, and a capacitor is formed. The individual component 26 is electrically connected to the connection portion 15 by a solder paste 27.

半導体チップ３１は、接着剤２４により基材１２上に配設されている。半導体チップ３１は、電極パッド３３を有しており、電極パッド３３と接続部１４との間は金ワイヤ３４により電気的に接続されている。半導体チップ３１は、金ワイヤ３４を保護するポッティング樹脂３５（ポッティング法により形成された樹脂）により覆われている（例えば、特許文献１参照）。   The semiconductor chip 31 is disposed on the base material 12 by the adhesive 24. The semiconductor chip 31 has an electrode pad 33, and the electrode pad 33 and the connection portion 14 are electrically connected by a gold wire 34. The semiconductor chip 31 is covered with a potting resin 35 (resin formed by a potting method) that protects the gold wire 34 (see, for example, Patent Document 1).

シールドケース３６は、個別部品２６及び半導体チップ３１を覆うと共に、はんだペースト３７によりグラウンド端子１６と電気的に接続されている。このようなシールドケース３６を設けることで、電磁波から個別部品２６及び半導体チップ３１を保護することができる。   The shield case 36 covers the individual component 26 and the semiconductor chip 31 and is electrically connected to the ground terminal 16 by a solder paste 37. By providing such a shield case 36, the individual component 26 and the semiconductor chip 31 can be protected from electromagnetic waves.

また、図２に示すように、基材４１の側面にグラウンド端子４２を設けて、はんだペースト３７によりグラウンド端子４２とシールドケース４４とを電気的に接続した半導体装置４０がある。
特開２００１−２６７６２８号公報 Further, as shown in FIG. 2, there is a semiconductor device 40 in which a ground terminal 42 is provided on a side surface of a base material 41 and the ground terminal 42 and the shield case 44 are electrically connected by a solder paste 37.
JP 2001-267628 A

しかしながら、ポッティング法を用いた場合には、ポッティング樹脂３５の高さＨ１の制御が難しいという問題や、半導体装置１０，４０の生産性が低下するという問題があった。また、ポッティング樹脂３５の凸形状がシールドケース３６，４４に転写されることを防止するため、ポッティング樹脂３５とシールドケース３６，４４との間に隙間Ｃ１，Ｃ２を設ける必要がある。そのため、半導体装置１０，４０の高さＨ２，Ｈ３が大きくなってしまい、半導体装置１０，４０を小型化することができないという問題があった。   However, when the potting method is used, there are problems that it is difficult to control the height H1 of the potting resin 35 and that the productivity of the semiconductor devices 10 and 40 is reduced. Further, in order to prevent the convex shape of the potting resin 35 from being transferred to the shield cases 36 and 44, it is necessary to provide gaps C1 and C2 between the potting resin 35 and the shield cases 36 and 44. Therefore, the heights H2 and H3 of the semiconductor devices 10 and 40 are increased, and there is a problem that the semiconductor devices 10 and 40 cannot be reduced in size.

さらに、シールドケース３６，４４を用いた場合、半導体装置１０，４０毎に用意したシールドケース３６，４４とグラウンド端子１６，４２との間をはんだにより電気的に接続する必要があるため、半導体装置１０，４０の生産性が低下してしまうという問題があった。   Further, when the shield cases 36 and 44 are used, it is necessary to electrically connect the shield cases 36 and 44 prepared for each of the semiconductor devices 10 and 40 and the ground terminals 16 and 42 with solder. There was a problem that the productivity of 10, 40 was lowered.

そこで本発明は、上述した問題点に鑑みなされたものであり、小型化ができると共に、生産性を向上することのできる半導体装置及びその製造方法を提供することを目的とする。   The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that can be reduced in size and improved in productivity and a method for manufacturing the same.

上記課題を解決するために本発明では、次に述べる各手段を講じたことを特徴とするものである。   In order to solve the above-mentioned problems, the present invention is characterized by the following measures.

請求項１記載の発明では、基板と、該基板に設けられたグラウンド端子と、前記基板に実装された少なくとも１つの電子部品とを備えた半導体装置において、前記グラウンド端子が露出された状態で前記少なくとも１つの電子部品を覆う樹脂と、該樹脂の表面に設けられ、前記グラウンド端子と電気的に接続された金属層とを設けたことを特徴とする半導体装置により、解決できる。   In the invention according to claim 1, in a semiconductor device comprising a substrate, a ground terminal provided on the substrate, and at least one electronic component mounted on the substrate, the ground terminal is exposed in the state. This can be solved by a semiconductor device comprising a resin covering at least one electronic component and a metal layer provided on the surface of the resin and electrically connected to the ground terminal.

上記発明によれば、樹脂の表面にグラウンド端子と電気的に接続される金属層を設けることにより、シールドケースを用いた従来の半導体装置と比較して、半導体装置を小型化することができる。   According to the above invention, by providing the metal layer electrically connected to the ground terminal on the surface of the resin, the semiconductor device can be reduced in size as compared with the conventional semiconductor device using the shield case.

請求項２記載の発明では、前記樹脂は、トランスファーモールド樹脂であることを特徴とする請求項１に記載の半導体装置により、解決できる。   According to a second aspect of the invention, the resin can be solved by the semiconductor device according to the first aspect, wherein the resin is a transfer mold resin.

上記発明によれば、樹脂としてトランスファーモールド樹脂を用いることで、ポッティング法による樹脂を用いた従来の半導体装置と比較して、半導体装置の生産性を向上することができる。   According to the above invention, by using the transfer mold resin as the resin, the productivity of the semiconductor device can be improved as compared with the conventional semiconductor device using the resin by the potting method.

請求項３記載の発明では、グラウンド端子を有し、少なくとも１つの電子部品が実装される基板を備えた半導体装置の製造方法において、前記少なくとも１つの電子部品が実装された基板に、前記グラウンド端子を露出した状態で前記少なくとも１つの電子部品を覆うようトランスファーモールド樹脂を形成するトランスファーモールド樹脂形成工程と、前記トランスファーモールド樹脂の表面に、前記グラウンド端子と電気的に接続される金属層を設ける金属層配設工程とを備えたことを特徴とする半導体装置の製造方法により、解決できる。   According to a third aspect of the present invention, in the method of manufacturing a semiconductor device having a ground terminal and having a substrate on which at least one electronic component is mounted, the ground terminal is mounted on the substrate on which the at least one electronic component is mounted. A transfer mold resin forming step of forming a transfer mold resin so as to cover the at least one electronic component in a state of exposing the metal, and a metal for providing a metal layer electrically connected to the ground terminal on the surface of the transfer mold resin This can be solved by a method for manufacturing a semiconductor device comprising a layer disposing step.

上記発明によれば、トランスファーモールド樹脂の表面にグラウンド端子と電気的に接続される金属層を設けることで、シールドケースを用いた従来の半導体装置と比較して、半導体装置を小型化することができる。また、トランスファーモールド樹脂は、複数の半導体装置に対して一括して樹脂を形成することが可能なため、トランスファーモールド樹脂に覆われた複数の半導体装置に対して一括して金属層を設けることで、半導体装置の生産性を向上させることができる。   According to the above invention, by providing the metal layer electrically connected to the ground terminal on the surface of the transfer mold resin, the semiconductor device can be downsized as compared with the conventional semiconductor device using the shield case. it can. In addition, since transfer molding resin can form a resin on a plurality of semiconductor devices at once, by providing a metal layer on a plurality of semiconductor devices covered with transfer molding resin at once. The productivity of the semiconductor device can be improved.

本発明によれば、小型化ができると共に、生産性を向上させることのできる半導体装置及びその製造方法を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, while being able to reduce in size, the semiconductor device which can improve productivity, and its manufacturing method can be provided.

次に、図面に基づいて本発明の実施例を説明する。
（実施例）
始めに、図３及び図４を参照して、本発明の実施例による半導体装置５０について説明する。図３は、本発明の本実施例による半導体装置の斜視図であり、図４は、図３に示した半導体装置のＡ−Ａ線方向の断面図である。なお、図３において、Ｗはグラウンド端子５７の幅（以下、「幅Ｗ」とする）、Ｌ１はグラウンド端子５７の長さ（以下、「長さＬ１」とする）、Ｊは金属層７７の厚さ（以下、「厚さＪ」とする）をそれぞれ示している。また、図４に示したＨ４は、半導体装置５０の高さ（以下、「高さＨ４」とする）、Ｋは基材５２の上面５２Ａを基準とした際のトランスファーモールド樹脂７５の厚さ（以下、「厚さＫ」とする）をそれぞれ示している。 Next, embodiments of the present invention will be described with reference to the drawings.
(Example)
First, a semiconductor device 50 according to an embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a perspective view of a semiconductor device according to this embodiment of the present invention, and FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. In FIG. 3, W is the width of the ground terminal 57 (hereinafter referred to as “width W”), L 1 is the length of the ground terminal 57 (hereinafter referred to as “length L 1”), and J is the metal layer 77. Each thickness (hereinafter referred to as “thickness J”) is shown. 4 is the height of the semiconductor device 50 (hereinafter referred to as “height H4”), and K is the thickness of the transfer mold resin 75 with respect to the upper surface 52A of the substrate 52 (see FIG. 4). Hereinafter, “thickness K” is shown.

半導体装置５０は、大略すると基板５１と、個別部品６７と、半導体チップ７０と、トランスファーモールド樹脂７５と、金属層７７とを有した構成とされている。基板５１は、大略すると基材５２と、貫通ビア５３と、第１の接続部５５と、第２の接続部５６と、グラウンド端子５７と、絶縁層５９と、配線６１と、ソルダーレジスト６３と、はんだボール６５とを有した構成とされている。貫通ビア５３は、基材５２を貫通するように設けられている。貫通ビア５３は、第１及び第２の接続部５５，５６と配線６１との間を電気的に接続するためのものである。   The semiconductor device 50 is roughly configured to include a substrate 51, individual components 67, a semiconductor chip 70, a transfer mold resin 75, and a metal layer 77. In short, the substrate 51 includes a base material 52, a through via 53, a first connection portion 55, a second connection portion 56, a ground terminal 57, an insulating layer 59, a wiring 61, and a solder resist 63. , And a solder ball 65. The through via 53 is provided so as to penetrate the base material 52. The through via 53 is for electrically connecting the first and second connecting portions 55 and 56 and the wiring 61.

第１及び第２の接続部５５，５６は、それぞれ貫通ビア５３と電気的に接続された状態で基材５２の上面５２Ａに設けられている。第１の接続部５５は、ワイヤ７４を介して半導体チップ７５と電気的に接続されるものである。ワイヤ７４には、例えば、Ａｕ、Ａｌ等を用いることができる。また、第２の接続部５６は、個別部品６７と電気的に接続されるものである。   The first and second connection portions 55 and 56 are provided on the upper surface 52 </ b> A of the base material 52 in a state of being electrically connected to the through via 53. The first connection portion 55 is electrically connected to the semiconductor chip 75 via the wire 74. For the wire 74, for example, Au, Al, or the like can be used. Further, the second connection portion 56 is electrically connected to the individual component 67.

グラウンド端子５７は、グラウンド電位とされた導体である。グラウンド端子５７の上面は、トランスファーモールド樹脂７５に形成された切欠き部７８により露出されている。グラウンド端子５７は、基材５２の外周縁近傍に位置する基材５２の上面５２Ａに２つ設けられている。グラウンド端子５７は、例えば、幅Ｗを０．３ｍｍ、長さＬ１を０．３ｍｍとすることができる。   The ground terminal 57 is a conductor having a ground potential. The upper surface of the ground terminal 57 is exposed by a notch 78 formed in the transfer mold resin 75. Two ground terminals 57 are provided on the upper surface 52 </ b> A of the base material 52 located in the vicinity of the outer peripheral edge of the base material 52. For example, the ground terminal 57 can have a width W of 0.3 mm and a length L1 of 0.3 mm.

絶縁層５９は、第１及び第２の接続部５５，５６間を隔てるように基材５２の上面５２Ａに設けられている。配線６１は、接続パッド６２を有した構成とされている。接続パッド６２は、はんだボール６５が接続されるものである。配線６１は、基材５２の下面５２Ｂに貫通ビア５３と接続されるよう設けられている。ソルダーレジスト６３は、接続パッド６２を露出すると共に、接続パッド６２以外の配線６１を覆うよう基材５２の下面５２Ｂ側に設けられている。はんだボール６５は、接続パッド６２に配設されている。はんだボール６５は、半導体装置５０をマザーボード等の他の基板に接続するための外部接続端子である。   The insulating layer 59 is provided on the upper surface 52 </ b> A of the base material 52 so as to separate the first and second connection portions 55 and 56. The wiring 61 is configured to have a connection pad 62. The connection pad 62 is connected to the solder ball 65. The wiring 61 is provided on the lower surface 52 </ b> B of the base material 52 so as to be connected to the through via 53. The solder resist 63 is provided on the lower surface 52 </ b> B side of the base material 52 so as to expose the connection pads 62 and cover the wiring 61 other than the connection pads 62. The solder ball 65 is disposed on the connection pad 62. The solder ball 65 is an external connection terminal for connecting the semiconductor device 50 to another substrate such as a mother board.

電子部品である個別部品６７は、電極６８を有した構成とされている。電極６８は、はんだペースト６９により第２の接続部５６と電気的に接続されている。個別部品６７は、例えば、トランジスタ、ダイオード、抵抗、コンデンサ等の基本となる電気的素子の１つの機能が１つの部品となっているものである（「ディスクリート部品」ともいう）。   The individual component 67 which is an electronic component is configured to have an electrode 68. The electrode 68 is electrically connected to the second connection portion 56 by a solder paste 69. The individual component 67 is a component in which one function of basic electrical elements such as a transistor, a diode, a resistor, and a capacitor is one component (also referred to as “discrete component”).

電子部品である半導体チップ７０は、半導体チップ本体７１と、電極パッド７２とを有した構成とされている。電極パッド７２が設けられていない側の半導体チップ本体７１は、接着剤７３により基材５２上に接着されている。半導体チップ７０は、電極パッド７２と第１の接続部５５との間を接続するワイヤ７４により基板５１と電気的に接続されている。   A semiconductor chip 70 that is an electronic component has a semiconductor chip body 71 and an electrode pad 72. The semiconductor chip body 71 on the side where the electrode pads 72 are not provided is bonded onto the base material 52 with an adhesive 73. The semiconductor chip 70 is electrically connected to the substrate 51 by a wire 74 that connects the electrode pad 72 and the first connection portion 55.

なお、請求項に記載の「少なくとも１つの電子部品」とは、本実施例の個別部品６７及び半導体チップ７０のことである。   Note that “at least one electronic component” described in the claims refers to the individual component 67 and the semiconductor chip 70 of the present embodiment.

トランスファーモールド樹脂７５は、グラウンド端子５７を露出させた状態で、基板５１に実装された個別部品６７及び半導体チップ７０を覆う（封止する）よう基材５２の上面５２Ａ側に設けられている。トランスファーモールド樹脂７５には、グラウンド端子５７の上面を露出する切欠き部７８が形成されている。また、トランスファーモールド樹脂７５の上面７５Ａは、平坦な面とされている。   The transfer mold resin 75 is provided on the upper surface 52A side of the base member 52 so as to cover (seal) the individual components 67 and the semiconductor chip 70 mounted on the substrate 51 with the ground terminal 57 exposed. The transfer mold resin 75 has a notch 78 that exposes the upper surface of the ground terminal 57. The upper surface 75A of the transfer mold resin 75 is a flat surface.

このように、トランスファーモールド樹脂７５の上面７５Ａを平坦な面とすることで、自動部品装着機により半導体装置５０をマザーボート等の他の基板に実装する際、自動部品装着機のハンドリング性能を向上させて、半導体装置５０をマザーボート等の他の基板に対して精度良く実装することができる。また、トランスファーモールド樹脂７５の厚さＫは、トランスファーモールド樹脂７５によりワイヤ７４を保護することの可能な厚さとすることができる。トランスファーモールド樹脂７５の厚さＫは、例えば、０．８ｍｍとすることができる。トランスファーモールド樹脂７５には、例えば、エポキシ系樹脂を用いることができる。   Thus, by making the upper surface 75A of the transfer mold resin 75 flat, the handling performance of the automatic component mounting machine is improved when the semiconductor device 50 is mounted on another board such as a mother boat by the automatic component mounting machine. As a result, the semiconductor device 50 can be accurately mounted on another substrate such as a mother board. Further, the thickness K of the transfer mold resin 75 can be set to a thickness capable of protecting the wire 74 by the transfer mold resin 75. The thickness K of the transfer mold resin 75 can be set to 0.8 mm, for example. For the transfer mold resin 75, for example, an epoxy resin can be used.

なお、トランスファーモールド樹脂７５とは、トランスファーモールド法により形成された樹脂のことである。トランスファーモールド法とは、封止したい部材（本実施例の場合、個別部品６７及び半導体チップ７０が配設された基板５１）を金型成型機にセットし、温度を上げて流動性を持たせたモールド樹脂に圧力をかけて、金型内に流し込んで（圧送）、金型の形に樹脂を成型する方法である。このようなトランスファーモールド法により形成されたトランスファーモールド樹脂７５で、個別部品６７及び半導体チップ７０の封止を行うことで、ポッティング樹脂を用いて封止した場合と比較して、封止工程に要する時間を短縮して、半導体装置５０の生産性を向上させることができる。   The transfer mold resin 75 is a resin formed by a transfer mold method. In the transfer molding method, a member to be sealed (in the case of the present embodiment, the substrate 51 on which the individual component 67 and the semiconductor chip 70 are disposed) is set in a mold molding machine, and the temperature is raised to give fluidity. In this method, pressure is applied to the mold resin, which is poured into the mold (pressure feeding), and the resin is molded into the mold shape. By sealing the individual components 67 and the semiconductor chip 70 with the transfer mold resin 75 formed by such a transfer mold method, the sealing process is required as compared with the case of sealing with potting resin. The time can be shortened and the productivity of the semiconductor device 50 can be improved.

金属層７７は、トランスファーモールド樹脂７５の上面７５Ａと、切欠き部７８に対応するトランスファーモールド樹脂７５の面と、切欠き部７８により露出されたグラウンド端子５７の上面とに設けられている。金属層７７は、グラウンド端子５７と電気的に接続されており、従来のシールドケース３６，４４に相当する機能（シールド効果）を有するものである。   The metal layer 77 is provided on the upper surface 75 </ b> A of the transfer mold resin 75, the surface of the transfer mold resin 75 corresponding to the notch 78, and the upper surface of the ground terminal 57 exposed by the notch 78. The metal layer 77 is electrically connected to the ground terminal 57 and has a function (shield effect) corresponding to the conventional shield cases 36 and 44.

金属層７７は、例えば、スパッタ法、真空蒸着法、めっき法等により形成することができる。また、スパッタ法、真空蒸着法を用いる場合、金属層７７の材料としては、例えば、Ａｌを用いることができる。めっき法を用いる場合には、金属層７７の材料としては、例えば、Ｃｕを用いることができる。また、金属層７７の厚さＪは、例えば、５μｍ〜４０μｍとすることができる。なお、請求項に記載の「樹脂の表面」とは、本実施例の場合、トランスファーモールド樹脂７５の上面７５Ａ、及び切欠き部７８に対応するトランスファーモールド樹脂７５の面のことである（以下、「トランスファーモールド樹脂７５の表面」とする）。   The metal layer 77 can be formed by, for example, a sputtering method, a vacuum evaporation method, a plating method, or the like. Moreover, when using a sputtering method and a vacuum evaporation method, as a material of the metal layer 77, Al can be used, for example. When the plating method is used, as the material of the metal layer 77, for example, Cu can be used. Further, the thickness J of the metal layer 77 can be set to, for example, 5 μm to 40 μm. In the present embodiment, the “resin surface” in the claims refers to the upper surface 75A of the transfer mold resin 75 and the surface of the transfer mold resin 75 corresponding to the notch 78 (hereinafter referred to as “the surface of the resin mold”). “The surface of the transfer mold resin 75”).

このように、グラウンド端子５７を露出した状態で、基板５１に実装された個別部品６７及び半導体チップ７０を覆うようトランスファーモールド樹脂７５を設け、トランスファーモールド樹脂７５の表面にグラウンド端子５７と接続される金属層７７を設けてシールド効果を得る構成としたことにより、ポッティング樹脂３５とシールドケース３６，４４とを併用した従来の半導体装置１０，４０よりも半導体装置５０の高さＨ４を小さくして、半導体装置５０を小型化することができる。また、従来の半導体装置１０，４０のように、はんだを用いてグラウンド端子５７と金属層７７との間を接続する必要がないため、製造工程を簡略化して、半導体装置５０の生産性を向上させることができる。   In this way, with the ground terminal 57 exposed, the transfer mold resin 75 is provided so as to cover the individual components 67 and the semiconductor chip 70 mounted on the substrate 51, and is connected to the ground terminal 57 on the surface of the transfer mold resin 75. By providing the metal layer 77 to obtain a shielding effect, the height H4 of the semiconductor device 50 is made smaller than the conventional semiconductor devices 10 and 40 using the potting resin 35 and the shielding cases 36 and 44 in combination, The semiconductor device 50 can be reduced in size. Further, unlike the conventional semiconductor devices 10 and 40, since it is not necessary to connect the ground terminal 57 and the metal layer 77 using solder, the manufacturing process is simplified and the productivity of the semiconductor device 50 is improved. Can be made.

なお、グラウンド端子５７には、例えば、基板５１に設けられたインデックスマーク（図示せず）やワイヤボンディング用の認識マーク（図示せず）をグラウンド電位としたものを用いることができる。インデックスマーク（図示せず）は、個別部品６７や半導体チップ７０を基板５１に実装する際に必要な位置合わせ用のマークである。このように、インデックスマークや認識マークをグラウンド端子５７として流用することで、基材５２上にグラウンド端子５７を配設するための領域を別途設ける必要がなくなり、半導体装置５０をさらに小型化することができる。また、金属層７７には、例えば、金属箔を用いても良い。この場合には、トランスファーモールド樹脂７５の表面に、グラウンド端子５７と電気的に接続される金属箔を導電性接着剤により貼り付けることで、本実施例と同様な効果を得ることができる。   As the ground terminal 57, for example, an index mark (not shown) provided on the substrate 51 or a wire bonding recognition mark (not shown) with a ground potential can be used. The index mark (not shown) is an alignment mark necessary when mounting the individual component 67 or the semiconductor chip 70 on the substrate 51. Thus, by using the index mark or the recognition mark as the ground terminal 57, it is not necessary to separately provide a region for disposing the ground terminal 57 on the base material 52, and the semiconductor device 50 can be further downsized. Can do. For example, a metal foil may be used for the metal layer 77. In this case, the same effect as that of this embodiment can be obtained by attaching a metal foil electrically connected to the ground terminal 57 to the surface of the transfer mold resin 75 with a conductive adhesive.

図５は、本実施例の基板が製造される基材の平面図である。なお、図５において、Ｅは基板５１が形成される領域（以下、「基板形成領域Ｅ」とする）を示している。図５に示すように、基板５１は、複数の基板形成領域Ｅを有した板状の基材５２に形成される。   FIG. 5 is a plan view of a base material on which the substrate of this embodiment is manufactured. In FIG. 5, E indicates a region where the substrate 51 is formed (hereinafter referred to as “substrate forming region E”). As shown in FIG. 5, the substrate 51 is formed on a plate-like base material 52 having a plurality of substrate formation regions E.

次に、図６乃至図１３を参照して、めっき法により金属層７７を形成する場合を例に挙げて、本実施例の半導体装置５０の製造方法について説明する。図６乃至図１３は、本実施例の半導体装置の製造工程を示した図である。なお、図６乃至図１３において、Ｄは半導体装置５０を個片化する際にダイサーが基材５２を切断する位置（以下、「ダイシング位置Ｄ」とする）を示している。また、図６乃至図１３において、図４に示した半導体装置５０と同一構成部分には同一符号を付す。   Next, with reference to FIGS. 6 to 13, a method for manufacturing the semiconductor device 50 of the present embodiment will be described by taking as an example the case where the metal layer 77 is formed by plating. 6 to 13 are views showing a manufacturing process of the semiconductor device of this embodiment. 6 to 13, D indicates a position where the dicer cuts the base material 52 when the semiconductor device 50 is separated into pieces (hereinafter referred to as “dicing position D”). 6 to 13, the same components as those of the semiconductor device 50 shown in FIG.

始めに、図６に示すように、複数の基板形成領域Ｅを有した基材５２に貫通ビア５３を形成し、続いて、基材５２の上面５２Ａに第１及び第２の接続部５５，５６とグラウンド端子用部材８１とを一度に形成する。グラウンド端子用部材８１は、ダイシング位置Ｄを境に略二等分されるような基材５２上の位置に配設されている。グラウンド端子用部材８１は、ダイサーにより基材５２を切断して半導体装置５０を個片化する際、２分割されて、２つのグラウンド端子５７となる。したがって、グラウンド端子用部材８１の長さＬ２は、グラウンド端子５７の長さＬ１の略２倍とされている。また、グラウンド端子用部材８１の幅は、グラウンド端子５７の幅Ｗと略等しい大きさとされている。続いて、基材５２の下面５２Ｂに、接続パッド６２を備えた配線６１を形成し、その後、基材５２の上面５２Ａに絶縁層５９を形成する。なお、図６に示したＦは、半導体チップ７０が配設される基材５２上の領域（以下、「半導体チップ配設領域Ｆ」とする）を示している。   First, as shown in FIG. 6, the through via 53 is formed in the base material 52 having a plurality of substrate formation regions E, and then the first and second connection portions 55, 56 and the ground terminal member 81 are formed at a time. The ground terminal member 81 is disposed at a position on the base member 52 so as to be approximately divided into two equal parts with the dicing position D as a boundary. The ground terminal member 81 is divided into two when the substrate 52 is cut by a dicer to separate the semiconductor device 50 into two ground terminals 57. Therefore, the length L2 of the ground terminal member 81 is approximately twice the length L1 of the ground terminal 57. In addition, the width of the ground terminal member 81 is approximately equal to the width W of the ground terminal 57. Subsequently, the wiring 61 including the connection pads 62 is formed on the lower surface 52 </ b> B of the base material 52, and then the insulating layer 59 is formed on the upper surface 52 </ b> A of the base material 52. In addition, F shown in FIG. 6 has shown the area | region (henceforth "semiconductor chip arrangement | positioning area | region F") on the base material 52 by which the semiconductor chip 70 is arrange | positioned.

次に、図７に示すように、電子部品である個別部品６７及び半導体チップ７０を基板５１に実装する。個別部品６７の電極６８は、はんだペースト６９により第２の接続部５６と電気的に接続される。半導体チップ７０は、接着剤７３により基材５２上の半導体チップ配設領域Ｆに接着され、電極パッド７２と第１の接続部５５とがワイヤ７４を介して電気的に接続される。   Next, as shown in FIG. 7, the individual component 67 and the semiconductor chip 70 which are electronic components are mounted on the substrate 51. The electrode 68 of the individual component 67 is electrically connected to the second connection portion 56 by the solder paste 69. The semiconductor chip 70 is bonded to the semiconductor chip arrangement region F on the base material 52 with an adhesive 73, and the electrode pad 72 and the first connection portion 55 are electrically connected via the wire 74.

次に、図８に示すように、凸部８６を有した金型８５を、凸部８６がグラウンド端子用部材８１と接触するように基材５２上に配置させ、トランスファーモールド法により、複数の基板形成領域Ｅを有した基材５２と金型８５との間にトランスファーモールド樹脂７５を充填する。トランスファーモールド樹脂７５には、例えば、エポキシ系樹脂を用いることができる。なお、基材５２と対向する金型８５の面８５Ａは、平坦な面とされている。凸部８６は、トランスファーモールド樹脂７５にグラウンド端子用部材８１を露出する開口部８８を形成するためのものであり、グラウンド端子用部材８１と対向する凸部８６の面８６Ａは平坦な面とされている。   Next, as shown in FIG. 8, a mold 85 having a convex portion 86 is arranged on the base material 52 so that the convex portion 86 contacts the ground terminal member 81, and a plurality of transfer mold methods are used. A transfer mold resin 75 is filled between the base material 52 having the substrate formation region E and the mold 85. For the transfer mold resin 75, for example, an epoxy resin can be used. The surface 85A of the mold 85 that faces the substrate 52 is a flat surface. The convex portion 86 is for forming an opening 88 exposing the ground terminal member 81 in the transfer mold resin 75, and the surface 86A of the convex portion 86 facing the ground terminal member 81 is a flat surface. ing.

その後、図９に示すように、金型８５を取り外すことで、上面７５Ａが平坦な面とされ、かつグラウンド端子用部材８１を露出する開口部８８を有したトランスファーモールド樹脂７５が形成される（トランスファーモールド樹脂形成工程）。図１４は、図９に示した構造体を平面視した図である。   Thereafter, as shown in FIG. 9, by removing the mold 85, the transfer mold resin 75 having an upper surface 75 </ b> A having a flat surface and an opening 88 exposing the ground terminal member 81 is formed ( Transfer mold resin forming step). 14 is a plan view of the structure shown in FIG.

このようなトランスファーモールド法を用いることで、複数の基板形成領域Ｅに存在する個別部品６７及び半導体チップ７０をトランスファーモールド樹脂７５により一括して封止することができ、ポッティング法を用いた従来の半導体装置１０，４０と比較して、半導体装置５０の生産性を向上させることができる。   By using such a transfer molding method, the individual components 67 and the semiconductor chips 70 existing in the plurality of substrate forming regions E can be collectively sealed with the transfer mold resin 75, and the conventional potting method is used. Compared with the semiconductor devices 10 and 40, the productivity of the semiconductor device 50 can be improved.

次に、図１０に示すように、基材５２の下面５２Ｂ側に配線６１を覆うレジスト層９１を形成する。レジスト層９１は、めっき法により金属層７７を形成した際、配線６１にめっき膜が形成されることを防止するための保護層である。なお、金属層７７をスパッタ法、真空蒸着法、金属箔の貼り付け等により形成する場合には、レジスト層９１を設ける必要はない。   Next, as illustrated in FIG. 10, a resist layer 91 that covers the wiring 61 is formed on the lower surface 52 </ b> B side of the substrate 52. The resist layer 91 is a protective layer for preventing a plating film from being formed on the wiring 61 when the metal layer 77 is formed by a plating method. Note that when the metal layer 77 is formed by sputtering, vacuum deposition, metal foil bonding, or the like, the resist layer 91 is not necessarily provided.

次に、図１１に示すように、トランスファーモールド樹脂７５の表面に対してデスミア処理及びパラジウム活性化処理等の前処理を行った後、無電解めっき法により、無電解めっき膜（図示せず）を析出させ、続いて、無電解めっき膜をシード層として電解めっき法により、電解めっき膜（図示せず）を析出、成長させて、グラウンド端子用部材８１の上面及びトランスファーモールド樹脂７５の表面に無電解めっき膜と電解めっき膜とよりなる金属層７７を形成する（金属層配設工程）。無電解めっき膜としては、例えば、Ｃｕ膜を用いることができ、無電解めっき膜の厚さは、例えば、０．２μｍとすることができる。また、電解めっき膜としては、例えば、Ｃｕ膜を用いることができる。金属層７７の厚さＪは、例えば、５μｍ〜４０μｍとすることができる。レジスト層９１は、電解めっき膜形成後に、レジスト剥離液により除去される。図１５は、図１１に示した構造体を平面視した図である。   Next, as shown in FIG. 11, after the surface of the transfer mold resin 75 is subjected to pretreatment such as desmear treatment and palladium activation treatment, an electroless plating film (not shown) is formed by electroless plating. Then, an electroplating film (not shown) is deposited and grown by electroplating using the electroless plating film as a seed layer, and is formed on the upper surface of the ground terminal member 81 and the surface of the transfer mold resin 75. A metal layer 77 composed of an electroless plating film and an electrolytic plating film is formed (metal layer disposing step). For example, a Cu film can be used as the electroless plating film, and the thickness of the electroless plating film can be set to 0.2 μm, for example. Further, as the electrolytic plating film, for example, a Cu film can be used. The thickness J of the metal layer 77 can be set to 5 μm to 40 μm, for example. The resist layer 91 is removed by a resist stripping solution after the electrolytic plating film is formed. 15 is a plan view of the structure shown in FIG.

このように、グラウンド端子用部材８１を露出した状態で、複数の基板形成領域Ｅに対し一括して形成されたトランスファーモールド樹脂７５の表面に、グラウンド端子用部材８１と電気的に接続される金属層７７を設けることで、従来の半導体装置１０，４０で行っていたグラウンド端子１６，４２とシールドケース３６，４４とをはんだ付けする作業が不要となり、半導体装置５０の生産性を向上させることができる。また、金属層７７をトランスファーモールド樹脂７５に直接設けることで、従来の半導体装置１０，４０よりも半導体装置５０の高さＨ４（図１３参照）を小さくして、半導体装置５０を小型化することができる。   In this way, the metal electrically connected to the ground terminal member 81 on the surface of the transfer mold resin 75 formed in a lump for the plurality of substrate formation regions E with the ground terminal member 81 exposed. By providing the layer 77, the work of soldering the ground terminals 16 and 42 and the shield cases 36 and 44 performed in the conventional semiconductor devices 10 and 40 becomes unnecessary, and the productivity of the semiconductor device 50 can be improved. it can. Further, by providing the metal layer 77 directly on the transfer mold resin 75, the height H4 (see FIG. 13) of the semiconductor device 50 can be made smaller than the conventional semiconductor devices 10 and 40, and the semiconductor device 50 can be downsized. Can do.

次に、図１２に示すように、接続パッド６２を露出させると共に、接続パッド６２以外の配線６１を覆うソルダーレジスト６３を形成し、続いて、接続パッド６２にはんだボール６５を配設する。その後、図１３に示すように、ダイサーによりダイシング位置Ｄに沿って基材５２を切断して、半導体装置５０を個片化することで、複数の半導体装置５０が製造される。図１６は、個片化された半導体装置の平面図である。この際、図１６に示すように、グラウンド端子用部材８１は、ダイサーにより略二等分され、１つの半導体装置５０に対して２つのグラウンド端子５７が形成される。また、グラウンド端子５７の上方には、開口部８８が２分割されることで切欠き部７８が形成される。   Next, as shown in FIG. 12, the connection pads 62 are exposed, and a solder resist 63 that covers the wirings 61 other than the connection pads 62 is formed. Subsequently, solder balls 65 are disposed on the connection pads 62. Thereafter, as shown in FIG. 13, a plurality of semiconductor devices 50 are manufactured by cutting the base material 52 along the dicing position D by a dicer and separating the semiconductor devices 50 into individual pieces. FIG. 16 is a plan view of a separated semiconductor device. At this time, as shown in FIG. 16, the ground terminal member 81 is approximately bisected by the dicer, and two ground terminals 57 are formed for one semiconductor device 50. Further, a notch 78 is formed above the ground terminal 57 by dividing the opening 88 into two.

以上説明したように、グラウンド端子５７を露出すると共に、基板５１上に実装された個別部品６７及び半導体チップ７０を覆うようトランスファーモールド樹脂７５を設け、トランスファーモールド樹脂７５の表面にグラウンド端子５７と電気的に接続される金属層７７を設けることで、半導体装置５０を小型化できると共に、生産性を向上させることができる。   As described above, the ground terminal 57 is exposed, and the transfer mold resin 75 is provided so as to cover the individual component 67 and the semiconductor chip 70 mounted on the substrate 51, and the ground terminal 57 and the electricity are provided on the surface of the transfer mold resin 75. By providing the metal layer 77 to be connected to the semiconductor device 50, the semiconductor device 50 can be reduced in size and productivity can be improved.

以上、本発明の好ましい実施例について詳述したが、本発明はかかる特定の実施形態に限定されるものではなく、特許請求の範囲内に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。なお、本実施例では、２つの基板形成領域Ｅに亘って、グラウンド端子用部材８１を設けたが、４つの基板形成領域Ｅに亘るよう、基板形成領域Ｅの角部にグラウンド端子用部材８１を設けても良い。また、基板形成領域Ｅ毎に、基板形成領域Ｅの外形よりも内側の領域にグラウンド端子５７を設けた構成としても良い。図１７は、トランスファーモールド樹脂の上面及び側面に金属層を設けた半導体装置の断面図である。さらに、図１７に示した半導体装置１００ように、トランスファーモールド樹脂７５を形成後、基材５２を切断して、トランスファーモールド樹脂７５の上面及び側面に金属層７７を設けても良い。また、本発明は、基材５２の側面にグラウンド端子を設けた半導体装置にも適用可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims. Deformation / change is possible. In this embodiment, the ground terminal member 81 is provided over the two substrate formation regions E. However, the ground terminal member 81 is provided at the corner of the substrate formation region E so as to extend over the four substrate formation regions E. May be provided. Further, for each substrate formation region E, a ground terminal 57 may be provided in a region inside the outer shape of the substrate formation region E. FIG. 17 is a cross-sectional view of a semiconductor device in which a metal layer is provided on the upper surface and side surfaces of the transfer mold resin. Further, as in the semiconductor device 100 shown in FIG. 17, after forming the transfer mold resin 75, the base material 52 may be cut and the metal layer 77 may be provided on the upper surface and the side surface of the transfer mold resin 75. The present invention is also applicable to a semiconductor device in which a ground terminal is provided on the side surface of the substrate 52.

本発明によれば、小型化ができると共に、生産性を向上させることのできる半導体装置及びその製造方法に適用できる。   The present invention can be applied to a semiconductor device and a manufacturing method thereof that can be downsized and improve productivity.

シールドケースを備えた従来の半導体装置の断面図（その１）である。It is sectional drawing (the 1) of the conventional semiconductor device provided with the shield case. シールドケースを備えた従来の半導体装置の断面図（その２）である。It is sectional drawing (the 2) of the conventional semiconductor device provided with the shield case. 本発明の本実施例による半導体装置の斜視図である。1 is a perspective view of a semiconductor device according to an embodiment of the present invention. 図３に示した半導体装置のＡ−Ａ線方向の断面図である。FIG. 4 is a cross-sectional view of the semiconductor device shown in FIG. 3 in the AA line direction. 本実施例の基板が製造される基材の平面図である。It is a top view of the base material with which the board | substrate of a present Example is manufactured. 本実施例の半導体装置の製造工程を示した図（その１）である。It is FIG. (The 1) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その２）である。It is FIG. (The 2) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その３）である。It is FIG. (The 3) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その４）である。It is FIG. (The 4) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その５）である。It is FIG. (The 5) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その６）である。It is FIG. (The 6) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その７）である。It is FIG. (The 7) which showed the manufacturing process of the semiconductor device of a present Example. 本実施例の半導体装置の製造工程を示した図（その８）である。It is FIG. (The 8) which showed the manufacturing process of the semiconductor device of a present Example. 図９に示した構造体を平面視した図である。FIG. 10 is a plan view of the structure shown in FIG. 9. 図１１に示した構造体を平面視した図である。It is the figure which planarly viewed the structure shown in FIG. 個片化された半導体装置の平面図である。It is a top view of the semiconductor device separated into pieces. トランスファーモールド樹脂の上面及び側面に金属層を設けた半導体装置の断面図である。It is sectional drawing of the semiconductor device which provided the metal layer on the upper surface and side surface of transfer mold resin.

符号の説明Explanation of symbols

１０，４０，５０，１００ 半導体装置
１１，５１ 基板
１２，４１，５２ 基材
１３，５３ 貫通ビア
１４，１５ 接続部
１６，４２，５７ グラウンド端子
１７，５９ 絶縁層
２１，６１ 配線
２２，６２ 接続パッド
２３，６３ ソルダーレジスト
２４，７３ 接着剤
２５，６５ はんだボール
２６，６７ 個別部品
２７，３７，６９ はんだペースト
３１，７０ 半導体チップ
３３，７２ 電極パッド
３４ 金ワイヤ
３５ ポッティング樹脂
３６，４４ シールドケース
５２Ａ，７５Ａ 上面
５２Ｂ 下面
５５ 第１の接続部
５６ 第２の接続部
６８ 電極
７１ 半導体チップ本体
７４ ワイヤ
７５ トランスファーモールド樹脂
７７ 金属層
７８ 切欠き部
８１ グラウンド端子用部材
８５ 金型
８５Ａ，８６Ａ 面
８６ 凸部
８８ 開口部
９１ レジスト層
Ｃ１，Ｃ２ 隙間
Ｄ ダイシング位置
Ｅ 基板形成領域
Ｆ 半導体チップ配設領域
Ｈ１〜Ｈ４ 高さ
Ｊ，Ｋ 厚さ
Ｌ１，Ｌ２ 長さ
Ｗ 幅 10, 40, 50, 100 Semiconductor device 11, 51 Substrate 12, 41, 52 Base material 13, 53 Through-via 14, 15, Connection portion 16, 42, 57 Ground terminal 17, 59 Insulating layer 21, 61 Wiring 22, 62 Connection Pad 23, 63 Solder resist 24, 73 Adhesive 25, 65 Solder ball 26, 67 Individual parts 27, 37, 69 Solder paste 31, 70 Semiconductor chip 33, 72 Electrode pad 34 Gold wire 35 Potting resin 36, 44 Shield case 52A , 75A Upper surface 52B Lower surface 55 First connection portion 56 Second connection portion 68 Electrode 71 Semiconductor chip body 74 Wire 75 Transfer mold resin 77 Metal layer 78 Notch portion 81 Ground terminal member 85 Mold 85A, 86A Surface 86 Convex Part 88 Opening 91 Resist C1, C2 gap D dicing position E substrate forming region F semiconductor chip formation regions H1~H4 height J, K thickness L1, L2 length W width

Claims (3)

基板と、
該基板に設けられたグラウンド端子と、
前記基板に実装された少なくとも１つの電子部品とを備えた半導体装置において、
前記グラウンド端子が露出された状態で前記少なくとも１つの電子部品を覆う樹脂と、
該樹脂の表面に設けられ、前記グラウンド端子と電気的に接続された金属層とを設けたことを特徴とする半導体装置。 A substrate,
A ground terminal provided on the substrate;
In a semiconductor device comprising at least one electronic component mounted on the substrate,
A resin covering the at least one electronic component with the ground terminal exposed;
A semiconductor device comprising a metal layer provided on a surface of the resin and electrically connected to the ground terminal. 前記樹脂は、トランスファーモールド樹脂であることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the resin is a transfer mold resin. グラウンド端子を有し、少なくとも１つの電子部品が実装される基板を備えた半導体装置の製造方法において、
前記少なくとも１つの電子部品が実装された基板に、前記グラウンド端子を露出した状態で前記少なくとも１つの電子部品を覆うようトランスファーモールド樹脂を形成するトランスファーモールド樹脂形成工程と、
前記トランスファーモールド樹脂の表面に、前記グラウンド端子と電気的に接続される金属層を設ける金属層配設工程とを備えたことを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device having a ground terminal and having a substrate on which at least one electronic component is mounted,
A transfer mold resin forming step of forming a transfer mold resin on the substrate on which the at least one electronic component is mounted so as to cover the at least one electronic component with the ground terminal exposed;
A method of manufacturing a semiconductor device, comprising: a metal layer disposing step of providing a metal layer electrically connected to the ground terminal on the surface of the transfer mold resin.
JP2004351343A 2004-12-03 2004-12-03 Semiconductor device and its manufacturing method Pending JP2006165109A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114291A (en) * 2008-11-07 2010-05-20 Renesas Technology Corp Electronic component having shield, and method for manufacturing the same
CN106783713A (en) * 2015-11-20 2017-05-31 环维电子(上海)有限公司 The manufacture of SIP modules, pick-up method and equipment and EMI electromagnetic shielding layer manufacturing methods
CN109524368A (en) * 2017-09-19 2019-03-26 东芝存储器株式会社 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280468A (en) * 2001-03-16 2002-09-27 Matsushita Electric Ind Co Ltd High frequency module and its manufacturing method
JP2004172176A (en) * 2002-11-18 2004-06-17 Taiyo Yuden Co Ltd Circuit module

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002280468A (en) * 2001-03-16 2002-09-27 Matsushita Electric Ind Co Ltd High frequency module and its manufacturing method
JP2004172176A (en) * 2002-11-18 2004-06-17 Taiyo Yuden Co Ltd Circuit module

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010114291A (en) * 2008-11-07 2010-05-20 Renesas Technology Corp Electronic component having shield, and method for manufacturing the same
US9001528B2 (en) 2008-11-07 2015-04-07 Renesas Electronics Corporation Shielded electronic components and method of manufacturing the same
CN106783713A (en) * 2015-11-20 2017-05-31 环维电子(上海)有限公司 The manufacture of SIP modules, pick-up method and equipment and EMI electromagnetic shielding layer manufacturing methods
CN109524368A (en) * 2017-09-19 2019-03-26 东芝存储器株式会社 Semiconductor device
JP2019054216A (en) * 2017-09-19 2019-04-04 東芝メモリ株式会社 Semiconductor device
CN109524368B (en) * 2017-09-19 2022-11-15 铠侠股份有限公司 Semiconductor device with a plurality of semiconductor chips

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