JP2006033197A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit for reducing variations in the oscillation frequency of a voltage-controlled oscillator, by suppressing variations in the resistance value of a voltage-current conversion circuit. <P>SOLUTION: The voltage-current conversion circuit suppresses variations in a process by incorporating a variable resistance circuit 4, prevents the influence of the parasitic capacity of the external resistance terminal, and can respond in a high band, without being affected by the influence of a PLL-loop band. A CMOS variable resistor is used in the variable resistance circuit 4 for continuously adjusting the resistance value. And the resistance value can be adjusted more precisely by using a constant current source. A lock range, corresponding to each worst condition, is taken out by adding a limit circuit 5, a control current value to be supplied according to the fluctuations by the variations of the process of a VCO ring by adding a current ratio adjustment circuit 6 is adjusted by changing a current ratio, and a fixed VCO gain is realized, regardless of the fluctuations of the process. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL circuit, and more particularly to a PLL circuit including a voltage-controlled oscillator in which a voltage-current conversion circuit that requires a wide oscillation frequency range is used.

  FIG. 8 is a block diagram showing a basic configuration of a conventional PLL circuit. 1 is a phase comparator, 2 is an LPF, and 3 is a voltage controlled oscillator (VCO). Each operation of the PLL block will be described. The reference signal Fr and the output signal Fv of the voltage controlled oscillator 3 are input to the phase comparator 1 and an error is output. Thereafter, the DC component of the signal output from the phase comparison by the LPF 2 is taken out and the control voltage VCOIN is output. By repeating these constituent loops, the output signal of the voltage controlled oscillator 3 can be accurately adjusted to the reference signal.

  FIG. 9 is a block diagram showing a basic configuration of the voltage controlled oscillator 3. The voltage-controlled oscillation is constituted by a voltage-current conversion circuit 31 that outputs a current according to a control voltage VCOIN input from the LPF 2 and a current-controlled oscillator 32 that outputs an oscillation frequency corresponding to the current.

  FIG. 10 shows a conventional example of the voltage-current conversion circuit 31. The source side of the NMOS transistor M0 to which the control voltage VCOIN input from the LPF 2 is applied to the gate is grounded via the resistor R0, and the drain side is connected to the Pch transistor M1 and the resistor R1. The sum of the current flowing through M0 and the current flowing through R1 flows through the PMOS M1, the gate voltage of M1 is applied to M2, and the current flowing through M2 is folded back by a current mirror formed by MOS transistors of M3, M4, and M5, thereby controlling the current. Control nodes PG and NG are formed. FIG. 13 shows the voltage-current conversion characteristics.

FIG. 11 shows an example of a conventional circuit of a voltage / current converter (referred to as a voltage / current converter 31 ′). The output of the operational amplifier circuit AMP having an inverting terminal as an input is given to the PMOS transistor M0, the drain side of the PMOS transistor M0 is grounded via the resistor R0, and the gate side is connected to the power source. In this circuit, the same voltage as that applied to the input terminal VCOIN is applied to both ends of the resistor R0 to generate a current at the output terminal. The current Iout flowing through M0 becomes Iout = VCOIN / R0, and a current proportional to the input voltage can be taken out.
The POS transistor M1 applies a gate voltage equal to that of the PMOS transistor M0, thereby causing a current equal to the current flowing through M0 to flow.

  FIG. 12 shows an example of a conventional circuit of a current controlled oscillator 32 constituted by a differential amplifier circuit. The current Iout input from the voltage-current converter circuit (31 or 31 ′) is turned back by a current mirror made up of M3, M4, and M5 MOS transistors to form the Pch control node PG and the Nch control node NG of the current control oscillation circuit 32, The oscillation frequency of the ring oscillator 321 composed of a differential amplifier circuit is controlled.

The following techniques are disclosed as application examples of the voltage-current converter circuit as described above.
For example, as a first technique, in a PLL circuit, a bias control voltage of an oscillation circuit gives an output of an amplifier input to one input terminal to a gate of a transistor grounded through a resistor, and a connection point between the transistor and the resistor is Some devices improve the linearity by forming a feedback loop connected to the other input terminal of the amplifier (see Patent Document 1).

As a second technique, there is a technique for eliminating variations in the resistance process of the VCO control bias circuit. In particular, Patent Document 2 discloses a technique in which fixed resistance elements are placed on a matrix, the resistance value is controlled in accordance with an external control signal, the resistance of the bias circuit is variable, and resistance process variation is suppressed. .
JP 2000-59181 A JP 2002-111490 A

  In the prior art, the oscillation frequency of the voltage controlled oscillator (VCO) of the PLL varies due to process variations, temperature variations, and power supply variations of the voltage-current conversion circuit and the current control oscillation circuit. In particular, fluctuations due to process variations become more prominent as the oscillation frequency required for the VCO becomes higher. Under the worst conditions of SLOW speed, it becomes difficult to satisfy the lock range required for the specification, while under the worst conditions of HIGH speed, there is a problem of deadlock of the PLL feedback loop due to overrange. In addition, since the optical media write clock generation PLL is compatible with CAV, it is necessary to achieve a constant VCO gain from low speed to high speed while satisfying a wide range of lock range.

  As a problem of the circuit of FIG. 10 and FIG. 11, which is a conventional example of the voltage-current converter, when the built-in POLY resistor is used as the resistor to be used, the resistance value varies by ± 20% due to variations due to process variations and temperature variations. However, it has a problem of affecting the voltage-current conversion characteristics. As a solution to the resistance variation due to the use of the built-in POLY resistor, it is conceivable to use an external resistor with little variation.

  However, there are disadvantages such as an increase in the number of components and an increase in chip area, and when an external resistor is used in the feedback loop of the differential amplifier circuit as shown in FIG. 12, the parasitic capacitance of the external resistor terminal As a result, the band of the negative feedback circuit may be lowered and affected by the PLL loop band. Even if the technique disclosed in Patent Document 1 is used, it contributes to the improvement of linearity, but is affected by variations in internal resistance.

  An object of the present invention is to provide a PLL circuit that reduces variations in oscillation frequency of a voltage controlled oscillator by suppressing variations in resistance values of a voltage-current converter circuit.

  An aspect of the present invention that achieves the above object includes a phase comparator, a loop filter, a voltage-current conversion circuit that converts a control voltage output from the loop filter into a current, and an output that is output from the voltage-current conversion circuit. A voltage control oscillator having a current source corresponding to a current and having at least one differential inverter circuit connected in a ring shape, wherein the voltage-current conversion circuit is a variable resistor for determining the output current It has a circuit and reduces process variations. By doing so, a control current that is not affected by process variations can be obtained.

  At this time, the variable resistance circuit includes one or more CMOS transistors that adjust the variable resistance value by adjusting the gate voltage according to the process variation, and further includes one or more fixed resistors as necessary. Thus, a continuous resistance value can be determined, and the resistance value can be determined with higher resolution than using only a fixed resistance.

  In addition, the variable resistance circuit includes a reference circuit that controls the gate voltage of the CMOS transistor according to a change in the reference voltage, thereby determining a constant resistance value that is not affected by the variation in the process variation. Increases accuracy.

  The voltage-current converter circuit includes a limit circuit that limits the upper limit of the oscillation frequency of the voltage-controlled oscillator when the voltage supplied from the loop filter exceeds a predetermined value according to the process variation. Since no oscillation corresponding to the voltage or higher is performed, deadlock can be prevented. This limit circuit may have a plurality of MOS transistors or a plurality of resistors connected in parallel with the control voltage input terminal.

  Further, the voltage-current conversion circuit has a current ratio adjustment circuit that adjusts the current value of the output current supplied according to the variation of the process variation by changing the current ratio, so that the VCO ring has a wide lock range. Since a constant gain can be maintained, a constant VCO gain can be obtained regardless of process variations.

  By suppressing the variation in the resistance value of the voltage-current conversion circuit, the variation in the oscillation frequency of the voltage controlled oscillator can be reduced.

FIG. 1 is a block diagram showing the configuration of the voltage-current converter circuit in this embodiment. The voltage-current conversion circuit includes a variable resistance circuit 4, a limit circuit 5, and a current ratio adjustment circuit 6.
By incorporating the variable resistor circuit 4, process variations when the resistor is incorporated can be controlled, and by incorporating the resistor, it is not affected by the parasitic capacitance of the external resistor terminal, and is not affected by the PLL loop band. A voltage-current conversion circuit capable of responding in a high band can be realized. By using a CMOS variable resistor for the variable resistor circuit 4, continuous resistance value adjustment is possible. If a constant current source with high accuracy that is not affected by process variations can be used, the resistance value can be adjusted with higher accuracy.
Further, by adding the limit circuit 5, it is possible to take out the lock range corresponding to each worst condition. Further, by adding the current ratio adjusting circuit 6, the control current value to be supplied is adjusted by changing the current ratio according to the fluctuation due to the process variation of the VCO ring, and a constant VCO gain is realized regardless of the process fluctuation.

  Next, the variable resistance circuit 4 will be described with reference to FIG. The reference voltage VCOIN is input to one input terminal of the AMP, the output of the amplifier is connected to the gate side of the NMOS transistor M0, and the connection point between the transistor M0 and the transistor M7 of the CMOS variable resistance circuit 41 is the other input of the amplifier. A negative feedback loop is formed which is connected to the terminal and has a current value of I0.

  The circuit for determining the operating point and resistance value of M7 is configured as follows. The reference voltage is input to one input terminal of AMP2, and the output of AMP2 is applied to the gate of the transistor connected to the drain side by the current source generated by the constant current circuit. Is connected to the other input terminal of the AMP2 to form a negative feedback loop having a current value of I1 so that a constant resistance value is determined in accordance with a change in the reference voltage. A reference circuit 42 for controlling the gate voltage of the CMOS variable resistor M6 is formed. A voltage equal to the gate voltage of M6 is monitored and applied to the gate of the transistor M7 of the CMOS variable resistance circuit 41 to determine the resistance value of the transistor M7. Then, the resistance value of the CMOS variable resistance circuit 41 used in the feedback loop of the bias control voltage is determined. Here, the current source needs to be a constant current source that follows the fluctuation of the reference voltage.

  The circuit of the current source that follows the fluctuation of the reference voltage can be implemented in the form of a circuit using the constant current circuit shown in FIG. The constant current circuit of FIG. 3 will be described. The reference voltage Vref is inputted to one input terminal of the amplifier, the output of the amplifier is given to the gate of the NMOS transistor M0 grounded through an external resistor, and the connection point between the drain of the M0 and the resistor is the other input of the amplifier. Connected to the terminal to form a negative feedback loop. Thereby, the current flowing through M0 is determined by the external resistor and the reference voltage. M0 is supplied to the CMOS variable resistance circuit 41 and the reference circuit 42 via PMOS transistors M1 and M2 configured as a current mirror.

  FIG. 4 is a circuit diagram showing the configuration of the limit circuit 6 and the differential amplifier input stage. A limit voltage is formed by connecting the MOS transistors M0, M1, and M2 connected to a diode, and the limit voltage is input to a limit input terminal connected in parallel with the input terminal of the control voltage VCOIN. As a result, a linear voltage-current conversion characteristic can be obtained when VCOIN is equal to or lower than the limit voltage. However, when VCOIN is equal to or higher than the limit voltage, the input voltage is limited, and oscillation corresponding to the limit voltage or higher is not performed. At this time, the limit voltage may be formed by an element using resistors R0 and R1 instead of the MOS transistors M0, M1 and M2 (see FIG. 5).

  FIG. 6 is taken up as another configuration of the CMOS variable resistance circuit 41. The variable resistor can be used in combination with a fixed resistor. You can earn dynamic range by using it together. The source side of the NMOS variable resistors M0 and M1 connected in parallel is grounded, and the drain side is a resistance element connected in series with the fixed POLY resistor R0. The NMOS M5 has a source side connected to the ground and a drain side connected to the gate and drain of the PMOS M6 and connected to the gate side. The source of the PMOS M6 is grounded to the power source, and the drain side of the PMOS M7, which is current mirror connected to the PMOS transistor M6, is connected to the source side of the PMOS transistor M4 and the gate side of the variable resistance transistor M0. Like M7, the drain side of M8, which is current-mirror connected from M6, is connected to the gate of variable resistance transistor M1 and the source side of PMOS M3 that is diode-connected. The drain of M4 is connected to ground.

  The reference voltage VCOIN is input to one input terminal of the amplifier, the output of the amplifier is applied to the gate M5 of the transistor, and the connection point between the other end of the resistor R0 connected in series with the CMOS variable resistors M0 and M1 and the constant current source is Connected to the other input terminal of the amplifier to form a feedback loop.

  Next, the operation of the configuration of FIG. 6 will be described. When the potential at the connection point between the variable resistors NMOS M0 and M1 and the fixed resistor fluctuates due to external factors such as external noise, the drain side of M0 and the PMOS M4 gate side connected thereto and the source side of the PMOS M4 and M0 connected thereto. The fluctuation of the oscillation frequency of the VCO can be reduced by the loop structure on the gate side. FIG. 7 shows the voltage-current characteristics of a voltage-current conversion circuit using the variable resistance circuit 41. In FIG.

  The above embodiment is the best for carrying out the present invention, but is not intended to be limited to this. Therefore, various modifications can be made without departing from the scope of the present invention.

  Development of a PLL circuit for frequency multiplication and a frequency synthesizer using the present invention is desired.

It is a block diagram of the voltage-current converter circuit in the present embodiment. 2 is a circuit diagram showing a configuration of a variable resistance circuit 4. FIG. 3 is a circuit diagram of a reference circuit 42. FIG. FIG. 3 is a circuit diagram showing a configuration of a limiter circuit 5 and a differential amplifier input stage. 6 is a circuit diagram illustrating another configuration of the limiter circuit 5. FIG. 6 is a circuit diagram showing another configuration of the CMOS variable resistance circuit 41. FIG. It is the graph which showed the voltage-current characteristic of the voltage-current conversion circuit of this form. It is a block diagram which shows the basic composition of the conventional PLL circuit. 3 is a block diagram showing a basic configuration of a voltage controlled oscillator 3. FIG. This is a conventional example of the voltage-current conversion circuit 31. An example of the conventional circuit of the voltage-current conversion circuit 31 'is shown. It is an example of the conventional circuit of the current control method oscillator comprised with the differential amplifier circuit. 3 is a graph showing voltage-current conversion characteristics of a voltage-current conversion circuit 31.

Explanation of symbols

1 Phase comparator 2 LPF
3 Voltage controlled oscillator (VCO)
31, 31 'Voltage-current conversion circuit 32 Current control oscillator 321 Ring oscillator 4 Variable resistance circuit 41 CMOS variable resistance circuit 42 Reference circuit 5 Limit circuit 6 Current ratio adjustment circuit

Claims (8)

A phase comparator;
A loop filter;
A voltage-current conversion circuit that converts a control voltage output from the loop filter into a current;
A current source corresponding to the output current output from the voltage-current converter circuit;
In a PLL circuit comprising a voltage controlled oscillator having one or more differential inverter circuits connected in a ring shape,
The voltage-current conversion circuit includes a variable resistance circuit that determines the output current, and reduces process variation. The variable resistance circuit is:
2. The PLL circuit according to claim 1, further comprising one or more CMOS transistors that adjust a variable resistance value by adjusting a gate voltage according to the process variation. The variable resistance circuit is:
The PLL circuit according to claim 2, further comprising one or more fixed resistors. The variable resistance circuit is:
The fixed resistance value which does not receive the fluctuation | variation of the said process variation is determined by providing the reference circuit which controls the gate voltage of a CMOS type transistor according to the fluctuation | variation of a reference voltage, The Claim 2 or 3 characterized by the above-mentioned PLL circuit. The voltage-current converter circuit is
5. A limit circuit for limiting an upper limit of an oscillation frequency of the voltage controlled oscillator when a voltage supplied from the loop filter becomes equal to or higher than a predetermined value according to the process variation. A PLL circuit according to any one of the above. The limit circuit is
6. The PLL circuit according to claim 5, further comprising a plurality of MOS transistors connected in parallel with the input terminal of the control voltage. The limit circuit is
6. The PLL circuit according to claim 5, further comprising a plurality of resistors connected in parallel with the control voltage input terminal. The voltage-current converter circuit is
8. The PLL circuit according to claim 5, further comprising a current ratio adjusting circuit that adjusts a current value of the output current supplied in accordance with a variation in the process variation by changing a current ratio.

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