JP2006030230A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress failure in patterning in a resist layer as much as possible in a method for manufacturing a chip size package type semiconductor device. <P>SOLUTION: After an aperture 10w is formed on the back face of a semiconductor substrate 10, a second insulating film 16 and a second resist layer 17 are formed thereon. The surface of the resist layer 17 is subjected to hydrophilic treatment by ashing. Then the substrate is exposed through a mask having an aperture in a region from a part on a pad electrode 12 in the bottom to a dicing line DL. Then the substrate 10 having the second resist layer 17 is immersed in a developing solution 20d to develop the second resist layer 17. As the developing solution 20d reaches the bottom and near the bottom of the aperture 10w, the second resist layer 17 in the region from a part on the pad electrode 12 to the dicing line DL is reliably removed to reliably expose a part of the second insulating film 16. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a chip size package type semiconductor device.

  In recent years, a chip size package has attracted attention as a package technology. The chip size package means a small package having an outer dimension substantially the same as the outer dimension of the semiconductor chip. Conventionally, a BGA type semiconductor device is known as a kind of chip size package type semiconductor device. In this BGA type semiconductor device, a plurality of ball-shaped conductive terminals made of a metal member such as solder are arranged in a grid pattern on one main surface of a package, and a semiconductor chip formed on the other main surface of the package is electrically connected. Connected.

  When incorporating this BGA type semiconductor device into an electronic device, each conductive terminal is crimped to a wiring pattern on the printed circuit board, thereby electrically connecting the semiconductor chip and the external circuit mounted on the printed circuit board. Connected.

  The BGA type semiconductor device according to the conventional example described above is manufactured by, for example, a manufacturing method through the following steps.

  First, a semiconductor substrate divided by dicing lines is prepared. Here, an electronic device is formed on the surface of the semiconductor substrate. Next, a pad electrode connected to the electronic device is formed on the surface of the semiconductor substrate via the first insulating film. Further, a support is formed on the surface of the semiconductor substrate. Next, along the dicing line, a part of the semiconductor substrate is selectively etched from the back surface to form an opening that penetrates the semiconductor substrate. A second insulating film is formed on the back surface of the semiconductor substrate including the opening. Then, the first and second insulating films at the bottom of the opening are selectively removed to expose part of the pad electrode. Next, a wiring layer that is electrically connected to the pad electrode exposed in the opening and extends from the opening to the back surface of the semiconductor substrate is formed. Further, the wiring layer is selectively etched and patterned so that the wiring layer has a predetermined wiring pattern. Next, a protective layer exposing a part of the wiring layer is formed on the back surface of the semiconductor substrate including the wiring layer, and a conductive terminal is formed on a part of the wiring layer. Finally, the semiconductor substrate is separated into a plurality of semiconductor chips by dicing along a dicing line.

In addition, as a technical document relevant to the technique mentioned above, the following patent documents are mentioned, for example.
Patent Publication 2002-512436

  In the method of manufacturing the BGA type semiconductor device according to the conventional example as described above, in the step of selectively removing the insulating film at the bottom of the opening and exposing a part of the pad electrode, a predetermined region of the bottom It is necessary to form a resist layer having an opening at 1 as an etching mask. Next, formation of a resist layer used as the etching mask will be described with reference to the drawings.

  16 and 17 are cross-sectional views showing a method of manufacturing a semiconductor device according to a conventional example. 16 and 17, it is assumed that the resist layer is a novolak-type positive resist layer in which exposed portions are removed by development and the surface has hydrophobicity. This novolac-type positive resist layer is generally used as an etching mask for an insulating film. 16 and 17, the first insulating film, the pad electrode, the support, and the like are not shown in the semiconductor device according to the conventional example.

  As shown in FIG. 16, a resist layer 57 is formed on the entire surface of the insulating film 56 formed on the back surface of the semiconductor substrate 50 including the opening 50w by, for example, spray coating. Thereafter, the resist layer 57 is exposed through a mask 60m that opens a predetermined removal region 57a at the bottom of the opening 50w along the dicing line DL. After this exposure, the semiconductor layer 50 including the resist layer 57 is immersed in a predetermined developer, and the resist layer 57 is developed.

  However, as shown in FIG. 17, since the surface of the resist layer 57 is hydrophobic, the developer is repelled and the air layer 61 is formed at the bottom of the opening 50w and in the vicinity thereof. Therefore, the developing solution does not reach the resist layer 57 in the removal region 57a at the bottom of the opening 50w where the exposure has been performed, and the resist layer 57 in the removal region 57a that should be removed is not removed. Remained. That is, in the process of forming a resist layer formed on a semiconductor substrate having a three-dimensional structure such as the opening 50w, a patterning defect has occurred.

  Although not shown, when the insulating film 56 is selectively etched using the resist layer 57 as an etching mask, it is removed at the bottom of the opening 50w that should be removed because of the poor patterning of the resist layer. The insulating film 56 in the region to be formed remains without being removed. That is, the patterning of the insulating film formed on the semiconductor substrate having a three-dimensional structure such as the opening 50w has been defective.

  Therefore, the present invention suppresses a defective patterning of a resist layer as much as possible in a manufacturing method of a chip size package type semiconductor device.

  The method of manufacturing a semiconductor device of the present invention has been made in view of the above problems, and has the following characteristics. That is, first, a part of the semiconductor substrate divided by the dicing line is selectively etched from the back surface to form an opening. Next, a layer to be patterned such as an insulating film is formed extending from the opening to the back surface of the semiconductor substrate. Next, a resist layer used as a mask for patterning the patterning layer is formed on the patterning layer. Then, the surface of the resist layer is subjected to hydrophilic treatment by, for example, ashing. Next, the resist layer is exposed through a mask that opens a predetermined region of the resist layer formed at the bottom of the opening, or through a mask that opens a region other than the predetermined region. Next, the resist layer is developed by being immersed in a developer.

  Thereafter, the layer to be patterned is selectively removed by using the resist layer as an etching mask, and the layer to be patterned is patterned. Finally, the semiconductor substrate is separated into a plurality of semiconductor chips by dicing along a dicing line.

  In addition to the above steps, the method of manufacturing a semiconductor device according to the present invention includes the step of forming a support on a semiconductor substrate on which a pad electrode is formed, and the etching using the resist layer as an etching mask. Removing a layer to be patterned (consisting of an insulating film) at the bottom of the part to expose a part of the pad electrode, and electrically connecting with a part of the pad electrode exposed at the bottom of the opening to form a semiconductor substrate The method includes a step of forming a wiring layer extending on the back surface, and a step of forming a conductive terminal on the wiring layer.

  According to the present invention, the surface of the resist layer is subjected to hydrophilic treatment before selectively removing the resist layer in a predetermined region at the bottom of the opening formed in the semiconductor substrate. Since the surface of the resist layer does not repel moisture by this hydrophilic treatment, that is, it has hydrophilicity, the developer spreads over the resist layer in a predetermined region at the bottom of the opening in development after exposure. Thereby, the resist layer in the predetermined region is surely removed, so that the occurrence of the patterning failure of the resist layer as seen in the conventional example can be suppressed as much as possible.

  In addition, a patterning layer such as an insulating film formed on a semiconductor substrate having a three-dimensional structure such as an opening is patterned by using the resist layer as an etching mask, so that the patterning as in the conventional example is achieved. The occurrence of patterning defects in the patterning layer can be suppressed as much as possible.

  Next, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. 1, 2, and 5 to 15 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the present embodiment. 3 and 4 are top views showing the method for manufacturing the semiconductor device according to the present embodiment. 1 to 15 show the vicinity of the dicing line DL in the semiconductor substrate.

  First, as shown in FIG. 1, a semiconductor substrate 10 on which electronic devices (not shown) divided by dicing lines are formed is prepared. Here, it is assumed that an electronic device (not shown) is a light receiving element such as a CCD (Charge Coupled Device) or an infrared sensor, or a light emitting element. Alternatively, the electronic device (not shown) may be an electronic device other than the light receiving element and the light emitting element. The semiconductor substrate 10 is made of, for example, a silicon substrate, but may be a substrate made of other materials.

  Next, a first insulating film 11 is formed as an interlayer insulating film on the surface of the semiconductor substrate 10 including an electronic device (not shown). The first insulating film 11 is made of, for example, a P-TEOS film or a BPSG film.

  Next, a pad electrode 12 that is an external connection electrode connected to an electronic device (not shown) is formed on the surface of the semiconductor substrate 10 via the first insulating film 11. The pad electrode 12 is preferably an electrode made of aluminum (Al) formed by sputtering, but may be an electrode made of other metals.

  Next, a substrate-like or tape-like support 14 is formed on the surface of the semiconductor substrate 10 including the pad electrode 12 via the resin layer 13. Here, when the electronic device (not shown) is a light receiving element or a light emitting element, the support 14 is formed of a material having a transparent or translucent property such as glass. When the electronic device (not shown) is not a light receiving element or a light emitting element, the support 14 may be formed of a material that does not have a transparent or translucent property.

  Next, as shown in FIG. 2, a first resist layer 15 opening along a part or the whole of the dicing line is formed on the back surface of the semiconductor substrate 10. Then, using the first resist layer 15 as a mask, a part of the semiconductor substrate 10 is selectively etched from the back surface, preferably by isotropic etching. As a result of this etching, an opening 10w is formed in a part of the semiconductor substrate 10 so as to penetrate therethrough. Here, the first insulating film 11 is exposed at the bottom of the opening 10w. This etching may be performed by anisotropic etching.

  When the opening 10w is viewed from the back surface of the semiconductor substrate 10, the top view thereof is as shown in FIG. That is, as shown in FIG. 3, the opening 10w locally opens a region where the pad electrode 12 exists in the main surface of the semiconductor substrate along a part of the dicing line DL. Alternatively, as shown in FIG. 4, the opening 10 w may open in a groove shape along the entire dicing line DL in the region of the main surface of the semiconductor substrate where the pad electrode 12 exists. .

Next, as shown in FIG. 5, a second insulating film 16 is formed as a back surface insulating film on the back surface of the semiconductor substrate 10 including the inside of the opening 10w. The second insulating film 16 is made of, for example, a silicon oxide film (SiO ₂ film) or a silicon nitride film (SiN film), and is formed by, for example, a plasma CVD method.

  Next, as shown in FIG. 6, the second resist layer 17 is used as an etching mask when the second insulating film 16 is selectively etched on the second insulating film 16 including the inside of the opening 10 w. Form. Here, the second resist layer 17 is a positive resist layer in which a portion to be exposed is removed by development. For example, the second resist layer 17 is a novolak-type positive resist layer formed by spray coating. The film thickness of the second resist layer 17 is preferably about 10 μm. This novolac-type positive resist layer is generally used as an etching mask when an insulating film made of an oxide film is patterned by etching. Note that the second resist layer 17 may be a positive resist layer other than a novolac type.

  Next, as shown in FIG. 7, the surface of the second resist layer 17 is subjected to a hydrophilic treatment. Here, the hydrophilic treatment is a predetermined treatment applied so that the surface of the second resist layer 17 does not repel moisture. The hydrophilic treatment in the present embodiment is performed, for example, by ashing the surface of the second resist layer 17.

Here, the ashing is not particularly limited as long as it is a predetermined treatment applied so that the surface of the second resist layer 17 does not repel moisture, but preferably is ashing by oxygen plasma. To do. As a suitable condition for the ashing, the flow rate of the plasma gas is, for example, 50 sccm (mm ³ / min). The power is 100 W, for example. The pressure in the reaction chamber is, for example, 0.8 Torr.

  By this hydrophilic treatment, the surface of the second resist layer 17 becomes a rough surface, so that the surface of the second resist layer 17 does not repel moisture, that is, has hydrophilicity. Therefore, it is possible to avoid as much as possible that the developer used for the development described later does not reach the bottom of the opening 50w and the vicinity thereof as in the conventional example, and the air layer 61 is formed at that location. That is, the developer spreads over the bottom of the opening 10w and the vicinity thereof, so that the predetermined area to be removed is surely removed, and the patterning defect of the second resist layer 17 is avoided as much as possible.

  The hydrophilic treatment is not limited to the ashing described above. That is, the hydrophilic treatment may be a treatment other than ashing as long as the treatment is performed so that the surface of the second resist layer 17 has a property of preventing moisture from being repelled.

  After the hydrophilic treatment, as shown below, the second resist layer 17 corresponds to a predetermined pattern so as to serve as an etching mask when the second insulating film 16 is selectively etched. The second resist layer 17 is selectively removed.

  As shown in FIG. 8, a mask 20m is provided above a region other than a region extending from a part of the pad electrode 12 at the bottom of the opening 10w to the dicing line DL. Then, the second resist layer 17 is exposed through the mask 20m.

  Next, as shown in FIG. 9, the semiconductor substrate 10 including the second resist layer 17 is immersed in a predetermined developer 20 d to develop the second resist layer 17. By this development, the second resist layer 17 in a region extending from a part of the pad electrode 12 at the bottom of the opening 10w to the dicing line DL is removed, and a part of the second insulating film 16 is exposed.

  Here, the surface of the second resist layer 17 has a property of not repelling moisture by the hydrophilic treatment described above, that is, has a hydrophilic property. Therefore, it is possible to avoid as much as possible that the developer 60d is repelled at the bottom of the opening 50w and in the vicinity thereof as in the conventional example to generate the air layer 61. That is, the developer spreads over the bottom of the opening 10w and the vicinity thereof. Therefore, as long as exposure is performed reliably, the second resist layer in the region extending from a part of the pad electrode 12 at the bottom of the opening 10w to the dicing line DL is reliably removed, which is seen in the conventional example. Such patterning defects of the second resist layer 17 are avoided as much as possible.

  Next, as shown in FIG. 10, using the second resist layer 17 as a mask, the underlying OLE_LINK1 first insulating film 11 and second insulating film 16OLE_LINK1 are selectively etched and removed. Here, the etching is not particularly limited, but is preferably wet etching using an etching solution made of hydrofluoric acid (HF) or a solution containing the same. Alternatively, the selective removal of the first insulating film 11 and the second insulating film 16 may be performed by etching other than the wet etching.

  By this etching, the first insulating film 11 and the second insulating film 16 in a region extending from a part of the bottom of the opening 10w to the dicing line DL are removed. That is, a part of the pad electrode 12 and a part of the back surface of the semiconductor substrate 10 are exposed at the bottom of the opening 10w.

  Here, since the patterning defect of the second resist layer 17 serving as the etching mask is avoided as much as possible as compared with the conventional example, the pattern of the second resist layer 17 serving as the etching mask is reflected. In the etching of the insulating film 16, the region to be removed can be surely removed.

  Next, after removing the second resist layer 17, as shown in FIG. 11, a wiring layer 18 extending from a part of the pad electrode 12 in the opening 10w to the back surface of the semiconductor substrate 10 is formed. That is, the wiring layer 18 is electrically connected to the pad electrode 12 exposed at the bottom of the opening 10w.

  The wiring layer 18 is made of, for example, aluminum (Al), and is formed by, for example, a sputtering method or other film forming methods. Alternatively, the wiring layer 18 may be made of a metal other than aluminum (Al). For example, although not shown, the wiring layer 18 may be made of a metal such as copper (Cu) plated on a barrier seed layer including a barrier metal layer and a seed layer.

  Next, as shown in FIG. 12, a third resist layer 19 for patterning the wiring layer 18 into a predetermined pattern is formed on the wiring layer 18 on the back surface of the semiconductor substrate 10 including the inside of the opening 10w. . Here, the third resist layer 19 opens, by predetermined exposure and development, a region where the pad electrode 12 at the bottom of the opening 10w is not formed and a region which is not necessary for forming a predetermined pattern. Formed as follows.

  Although not shown, before the predetermined exposure and development are performed on the third resist layer 19, the same hydrophilic treatment as that performed on the surface of the second resist layer 17 is applied to the third resist layer 19. You may perform with respect to the surface of the resist layer 19. FIG. In this case, the third resist layer 19 in a predetermined region at the bottom of the opening 10w can be surely removed as in the exposure and development of the second resist layer 17.

  Next, as shown in FIG. 13, in order to pattern the wiring layer 18 into a predetermined pattern, a part of the wiring layer 18 is selectively removed by using the third resist layer 19 as a mask. The selective removal of the wiring layer 18 is preferably performed by wet etching using sodium hydroxide (NaOH). Alternatively, the selective removal of the wiring layer 18 may be performed by etching other than the wet etching.

  Further, as shown in FIG. 14, after removing the third resist layer 19, a protective layer 21 is formed on the back surface of the semiconductor substrate 10 including the wiring layer 18. The protective layer 21 is made of a resist material or other material. Further, the protective layer 21 is opened so that a part of the wiring layer 18 is exposed, and the conductive terminal 22 is formed on a part of the wiring layer 18. The conductive terminal 22 is made of, for example, solder and is formed in a ball shape.

  Finally, as shown in FIG. 15, by dicing along the dicing line DL, the semiconductor substrate 10 and each layer stacked thereon are separated into a plurality of semiconductor chips 10A and a semiconductor device including each layer stacked thereon.

  In the present embodiment, the conductive terminal 22 is formed on the wiring layer 18, but the present invention is not limited to this. That is, the present invention may be applied to a semiconductor device in which no conductive terminal is formed, for example, an LGA (Land Grid Array) type semiconductor device.

  In the present embodiment, the second insulating film 16 is formed below the second resist layer 17 to be subjected to the hydrophilic treatment, but the present invention is not limited to this. That is, a layer to be patterned other than the second insulating film 16 may be used as long as it is formed at least in the opening 10w.

  In the present embodiment, the second resist layer 17 to be subjected to hydrophilic processing is a positive resist layer, but the present invention is not limited to this. That is, the present invention is also applied to the case where the second resist layer 17 is a negative resist layer.

  In the present embodiment, the opening 10w is formed so as to penetrate the semiconductor substrate 10, but the present invention is not limited to this. That is, the opening 10 w may be a recess formed without penetrating the semiconductor substrate 10 from the back surface of the semiconductor substrate 10. In this case, the support 14 formed on the surface of the semiconductor substrate 10 may be removed in any of the above steps. Alternatively, the support 14 may be left without being removed. Alternatively, the formation of the support 14 may be omitted.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a top view which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a top view which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the past. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the past.

Claims (7)

A step of selectively etching a part of the semiconductor substrate divided by the dicing line from the back surface to form an opening;
Forming a patterning layer extending on the back surface of the semiconductor substrate from within the opening;
Forming a resist layer used as a mask for patterning the patterning layer on the patterning layer;
Hydrophilic treatment of the surface of the resist layer;
Exposing the resist layer through a mask that opens a predetermined region of the resist layer formed on the bottom of the opening, or through a mask that opens a region other than the predetermined region; and
Developing the resist layer by immersing it in a developer;
And a step of selectively etching and removing the layer to be patterned using the resist layer as a mask and patterning the layer to be patterned. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the hydrophilic treatment is ashing on the surface of the resist layer. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of separating the semiconductor substrate into a plurality of semiconductor chips by dicing along the dicing line. Forming a support via a resin layer on a semiconductor substrate which is divided by a dicing line and has a pad electrode formed along the dicing line via the first insulating film;
Selectively etching a part of the semiconductor substrate from the back surface to form an opening that opens along a part or the whole of the dicing line;
Forming a second insulating film on the back surface of the semiconductor substrate including the inside of the opening;
Forming a positive resist layer on the second insulating film;
Hydrophilic treatment of the surface of the positive resist layer;
Exposing the positive resist layer through a mask that opens a region from a part of the pad electrode at the bottom of the opening to the dicing line; and
Developing by immersing the positive resist layer in a developer;
Selectively etching and removing the first and second insulating films using the positive resist layer as a mask to expose a part of the pad electrode;
Forming a wiring layer electrically connected to the pad electrode and extending from the opening to the back surface of the semiconductor substrate;
And a step of patterning the wiring layer into a predetermined pattern. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the hydrophilic treatment is ashing on the surface of the positive resist layer. Forming a protective layer on the back surface of the semiconductor substrate including the wiring layer;
6. The method of manufacturing a semiconductor device according to claim 4, further comprising: exposing a part of the wiring layer and forming a conductive terminal on a part of the wiring layer. 7. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of separating the semiconductor substrate into a plurality of semiconductor chips by dicing along the dicing line.

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