JP2006030289A - El display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems wherein an image is not displayed with good quality even using a current program method and driving is not performed well in a low grayscale area, particularly, as a current of o-th grayscale is o (no flow), a display image is not rewritable. <P>SOLUTION: A reference current Ic is applied to a transistor group 251b. The transistor group 251b and each output stage 251c constitute a current mirror circuit. An output selection circuit 1531 is arranged between the output stage 251c and an output terminal 93. The output selection circuit 1531 periodically changes the output stage 251c for outputting currents to each terminal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a self-luminous display panel such as an EL display panel (display device) using an organic or inorganic electroluminescence (EL) element. Further, the present invention relates to a driving circuit (such as an IC) and a driving method of these display panels.

  In an active matrix image display device using an organic electroluminescence (EL) material as an electro-optic conversion substance, light emission luminance changes according to a current written to a pixel. The organic EL display panel is a self-luminous type having a light emitting element in each pixel. The organic EL display panel has advantages such as higher image visibility than the liquid crystal display panel, no backlight, and high response speed.

  The organic EL display panel can also be configured in a simple matrix system and an active matrix system. Although the former has a simple structure, it is difficult to realize a large and high-definition display panel. However, it is cheap. The latter can realize a large, high-definition display panel. However, there is a problem that the control method is technically difficult and relatively expensive. At present, active matrix systems are actively developed. In the active matrix system, a current flowing through a light emitting element provided in each pixel is controlled by a thin film transistor (transistor) provided in the pixel.

  An active matrix organic EL display panel is disclosed in Patent Document 1. An equivalent circuit of one pixel of this display panel is shown in FIG. The pixel 16 includes an EL element 15 that is a light emitting element, a first transistor (driving transistor) 11 a, a second transistor (switching transistor) 11 b, and a storage capacitor (capacitor) 19. The light emitting element 15 is an organic electroluminescence (EL) element. In this specification, the transistor 11 a that supplies (controls) current to the EL element 15 is referred to as a driving transistor 11. A transistor that operates as a switch, such as the transistor 11b in FIG.

  Since the organic EL element 15 often has a rectifying property, it is sometimes called an OLED (organic light emitting diode). In FIG. 1, FIG. 2, etc., the symbol of a diode is used as the light emitting element 15.

  The light-emitting element 15 in the present invention is not limited to the OLED, and any element can be used as long as the luminance is controlled by the amount of current flowing through the element 15. For example, an inorganic EL element is illustrated. In addition, a white light emitting diode made of a semiconductor is exemplified. Further, a light emitting transistor may be used. In addition, the light emitting element 15 is not necessarily required to have rectification. A bidirectional element may be used.

The operation of FIG. 2 will be described. The gate signal line 17 is selected, and a video signal having a voltage representing luminance information is applied to the source signal line 18. The transistor 11 a is turned on, and the video signal is charged in the storage capacitor 19. When the gate signal line 17 is not selected, the transistor 11a is turned off. The transistor 11b is electrically disconnected from the source signal line 18. However, the gate terminal potential of the transistor 11 a is stably held by the storage capacitor (capacitor) 19. The current flowing through the light emitting element 15 through the transistor 11a has a value corresponding to the gate-drain terminal voltage Vgd of the transistor 11a. The light emitting element 15 continues to emit light with a luminance corresponding to the amount of current supplied through the transistor 11a.
JP-A-8-234683

  The organic EL display panel is configured by using a low-temperature polysilicon transistor array. However, display variations occur in organic EL elements when the transistor characteristics of the polysilicon transistor array vary.

  FIG. 2 shows a pixel configuration of a voltage program method. In the pixel configuration shown in FIG. 2, the voltage video signal is converted into a current signal by the transistor 11a. Therefore, if the transistor 11a has a characteristic variation, the current signal to be converted also varies. Normally, the transistor 11a has a characteristic variation of 50% or more. Therefore, display unevenness occurs in the configuration of FIG.

  Display unevenness can be reduced by adopting a current program system configuration. In order to implement the current program, a current drive type driver circuit is required. However, variation also occurs in the transistor elements constituting the current output stage in the current drive type driver circuit. For this reason, there is a problem in that the gradation output current from each output terminal varies and a good image display cannot be performed. In the current program method, the drive current is small in the low gradation region. For this reason, there has been a problem that the source signal line 18 cannot be driven satisfactorily due to the parasitic capacitance. In particular, the current at the 0th gradation is 0 (does not flow). Therefore, there is a problem that the image display cannot be rewritten.

  The driver circuit of the display panel (display device) of the present invention includes a plurality of transistors that mainly output unit current, and outputs an output current by changing the number of transistors. In addition, the unit transistor group connected to each output terminal is sequentially switched. The display device of the present invention performs duty ratio control, reference current control, and the like.

  The source driver circuit of the present invention includes a reference current generation circuit, and realizes current control and luminance control by controlling the gate driver circuit. Further, the pixel has a plurality of or single drive transistors, and is driven so as not to cause a variation in current flowing through the EL element 15. Further, the unit transistor group connected to each terminal is changed. Therefore, it is possible to suppress the occurrence of display unevenness due to variations in threshold values of transistors. The temperature dependence of the driving transistor element is also compensated. Also, an image display with a wide dynamic range can be realized by duty ratio control or the like.

  The display panel, display device, and the like of the present invention exhibit distinctive effects according to their respective configurations such as high image quality, good moving image display performance, low power consumption, low cost, and high brightness.

  If the present invention is used, an information display device or the like with low power consumption can be configured, and power is not consumed. Moreover, since it can be reduced in size and weight, resources are not consumed. Therefore, it is friendly to the global environment and space environment.

  In the present specification, each drawing includes parts omitted, enlarged, or reduced for easy understanding and drawing. For example, in the cross-sectional view of the display panel shown in FIG. 4, the thin film sealing film 41 and the like are shown to be sufficiently thick. On the other hand, in FIG. 3, the sealing lid 40 is shown thinly. Also, there are some omitted parts. For example, in the display panel of the present invention, a phase film (38, 39) such as a circularly polarizing plate is necessary for preventing reflection. However, a circularly polarizing plate and the like are omitted in each drawing of this specification. The same applies to the following drawings. Moreover, the part which attached | subjected the same number or the symbol etc. has the same or similar form, material, function, or operation | movement.

  In this specification, the driving transistor 11 and the switching transistor 11 are described as thin film transistors, but the present invention is not limited thereto. A thin film diode (TFD), a ring diode, or the like can also be used. The transistor is not limited to a thin film element, and may be a transistor formed on a silicon wafer. Of course, an FET, a MOS-FET, a MOS transistor, or a bipolar transistor may be used. These are also basically thin film transistors. In addition, it goes without saying that varistors, thyristors, ring diodes, photodiodes, phototransistors, PLZT elements may be used. That is, any of these can be used for the transistor 11, the gate driver circuit 12, the source driver circuit (IC) 14 and the like of the present invention.

  The source driver circuit (IC) 14 has not only a simple driver function but also a power supply circuit, a buffer circuit (including a circuit such as a shift register), a data conversion circuit, a latch circuit, a command decoder, a shift circuit, an address conversion circuit, and an image memory. Etc. may be incorporated.

  Although the substrate 30 is described as a glass substrate, it may be formed of a silicon wafer. The substrate 30 may be a metal substrate, a ceramic substrate, a plastic sheet (plate), or the like. Further, the transistor 11, the gate driver circuit 12, the source driver circuit (IC) 14 and the like constituting the display panel of the present invention are formed on a glass substrate and transferred to another substrate (plastic sheet) by a transfer technique. Needless to say, it may be configured or formed. The material or configuration of the lid 40 is the same as that of the substrate 30. Needless to say, sapphire glass or the like may be used for the lid 40 and the substrate 30 to improve heat dissipation.

  Hereinafter, the EL display panel of the present invention will be described with reference to the drawings. As shown in FIG. 3, the organic EL display panel includes at least an electron transport layer, a light emitting layer, a hole transport layer, and the like on a glass plate 30 (array substrate 30) on which a transparent electrode 35 as a pixel electrode is formed. One organic functional layer (EL layer) 29 and a metal electrode (reflective film) (cathode) 36 are laminated. By applying a positive voltage to the anode (anode) which is the transparent electrode (pixel electrode) 35 and a negative voltage to the cathode (cathode) of the metal electrode (reflection electrode) 36, and applying a direct current between the transparent electrode 35 and the metal electrode 36. The organic functional layer (EL film) 29 emits light.

  In the present invention, the film thickness of the transparent electrode (ITO) as the pixel electrode is changed for each RGB sub-pixel. The While the light emitted from the organic EL layer 29 is repeatedly reflected between the interface of the transparent electrode (ITO) layer 35, the organic EL layer 29, and the metal electrode 36, it has a specific wavelength according to the distance between the interfaces. Only the interference increases, and the intensity of light of other wavelengths decreases. The color purity of each RGB light is improved by changing the thickness of the transparent electrode (ITO) layer 35 for each RGB subpixel. The longer the wavelength of extracted light (R> G> B), the thicker the ITO layer. The light spectrum of the present invention has a slightly sharp peak in red (R) and blue (B) colors and a gentle peak in green (G).

  A desiccant 37 is disposed in the space between the sealing lid 40 and the array substrate 30. This is because the organic EL film 29 is vulnerable to humidity. The desiccant 37 absorbs moisture penetrating the sealing agent and prevents the organic EL film 29 from deteriorating. Further, as shown in FIG. 251, the sealing lid 40 and the array substrate 30 have their peripheral portions sealed with a sealing resin 2511. The moisture absorbing means such as the desiccant 37 may be formed by directly applying or vapor-depositing on the sealing lid 40 or the like.

  The sealing lid 40 is a means for preventing or suppressing entry of moisture from the outside, and is not limited to the shape of the lid. For example, a glass plate, a plastic plate, or a film may be used. Further, it may be a fused glass or a metal such as stainless steel. Moreover, constituents, such as resin or an inorganic material, may be sufficient. Further, it may be formed in a thin film shape (see FIG. 4) using a vapor deposition technique or the like. The distance from the surface of the desiccant 37 to the EL film is preferably 0.2 mm or more.

  The organic EL display panel of the present invention shown in FIG. 3 is configured to be sealed using a glass lid 40. However, the present invention is not limited to this. For example, as shown in FIG. 4, a sealing structure using a film 41 (which may be a thin film, that is, a thin film sealing film 41) 41 may be used.

  Examples of the sealing film (thin film sealing film) 41 include a film of an electrolytic capacitor on which DLC (diamond-like carbon) is vapor-deposited. This film has extremely poor moisture permeability (high moisture resistance). This film is used as the sealing film 41. Needless to say, a structure in which a DLC (diamond-like carbon) film or the like is directly deposited on the surface of the electrode 36 is preferable. In addition, a thin film sealing film may be configured by laminating a resin thin film and a metal thin film in multiple layers.

  The thickness of the thin film 41 or the film forming the sealing structure is not limited to the thickness of the interference region. Needless to say, the thickness may be 5 to 10 μm or more, or 100 μm or more. In addition, when the sealed thin film 41 or the like has transparency, the A side in FIG. 4 is the light emission side, and when it has an opaque or light reflective function or structure, the B side is the light emission side. .

  You may comprise so that light may be radiate | emitted from both A side and B side. In the case of adopting this configuration, the image is reversed horizontally when viewing the image of the EL display panel from the A side and when viewing the image of the EL display panel from the B side. Therefore, when viewing the image of the EL display panel from the A side and when viewing the image of the EL display panel from the B side, a function of inverting the left and right of the image manually or automatically is added. This function can be realized by storing one pixel row or a plurality of pixel rows of the video signal in the line memory and inverting the reading direction of the line memory.

  A configuration in which the sealing lid 40 is not used as shown in FIG. 4 and the sealing film 41 is sealed is called thin film sealing. The thin film sealing 41 in the case of “lower extraction (see FIG. 3; the light extraction direction is the direction indicated by the arrow B in FIG. 3)” for extracting light from the substrate 30 side is the EL film after forming the EL film. An aluminum electrode to be a cathode is formed. Next, a resin layer as a buffer layer is formed on the aluminum film. Examples of the buffer layer include organic materials such as acrylic and epoxy. Further, the film thickness is suitably 1 μm or more and 10 μm or less. More preferably, the film thickness is 2 μm or more and 6 μm or less. A sealing film 74 on the buffer film is formed.

  Without the buffer film, the structure of the EL film collapses due to the stress, and a line-like defect occurs. As described above, the sealing film 41 is exemplified by DLC (Diamond Like Carbon) or a layer structure of an electric field capacitor (a structure in which dielectric thin films and aluminum thin films are alternately deposited).

  Thin film sealing in the case of “upward extraction (see FIG. 4, the light extraction direction is the direction of arrow A in FIG. 4)” for extracting light from the organic EL film 29 side is as follows: An Ag—Mg film serving as a cathode (or anode) is formed on the organic EL film 29 with a film thickness of 20 angstroms or more and 300 angstroms. A transparent electrode such as ITO is formed thereon to reduce the resistance. Next, a resin layer as a buffer layer is preferably formed on this electrode film. A sealing film 41 is formed on the buffer film.

  In FIG. 3 and the like, half of the light generated from the organic EL film 29 is reflected by the reflective film (cathode electrode) 36 and transmitted through the array substrate 30 to be emitted. However, external light is reflected on the reflective film (cathode electrode) 36, and reflection occurs to reduce display contrast. For this measure, a λ / 4 plate (phase film) 38 and a polarizing plate (polarizing film) 39 are arranged on the array substrate 30. What united the polarizing plate 39 and the phase film 38 is called a circularly-polarizing plate (circularly polarizing sheet).

  In the configurations of FIGS. 3 and 4, the display luminance can be improved by forming a prism such as a fine quadrangular pyramid or a triangular pyramid on the light emitting surface. In the case of a quadrangular pyramid, one side of the base is 100 μm or less and 10 μm or more. More preferably, it is 30 μm or less and 10 μm or more. In the case of a triangular pyramid, the diameter of the base is set to 100 μm or less and 10 μm or more. More preferably, it is 30 μm or less and 10 μm or more.

  When the pixel 16 is a reflective electrode, light generated from the EL film 29 is emitted upward (light is emitted in the direction A in FIG. 4). Therefore, it goes without saying that the phase plate 38 and the polarizing plate 39 are arranged on the light emitting side.

  The reflective pixel 16 is obtained by configuring the pixel electrode 35 with aluminum, chromium, silver or the like. Further, by providing a convex portion (or a concave-convex portion) on the surface of the pixel electrode 35, the interface with the organic EL film 29 is widened, the light emission area is increased, and the light emission efficiency is improved. Note that the circularly polarizing plate is not necessary when the reflective film to be the cathode 36 (anode 35) is formed on the transparent electrode, or when the reflectance can be reduced to 30% or less. This is because the reflection is greatly reduced. It is also desirable to reduce light interference.

  Protruding portions (or uneven portions) having a diffraction grating is effective for light extraction. The diffraction grating has a two-dimensional or three-dimensional structure. The pitch of the diffraction grating is preferably 0.2 μm or more and 2 μm or less. In this range, a result with good light efficiency can be obtained. In particular, the pitch of the diffraction grating is preferably 0.3 μm or more and 0.8 μm or less. Further, the shape of the diffraction grating is preferably a sine curve.

  The EL display device is colored by mask vapor deposition, but the present invention is not limited to this. For example, a blue light emitting EL layer may be formed, and the emitted blue light may be converted into R, G, B light by an R, G, B color conversion layer (CCM: Color Change Mediums). For example, in FIG. 4, a color filter is disposed on or below the thin film sealing film 41. Of course, an RGB organic material (EL material) placement method using a precision shadow mask may be employed. Any of these methods may be used for the color EL display panel of the present invention.

  In the structure of the pixel 16 of the EL panel (EL display device) of the present invention, one pixel 16 is formed by four transistors 11 and EL elements 15 as shown in FIG. The pixel electrode 35 is configured to overlap the source signal line 18. A planarization film 32 made of an insulating film or an acrylic material is formed on the source signal line 18 for insulation, and a pixel electrode 35 is formed on the planarization film 32. A configuration in which the pixel electrode 35 is overlaid on at least a part of the source signal line 18 in this way is called a high aperture (HA) structure. Unnecessary interference light and the like are reduced, and a good light emission state can be expected.

  The planarizing film 32 also functions as an interlayer insulating film. The planarizing film 32 is configured or formed with a film thickness of 0.4 μm or more and 2.0 μm or less. If the thickness of the planarization film 32 is 0.4 μm or less, the interlayer insulation tends to be defective (yield reduction). If the thickness is 2.0 μm or more, formation of the contact connecting portion 34 becomes difficult, and contact failure is likely to occur (yield decreases).

  In this specification, an organic EL element (described by various abbreviations such as OEL, PEL, PLED, and OLED) will be described as an example of the EL element 15, but the present invention is not limited to this, and an inorganic EL element is also used. It goes without saying that it applies.

  The active matrix method used for the organic EL display panel is to select a specific pixel and provide necessary display information. Two conditions must be satisfied that current can flow through the EL element throughout one frame period.

  In order to satisfy these two conditions, in the pixel configuration of the conventional organic EL shown in FIG. 2, the first transistor 11b functions as a switching transistor for selecting a pixel. Further, the second transistor 11 a functions as a driving transistor for supplying current to the EL element 15.

  In the case of displaying gradation using this configuration, it is necessary to apply a voltage corresponding to the gradation as the gate voltage of the driving transistor 11a. Therefore, the variation in the on-state current of the driving transistor 11a appears in the display as it is.

  The on-current of a transistor is very uniform if it is a transistor formed of a single crystal. The threshold value varies within a range of ± 0.2V to ± 0.5V. For this reason, the on-current flowing through the driving transistor 11a varies correspondingly, and the display is uneven. These irregularities are caused not only by variations in threshold voltage, but also by transistor mobility, gate insulating film thickness, and the like. The characteristics also change due to deterioration of the transistor 11.

  This phenomenon is not limited to low-temperature polysilicon technology, and transistors and the like are formed using solid-phase (CGS) grown semiconductor films even in high-temperature polysilicon technology with a process temperature of 450 degrees Celsius or higher. Even things can occur. In addition, it occurs in organic transistors. It also occurs in amorphous silicon transistors.

  As shown in FIG. 2, in the method of displaying gradation by writing a voltage, it is necessary to strictly control the device characteristics in order to obtain a uniform display. However, this variation cannot be suppressed within a predetermined range in a current low-temperature polycrystalline polysilicon transistor or the like.

  The transistor 11 constituting the pixel 16 of the display panel of the present invention is configured as a p-channel polysilicon thin film transistor. The transistor 11b has a multi-gate structure that is more than a dual gate.

  The transistor 11b constituting the pixel 16 of the display panel of the present invention functions as a source-drain switch of the transistor 11a. Therefore, the transistor 11b is required to have as high a ON / OFF ratio as possible. By setting the gate structure of the transistor 11b to a multi-gate structure that is equal to or higher than the dual gate structure, a characteristic with a high ON / OFF ratio can be realized.

  In this specification, an organic EL element (described by various abbreviations such as OEL, PEL, PLED, and OLED) will be described as an example of the EL element 15, but the present invention is not limited to this, and an inorganic EL element is also used. It goes without saying that it applies.

  The pixel circuit in FIG. 1 has four transistors 11 in one pixel. The gate terminal of the driving transistor 11a is connected to the source terminal of the transistor 11b. The gate terminals of the transistors 11b and 11c are connected to the gate signal line 17a. The drain terminal of the transistor 11 b is connected to the source terminal of the transistor 11 c and the source terminal of the transistor 11 d, and the drain terminal of the transistor 11 c is connected to the source signal line 18. The gate terminal of the transistor 11d is connected to the gate signal line 17b, and the drain terminal of the transistor 11d is connected to the anode electrode of the EL element 15.

  In FIG. 1, all the transistors are configured by P-channel. The P channel has a lower mobility than an N channel transistor, but is preferable because it has a high breakdown voltage and is less likely to deteriorate. However, the present invention is not limited to the configuration of the EL element with the P channel. You may comprise only N channel. Moreover, you may comprise using both N channel and P channel.

  In order to manufacture a panel at low cost, it is preferable that all the transistors 11 constituting the pixel are formed with a P channel and the built-in gate driver circuit 12 is also formed with a P channel. By forming the array with only P-channel transistors in this way, the number of masks becomes five, and cost reduction and high yield can be realized.

  As shown in FIG. 1, when the driving transistor 11a and the selection transistors (11b, 11c) of the pixel 16 are P-channel transistors, a punch-through voltage is generated. This is because the potential fluctuation of the gate signal line 17a penetrates to the terminal of the capacitor 19 through the GS capacitance (parasitic capacitance) of the selection transistors (11b, 11c). When the P-channel transistor 11b is turned off, the voltage becomes Vgh. Therefore, the terminal voltage of the capacitor 19 is slightly shifted to the Vdd side. For this reason, the gate (G) terminal voltage of the transistor 11a rises, resulting in a black display. Therefore, good black display can be realized.

  In the above embodiment, the potential of the capacitor 19 is changed via the GS capacitance (parasitic capacitance) of the transistor 11b, and the black display is improved by the potential change of the capacitor 19. However, the present invention is not limited to this. For example, it goes without saying that the capacitor 19b may be formed of an element. The capacitor 19b is preferably formed with two electrodes, an electrode layer constituting the gate signal line 17 of the transistor 11 and an electrode layer constituting (forming) the source signal line 18. The capacity of the capacitor 19b is preferably not less than 1/4 and not more than 1/1 of the capacity of the capacitor 19a.

  This is because the amount of shift of the punch-through voltage due to the capacitor 19b or the like is constant, and the Vgh voltage and the Vgl voltage are constant values. In the current drive method (current program method), the program current becomes small at a low gradation, and it is difficult to charge and discharge the parasitic capacitance of the source signal line 18. However, the program current applied to the source signal line 18 can be made relatively large by using the punch-through voltage generated by the capacitor 19b, and the current that the driving transistor 11a passes through the EL element 15 can be made smaller than the program current. it can. That is, a minute program current can be written into the pixel 16.

  Conversely, in order to vary the punch-through voltage, the Vgh voltage, the Vgl voltage, or the potential difference between the Vgh voltage and the Vgl voltage may be changed. For example, a driving method of changing or operating the Vgh voltage and the Vgl voltage according to the lighting rate (described later) is exemplified. Moreover, what is necessary is just to change the capacity | capacitance of the capacitor | condenser 19b. Further, the anode voltage Vdd may be changed. For example, a driving method of changing or operating the anode voltage (Vdd) according to the lighting rate (described later) is exemplified. By changing or changing these, the magnitude of the punch-through voltage can be controlled, the amount of current flowing through the driving transistor 11a can be controlled, and good black display can be realized.

  Since the magnitude of the punch-through voltage is a constant value regardless of the gradation number, the ratio of the program current amount that decreases relatively increases in the low gradation area. Therefore, a better black display can be realized as the gradation is lower.

  Hereinafter, in order to facilitate understanding of the present invention, the EL element configuration of the present invention will be described with reference to FIG. The EL device configuration of the present invention is controlled by two timings. The first timing is a timing for storing a necessary current value. When the transistor 11b and the transistor 11c are turned on at this timing, an equivalent circuit is shown in FIG. Here, a predetermined current Iw is written from the signal line. As a result, the gate and drain of the transistor 11a are connected, and a current Iw flows through the transistor 11a and the transistor 11c. Therefore, the gate-source voltage of the transistor 11a is a voltage at which I1 flows.

  The second timing is a timing at which the transistor 11a and the transistor 11c are closed and the transistor 11d is opened, and the equivalent circuit at that time is shown in FIG. The voltage between the source and gate of the transistor 11a remains held. In this case, since the transistor 11a always operates in the saturation region, the current Iw is constant.

  The above operation is illustrated in FIG. Reference numeral 61 a in FIG. 6A indicates a pixel (row) (write pixel row) in which current is programmed at a certain time on the display screen 64. The pixels (rows) 61a are not lit (non-displayed pixels (rows)) as shown in FIG.

  In the case of the pixel configuration of FIG. 1, as shown in FIG. 5A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the driving transistor 11a and the current through which the program current Iw flows is held. At this time, the transistor 11d is in an open state (off state). Note that one terminal of the capacitor 19 in FIG. 1 or the like may be connected to the gate signal line 17a in the previous stage (pixels in the previous row) or the subsequent stage (pixels to be selected next).

  Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d is operated as shown in FIG. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned on.

  FIG. 7 shows a timing chart of the driving method of FIG. As can be seen from FIG. 7, in each selected pixel row (the selection period is 1H), when the on-voltage (Vgl) is applied to the gate signal line 17a (see FIG. 7A). In FIG. 7, an off voltage (Vgh) is applied to the gate signal line 17b (see FIG. 7B). During this period, no current flows through the EL element 15 (non-lighting state).

  In an unselected pixel row, an off voltage (Vgh) is applied to the gate signal line 17a, and an on voltage (Vgl) is applied to the gate signal line 17b. Further, during this period, a current flows through the EL element 15 (lighting state). In the lighting state, the EL element 15 is lit with a predetermined N times luminance (N · B), and the lighting period is 1 F / N. Therefore, the display luminance of the display panel that averages 1F is (N · B) × (1 / N) = B (predetermined luminance). N may be any value as long as N is 1 or more.

  Next, a power supply (voltage) used in the EL display panel of the present invention will be described with reference to FIG. The gate driver circuit 12 includes a buffer circuit 82 and a shift register circuit 81. The buffer circuit 82 uses the off voltage (Vgh) and the on voltage (Vgl) as power supply voltages. On the other hand, the shift register circuit 81 uses the power supply VGDD and the grant (GND) voltage of the shift register, and also uses the VREF voltage for generating an inverted signal of the input signals (CLK, UD, ST). The source driver circuit (IC) 14 uses a power supply voltage Vs and a ground (GND) voltage.

  The gate driver circuit 12a includes a shift register circuit 81a and a buffer circuit 82. Therefore, the gate driver circuit 12a controls on / off of the gate signal line 17a. The gate signal line 17b incorporates a shift register circuit 81b (not shown) and a buffer circuit 82 (not shown). For ease of explanation, the pixel configuration will be described using FIG. 1 as an example.

  Each shift register circuit 81 is controlled by positive and negative phase clock signals CLKx (CLKxP, CLKxN) and a start pulse (STx). Note that x is a subscript. In addition, it is preferable to add an enable (ENABL) signal for controlling the output and non-output of the gate signal line and an up / down (UPDWM) signal for reversing the shift direction up and down. In addition, it is preferable to provide an output terminal for confirming that the start pulse is shifted to the shift register circuit 81 and output.

  The shift timing of the shift register circuit 81 is controlled by a control signal from a control IC 722 (described later). A level shift circuit 81 for shifting the level of external data is also incorporated. Note that the clock signal may have only a positive phase. By using only positive phase clock signals, the number of signal lines can be reduced, and a narrow frame can be realized.

  Since the buffer capacity of the shift register circuit 81 is small, the gate signal line 17 cannot be driven directly. For this reason, at least two or more inverter circuits are formed between the output of the shift register circuit 81 and the output gate for driving the gate signal line 17.

  The same applies to the case where the source driver circuit (IC) 14 is formed directly on the substrate 30 by a polysilicon technique such as low-temperature polysilicon. The gate of an analog switch such as a transfer gate for driving the source signal line 18 and the source driver circuit (IC) A plurality of inverter circuits are formed between the 14 shift registers.

  The following items (the output of the shift register and the output stage that drives the signal line (items related to the inverter circuit arranged between the output stages such as the output gate or the transfer gate) are common to the source drive and the gate driver circuit. is there.

  Here, in order to facilitate understanding, a voltage value is defined. First, the anode voltage Vdd is set to 6 (V), and the cathode voltage Vss is set to −9 (V) (see FIG. 1 and the like). The GND voltage is 0 (V), and the Vs voltage of the source driver circuit is 6 (V), which is the same as the Vdd voltage. The Vgh1 and Vgh2 voltages are preferably 0.5 (V) to 3.0 (V) from Vdd. Here, Vgh1 = Vgh2 = 8 (V).

  Vgl1 of the gate driver circuit 12 needs to be lowered in order to sufficiently reduce the on-resistance of the transistor 11c in FIG. Here, in order to facilitate the circuit configuration, Vgl1 = −8 (V) whose absolute value is opposite to Vgh1 is set. The VGDD voltage needs to be lower than Vgh and higher than the GND voltage. Here, in order to facilitate the generated voltage circuit and reduce the circuit cost, it is set to 4 (V) which is 1/2 of the Vgh voltage. On the other hand, if the Vgl2 voltage is too low, there is a risk of leakage of the transistor 11b. Therefore, it is preferable that the Vgl2 voltage be an intermediate voltage between the VGDD voltage and the Vgl1 voltage. Here, in order to facilitate the voltage circuit and reduce the circuit cost, the VGDD voltage is set to -4 (V) having the same absolute value and the opposite polarity.

  In the above embodiment, one selected pixel row is arranged (formed) for each pixel row. The present invention is not limited to this, and one gate signal line 17a may be arranged (formed) in a plurality of pixel rows.

  FIG. 10 shows an example. In order to facilitate the description, the pixel configuration will be described mainly using the case of FIG. In FIG. 10, the gate signal line 17a simultaneously selects three pixels (16R, 16G, 16B). The symbol “R” means a red pixel relationship, the symbol “G” means a green pixel relationship, and the symbol “B” means a blue pixel relationship.

  By selecting the gate signal line 17a, the pixel 16R, the pixel 16G, and the pixel 16B are simultaneously selected to enter a data writing state. The pixel 16R writes video data from the source signal line 18R to the capacitor 19R, and the pixel 16G writes video data from the source signal line 18G to the capacitor 19G. The pixel 16B writes video data from the source signal line 18B to the capacitor 19B.

  The transistor 11d of the pixel 16R is connected to the gate signal line 17bR. The transistor 11d of the pixel 16G is connected to the gate signal line 17bG, and the transistor 11d of the pixel 16B is connected to the gate signal line 17bB. The EL element 15R of the pixel 16R, the EL element 15G of the pixel 16G, and the EL element 15B of the pixel 16B can be separately controlled on and off. That is, the EL element 15R, the EL element 15G, and the EL element 15B can individually control the lighting time and the lighting cycle by controlling the gate signal lines 17bR, 17bG, and 17bB.

  In the configuration of the display panel of FIG. 10, the R pixel 16R can be controlled to be turned on / off by applying an on / off voltage to the gate signal line 17bR. By applying an on / off voltage to the gate signal line 17bG, the G pixel 16G can be on / off controlled. By applying an on / off voltage to the gate signal line 17bB, the B pixel 16B can be on / off controlled.

  In order to realize the above driving, as shown in FIG. 11, the gate driver circuit 12bR for controlling the gate signal line 17bR, the gate driver circuit 12bG for controlling the gate signal line 17bG, and the gate signal line 17bB are controlled. The gate driver circuit 12bB to be formed may be formed or arranged.

  In the above embodiment, the source driver circuit (IC) 14 is configured by an IC mainly composed of a silicon chip. However, the present invention is not limited to this, and the output stage circuit 91 or the like (polysilicon current holding circuit) using polysilicon technology (CGS technology, low temperature polysilicon technology, high temperature polysilicon technology, etc.) directly on the array substrate 30. 92) may be formed or configured.

  FIG. 9 shows an example. An output stage circuit 91 for R, G, and B (91R for R, 91G for G, and 91B for B) and a switch S for selecting the RGB output stage circuit 91 are formed (configured) by polysilicon technology. Yes. The switch S operates by time-sharing the 1H period. Basically, the switch S is connected to the R output stage circuit 91R during the 1/3 period of 1H, is connected to the G output stage circuit 91G during the 1/3 period of 1H, and the remaining 1/3 period of 1H. The period is connected to the B output stage circuit 91B.

  As shown in FIG. 9, a source driver (circuit) 14 having a shift register circuit, a sampling circuit, and the like is connected to a source signal line 18 at an output terminal 93. The switch S made of polysilicon is switched in a time division manner and connected to the output stage circuit 91RGB. The output stage circuit 91RGB holds a current made up of RGB video data. In FIG. 9, only one stage of the polysilicon current holding circuit 92 is shown, but it goes without saying that it is actually composed of two stages.

  In FIG. 9, the switch S is connected to the R output stage circuit 91R for the 1/3 period of 1H, the 1/3 period of 1H is connected to the G output stage circuit 91G, and the remaining 1/3 period of 1H. Is connected to the B output stage circuit 91B, but the present invention is not limited to this. The period for selecting R, G, and B may be different. This is because the R, G, and B program currents Iw are different in magnitude. Since the efficiency of the EL element 15 differs between R, G, and B, the magnitude of the program current differs between R, G, and B. If the magnitude of the program current is small, it is likely to be affected by the parasitic capacitance of the source signal line 18. Therefore, it is necessary to lengthen the application period of the program current and sufficiently ensure the charge / discharge period of the parasitic capacitance of the source signal line 18. is there. On the other hand, the parasitic capacitance of the source signal line 18 is often the same for R, G, and B.

  In the above embodiment, the configuration is such that the pixels 16 corresponding to RGB are simultaneously scanned. The present invention is not limited to this configuration. An image may be displayed by individually selecting RGB without a frame (field). FIG. 12 shows an embodiment thereof.

  In FIG. 12A, the R display area 63R, the G display area 63G, and the B display area 63B are scanned from the top to the bottom of the screen (or from the bottom to the top) in one frame (one field) period. An area other than the RGB display area is a non-display area 62. That is, intermittent driving is performed. R, G, and B display areas 63 are individually intermittently displayed.

  FIG. 12B shows an embodiment in which a plurality of R, G, and B display areas 63 are generated in one field (one frame) period. This driving method is similar to the driving method of FIG. Therefore, no explanation will be required. By dividing the display area 63 into a plurality of parts in FIG. 12B, the occurrence of flicker is eliminated even at a lower frame rate.

  FIG. 13A shows the RGB display area 63 with different areas of the display area 63. Needless to say, the area of the display region 63 is proportional to the lighting period. In FIG. 13A, the R display area 63R and the G display area 63G have the same area. The area of the B display area 63B is made larger than that of the G display area 63G.

  In organic EL display panels, the light emission efficiency of B is often poor. By making the B display area 63B larger than the display areas 63 of other colors as shown in FIG. 13A, it is possible to efficiently achieve white balance. Also, white balance adjustment and color temperature adjustment can be easily realized by changing the area of the R, G, B display area 63.

  FIG. 13B shows an example in which the B display period 63B is plural (63B1, 63B2) in one field (frame) period. FIG. 13A shows a method of changing one B display area 63B. By changing it, the white balance can be adjusted well. FIG. 13B improves white balance adjustment (correction) by displaying a plurality of B display areas 63B having the same area. In addition, color temperature correction (adjustment) is improved. For example, it is effective to change the color temperature outdoors and indoors. For example, the color temperature is decreased indoors and the color temperature is increased outdoors.

  The drive system of the present invention is not limited to either FIG. 12 or FIG. 12 and 13, the R, G, and B display areas 63 are generated and intermittently displayed. As a result, the moving image blur can be eliminated, and the writing shortage to the pixel 16 is improved.

  Needless to say, FIG. 13A and FIG. 13B may be combined. For example, a drive method is implemented in which the RGB display area 63 in FIG. 13A is changed and a plurality of RGB display areas 63 in FIG. 13B are generated.

  In FIG. 6, the display area 63 is integrated into one. However, the present invention is not limited to this. For example, as shown in FIG. 14, the display area 63 and the non-display area 62 may be dispersed in a plurality.

  Further, as illustrated in FIG. 14, intermittent intervals (non-display area 62 / display area 63) are not limited to equal intervals. For example, it may be random (as a whole, the display period or the non-display period may be a predetermined value (a constant ratio)). Also, it may be different for RGB. That is, it is only necessary to adjust (set) the R, G, B display period or the non-display period to a predetermined value (a constant ratio) so that the white balance is optimal.

  The non-display area 62 is a pixel 16 area of the non-lighting EL element 15 at a certain time. The display area 63 is the pixel 16 area of the lighting EL element 15 at a certain time. The positions of the non-display area 62 and the display area 63 are shifted by one pixel row in synchronization with the horizontal synchronization signal.

  In order to facilitate the description of the driving method of the present invention, 1 / N is described on the assumption that 1F is set to 1 / N on the basis of 1F (one field or one frame). However, there is a time during which one pixel row is selected and the current value is programmed (usually, one horizontal scanning period (1H)), and it goes without saying that an error may occur depending on the scanning state. Of course, it changes from the ideal state also by the penetration voltage from the gate signal line 17a. Here, in order to facilitate the description, the description will be made in an ideal state.

  The liquid crystal display panel holds the current (voltage) written to the pixel for a period of 1F (one field or one frame). For this reason, when a moving image is displayed, there is a problem that the outline of the display image is blurred.

  The organic (inorganic) EL display panel (display device) also holds the current (voltage) written in the pixel during the period of 1F (one field or one frame). Therefore, the same problem as the liquid crystal display panel occurs. On the other hand, a display that displays an image as a set of line displays with an electron gun, such as a CRT, displays an image using the afterimage characteristics of the human eye, so that the outline blur of a moving image display image does not occur.

  In the driving method of the present invention, current is passed through the EL element 15 only during the period of 1F / N, and no current is passed during the other period (1F (N-1) / N). Consider a case where the driving method of the present invention is implemented and one point on the screen is observed. In this display state, image data display and black display (non-lighting) are repeatedly displayed every 1F. That is, the image data display state is intermittently displayed over time. When the moving image data display is viewed in the intermittent display state, the outline of the image is not blurred and a good display state can be realized. That is, a moving image display close to a CRT can be realized.

  In the driving method of the present invention, intermittent display is realized. However, when performing intermittent display, the transistor 11d only needs to be on / off controlled at a maximum of 1H period. Therefore, the main clock of the circuit is not different from the conventional one, and the power consumption of the circuit does not increase. In the liquid crystal display panel, an image memory is necessary to realize intermittent display. In the present invention, image data is held in each pixel 16. Therefore, in the driving method of the present invention, an image memory for performing intermittent display is unnecessary.

  The driving method of the present invention controls the current passed through the EL element 15 simply by turning on and off the switching transistor 11d (see FIG. 1 and the like). That is, even if the current Iw flowing through the EL element 15 is turned off, the image data is held in the capacitor 19 of the pixel 16 as it is. Therefore, if the switching element 11d and the like are turned on at the next timing and a current flows through the EL element 15, the flowing current is the same as the previously flowing current value.

  In the present invention, it is not necessary to increase the main clock of the circuit even when black insertion (intermittent display such as black display) is realized. Further, there is no need for an image memory because it is not necessary to perform time axis expansion. Further, the organic EL element 15 has a short time from application of current to light emission, and responds at high speed. Therefore, it is suitable for moving image display and can solve the problem of moving image display, which is a problem of conventional data retention type display panels (liquid crystal display panel, EL display panel, etc.) by performing intermittent display.

  Further, when the wiring length of the source signal line 18 is increased and the parasitic capacitance of the source signal line 18 is increased in a large display device, it is possible to cope with the problem by increasing the N value. When the program current value applied to the source signal line 18 is increased N times, the conduction period of the gate signal line 17b (transistor 11d) may be set to 1 F / N. Accordingly, the present invention can be applied to large display devices such as televisions and monitors.

  In current driving, it is necessary to program the capacitor 19 of the pixel with a very small current of 20 nA or less, particularly for black level image display. Therefore, if the parasitic capacitance is generated with a magnitude greater than or equal to a predetermined value, the time for programming to one pixel row (basically within 1H. However, it is limited to within 1H since two pixel rows may be written simultaneously. The parasitic capacitance cannot be charged or discharged within. If charging / discharging is not possible in the 1H period, writing into the pixel is insufficient and the resolution is not high.

  In the case of the pixel configuration of FIG. 1, as shown in FIG. 5A, the program current Iw flows through the source signal line 18 during current programming. The voltage is set (programmed) in the capacitor 19 so that the current Iw flows through the transistor 11a and the current flowing through Iw is maintained. At this time, the transistor 11d is in an open state (off state).

  Next, during a period in which a current flows through the EL element 15, the transistors 11c and 11b are turned off and the transistor 11d is operated as shown in FIG. That is, the off voltage (Vgh) is applied to the gate signal line 17a, and the transistors 11b and 11c are turned off. On the other hand, an on voltage (Vgl) is applied to the gate signal line 17b, and the transistor 11d is turned on.

  Assuming that the program current Iw is N times the current (predetermined value) that flows originally, the current Ie that flows through the EL element 15 in FIG. Therefore, the EL element 15 emits light with a luminance 10 times the predetermined value. That is, as shown in FIG. 18, as the magnification N is increased, the instantaneous display brightness B of the pixel 16 is also increased. Basically, the magnification N and the luminance of the pixel 16 are in a proportional relationship.

  In the present invention, the pixel configuration is not limited to the current program method. For example, the present invention can be applied to a voltage-programmed pixel configuration as shown in FIG. This is because displaying a predetermined period of one frame (field) with high luminance and turning off the other period is effective in improving the moving image display performance even in the voltage driving method. Even in the voltage drive system, the influence of the parasitic capacitance of the source signal line 18 cannot be ignored. Particularly in a large EL display panel, since the parasitic capacitance is large, it is effective to implement the driving method of the present invention. The above matters also apply to other embodiments of the present invention.

  As shown in FIG. 6B, the pixel row including the writing pixel row 61a is a non-lighting region 62, and the S / N (1F / N in terms of time) range of the upper screen from the writing pixel row 61a is set. The display area 63 is used (when the writing scan is from the top to the bottom of the screen, the opposite is true when the screen is scanned from the bottom to the top). In the image display state, the display area 63 has a band shape and moves from the top to the bottom of the screen.

  In the display of FIG. 6, one display area 63 moves downward from the top of the screen. When the frame rate is low, it is visually recognized that the display area 63 moves. In particular, it becomes easier to recognize when the eyelid is closed or when the face is moved up and down.

  For this problem, the display area 63 may be divided into a plurality of parts as shown in FIG. If the divided sum is an area of S (N-1) / N, it is equivalent to the brightness of FIG. Note that the divided display areas 63 do not have to be equal (equally divided). Further, the divided non-display areas 62 need not be equal.

  As described above, screen flickering is reduced by dividing display area 63 into a plurality of parts. Therefore, no flicker occurs and a good image display can be realized. The division may be made finer. However, the moving image display performance decreases as it is divided.

  FIG. 15 illustrates the voltage waveform of the gate signal line 17 and the light emission luminance of EL. As is apparent from FIG. 15, the period (1F / N) during which the gate signal line 17b is set to Vgl is divided into a plurality of numbers (the number of divisions K). That is, a period of 1 gl / (K · N) is performed K times for the period of Vgl. By controlling in this way, the occurrence of flicker can be suppressed and an image display with a low frame rate can be realized.

  It is preferable that the number of image divisions is variable. For example, this change may be detected and the value of K may be changed by the user pressing a brightness adjustment switch or turning the brightness adjustment volume. Moreover, you may comprise so that a user may adjust a brightness | luminance. You may comprise so that it may change manually or automatically by the content and data of the image to display.

  In FIG. 15 and the like, the period (1F / N) for setting the gate signal line 17b to Vgl is divided into a plurality (number of divisions K), and the period of 1F / (K · N) is executed K times for the period to set Vgl. However, this is not a limitation. The period of 1F / (K · N) may be performed L (L ≠ K) times. In other words, the present invention displays the display screen 64 by controlling the period (time) flowing through the EL element 15. Therefore, it is included in the technical idea of the present invention to execute the period of 1F / (K · N) L (L ≠ K) times. Further, the luminance of the display screen 64 can be changed digitally by changing the value of L. For example, when L = 2 and L = 3, the luminance (contrast) changes by 50%. Further, when the image display area 63 is divided, the period during which the gate signal line 17b is set to Vgl is not limited to the same period.

  FIG. 16 shows an example of a driving method for simultaneously selecting two pixel rows. Ideally, the transistors 11a of two pixels (rows) each have Iw × 5 (N = 10. That is, since K = 2, the current flowing through the source signal line 18 is Iw × K × 5 = Iw × 10) is passed through the source signal line 18. Then, the capacitor 19 of each pixel 16 is programmed and held with 5 times the current.

  Since two pixel rows (K = 2) are selected at the same time, the two driving transistors 11a operate. That is, a current of 10/2 = 5 times flows through the transistor 11a per pixel. A current obtained by adding the program currents of the two transistors 11a flows through the source signal line 18.

  For example, the write current Id is originally set to the write pixel row 61 a and a current of Iw × 10 is supplied to the source signal line 18. There is no problem in the writing pixel row 61b because normal image data is written later. The pixel row 61b has the same display as 61a during the 1H period. Therefore, at least the non-display state 62 is set to the writing pixel row 61a and the pixel row 61b selected to increase the current.

  After the next 1H, the gate signal line 17a (1) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (3) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (3) toward the source driver 14 through the source signal line 18. By operating in this way, regular image data is held in the pixel row (1).

  After the next 1H, the gate signal line 17a (2) is not selected, and the ON voltage (Vgl) is applied to the gate signal line 17b. At the same time, the gate signal line 17 a (4) is selected (Vgl voltage), and a program current flows from the transistor 11 a of the selected pixel row (4) toward the source driver 14 through the source signal line 18. By operating in this way, regular image data is held in the pixel row (2). The above operation and shift by one pixel row (of course, multiple pixel rows may be shifted. For example, if pseudo-interlace driving is used, shift by two rows will be performed. One screen is rewritten by scanning while the same image may be written in the pixel row.

  As shown in FIGS. 16A and 16B, two write pixel rows 61 (61a and 61b) are selected and sequentially selected from the upper side to the lower side of the screen 64. However, as shown in FIG. 16B, when it reaches the lower side of the screen, the writing pixel row 61a exists, but 61b disappears. That is, only one pixel row is selected. Therefore, all the current applied to the source signal line 18 is written to the pixel row 61a. Therefore, twice as much current is programmed in the pixel as compared with the pixel row 61a.

  In response to this problem, the present invention forms (arranges) a dummy pixel row 161 on the lower side of the screen 64 as shown in FIG. Therefore, when the selected pixel row is selected up to the lower side of the screen 64, the last pixel row and the dummy pixel row 161 on the screen 64 are selected. Therefore, a prescribed current is written into the write pixel row in FIG. Although the dummy pixel row 161 is illustrated as being formed adjacent to the upper end or the lower end of the display area 64, the present invention is not limited to this. It may be formed at a position away from the display area 64. Further, it is not necessary to form the switching transistor 11d, the EL element 15 and the like in FIG. 1 in the dummy pixel row 161. By not forming the panel, the size of the dummy pixel row 161 is reduced, so that the frame of the panel can be shortened.

  FIG. 17 shows the state of FIG. As apparent from FIG. 17, when the selected pixel rows are selected up to the pixel 16c row on the lower side of the screen 64, the last pixel row 161 of the screen 64 is selected. The dummy pixel row 161 is arranged outside the display area 64. That is, the dummy pixel row 161 is configured not to be lit, not to be lit, or not to be displayed as a display even when lit. For example, the contact hole between the pixel electrode and the transistor 11 is eliminated, or the EL element 15 is not formed in the dummy pixel row. Although the dummy pixel row 161 in FIG. 17 illustrates the EL element 15, the transistor 11d, and the gate signal line 17b, it is not necessary to implement the driving method. In the actually developed display panel of the present invention, the EL element 15, the transistor 11d, and the gate signal line 17b are not formed in the dummy pixel row 161. However, it is preferable to form a pixel electrode. This is because the parasitic capacitance in the pixel is not the same as that of the other pixels 16 and a difference may occur in the retained program current.

  In FIGS. 16A and 16B, the dummy pixels (rows) 161 are provided (formed or arranged) on the lower side of the screen 64, but the present invention is not limited to this. For example, when scanning upside down, the dummy pixel row 161 should be formed on the upper side of the screen 64. That is, the dummy pixel row 161 is formed (arranged) on the upper side and the lower side of the screen 64, respectively. With the configuration described above, it is possible to cope with upside down scanning of the screen.

  In the above embodiment, two pixel rows are selected simultaneously. The present invention is not limited to this. For example, a method of simultaneously selecting five pixel rows may be used. That is, in the case of simultaneous driving of five pixel rows, the dummy pixel rows 161 may be formed for four rows.

  The number of dummy pixel rows 161 may be formed as many as M-1 pixel rows selected simultaneously. For example, if the pixel rows to be selected simultaneously are 5 pixel rows, the writing pixel row 61 is 4 pixel rows. If the simultaneously selected pixel rows are 10 pixel rows, 10-1 = 9 pixel rows.

  FIG. 16 is an explanatory diagram of the arrangement positions of the dummy pixel rows when the dummy pixel row 161 is formed. Basically, the display panel is driven upside down, and dummy pixel rows 161 are arranged above and below the screen 64.

  In the above-described embodiments, one pixel row is sequentially selected and current programming is performed on the pixels, or a plurality of pixel rows are sequentially selected and current programming is performed on the pixels. However, the present invention is not limited to this. A method in which one pixel row is sequentially selected according to image data and current programming is performed on the pixel may be combined with a method in which a plurality of pixel rows are sequentially selected and current programming is performed on the pixel.

  Even if the current mirror method is one of the current programming methods, the transistor 11e as a switching element is formed or disposed between the driving transistor 11b and the EL element 15 as shown in FIG. As a result, the current flowing through the EL element 15 can be turned on and off. Therefore, the above driving method can be realized.

  In the pixel configuration described with reference to FIG. 1 and the like, the driving transistor 11 a has one configuration for each pixel 16. However, in the present invention, the driving transistor 11a is not limited to one. For example, the pixel configuration of FIG. 19 is illustrated.

  In FIG. 19, the number of transistors constituting the pixel 16 is six, and the program transistor 11an is configured to be connected to the source signal line 18 via the two transistors 11b2 and 11c. 11a1 is an embodiment configured to be connected to the source signal line 18 via two transistors 11b1 and 11c.

  In FIG. 19, the gate terminal of the driving transistor 11a1 and the gate terminal of the programming transistor 11an are made common. The transistor 11b1 operates so as to short-circuit the drain terminal and the gate terminal of the driving transistor 11a1 during current programming. The transistor 11b2 operates so as to short-circuit the drain terminal and the gate terminal of the programming transistor 11an during current programming.

  The transistor 11c is connected to the gate terminal of the driving transistor 11a1, and the transistor 11d is formed or arranged between the driving transistor 11a1 and the EL element 15, and controls the current flowing through the EL element 15. An additional capacitor 19 is formed or disposed between the gate terminal and the anode (Vdd) terminal of the driving transistor 11a1, and the source terminals of the driving transistor 11a1 and the programming transistor 11an are connected to the anode (Vdd) terminal. ing.

  As described above, by configuring the driving transistor 11a1 and the programming transistor 11an to pass through the same number of transistors, the accuracy can be improved. That is, the current flowing through the driving transistor 11a1 flows to the source signal line 18 through the transistors 11b1 and 11c. The current flowing through the programming transistor 11an flows to the source signal line 18 through the transistor 11b2 and the transistor 11c. Therefore, the current of the driving transistor 11a1 and the current of the programming transistor 11an pass through the same number of two transistors and flow to the source signal line 18.

  In FIG. 19, the driving transistor 11an is illustrated as one transistor, but the present invention is not limited to this. The driving transistor 11an may be composed of a plurality of transistors having the same channel width W, the same channel length L, or the same WL ratio. Further, it is preferable that the drive transistor 11an of the drive transistor 11a1 has the same channel width W, the same channel length L, or the same WL ratio. It is preferable to form a plurality of transistors having the same WL or WL ratio because the output variation of each transistor 11a is reduced and the variation between the pixels 16 is reduced.

  When a selection voltage (ON voltage) is applied to the gate signal line 17a, a combination of currents from the transistors 11an and 11a1 becomes the program current Iw. The program current Iw is set to a predetermined magnification of the current Ie flowing from the driving transistor 11a1 to the EL element 15.

Iw = n · Ie (n is a natural number of 1 or more)
In the above formula, the display brightness B (nt) at the maximum white raster of the display panel, the pixel area S (square millimeter) of the display panel (the pixel area is treated with RGB as one unit. Therefore, each of R, G, B If the picture element is 0.1 mm long and 0.05 mm wide, S = 0.1 × (0.05 × 3) (square millimeter)), one pixel row selection period (one horizontal scanning ( 1H) When the period) is H (milliseconds), the following conditions are satisfied. Note that the display brightness B is the maximum displayable brightness specified in the panel specification.

5 ≦ (B · S) / (n · H) ≦ 222
More preferably, the following conditions are satisfied.

10 ≦ (B · S) / (n · H) ≦ 100
Iw is a program current output from the source driver circuit (IC) 14, and a voltage corresponding to the program current is held in the capacitor 19 of the pixel 16. Ie is a current that the driving transistor 11a1 passes through the EL element 15.

  The output variations of the transistors 11a1 and 11an can be improved by forming or arranging the transistors 11an and the driving transistor 11a1 close to each other. Further, the characteristics of the transistor 11an and the transistor 11a1 may differ depending on the formation direction. Therefore, it is preferable to form in the same direction.

  When the gate signal line 17a is selected, both the driving transistor 11a1 and the programming transistor 11an are turned on. It is preferable that the current Iw1 flowing through the driving transistor 11a1 and the current Iw2 flowing through the programming transistor 11a1 are substantially matched. Most preferably, the sizes (W, L) of the programming transistor 11an and the driving transistor 11a1 are matched. That is, it is preferable to satisfy the relationship of Iw1 = Iw2 and Iw = 2Ie. Of course, satisfying the relationship of Iw1 = Iw2 is not limited to matching the transistor sizes (W, L), but may be matched by changing the size. This can be easily realized by adjusting the WL of the transistor. If approximately Iw2 / Iw1 = 1, the sizes of the transistors 11b1 and 11b1 can be configured or formed to be substantially the same.

  It should be noted that Iw2 / Iw1 preferably satisfies the relationship of 1 or more and 10 or less. Iw2 / Iw1 preferably satisfies a relationship of 1 or more and 10 or less. More preferably, the relationship of 1.5 to 5 is preferably satisfied.

  When Iw2 / Iw1 is 1 or less, the effect of improving the influence of the parasitic capacitance of the source signal line 18 is hardly expected. On the other hand, if Iw2 / Iw is 10 or more, the relationship between Ie and Iw varies from pixel to pixel, and a uniform image display cannot be realized. In addition, the transistor 11b is greatly affected by the on-resistance, and pixel design becomes difficult.

  When the current Iw2 flowing through the programming transistor 11an is larger than the current Iw1 flowing through the driving transistor 11a1 (Iw2> Iw1), the on-resistance of the switching transistor 11b2 is set higher than the on-resistance of the switching transistor 11b1. Need to be smaller. This is because the switching transistor 11b2 needs to be configured so that a current larger than that of the transistor 11b1 flows to the voltage of the same gate signal line 17a.

  That is, it is necessary to match the magnitude of the transistor 11b1 with respect to the magnitude of the output current of the driving transistor 11a1 and the magnitude of the transistor 11b2 with respect to the magnitude of the output current of the programming transistor 11an.

  In other words, it is necessary to change the on-resistance of the transistor 11b with respect to the program current Iw2 and the program current Iw1. Further, it is necessary to change the sizes of the transistors 11b1 and 11b2 with respect to the program current Iw2 and the program current Iw1.

  If the program current Iw2 is larger than the program current Iw1, the on-resistance of the transistor 11b2 needs to be smaller than the on-resistance of the transistor 11b1 (in the case where the gate terminal voltages of the transistor 11b1 and the transistor 11b2 are the same). If the program current Iw2 is larger than the program current Iw1, the on-current (Iw2) of the transistor 11b2 needs to be larger than the on-current (Iw1) of the transistor 11b1 (when the gate terminal voltages of the transistor 11b1 and the transistor 11b2 are the same) Is).

  When Iw2: Iw1 = n: 1, an on-voltage is applied to the gate signal line 17a, and when the transistor 11b1 and the transistor 11b2 are turned on, the on-resistance of the transistor 11b2 is R2, and the on-resistance of the transistor 11b1 is R1. At this time, R2 is configured to satisfy the relationship of R1 / (n + 5) or more and R1 / (n) or less. To configure means to form, arrange or operate the transistor 11b in a predetermined size. However, n is a value larger than 1.

  The above item is an explanation of the on-resistance R of the transistor 11b1 and the transistor 11b2 or the program current Iw. Accordingly, any configuration is possible as long as the pixel configuration is realized so as to satisfy the above-described conditions. For example, when the gate signal line 17 connected to the gate terminal of the transistor 11b1 and the gate signal line 17 connected to the gate terminal of the transistor 11b2 are different signal lines, the voltage applied to each gate signal line is changed. As a result, the on-resistance and the like can be changed, and the conditions of the present invention can be satisfied.

  FIG. 20 is an explanatory diagram of the operation of the pixel configuration of FIG. FIG. 20A shows a current program state, and FIG. 19B shows a state in which current is supplied to the EL element 15. Needless to say, intermittent display may be performed by turning on and off the transistor 11d in the state of FIG.

  In FIG. 20A, an on voltage is applied to the gate signal line 17a, and the transistors 11b1, 11b2, and 11c are turned on. The transistor 11a1 supplies a current Ie, the transistor 11an supplies a current Iw-Ie, and the combined current Iw becomes a program current for the source driver Ic. With the above operation, a voltage corresponding to the program current Iw is held in the capacitor 19. During current programming, the transistor 11d is held in the off state (the off voltage is applied to the gate signal line 17b).

  The case where a current is passed through the EL element 15 is set to the operation state shown in FIG. An off voltage is applied to the gate signal line 17a, and an on voltage is applied to the gate signal line 17b. In this state, the transistors 11b1, 11b2, and 11c are turned off, and the transistor 11d is turned on. An Ie current is supplied to the EL element 15.

  The above embodiment is mainly an embodiment of the modification of FIG. The present invention is not limited to this, and can be applied to a pixel configuration of a current mirror as shown in FIG. Needless to say, the present invention can also be applied to FIGS. 21 (a), 21 (b) and 21 (c).

  In order to facilitate understanding, description will be made assuming that the video data and the program current are converted in a proportional relationship. Actually, video data and program current can be converted more easily. This is because the unit current of the unit transistor 224 corresponds to 1 of the video data as shown in FIG. Furthermore, the unit current can be easily adjusted to an arbitrary value by adjusting the reference current circuit. This is because the reference current is provided for each of the R, G, and B circuits, and white balance can be achieved over the entire gradation range by adjusting the reference current circuit to the RGB circuit. This is a synergistic effect of the current program method and the configuration of the source driver circuit (IC) 14 and the display panel of the present invention.

  The EL display panel is characterized in that the program current and the light emission luminance of the EL element 15 have a linear relationship. This is a major feature of the current programming method. That is, the emission luminance of the EL element 15 can be adjusted linearly by controlling the magnitude of the program current.

  In the driving transistor 11a, the voltage applied to the gate terminal and the current flowing through the driving transistor 11a are nonlinear (often a square curve). Therefore, in the voltage program method, the program voltage and the light emission luminance are in a non-linear relationship, and the light emission control is extremely difficult. Compared with the voltage program, the light emission control is extremely easy in the current program method.

  Hereinafter, the source driver circuit (IC) 14 of the present invention will be described with reference to FIGS. In the source driver circuit (IC) 14, output stages (transistor groups) 251c corresponding to the number of output terminals are formed or arranged. In each output stage 251c, a transistor (current source (one unit) current) 224 corresponding to the number of bits of the video signal is formed or arranged. For example, when the video signal is 6 bits (D0 to D5), 2 6 −1 = 63 transistors 224 are formed. When the video signal is 8 bits (D0 to D7), 2 8 −1 = 255 transistors 224 are formed.

  Each transistor 224 is arranged for each video data bit (D0 to D5). One transistor 224 is arranged for the D0 bit. Two transistors 224 are arranged in the D1 bit. Four transistors 224 are arranged for the D2 bit, eight transistors 224 are arranged for the D3 bit, and sixteen transistors 224 are arranged for the D4 bit. Similarly, 32 transistors 224 are arranged in the D5 bit.

  Whether or not the output current of the transistor 224 of each bit is output to the output terminal 93 is realized by on / off control by the analog switch 221 (221a to 221f). The analog switches 221a to 221f correspond to each bit (6 bits as an example) of the video signal. When the switch 221a corresponding to the D0 bit is closed, one unit current is output (input) from the output terminal 93. A source signal line 18 is connected to the output terminal 93. Similarly, when the switch 221b corresponding to the D1 bit is closed, 2 unit currents are output (input) from the output terminal 93. Hereinafter, when the switch 221c corresponding to the D2 bit is closed, 4 unit current is output (input) from the output terminal 93, and when the switch 221c corresponding to the D3 bit is closed, 8 unit current is output (input) from the output terminal 93. When the switch 221d corresponding to the D4 bit is closed, 16 unit current is output (input) from the output terminal 93, and when the switch 221c corresponding to the D5 bit is closed, 32 unit current is output (input) from the output terminal 93. Is done. As described above, the switch 221 is digitally closed or opened corresponding to the bit of the video signal, and a current (program current) is output from the output terminal 93 according to the video signal.

  The program current flows through the internal wiring 222. The potential Vw of the internal wiring 222 becomes the potential of the source signal line 18. The potential of the source signal line 18 is the gate voltage of the driving transistor 11a of the pixel 16 during current programming.

  The unit transistor 224 forms a current mirror circuit with the transistor 228b. In FIGS. 22 and 23, the unit transistor 224 and one transistor 228b constituting the current mirror circuit are illustrated, but in actuality, it is configured (formed) by a plurality of transistors (transistor groups) (see FIG. 28). That). The transistor 228b and the transistor group 251c constitute a current mirror circuit with a predetermined current mirror ratio.

  A reference current Ic flows through the transistor 228b, and a current corresponding to the current mirror ratio of the reference current Ic flows through the unit transistor 224. All the 63 unit transistors 224 in FIG. 22 output the same unit current. However, in order for the unit current to flow, it is necessary to close the corresponding switch 221 and configure a current path.

  The reference current Ic is generated by a constant current circuit including an operational amplifier 231a and a resistor R1. The reference current Ic is made constant by stabilizing and increasing the accuracy of the reference voltage Vs. The voltages Vi and Vs that set the reference current Ic are applied across the resistor R1. Therefore, the reference current Ic = (Vs−Vi) / R1. The reference current Ic can be set for each RGB. That is, a transistor group 251c is configured (formed) for each RGB. A current Ic flowing through the transistor 228b of the transistor group 251c can be set (adjusted).

  FIG. 23A shows a circuit configuration for generating the reference current Ic using the Vs voltage. In FIG. 23B, a basic current is generated by using a resistor R1 disposed (inserted) between GND and the negative terminal of the operational amplifier 231a, and is turned back by a current mirror circuit including a transistor 232b and a transistor 228a. In this configuration, the reference current Ic is supplied. In FIG. 23B, it is easier to adjust the magnitude of the reference current Ic. However, since the current mirror circuit composed of the transistor 232b and the transistor 228a is folded back, variations tend to occur.

  In the present invention, as shown in FIG. 22B, a plurality of unit transistors 224 are formed or arranged in each bit (excluding the least significant bit). However, the present invention is not limited to this. For example, it goes without saying that one transistor 224 that outputs a current corresponding to each bit may be formed or arranged in each bit.

  In the case of 64 gradations (6 bits for each of RGB), 63 unit transistors 224 are formed. Therefore, in the case of 256 gradations (8 bits for each of RGB), 255 unit transistors 224 are required.

  The current driving method has a characteristic effect that current can be added. Further, in the unit transistor 224, if the channel length L is fixed and the channel width W is halved, there is a characteristic effect that the current flowing through the unit transistor 224 is approximately halved. Similarly, if the channel length L is made constant and the channel width W is made 1/4, there is a characteristic effect that the current flowing through the unit transistor 224 becomes about 1/4.

  FIG. 24A shows a configuration of a transistor group 251c in which unit transistors 224 having the same size are arranged for each bit. For ease of explanation, it is assumed in FIG. 24A that 63 unit transistors 224 are configured and a 6-bit transistor group 251c is configured (formed). Further, FIG. 24B is assumed to be 8 bits.

  In FIG. 24B, the lower 2 bits (indicated by A) are composed of transistors having a size smaller than that of the unit transistor 224. The 0th bit of the minimum bit is formed by 1/4 of the channel width W of the unit transistor 224 (indicated by the unit transistor 224b). The first bit is formed with a half of the channel width W of the unit transistor 224 (indicated by the unit transistor 224a). The unit transistor 224a may be formed of two unit transistors 224b that are ¼ of the channel width W of the unit transistor 224.

  In the above embodiment, the W of the unit transistor 224b is ¼ of the W of the unit transistor 224. For example, if the W of the unit transistor 224 is 6 μm, the W of the unit transistor 224b is 1/4 of 1.5 μm. However, this is a case where ideal characteristics are exhibited. In the present invention, it is larger than 1.5 μm. That is, it is increased to 2.0 μm or the like. By increasing the size, a current that is four times that of the unit transistor 224b matches the current of the unit transistor 224. The above items will be described in more detail later.

  The gate terminals of the unit transistors 224a, 224b, and 224 are connected to the same gate wiring 222. The gate wiring 223 is connected to the gate terminal of the transistor 228b.

  As described above, the lower 2 bits are formed by unit transistors (224a, 224b) having a size smaller than that of the upper unit transistor 224. Further, the number of regular unit transistors 224 is 63, which is not changed. Therefore, even if the bit number is changed from 6 bits to 8 bits, the formation area of the transistor group 251c is not significantly different between FIG. 24 (a) and FIG. 24 (b).

  As shown in FIG. 24B, the size of the transistor group 251c in the output stage does not increase even when the 6-bit specification is changed to the 8-bit specification because the current can be added. This is because if the length L is kept constant and the channel width W is 1 / n, the current flowing through the unit transistor 224 is approximately 1 / n.

  Further, as illustrated in FIG. 24B, when the transistor size is reduced as in the unit transistors 224a and 224b, the output current variation is also increased. However, no matter how large the variation is, the output currents of the unit transistors 224a or 224b are added. Therefore, the 8-bit specification of FIG. 24B can realize higher gradation output than the 6-bit specification of FIG. Of course, since the output variations of the unit transistors 224a and 224b are large, there is a possibility that accurate 8-bit display cannot be realized. However, it is possible to realize a high-definition display as compared with FIG.

  Actually, even if the channel width W is halved, the output current is not exactly halved. Some correction is required. As a result of the examination, when the channel width W is halved, the output current becomes ½ or less when the gate terminal voltages of the transistors are the same. Therefore, in the present invention, when changing the size of the transistor constituting the lower bit and the size of the transistor constituting the upper bit, the transistor size is set as follows.

  First, the unit transistor 224 of the source driver circuit (IC) 14 is configured with a small shape such as two types of sizes. The channel lengths L of the plurality of unit transistors 224 are the same. That is, only the channel width W is changed. The ratio of the first unit output current of the first unit transistor to the second unit output current of the second unit transistor is n (first unit output current: second unit output current = 1: n, where , N is a value smaller than 1), the channel width W1 of the first unit transistor <the channel width W2 × n × a (a = 1) of the second unit transistor.

  When W1 × n × a = W2, it is preferable that the relationship of 1.05 <a <1.3 is satisfied. In the correction a, a correction coefficient can be easily grasped by forming and measuring a test transistor.

  In the present invention, a small unit transistor smaller than the unit transistor 224 of the upper bit is formed or arranged in order to produce (configure) the lower bit. This concept of small means that it is smaller than the output current of the unit transistor 224 constituting the upper bit. Therefore, not only the channel width W is smaller than that of the unit transistor 224, but also the case where the channel length L is also small is included. Other shapes are also included.

  FIG. 24 shows a plurality of types of unit transistors 224 constituting the transistor group 251c. In FIG. 24, there are two types. This is because, as described above, when the size of the unit transistor 224 is different, the magnitude of the output current is not proportional to the shape, so that the design becomes difficult. Therefore, the size of the unit transistor 224 included in the transistor 251c is preferably two types for low gradation and high gradation. However, the present invention is not limited to this. Needless to say, there may be three or more types.

  As shown in FIG. 43, the gate terminals of the unit transistors 224 constituting the transistor group 251c are connected by a single gate wiring 223. The output current of the unit transistor 224 is determined by the voltage applied to the gate wiring 223. Therefore, if the unit transistors 224 in the transistor group 251c have the same shape, each unit transistor 224 outputs the same unit current.

  The present invention is not limited to the common gate wiring 223 of the unit transistors 224 constituting the transistor group 251c. For example, it may be configured as shown in FIG. In FIG. 25A, a unit transistor 224 that forms a current mirror circuit with a transistor 228b1, and a unit transistor 224 that forms a current mirror circuit with a transistor 228b1 are arranged.

  The transistor 228b1 is connected to the gate wiring 223a. The transistor 228b2 is connected to the gate wiring 223b. In FIG. 25A, the uppermost unit transistor 224 is LSB (0th bit), and the second stage two unit transistors 224 are the first bit and the third stage four unit transistors. 224 is the second bit. The eight unit transistors 224 in the fourth stage set are the third bit.

  In FIG. 25A, by changing the voltage applied to the gate wiring 223a and the gate wiring 223b, the output current of each unit transistor 224 is supplied to the gate wiring 223 even if the size and shape of each unit transistor 224 are the same. It can be changed (changed) by the applied voltage.

  In FIG. 25A, the unit transistors 224 have the same size and the like, and the voltages of the gate wirings 223a and 223b are different. However, the present invention is not limited to this. The unit transistors 224 may have the same output current by changing the sizes of the unit transistors 224 and adjusting the voltages of the gate wirings 223a and 223b to be applied.

  In FIG. 24, the size of the unit transistor 224 constituting the low gradation bit is made smaller than that of the unit transistor 224 constituting the high gradation. As the size of the unit transistor 224 decreases, the output variation increases. In order to solve this problem, the unit transistor 224 having a low gradation actually has a channel length L larger than that of the high gradation, so that the area of the unit transistor 224 is not reduced, thereby suppressing variations.

  The minimum output current of the unit transistor 224 of the source driver circuit (IC) 14 is 0.5 nA or more and 10 nA. In particular, the minimum output current of the unit transistor 224 is preferably 2 nA or more and 20 nA. This is to ensure the accuracy of the unit transistors 224 constituting the unit transistor group 251c in the driver IC 14.

  By configuring as described above, the output variation of each output terminal 93 can be reduced. In particular, the adjacent variation between the terminals can be reduced. Furthermore, in order to reduce the output variation, the configuration is as shown in FIG.

  The difference between FIG. 153 and FIG. 26, FIG. 27, FIG. 29, FIG. 31 and the like is the configuration having the output selection circuit 1531 on the output side of the output stage 251c. The output selection circuit 1531 mainly comprises a selection circuit and an analog switch. The output selection circuit 1531 can output the output current of an arbitrary output stage 251c from an arbitrary output terminal 93. For example, the output current of the output stage 251c1 can be output to the output terminal 93a, and can also be output to the output terminals 93c and 93n. That is, the program current of the output stage 251c1 can be output to any output terminal 93. The switching timing (operation timing) of the output selection circuit 1531 is controlled by the controller 722. For example, the output selection circuit 1531 can control the output signal of the output stage 251a to be output to the output terminal 93a in the first half of one horizontal scanning period and to the output terminal 93b in the second half. Further, the output selection circuit 1531 can change the operation according to the gradation number set in the output stage 251c.

  It goes without saying that the output selection circuit 1531 can be operated so that an output signal (voltage or current) from one or more output stages 251c is output from one or more output terminals 93. For example, the output currents of the output stages 251c1, 251c3, and 251c5 can be combined and output to the output terminal 93a. Further, the output currents of the output stages 251c1, 251c3, and 251c5 can be combined and output to both the output terminal 93a and the output terminal 93b. Further, the output current of the output stage 251c1 can be combined and output to both the output terminal 93a and the output terminal 93b.

  The output selection circuit 1531 of the present invention will be described assuming that the output stage 251c is a current output, but the present invention is not limited to this. For example, the output stage 251c may be a voltage output. That is, a case where the source driver circuit (IC) 14 performs voltage driving like a liquid crystal display panel is exemplified. The same applies when the EL display panel is voltage driven. Further, the output selection circuit 1531 is described assuming that the source driver circuit (IC) 14 is configured as a silicon chip and is built in the chip 14, but is not limited thereto. For example, the output selection circuit 1531 may be directly formed on the glass substrate 30 by polysilicon technology or the like. Moreover, you may form or comprise in another chip | tip.

  Since the output stage 251c includes the unit transistor 224, the output current variation of each output stage 251 is small. However, a source driver circuit (IC) chip has gentle mobility characteristics and undulations of Vt characteristics. This undulation changes the output current from the output stage 251c.

  In order to prevent the influence of this undulation, the formation region of the unit transistor 224 constituting one output stage 251c may be formed in a size (range or area) that spans the undulation period. However, in this case, the unit transistor 224 is formed in a large area, resulting in a huge chip size. In the present invention, the current to be output to the output terminal 93 is selected (selected) from a relatively wide area in the chip 14 and formed (generated) by changing the selected area under a certain condition. For example, a case where a 38th gradation program current is output to the output terminal 93a and a 32nd gradation program current is written to a certain pixel 16 is exemplified. In the first field (frame), the output selection circuit 1531 controls the output stage 251c1 to output the 38th gradation program current, and the output stage 251c1 outputs the program current from the output terminal 93a.

  In the next field (frame), control is performed so that the program current of the 38th gradation is output from the output stage 251c2, and the program current is output from the output stage 251c2 from the output terminal 93a. In the next field (frame), the output selection circuit 1531 controls the output stage 251c3 to output the 38th gradation program current, and outputs the program current from the output stage 251c3 from the output terminal 93a. . Thereafter, this operation is sequentially repeated. Also, from each output terminal 93, the gradation of each output stage 251 c is set according to the corresponding (written) pixel, and a program current is output to the source signal line 18.

  FIG. 154 summarizes the above operations in a table. FIG. 154 shows the relationship between the output terminal 93 and the horizontal scanning period (H). However, in order to facilitate understanding, description regarding gradation is omitted. That is, the output terminal 93 simply indicates from which output stage 251 c the program current is output to each H.

  In FIG. 154, the output stage 251c1 is selected at the 1H level by the output selection circuit 1531 as the output terminal 93a. In the table, 1 of the output stage 251c1 is illustrated. The output stage 251c2 is selected at 2H (shown as 2 in the table), and the output stage 251c3 (shown at 3 in the table of FIG. 154) is selected at 3H. Further, in the next 4H, the output stage 251c4 is selected (4 is shown in the table of FIG. 154), and in the 5H, the output stage 251c5 is selected.

  Similarly, for the output terminal 93b, the output stage 251cn (the final output stage) is selected at the 1H level by the output selection circuit 1531. In the table, n of the output stage 251cn is illustrated. Output stage 251c1 is selected at 2H (shown as 1 in the table), and output stage 251c2 (shown at 2 in the table of FIG. 154) is selected at 3H. Further, the output stage 251c3 is selected in the next 4H (3 is shown in the table of FIG. 154), and the output stage 251c4 is selected in the 5H. The same applies hereinafter.

  Similarly, for the output terminal 93c, the output stage 251cn-1 is selected at the 1H level by the output selection circuit 1531. In the table, n-1 is illustrated. The output stage 251cn is selected at 2H (shown as n in the table), and the output stage 251c1 (shown at 1 in the table of FIG. 154) is selected at 3H. Further, in the next 4H, the output stage 251c2 is selected (2 is shown in the table of FIG. 154), and in the 5H, the output stage 251c3 is selected. The same applies hereinafter.

  As described above, for example, the program current from the output stage 251 c different for each H is output to the output terminal 93 a and sequentially applied to the pixels via the source signal line 18.

  For easier understanding, the output terminal 93a will be described as an example. At 1H, the output stage applied (output) to the source signal line 18a (source signal line connected to the output terminal 93a) is 251c1. At 1H, the signal from the output stage 251c1 is applied to the pixel in the first pixel row and connected to the source signal line 18a. At 2H, the output stage applied (output) to the source signal line 18a (source signal line connected to the output terminal 93a) is 251c2. In 2H, the signal from the output stage 251c2 is applied to the pixel in the second pixel row and connected to the source signal line 18a. Similarly, the output stage applied to (output to) the source signal line 18a (the source signal line connected to the output terminal 93a) is 251c3 at the 3rd H. In 3H, the signal from the output stage 251c3 is applied to the pixel in the third pixel row and connected to the source signal line 18a. The above operation is sequentially performed on the pixels in the final m pixel row (m is the final pixel row number). The pixel is selected by the gate driver circuit 17a.

  When the above operation is performed up to the final pixel row, the above operation is performed on the first pixel row. However, an output signal other than the output stage 251c1 is applied to the pixels in the first pixel row. For example, the output signal of the output stage 251c2 is applied. That is, the output signal of the output stage 251c that is different for each field (frame) is applied, and the signal written to each pixel 16 is averaged so that the output unevenness distribution of the output stage 251c is not reflected. The signal from the output stage 251c written to each pixel 16 is preferably randomized, but if this is not possible, control is performed so that the outputs of at least two output stages 251c are written and averaged. The above matters are similarly applied to the pixels after the pixel in the second pixel row. In addition, the same operation is performed for other than the output terminal 93a (93b to 93n).

  As described above, basically, the output of one output stage 251 c and one output terminal are selected by the output selection circuit 1531, and the output of each output stage 251 c is applied to the source signal line 18. The signal output from the source signal line 18 is latched and held in the latch circuit 351 so that a normal (normal) image display is obtained.

  When one screen or a fixed display cycle is completed, the order of the output stage 521c output from the output terminal 93 is preferably changed. For example, the state of the table in FIG. 154 is the first frame. In the next second frame, the selection state (251c1, 251c2, 251c3, 251c4,...) Of the output stage 251c of the output terminal 93a in the table of FIG. 251cn, 251c1, 251c2, 251c3, 251c4. The selection state (251cn, 251c1, 251c2, 251c3, 251c4,...) Of the output stage 251c of the output terminal 93b in the table of FIG. 154 is changed to the selection state (251cn-1, 251cn) of the output stage 251c of the output terminal 93c. , 251c1, 251c2, 251c3, 251c4,. The selection state (251cn-1, 251cn, 251c1, 251c2, 251c3, 251c4,...) Of the output stage 251c of the output terminal 93c in the table of FIG. 154 is the selection state (251cn) of the output stage 251c of the output terminal 93d. -2, 251cn-1, 251cn, 251c1, 251c2, 251c3, 251c4. Thereafter, the same shift is performed.

  In the next third frame, the selection state (251cn, 251c1, 251c2, 251c3, 251c4,...) Of the output stage 251c of the output terminal 93a is changed to the selection state (251cn-1) of the output stage 251c of the output terminal 93b. , 251cn, 251c1, 251c2, 251c3, 251c4,. The selection state of the output stage 251c of the output terminal 93b (251cn-1, 251cn, 251c1, 251c2, 251c3, 251c4,...) And the selection state of the output stage 251c of the output terminal 93c (251cn-1, 251cn− 1, 251cn, 251c1, 251c2, 251c3, 251c4. The selection state of the output stage 251c of the output terminal 93c (251cn-2, 251cn-1, 251cn, 251c1, 251c2, 251c3, 251c4,...) And the selection state of the output stage 251c of the output terminal 93d (251c− 3, 251cn-2, 251cn-1, 251cn, 251c1, 251c2, 251c3, 251c4. Thereafter, the same shift is performed.

  In the present invention, for ease of explanation, the state output from the output terminal 93 in one frame or one field is described as being replaced, but the present invention is not limited to this. It may be replaced by a plurality of frames or fields. Moreover, you may replace every several pixel rows (multiple horizontal scanning periods). Moreover, it is not limited to a frame or a pixel row (horizontal scanning period), and may be exchanged at a constant cycle or a random cycle. It goes without saying that the above matters also apply to other embodiments of the present invention.

  By shifting, the display state of the screen 94 is not affected by the characteristics of the output stage 251c, and a uniform display can be realized. Other methods are also exemplified for the shift method.

  For example, the states of the output terminal 93a and the output terminal 93n are switched for each frame. The states of the output terminal 93b and the output terminal 93n-1 are switched. The states of the output terminal 93c and the output terminal 93n-2 are switched. The same applies to the following. That is, the left and right sides of the screen are switched.

  Other methods are also exemplified. For example, the states of the odd-numbered output terminals 93 and the even-numbered output terminals 93 are switched for each frame. Of course, you may replace at random.

  In the first frame, the states of the output terminal 93a and the output terminal 93b are switched. In the next second frame, the states of the output terminal 93a and the output terminal 93c are switched. In the next third frame, the states of the output terminal 93a and the output terminal 93d are switched. In the next fourth frame, the output terminal 93a and the output terminal 93ce state are switched. Hereinafter, a method of replacing other output terminals in the same manner is exemplified.

  In odd-numbered frames such as the first and third frames, the odd-numbered output terminals 93 are switched and the even-numbered output terminals 93 are switched. In the even-numbered frames such as the second and fourth frames, a method of switching between adjacent odd-numbered and even-numbered output terminals 93 is exemplified.

  In the source driver circuit (IC) 14, the characteristic period is distributed with a period of 4 mm to 8 mm. This occurs due to a diffusion process during IC manufacturing. Therefore, the replacement range of the output terminal 93 is performed in a range of 4 mm or more. For example, when the formation length of the output stages 251a to 251n is 20 mm and there is a possibility that the characteristic distribution may occur at a cycle of 4 mm, the output terminal 93 and the output stage 251c are at least within a range of 20/5 = 5 blocks or less. It is preferable to replace the connection by the output selection circuit 1351.

  In the above description, when the above operation is performed up to the last pixel row, and the same operation is performed on the first pixel row, the present invention is not limited to this. For example, one cycle may be completed before the last pixel row minus one pixel row, and the next cycle may be started from the last pixel row. That is, if the output terminal 93a is exemplified, a signal from the output stage 251c1 is applied to the pixels in the first pixel row. A signal from the output stage 251c2 is applied to the pixels in the second pixel row, a signal from the output stage 251c3 is applied to the pixels in the third pixel row, and an output stage 251c4 is applied to the pixels in the fourth pixel row. The signal from is applied. If the above operation is sequentially performed and a signal of the output stage 251n is applied to the pixel line immediately before the last pixel line, for example, the signal of the output stage 251c1 is applied to the final pixel line. Therefore, the signal from the output stage 251c2 is applied to the pixels in the first pixel row which is the next frame. A signal from the output stage 251c3 is applied to the pixels in the second pixel row, and a signal from the output stage 251c4 is applied to the pixels in the third pixel row. By driving in this manner, the output stage 251c is selected with a shift of one pixel row or more in the frame (field) cycle, and the output stage 251c applied to each pixel is changed over a long period of time. be able to. Therefore, each pixel 16 is driven by signals from a number of output stages 251c, and the image display is made uniform. Note that the same control is performed on the other output terminals 93.

  Further, after the selection from the first pixel row to the last pixel row on the screen, the output stage 251c selected in the direction from the last pixel row to the first pixel row may be changed. That is, if the output terminal 93a is exemplified, a signal from the output stage 251c1 is applied to the pixels in the first pixel row. A signal from the output stage 251c2 is applied to the pixels in the second pixel row, a signal from the output stage 251c3 is applied to the pixels in the third pixel row, and an output stage 251c4 is applied to the pixels in the fourth pixel row. The signal from is applied. If the above operation is sequentially performed and the signal of the output stage 251n is applied to the final pixel row, for example, the signal from the output stage 251cn is applied to the pixel of the first pixel row which is the next frame. . A signal from the output stage 251cn-1 is applied to the pixels in the second pixel row, and a signal from the output stage 251cn-3 is applied to the pixels in the third pixel row. By driving in this way, the output stage 251c applied to each pixel can be changed over a long period in a frame (field) cycle. Therefore, each pixel 16 is driven by signals from a number of output stages 251c, and the image display is made uniform. Note that the same control is performed on the other output terminals 93.

  The order of the output stage 251c that sequentially selects the output terminals 93 may be randomized. Further, the output stage 251c may be selected by skipping 2 or skipping 3 or more.

  Needless to say, the above items or methods can also be applied to the methods of FIGS. 158 to 164.

  Note that the number of output stages 251 is equal to or greater than the number of dots in the row direction (number of source signal lines 18), and the required number (basically the number of source signal lines 18). And an output signal from the output stage 251c may be applied to each source signal line 18.

  In the above embodiment, the output stages 251 for R, G, and B are not described, but an output selection circuit 1531 is also formed or configured for the output of each output stage 251c for R, G, and B. . Under the control of the R, G, and B output selection circuits 1531, signals output from the output terminals 93 are selected and output from the output stage 251c. The present invention is not limited to this, and an output selection circuit 1531 common to R, G, and B is formed or configured so that the output stage 251c is selected without discrimination between RGB and output from each output terminal 93. Needless to say, it may be configured.

  Other configurations are the same as those of FIG. 26, FIG. 27, FIG. 29, FIG.

  Hereinafter, other embodiments of the present invention will be described with reference to the drawings. FIG. 155 summarizes the second embodiment of the present invention in a table. The circuit configuration is the same as or similar to that in FIG. FIG. 155 shows the relationship between the output terminal 93 and the horizontal scanning period (H), as in FIG. The output terminal 93 indicates from which output stage 251c the program current is output to each H.

  In FIG. 155, the output stage 251c1 is selected at the 1H level by the output selection circuit 1531 as the output terminal 93a. The output stage 251c3 is selected at 2H, and the output stage 251c5 is selected at 3H. Further, the output stage 251c7 is selected in the next 4H, and the output stage 251c9 is selected in the 5H. That is, the odd-numbered output stage 251c is sequentially selected from the output terminal 93a and applied to each pixel 16.

  Similarly, the output stage 251cn is selected at the 1H level by the output selection circuit 1531 for the output terminal 93b. The output stage 251c2 is selected at 2H, and the output stage 251c4 is selected at 3H. Further, the output stage 251c6 is selected in the next 4H, and the output stage 251c8 is selected in the 5H. That is, the even-numbered output stage 251c is sequentially selected for the output terminal 93b and applied to each pixel 16.

  For the output terminal 93c, the output stage 251cn-1 is selected at the 1H level by the output selection circuit 1531. The output stage 251c1 is selected at 2H, and the output stage 251c3 is selected at 3H. Further, the output stage 251c5 is selected in the next 4H, and the output stage 251c7 is selected in the 5H. That is, an odd-numbered output stage 251c delayed by 1H from the output terminal 93a is selected as the output terminal 93c and applied to each pixel 16.

  As in the embodiment of FIG. 155, the odd-numbered output terminal 93 is selected to output the odd-numbered output stage 251c, and the even-numbered output terminal 93 is selected to output the even-numbered output stage 251c. By being configured to output, the circuit configuration of the output selection circuit 1531 and the configuration of the latch circuit for sequentially latching the video signal can be simplified, the circuit scale can be reduced, and the cost can be reduced. Since other operations are the same as or similar to those in FIG.

  The above embodiment has been described on the assumption of progressive display. FIG. 157 shows an example in the case of interlaced display. In interlaced display, one frame is composed of an odd field and an even field, and a one-screen display is realized.

  FIG. 157 shows the operation of the output selection circuit 1531 for interlace display. In FIG. 157, in the even field (FIG. 157 (a)), it is assumed that the odd-numbered pixel rows are sequentially selected and the image is rewritten, and in the odd field (FIG. 157 (b)), the even-numbered pixel. Assume that rows are selected sequentially and the image is rewritten.

  In the even number F (even field) in FIG. 157 (a), the output stage 251c1 is selected for the output terminal 93a by the output selection circuit 1531 at the 1H level. The output stage 251c2 is selected at the 3rd H. The output stage 251c3 is selected at the 5th H. Further, in the next 7H, the output stage 251c4 is selected, and in the 9H, the output stage 251c5 is selected.

  Similarly, the output stage 251cn is selected at the 1H level by the output selection circuit 1531 for the output terminal 93b. In the 3rd H, the output stage 251c1 is selected. The output stage 251c3 is selected at the 5th H. Further, in the next 7H, the output stage 251c4 is selected, and in the 9H, the output stage 251c5 is selected. The same applies to the output terminals 93c.

  In the odd number F (odd field) of FIG. 157 (b), the output stage 251c1 is selected at the second H by the output selection circuit 1531 for the output terminal 93a as in the even field. In the 4th H, the output stage 251c2 is selected. The output stage 251c3 is selected at the 6th H. Further, the output stage 251c4 is selected in the next 8H, and the output stage 251c5 is selected in the 10H.

  Similarly, for the output terminal 93b, the output stage 251cn is selected at the second H by the output selection circuit 1531. The output stage 251c1 is selected at the 4th H. The output stage 251c3 is selected at the 6th H. Further, the output stage 251c4 is selected in the next 8H, and the output stage 251c5 is selected in the 10H. The same applies to the output terminals 93c. Other operations, configurations, and the like are the same as or similar to those in FIG.

  As in the embodiment of FIG. 157, by making the selection of the output stage 251c output from each output terminal 93 the same in the odd field and the even field, the circuit scale can be reduced and the cost can be reduced. Can do.

  Obviously, a method as shown in FIG. In the even number F (even field) in FIG. 156 (a), the output stage 251c2 is selected at the 1H level by the output selection circuit 1531 as the output terminal 93a. The output stage 251c4 is selected at the 3rd H. The output stage 251c6 is selected at the 5th H. Further, in the next 7H, the output stage 251c8 is selected, and in the 9H, the output stage 251c10 is selected.

  Similarly, the output stage 251cn is selected at the 1H level by the output selection circuit 1531 for the output terminal 93b. The output stage 251c2 is selected at the 3rd H. In the 5th H, the output stage 251c4 is selected. Further, in the next 7H, the output stage 251c6 is selected, and in the 9H, the output stage 251c8 is selected. The same applies to the output terminals 93c.

  In odd number F (odd field) in FIG. 156 (b), the output stage 251c1 is selected at the second H by the output selection circuit 1531 for the output terminal 93a as in the even field. The output stage 251c3 is selected at the 4th H. At the 6th H, the output stage 251c5 is selected. Further, the output stage 251c7 is selected in the next 8H, and the output stage 251c9 is selected in the 10H.

  Similarly, for the output terminal 93b, the output stage 251cn-1 is selected at the 2nd H by the output selection circuit 1531. The output stage 251c1 is selected at the 4th H. The output stage 251c3 is selected at the 6th H. Further, the output stage 251c5 is selected in the next 8H, and the output stage 251c7 is selected in the 10H. The same applies to the output terminals 93c. Other operations, configurations, and the like are the same as or similar to those in FIG.

  In the above embodiment, the control (driving method) mainly includes the horizontal scanning period. However, the present invention is not limited to this. It may be controlled (driven) by 1F (frame or field). FIG. 158 shows an example.

  FIG. 158 shows the number of the output stage 251c connected to the output terminal 93c as in FIG. 154 and the like. For example, as the output stage 93a connected to the source signal line 18a in FIG. 154, the output stage 251c1 (described as 1 in the table) is selected in the period of the 1F. In the next 2F period, the output stage 251c2 (described as 2 in the table) is selected. The output stage 251c3 (denoted as 3 in the table) is selected during the 3rd period, and the output stage 251c4 (denoted as 4 in the table) is selected during the next 4th period. The same applies hereinafter.

  As the output stage 93b connected to the source signal line 18b adjacent to the source signal line 18a, the output stage 251cn (denoted by n in the table) is selected in the first period. In the next 2F period, the output stage 251c1 (described as 1 in the table) is selected. The output stage 251c2 (described as 2 in the table) is selected during the 3F period, and the output stage 251c3 (described as 3 in the table) is selected during the next 4F period. The same applies hereinafter. Similarly, one or a plurality of output stages 251c are selected for other terminals and output from the output terminal 93.

  In the above embodiment, the 1F cycle is used, but the present invention is not limited to this, and the output stage 251c selected in a plurality of cycles may be changed (changed). Further, the output stage 251c selected by a period such as 0.5F or 1.5F may be changed (changed) without being limited to the period of 1F. Needless to say, the above matters can be applied to other embodiments of the present invention. Moreover, it cannot be overemphasized that it can combine with another Example.

  In the above-described embodiment, the driving method is such that by changing the output stage 251c to be selected, the characteristic variation of the output stage 251c is averaged and a uniform image display is realized. However, the present invention is not limited to this.

  As a uniform method, there is a method of changing the reference current. This is because the characteristics of the output stage 251c change depending on the reference current Ic illustrated in FIG. By changing the signal (output current or output voltage) of the output stage 251c with a plurality of reference currents Ic, more uniform image display can be realized. In this method, the output selection circuit 1531 is not necessary, but it goes without saying that a more uniform image display can be realized by changing the output stage 251c to be selected by the output selection circuit 1531.

  The magnitude of the reference current Ic is basically proportional to the program current output from the output stage 251c. However, the program current Ic varies depending on the number of unit transistors selected. From the above, uniform image display can be realized by changing the reference current and driving the program current written in the pixels 16 to have an average target value.

  FIG. 159 shows an example. In the example of FIG. 159, the case of driving with reference currents Ic1 and Ic2 is illustrated as an example. In FIG. 159, the reference currents Ic1 and Ic2 are changed every horizontal scanning period. Note that the target reference current Ic and Ic1 and Ic2 are adjusted to a relationship of Ic = (Ic1 + Ic2) / 2.

  In the following embodiments, it is described that the reference current is changed at a constant cycle. The reference current is changed by a method of changing the electronic volume 291 shown in FIG. In addition, when performing cascade connection, there is a configuration in which a reference current (in this case, cascade current) is transferred from the master chip (source driver circuit (IC) 14) to the slave chip (source driver circuit (IC) 14). . A reference current (cascade current) is applied to the transistor group 251b, and a program current is output from the output stage 251c corresponding to the cascade current. Therefore, changing the reference current is synonymous with changing the cascade current.

  When three or more source driver circuits (ICs) 14 are used to form one display region 94, a configuration in which a slave chip receives reference currents (cascade currents) from a plurality of master chips in cascade connection is implemented. Is done. In this case, there are a plurality of master chips that generate a reference current (cascade current). Therefore, the slave chip receives the reference current (cascade current) from the plurality of master chips. That is, there are a plurality of reference currents. The slave chip realizes a good cascade connection by averaging a plurality of input reference currents. That is, the slave chip performs an operation of switching the reference current for image display. This operation is realized in an embodiment in which the reference current described below is changed.

  In FIG. 159, in the first F (frame or field), the first 1H (first pixel row) applies the reference current Ic1 (which may be considered as a cascade current from the first master chip), and the output terminal A program current corresponding to the reference current Ic 1 is output from the source signal line 18 to the source signal line 18. In the next 2H (second pixel row), a reference current Ic2 (which may be considered as a cascade current from the second master chip) is applied, and a program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source. It is output to the signal line 18. Similarly, 3H (third pixel row) applies the reference current Ic1, and the program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18. In the fourth pixel row), the reference current Ic2 is applied, and a program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18.

  The first 2H (first pixel row) applies the reference current Ic2 so that the reference current is averaged to the target reference current Ic in the second F after the first F (frame or field), A program current corresponding to the reference current Ic 2 is output from the output terminal 93 to each source signal line 18. In the next 2H (second pixel row), the reference current Ic1 is applied, and the program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18. Similarly, 3H (third pixel row) applies the reference current Ic2, and the program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18. In the fourth pixel row), the reference current Ic1 is applied, and a program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18.

  Needless to say, the change in the reference current is not limited to two and may be three or more. Further, the reference current is not limited to every 1H, but may be changed every plural H (multiple horizontal scanning periods). Further, the reference current is not limited to the horizontal scanning period, and the reference current may be changed in an F (frame or field) cycle. Moreover, it is not limited to the change of 1H or 1F unit. The reference current may be changed at 1.5H or 1.5F.

  In FIG. 160, 1H is divided into the first half period B and the second half period A. In addition, the magnitude of the reference current applied in the first half and the second half is changed. 160, in the first half (1B) of the first 1H (first pixel row), the reference current Ic1 is applied, and the program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18. . In the second half (1A) of 1H (first pixel row), the reference current Ic2 is applied, and the program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18.

  In the first half (2B) of the next 2H (second pixel row), the reference current Ic1 is applied, and the program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18. In the second half (2A) of 2H (second pixel row), the reference current Ic2 is applied, and the program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18.

  Similarly, in the first half (3B) of the next 3H (third pixel row), the reference current Ic1 is applied, and the program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18. . In the second half (3A) of 3H (third pixel row), the reference current Ic2 is applied, and the program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18.

  In the above embodiments, it is needless to say that the change in the reference current is not limited to two, and may be three or more. Further, the change in the reference current is not limited to every 1H, but may be changed every plural Hs (multiple horizontal scanning periods). Further, the reference current is not limited to the horizontal scanning period, and the reference current may be changed in an F (frame or field) cycle. Moreover, it is not limited to the change of 1H or 1F unit. The reference current may be changed at 1.5H or 1.5F.

  In the above embodiment, the reference current is changed with the horizontal scanning period as a reference. However, the present invention is not limited to this. The embodiment shown in FIG. 161 changes the reference current in a 1F (field or frame) cycle.

  In the first F (frame or field), a reference current Ic1 (which may be considered as a cascade current from the first master chip) is applied. A program current corresponding to the reference current Ic 1 is output from the output terminal 93 to each source signal line 18. The next second F applies a reference current Ic2 (which may be considered as a cascade current from the second master chip), and a program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18. The Similarly, the third F applies the reference current Ic 1, and the program current corresponding to the reference current Ic 1 is output from the output terminal 93 to each source signal line 18. The fourth F applies a reference current Ic 2, and a program current corresponding to the reference current Ic 2 is output from the output terminal 93 to each source signal line 18.

  In the above embodiment, the reference current is changed with 1F as a reference. However, the present invention is not limited to this. The reference current may be changed at a period of 0.5 or 1.5 (field or frame).

  In the above embodiment, the reference current Ic applied to the transistor group 251b illustrated in FIG. 153 is changed. The present invention is not limited to this. For example, as shown in FIG. 162, a transistor group 251b (a transistor group 251b1 at the left end of the chip and a transistor group 251b2 at the right end of the chip) is arranged or formed on both sides of the transistor group 251c (output stage 251c), and the transistor group 251b1 The reference current Ic1 may be applied to the transistor group 251b2, and the reference current Ic may be applied to the transistor group 251b2.

  Whether to select the reference current Ic1 or the reference current Ic2 is realized by controlling the switch S1 and the switch S2. If the switch S1 is closed and the switch S2 is opened, a program current corresponding to the reference current Ic1 is output from the output stage 251c. If the switch S2 is closed and the switch S1 is opened, a program current corresponding to the reference current Ic2 is output from the output stage 251c.

  If the configuration of FIG. 162 is used, the driving method of FIG. 163 can be easily realized. This is because the reference currents Ic1 and Ic2 can be easily switched by controlling the switches S1 and S2.

  In FIG. 163, in the first F (frame or field), the first 1H (first pixel row) applies the reference current Ic1 (which may be considered as a cascade current from the first master chip), and the output terminal A program current corresponding to the reference current Ic 1 is output from the source signal line 18 to the source signal line 18. In the next 2H (second pixel row), a reference current Ic2 (which may be considered as a cascade current from the second master chip) is applied, and a program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source. It is output to the signal line 18. Similarly, 3H (third pixel row) applies the reference current Ic1, and the program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18. In the fourth pixel row), the reference current Ic2 is applied, and a program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18.

  The first 2H (first pixel row) applies the reference current Ic2 so that the reference current is averaged to the target reference current Ic in the second F after the first F (frame or field), A program current corresponding to the reference current Ic 2 is output from the output terminal 93 to each source signal line 18. In the next 2H (second pixel row), the reference current Ic1 is applied, and the program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18. Similarly, 3H (third pixel row) applies the reference current Ic2, and the program current corresponding to the reference current Ic2 is output from the output terminal 93 to each source signal line 18. In the fourth pixel row), the reference current Ic1 is applied, and a program current corresponding to the reference current Ic1 is output from the output terminal 93 to each source signal line 18.

  Needless to say, the change in the reference current is not limited to two and may be three or more. In this case, the number of transistors 251b may be increased. The reference current is not limited to every 1H, and may be changed every plural H (multiple horizontal scanning periods). Further, the reference current is not limited to the horizontal scanning period, and the reference current may be changed in an F (frame or field) cycle. For example, the embodiment of FIG. 164 is illustrated. In FIG. 164, the reference current is changed in a 2F cycle. Moreover, it is not limited to the change of 1H or 1F unit. The reference current may be changed at 1.5H or 1.5F.

  Needless to say, the driving methods or configurations described in FIGS. 153 to 164 can be combined with each other. For example, a combination of FIG. 157 with FIG. 160, FIG. 161, FIG. 162, etc. is illustrated. Moreover, the combination of FIG. 162 and FIG. 153, the combination of FIG. 153, FIG. 160, FIG. 161 etc. are illustrated. As described above, the present invention can be combined with each other.

  In the present invention, the source driver circuit (IC) 14 is formed of a semiconductor silicon chip, and is connected to the terminal of the source signal line 18 of the substrate 30 by glass-on-chip (COG) technology. On the other hand, the gate driver circuit 12 is formed by low-temperature polysilicon technology. That is, it is formed by the same process as the pixel transistor. This is because the internal structure is easier and the operating frequency is lower than that of the source driver circuit (IC) 14. Therefore, even if it is formed by low-temperature polysilicon technology, it can be formed easily, and a narrow frame of the display panel can be realized. Of course, it goes without saying that the gate driver circuit 12 may be formed of a silicon chip and mounted on the substrate 30 using COG technology or the like. Further, the gate driver circuit (IC) 12 and the source driver circuit (IC) 14 may be mounted by COF or TAB technology. In addition, switching elements such as pixel transistors, gate drivers, and the like may be formed by high-temperature polysilicon technology or organic materials (organic transistors).

  When the transistor 11 constituting the pixel 16 is configured by a P channel, the program current flows in the direction from the pixel 16 to the source signal line 18. Therefore, the unit transistor 224 of the source driver circuit needs to be configured with an N-channel transistor. That is, the source driver circuit (IC) 14 needs to be configured to draw the program current Iw.

  When the driving transistor 11a of the pixel 16 (in the case of FIG. 1) is a P-channel transistor, the unit transistor 224 is configured by an N-channel transistor so that the source driver circuit (IC) 14 always draws the program current Iw.

  In order to form the source driver circuit (IC) 14 on the array substrate 30, it is necessary to use both an N channel mask (process) and a P channel mask (process). Describing conceptually, the display panel (display device) of the present invention comprises the pixel 16 and the gate driver circuit 12 by P-channel transistors, and the source current source transistor of the source driver by N-channel.

  In one embodiment of the present invention, the transistor 11 of the pixel 16 is formed by a P-channel transistor, and the gate driver circuit 12 is formed by a P-channel transistor. Thus, by forming both the transistor 11 and the gate driver circuit 12 of the pixel 16 with P-channel transistors, the cost of the substrate 30 can be reduced.

  The source driver circuit (IC) 14 needs to form the unit transistor 224 with an N-channel transistor. However, the source driver circuit (IC) 14 cannot be formed directly on the substrate 30 in the process of only the P channel. Therefore, a source driver circuit (IC) 14 is separately manufactured using a silicon chip or the like and mounted on the substrate 30. That is, the present invention has a configuration in which a source driver IC 14 (means for outputting a program current as a video signal) is externally attached.

  When the area of the unit transistor 224 is the same, the variation of the unit transistor 224 formed by the N channel is 70% compared to the variation of the unit transistor formed by the P channel. That is, when the unit transistor 224 is formed with the N channel, the variation can be reduced with the same transistor formation area. According to the result of the examination, in order to make the variation of the P-channel unit transistor the same as that of the N-channel unit transistor, a double formation area is required.

  Although the source driver circuit (IC) 14 is composed of a silicon chip, it is not limited to this. For example, a large number of glass substrates may be simultaneously formed by low-temperature polysilicon technology, cut into chips, and loaded on the substrate 30.

  Further, although it has been described that the source driver circuit is mounted on the substrate 30, it is not limited to stacking. Any form may be employed as long as the output terminal 251 of the source driver circuit (IC) 14 is connected to the source signal line 18 of the substrate 30. For example, a method of connecting the source driver circuit (IC) 14 to the source signal line 18 by TAB technology is exemplified. By separately forming a source driver circuit (IC) 14 on a silicon chip or the like, variation in output current can be reduced and good image display can be realized. Moreover, cost reduction is possible.

  Further, the configuration in which the selection transistor of the pixel 16 is configured by a P channel and the gate driver circuit is configured by a P channel transistor is not limited to a self-luminous device (display panel or display device) such as an organic EL. For example, the present invention can be applied to a liquid crystal display device and FED (field emission display).

  The above configuration is schematically shown in FIG. Unit transistor groups 251c are arranged in parallel by the number of output terminals. A plurality of transistor groups 251b are formed on both sides of the unit transistor group 251c. The gate terminal of the transistor 228b of the transistor group 251b and the gate terminal of the unit transistor 224 of the unit transistor group 251c are connected by a gate wiring 223.

  The above description has been made like a single color source driver IC 14 for ease of explanation. However, in the transistor group 251b and the unit transistor group 251c, red (R), green (G), and blue (B) transistor groups are alternately arranged. As described above, output variations between RGB are reduced by alternately arranging RGB transistor groups. This configuration is also an important requirement for the layout in the source driver circuit (IC) 14.

  In FIG. 27, the transistor group 251b (transistor 228b) through which the reference current flows is arranged near the outside of the IC chip. A plurality of transistors 228b are formed instead of one to form a transistor group. Here, for ease of description, the transistor group 251b is described as the transistor 228b. The same applies to other embodiments of the present invention (for example, FIG. 26 corresponds).

  With the circuit configuration shown in FIG. 61, white balance adjustment is easy. First, the RGB electronic volume 291 is adjusted to the same set value. Next, the white balance is adjusted by adjusting the external resistors R1r, R1g, and R1b.

  The source driver circuit (IC) 14 can adjust the brightness of the display screen 64 while maintaining the white balance if the value of the electronic volume 291 is the same if the white balance is set at any electronic volume setting value. There is.

  FIG. 26 shows a configuration in which power is supplied from both sides of the transistor group 251c, but the above items are not limited to this. As shown in FIGS. 27 and 29, the same applies to the one-side power feeding configuration. First, the R, G, B electronic controls 291 are set to the same value, and the external resistors R1r, R1g, R1b are adjusted to achieve white balance. Generally, white balance is achieved by setting Icr of the R circuit, Icg of the G circuit, and Icb of the B circuit to a predetermined ratio in consideration of the light emission efficiency of each RGB EL element.

  The source driver circuit (IC) 14 is characterized in that if white balance is achieved with a setting value of some electronic volume, the luminance of the display screen 64 can be adjusted while maintaining the white balance if the value of the electronic volume 291 is the same. There is. In addition, although it is preferable to form or arrange | position R, G, and B independently, the electronic volume of RGB is not limited to this. For example, it is possible to adjust the screen brightness while maintaining white balance even with one electronic volume 291 for R, G, and B.

  In the present invention, by forming or arranging an electronic volume inside the source driver circuit (IC) 14, the reference current can be varied or changed by digital data control from the outside of the source driver circuit (IC) 14. . This matter is an important matter in the current drive driver. In current driving, video data is proportional to the current flowing through the EL element 15. Therefore, the current flowing through all the EL elements can be controlled by performing logic processing on the video data. Since the reference current is also proportional to the current flowing through the EL elements 15, the current flowing through all the EL elements 15 can be controlled by digitally controlling the reference current. From the above, by performing the reference current control based on the video data, it is possible to easily realize the expansion of the dynamic range of display luminance.

  By changing or changing the reference current, the output current of the unit transistor 224 can be changed. For example, when the reference current Ic is 100 μA, the output current when one unit transistor 224 is on is 1 μA. In this state, if the reference current Ic is 50 μA, the output current of one unit transistor 224 is 0.5 μA. Similarly, if the reference current Ic is 200 μA, the output current of one unit transistor 224 is 2.0 μA. That is, it is preferable that the reference current Ic and the output current Id of the unit transistor 224 satisfy a proportional relationship.

  The setting data for setting the reference current Ic and the reference current Ic are preferably configured to have a proportional relationship. For example, when the setting data is 1, the reference current Ic is 100 μA, and if this is the base, the reference current Ic is 200 μA when the setting data is 100. That is, it is preferable that the reference current Ic increase by 1 μA when the setting data increases by one.

  With the configuration described above, the RGB reference currents (Icr, Icg, Icb) can be changed while maintaining the linear relationship according to the setting data of the electronic volume 291. Accordingly, since the linear relationship is maintained, if the white balance is adjusted at any setting data, the white balance is maintained at any setting data. In this configuration, it is important to configure the white balance by adjusting the external resistors R1r, R1g, and R1b described above (this is a characteristic configuration).

  In the above embodiment, the white balance is adjusted by an external resistor, but it goes without saying that the resistor R1 may be built in the IC chip.

  For example, a resistor R built in the source driver circuit (IC) 14 is formed or arranged in series in the electronic volume 291. The switch S1 and the reference voltage Vstd are connected by a built-in resistor Ra. The switch Sn and the ground voltage GND are connected by a built-in resistor Rb. The reference voltage Vstd is a precise fixed voltage. Therefore, even if the Vdd voltage of the EL display panel varies, the Vstd voltage does not vary. This is because when the Vstd changes, the reference current Ic changes, so that this change is prevented and the luminance of the display panel is made constant.

  As described above, since the resistors Ra, R, and Rb are formed by the built-in resistors (polysilicon resistors) of the source driver circuit (IC) 14, the relative values of the resistors Ra, R, and Rb are the individual source values. Even if the sheet resistance value of the polysilicon (polysilicon) resistance of the driver circuit (IC) 14 fluctuates, it does not fluctuate. Therefore, the source driver circuit (IC) 14 does not vary the reference current Ic.

  The R reference current Icr is determined by the output voltage of the electronic regulator 291 and the resistor R1r. The G reference current Icg is determined by the output voltage of the electronic regulator 291 and the resistor R1g. The reference current Icb for B is determined by the output voltage of the electronic regulator 291 and the resistor R1b. The reference voltage Vstd is shared by RGB, and the white balance is adjusted by the resistors R1r, R1g, and R1b. In addition, the relative values of the built-in resistor Ra, resistor R, and resistor Rb are made to coincide with the electronic volume 291, and the voltage of the electronic volume 291 is also set to Vstd. Therefore, the reference currents Icr, Icg, and Icb can be accurately maintained constant between the source driver circuits (IC) 14. IDATA for changing the reference current Ic is controlled by a controller circuit (IC) 722.

  The resistors R1r, R1g, and R1b are external resistors or external variable resistors. Further, when the reference voltage Vstd is not used, or when it is desired to change or adjust the voltage corresponding to Vstd, it is preferable that the external voltage Vs can be applied by the switch SW1. Further, it is preferable that the external voltage Va can be applied by the switch SW2 so that the potential of the S1 switch can be changed or changed. Further, it is preferable to draw out the voltage application terminal outside the source driver circuit (IC) 14 so that the output voltage of the switch Sn can be changed.

  As shown in FIG. 30, the reference voltage Vstd is also preferably configured to be changed or variable according to data applied to the DA conversion circuit 291b. Further, as shown in FIG. 231, a current Ir is generated by a constant current circuit composed of a transistor 228 and an operational amplifier, and this current Ir is passed through the built-in resistor R of the electronic volume 291 to change the voltage output from the b terminal. You may comprise so that it can do.

  In FIG. 31, transistors (transistor groups) 228b for supplying a reference current are formed or configured on the left and right of each source driver IC. The source driver IC 14 selects the transistor 228b by the switch S and applies the reference current. The unselected transistor 228b is configured in an open state.

  In the source driver IC 14a, the reference current is supplied to the rightmost transistor 228b2. The switch Sa2 is closed and the switch Sa1 is opened. Which of the switches Sa and Sb is opened is controlled by a logic signal applied to the master / slave terminal. In the source driver IC (circuit) 14a, a reference current is supplied to the right end, and the left end is open. Therefore, the reference current Ic1 flows through the transistor 228b2 (only the current flowing into the gate terminal of the unit transistor 224 flows through the gate wiring 223a).

  In the source driver IC 14b, the reference current is supplied to the leftmost transistor 228b1. The switch Sb1 is closed and the switch Sb2 is opened. Which of the switches Sa and Sb is opened is controlled by a logic signal applied to the master / slave terminal. In the adjacent source driver IC 14, the open / close relationship is reversed between the switch S * 1 and the switch S * 2. Note that * is the symbol a or b.

  In the source driver IC (circuit) 14b, the reference current is supplied to the left end, and the right end is open. Therefore, the reference current Ic2 flows through the transistor 228b1.

  In FIG. 31, the transistor 228b is illustrated as one transistor, but actually, as illustrated in FIG. 28 and the like, the transistor 228b includes a transistor group 251b including a plurality of transistors.

  The description will be made assuming that the reference currents Ic1 and Ic2 are equal. The output terminal 93a1 and the transistor 228b2 constituting the current mirror circuit and a current with high current mirror accuracy are output.

  In the source driver IC 14b, a transistor 228b1 for supplying a reference current is configured at the left end, and the right end is in an open state. Therefore, the reference current Ic1 flows through the transistor 228b1 (only the current flowing into the gate terminal of the unit transistor 224 flows through the gate wiring 223b). The output terminal 93a2 and the transistor 228b1 constituting the current mirror circuit and a current with high current mirror accuracy are output. Therefore, if the reference currents Ic1 and Ic2 are equal, the gradation current output from the output terminal 93a1 of the source driver IC 14a is the same as the gradation current output from the output terminal 93a2 of the source driver IC 14b. For the above reasons, the two source driver ICs 14a and the source driver ICs 14b are well cascaded. The above configuration is effective for a QVGA panel of 320 RGB × 240 dots or the like that uses two 160 RGB output source driver ICs 14.

  In FIG. 31, the gradation current (program current) output from the right end output terminal 93a3 of the source driver IC 14a and the gradation current (program current) output from the left end output terminal 93a1 of the source driver IC 14a match. It ’s not that hard. This is because the characteristics of the unit transistor 224 in the IC chip 14a change more.

  Further, the grayscale current output from the rightmost output terminal 93a2 of the source driver IC 14b does not always match the grayscale current output from the leftmost output terminal 93a3 of the source driver IC 14b. This is because the characteristics of the unit transistor 224 in the IC chip 14b change more. However, since the source driver ICs 14 to be cascaded are two chips, there is no problem as long as the gradation current from the output terminal 93a1 of the source driver IC 14a matches the gradation current from the output terminal 93a2 of the source driver IC 14b. . Therefore, the gate wiring 223 may be formed of a low resistance wiring.

In order to realize the configuration of FIG. 31, it is necessary to open one of the transistors 228b located at both ends of the gate wiring 223 of the IC chip 14a (a state in which no current flows through the transistor 228b).
It is divided into a plurality of parts (drain terminals 323a, 323b, 323c,. By cutting along line A in FIG. 32A, the drain terminal 323e is cut, and the output current of the transistor 323 can be reduced.

  FIG. 32B shows an example in which the trimming interval of the drain terminal 323 is changed. Depending on the magnitude of the current to be reduced, one or more drain terminals 323 are trimmed to adjust the output current. In FIG. 32 (b), trimming is performed along the line B.

  The trimming method shown in FIG. 32 is particularly effective when applied to an element (such as a transistor) responsible for cascade connection. This is because the magnitude of the current passed through the cascade connection can be adjusted by trimming, so that a good cascade connection can be realized. The above matters can be applied to other embodiments of the present invention.

  In the above embodiment, the drain terminal 323 or the source terminal 321 is trimmed at one place or a plurality of places, but the present invention is not limited to this. For example, the gate terminal 322 may be trimmed. Further, the invention is not limited to trimming. Needless to say, output current or the like may be adjusted by irradiating the semiconductor film of the transistor 324 with laser light or thermal energy to deteriorate the transistor 324. Further, it is needless to say that the embodiment of FIG. 32 and the like is not limited to the transistor, but may be applied to a diode, a crystal, a thyristor, a capacitor, a resistor, and the like.

  Also, as shown in FIG. 24, when the transistor size is different for each bit (such as when proportional to the bit size), the trimming length (such as the drain length) is also proportional to the bit size. It is preferable to configure as described above.

  The source driver circuit (IC) 14 includes a precharge circuit that forcibly releases or charges the source signal line 18. The voltage (current) output value of the precharge or discharge circuit that forcibly releases or charges the source signal line 18 is preferably configured to be set independently by R, G, and B. This is because the threshold value of the EL element 15 differs between RGB.

  FIG. 33 is a block diagram of the precharge unit. Vp is a precharge voltage. The output period range of the precharge voltage is determined by the video data D0 to D5. The precharge voltage is output in synchronization with the clock CLK. The time for outputting the precharge voltage is determined by the set value of the counter 332 with the horizontal synchronization signal HD as a base point. The counter 332 is counted up in synchronization with the clock CLK signal. The precharge voltage output period starts from the beginning of HD. When the count value counted by the counter 332 matches the set value, the precharge voltage output period ends. The output of the counter circuit 332 becomes the a terminal input of the AND circuit 333. For ease of explanation, the video data is assumed to be 6 bits.

  In the configuration of FIG. 33, the voltage range to be precharged is determined by the matching circuit 331. Video data D0 to D5 are applied to the matching circuit 331. The coincidence circuit stores a precharge range. When the video data D0 to D5 is smaller than the stored value, a precharge voltage is output. The coincidence circuit 331 operates in synchronization with the clock CLK. When the enable signal EN is H, the precharge voltage is output. When the enable signal EN is L, the precharge voltage is not output regardless of the value of the video data. The output of the coincidence circuit 331 becomes the b terminal input of the AND circuit 333.

  When the a terminal input of the AND circuit 333 is H and the b terminal input is H, the switch 221a is closed, the precharge voltage Vp is applied to the internal wiring 222, and when the HI signal is H, the switch 221b is closed and output. A precharge voltage is output from the terminal 93.

  The current output circuit 334 outputs a program current based on the video data D0 to D5. In the present invention, the precharge voltage and the program current are output simultaneously. However, the precharge voltage is a certain period from the beginning of HD.

  The precharge voltage can be considered as a method of applying a rising voltage or a voltage equal to or lower than the rising voltage to the gate (G) terminal of the driving transistor 11a. That is, by turning off the driving transistor 11a, a state in which the program current Iw becomes 0 is generated, so that no current flows through the EL element 15.

  The source driver circuit of the present invention includes an electronic volume 291 as shown in FIG. Therefore, the precharge voltage can be easily changed by controlling the electronic regulator 291. Needless to say, the precharge voltage may be generated and applied not only by the electronic control 291 but also by a DA circuit outside the source driver circuit (IC) 14.

  FIG. 35 is a block diagram centering on a precharge circuit (circuit configuration unit for outputting a precharge voltage) 353 of the source driver circuit (IC) 14. The precharge circuit 353 outputs a precharge control signal PC signal (red (RPC), green (GPC), blue (BPC)) by the precharge control circuit.

  The selector circuit 352 sequentially latches in the latch circuit 351 corresponding to the output stage in synchronization with the main clock. The latch circuit 351 has a two-stage configuration of a latch circuit 351a and a latch circuit 351b. The latch circuit 351b sends data to the precharge circuit 353 in synchronization with the horizontal scanning clock (1H). That is, the selector sequentially latches the image data and PC data for one pixel row, and stores the data in the latch circuit 351b in synchronization with the horizontal scanning clock (1H).

  In FIG. 35, R, G, and B of the latch circuit 351 are RGB image data 6-bit latch circuits, and P is a latch circuit that latches 3 bits of the precharge signal (RPC, GPC, BPC). .

  The precharge circuit 353 turns on the switch 221a and outputs a precharge voltage to the source signal line 18 when the output of the latch circuit 351b is at the H level. The current output circuit 334 outputs a program current to the source signal line 18 according to the image data.

  In the configuration of FIG. 35, a precharge control (PC) signal is generated corresponding to each RGB image data. The precharge is preferably applied for each RGB as described above. However, in moving image display and natural image display, it is often unnecessary to determine whether or not to precharge for each RGB. That is, RGB may be converted (converted) into a luminance signal, and it may be determined whether or not to precharge based on the luminance.

  In the configuration of FIG. 36, the PC signal requires 3 bits (RPC, GPC, BPC), but in the configuration of FIG. 79, the PC signal may be 1 bit of RGBPC. Therefore, in the latch circuit 351 of FIG. 35, P may be a 1-bit latch. In the following description, the description will be made without considering RGB from the viewpoint of facilitating the explanation and drawing.

  In the configuration of the present invention described above, the controller circuit (IC) generates the PC signal (precharge control signal) based on the image data, and the source driver IC 14 latches the PC signal and synchronizes with the 1H synchronization signal. It is characterized in that it is applied to the signal line 18. The generation of the precharge signal can be easily changed by the precharge mode (PMODE) signal.

  For example, PMODE is a mode in which only gradation 0 is precharged, a mode in which a certain gradation range such as gradation 0-7 is precharged, and precharge when image data changes from bright image data to dark image data. Examples include a mode for precharging when low gradation display is continuously performed in a certain frame.

  It is not limited to determining whether or not to precharge data for one pixel. For example, the precharge determination may be performed based on the image data of a plurality of pixel rows. In addition, the precharge determination may be performed in consideration of the image data of the surrounding pixels to be precharged (for example, weighting processing). Further, a method of changing the precharge judgment between a moving image and a still image is also exemplified. The above matter is important in that good versatility is exhibited when the controller generates a precharge signal based on image data. Hereinafter, the precharge determination and the precharge mode will be mainly described.

  The determination as to whether or not to precharge may be performed based on the image data of the previous pixel row (or the image data applied to the source signal line immediately before). For example, if the image data applied to a certain source signal line 18 is white-> black-> black, a precharge voltage is applied when changing from white to black. This is because black gradation is difficult to write. In the case of black to black, no precharge voltage is applied. This is because the potential of the source signal line 18 in the black display first is the black display potential to be written next. The above operation can be realized more easily by forming (arranging) a line memory for one pixel row (requires two lines of memory for FIFO) in the controller 81.

  In the present invention, the precharge drive is described as outputting a precharge voltage, but the present invention is not limited to this. A method of writing a current shorter than one horizontal scanning period and larger than the program current to the source signal line 18 may be used. That is, a method of writing the precharge current to the source signal line 18 and then writing the program current to the source signal line 18 may be used. There is no difference in that the precharge current also physically causes a voltage change. A method of performing precharge with a precharge current is also within the technical category of precharge driving of the present invention (within the scope of the present invention).

  In the precharge drive of the present invention, a predetermined voltage is applied to the source signal line 18. The source driver IC outputs a program current. However, in the present invention, the output voltage may be changed in accordance with the gradation in the precharge driving. That is, the precharge voltage output to the source signal line 18 is a program voltage. FIG. 37 shows a circuit configuration in which the program voltage circuit 371 for the precharge voltage is introduced in the source driver IC.

  FIG. 37 is a block diagram of one output circuit corresponding to one source signal line 18. The current gradation circuit 334 outputs a program current according to the gradation, and a voltage gradation circuit 371 outputs a precharge voltage according to the gradation. Video data is applied to the current gradation circuit 334 and the voltage gradation circuit 371. The output of the voltage gradation circuit 371 is applied to the source signal line 18 when the switches 221a and 221b are turned on. The switch 221a is controlled by a precharge enable (precharge ENBL) signal and a precharge signal (precharge SIG).

  The voltage gradation circuit 371 includes a sample hold circuit, a DA circuit, and the like (see FIG. 38). Based on the digital video data, the DA circuit converts the precharge voltage. The converted precharge voltage is sampled and held by the sample and hold circuit 381 and applied to one terminal of the switch 221a via the operational amplifier. The DA circuit does not need to be configured or formed for each voltage gradation circuit 371. The DA circuit is configured outside the source driver circuit (IC) 14, and the output of the DA circuit is sampled in the voltage gradation circuit 371. You may hold it. Further, it may be formed by polysilicon technology.

  As shown in FIG. 38, a voltage (program voltage) corresponding to 8-bit video DATA is output from the electronic volume 291 in synchronization with the video clock. The program voltage is a voltage applied as a precharge voltage to the driving transistor 11a. The program voltage is a voltage that is held at the gate terminal of the driving transistor 11a so that by applying this voltage, a current substantially corresponding to the gradation is applied to the EL element 15.

  The program voltage is temporarily held in the Cc capacity and output from the buffer amplifier 231a. The output voltage is sequentially distributed to each output terminal 93 by a sample and hold circuit (illustrated as a switching circuit in this embodiment) 381 (output terminals 93a, 93b, 93c, 93d... , 93n, 93a, 93b, 93c,... 93n,. The distribution is performed in synchronization with the clock CLK. In the present invention, a program voltage can be distributed to an arbitrary terminal by an 8-bit address signal PADRS. In this way, the address signal PADRS is configured so that it can be distributed to any output terminal 93 (because it is 8 bits, it can be distributed to any of 256 terminals), so that the program voltage needs to be rewritten. Only a new program voltage can be applied. In addition, program voltage distribution can be randomized. The program voltage is held in the capacitor C (sampled), and the output of the buffer circuit 231b is applied to the output terminal 93 or cut off by the control of the switch Sp. The switch Sp corresponds to the switch 221a in FIG. The above configuration corresponds to the voltage gradation circuit 371 in FIG.

  Specifically, the current gradation circuit 334 corresponds to the circuit configuration of FIG. The program current output of the current gradation circuit 334 is controlled by the switch Si. As described above, the outputs of the current gradation circuit 334 and the voltage gradation circuit 371 are controlled by the switches Si and Sp, and precharge driving (voltage program) + current programming is realized. The above signals are applied from the output terminal 93 to the source signal line terminal 382. The program voltage charges and discharges the parasitic capacitance Ca of the source signal line 18 in a short period.

  The output of the voltage gradation circuit 371 is applied at the beginning of 1H (indicated by symbol A) as shown in FIG. Thereafter, a program current is supplied to the source signal line by the current output circuit 334 (indicated by symbol B). That is, the voltage is set to the approximate source signal line potential by the precharge voltage. Therefore, the driving transistor 11a is set at a high speed up to a value close to the target current. Thereafter, the target current (= program current) for compensating for the characteristic variation of the driving transistor 11a is set by the program current output from the current gradation circuit 334.

  The period A during which the precharge voltage signal is applied is preferably a period of 1/100 to 1/5 of 1H. Alternatively, it is preferably set to a period of 0.2 μsec to 10 μsec. Therefore, a period other than the A period is a program current application period of the B period. If the A period is short, charge and discharge of the source signal line 18 are not sufficiently performed, and thus insufficient writing occurs. On the other hand, if it is too long, the current application period (B) is shortened, and the program current cannot be sufficiently applied. Therefore, the current correction of the driving transistor 11a is insufficient.

  The voltage application period (A period) is preferably implemented from the beginning of 1H, but is not limited thereto. For example, the blanking period at the end of 1H may be started. Moreover, you may implement A period in the middle of 1H. That is, the voltage application period may be performed in any period of 1H. However, it is preferable that the voltage application period be implemented within a period of 1 / 4H (0.25H) from the beginning of 1H.

  In the embodiment of FIG. 41, the current is applied (B period) after the voltage precharge (A) period, but the present invention is not limited to this. For example, as shown in FIG. 42A, all (or most or most) of the 1H periods may be voltage precharge (* A) periods.

  In the period * A in FIG. 42A, the voltage program is executed in the period 1H. * A period is a low gradation area. Even if the current program is executed in the low gradation region, the current to be programmed is very small. Therefore, the potential of the source signal line 18 cannot be changed due to the parasitic capacitance of the source signal line 18. That is, the characteristic compensation of the TFT 11a (driving transistor) cannot be performed. In the current programming method, the programming current I and the brightness B are in a linear relationship. Therefore, the luminance change for one gradation is too large in the low gradation area. Therefore, gradation skip is likely to occur in the low gradation region.

  In order to solve this problem, in the present invention, as shown in FIG. 42A, a voltage program is executed over a period of 1H in the low gradation region (indicated by * A). The voltage step increment of the voltage program is reduced in the low gradation region. When the voltage applied to the TFT 11a of the pixel 16 is set to a certain step, the output current of the TFT 11a to the EL element 15 has a substantially square characteristic. Therefore, the luminance B with respect to the applied voltage (the luminance B is proportional to the output current to the EL element 15) has a linear human visual sensitivity (the human visual sensitivity changes in a low step when it has a square characteristic. For recognizing

  In the voltage program method, the characteristic compensation of the TFT 11a cannot be performed satisfactorily. However, since the display brightness of the display screen 64 is low in the low gradation region, even if display unevenness due to insufficient characteristic compensation occurs, it is not visually recognized. On the other hand, in the voltage program method, the source signal line 18 can be charged and discharged satisfactorily. Therefore, the source signal line 18 can be sufficiently charged / discharged even in the low gradation region, and appropriate gradation display can be realized.

  As can be understood from FIG. 42A, when the potential of the source signal line 18 is close to the anode potential (Vdd), the voltage is applied to all (mostly) the period of 1H. When the potential of the source signal line 18 becomes close to 0 (V), the voltage program (A period) and the current program (B) are executed within the period of 1H. Note that in the case where the potential of the source signal line 18 is close to 0 (V) (high gradation region), the current program may be performed over the entire period of 1H.

  In a period other than * A in FIG. 42A, a voltage according to the voltage program is applied to the source signal line 18 during a fixed period of 1H (indicated by A), and then a current according to the current program is applied during the period B. Yes. As described above, a predetermined voltage is applied to the gate potential of the TFT 11a of the pixel 16 by applying the voltage during the period A, so that the current flowing through the EL element 15 becomes a desired value. Thereafter, the current flowing through the EL element 15 is set to a predetermined value by the program current during the B period. * In the period A, the voltage program is executed throughout the period of 1H (voltage is applied).

  FIG. 42A shows a signal waveform applied to the source signal line 18 when the TFT 11a (driving transistor) of the pixel 16 is a P channel. However, the present invention is not limited to this. The TFT 11a of the pixel 16 may be an N channel. In this case, as shown in FIG. 42B, when the potential of the source signal line 18 is close to 0 (V), the voltage is applied to all (most) of the 1H period. When the potential of the source signal line 18 becomes close to the anode voltage (Vdd), the voltage program (A period) and the current program (B) are executed during the 1H period.

  Note that in the case where the potential of the source signal line 18 is close to Vdd (high gradation region), the current program may be executed over the entire period of 1H.

  In the present invention, the driving transistor 11a is described as a P-channel, but the present invention is not limited to this, and it goes without saying that the driving transistor 11a may be an N-channel. For ease of explanation, the explanation is made only assuming that the driving transistor 11a is a P-channel transistor.

  In the embodiment of the present invention such as FIG. 42, the voltage program is mainly written in the low gradation region, and the pixel is written. In the middle / high gradation region, the current program is mainly used for writing. In other words, it is possible to realize a good fusion of both current and voltage driving. This is because the low gradation region is displayed with a predetermined gradation by the voltage. This is because the write current is very small in current drive, and the voltage applied first for 1H (by voltage drive or precharge drive. Precharge drive and voltage drive are conceptually the same. If greatly differentiated, This is because precharge driving has a relatively small number of types of applied voltage, and voltage driving has a large number of types of applied voltage).

  In the middle gradation area, after writing by voltage, the amount of voltage deviation is compensated by the program current. That is, the program current is dominant (current drive is dominant). The high gradation region is written with a program current. No program voltage application is required. This is because the applied voltage is rewritten by the program current. That is, the current drive is overwhelmingly dominant (see FIGS. 43B and 44). Of course, it goes without saying that a voltage may be applied.

  The reason why the output of the voltage gradation circuit and the output of the current gradation circuit (including the precharge circuit) can be short-circuited at the output terminal 93 is that the current gradation circuit has a high impedance. In other words, since the current gray scale circuit has high impedance, even if the voltage from the voltage gray scale circuit is applied to the current gray scale circuit, a problem (such as an overcurrent flowing due to a short circuit) does not occur in the circuit.

  Therefore, although the voltage output and the current output state are switched in the present invention, the present invention is not limited to this. It goes without saying that the switch 221 (see FIG. 37) may be turned on and the voltage of the voltage gradation circuit 371 may be applied to the output terminal 93 while the program current is output from the current gradation circuit 334. .

  The program current may be output from the current gradation circuit 334 in a state where the switch 221 is closed and a voltage is applied to the output terminal 93. Since the current gradation circuit 334 has a high impedance, there is no problem in the circuit. The above state is also an operation category in which the present invention switches between the voltage drive state and the current drive state. The present invention takes advantage of the nature of current and voltage circuits. This is a characteristic configuration not found in other driver circuits.

  As shown in FIG. 43, it goes without saying that the program applied in the 1H period may be either voltage or current. In FIG. 43, the period * A is a 1H period in which the voltage program is implemented, and the period B is a 1H period in which the current program is implemented. The voltage program is implemented mainly in the low gradation region (indicated by * A), and the current program is implemented in the region of halftone or higher (indicated by B). As described above, switching between voltage driving and current driving may be switched according to the gradation or the magnitude of the program current.

  In the embodiment of the present invention shown in FIG. 37, the same video data is input to the voltage gradation circuit 371 and the current gradation circuit 334. Accordingly, the latch circuit for the video data may be common to the voltage gradation circuit 371 and the current gradation circuit 334. That is, it is not necessary to provide the video data latch circuit independently for the voltage gradation circuit 371 and the current gradation circuit 334. Based on the data from the common video data latch circuit, the current gradation circuit 334 or (and) the voltage gradation circuit 371 outputs the data to the output terminal 93.

  FIG. 45 is a timing chart of the driving method of the present invention. In FIG. 45, DATA in (a) is image data. CLK in (b) is a circuit clock. Pcntl in (c) is a precharge control signal. When the Pcntl signal is at the H level, only the voltage driving mode is set, and when it is at the L level, the voltage + current driving mode is set. Ptc in (d) is a precharge voltage or output switching signal from the voltage gradation circuit 371. When the Ptc signal is at the H level, a voltage output such as a precharge voltage is applied to the source signal line 18. When the Ptc signal is at the L level, the program current from the current gradation circuit 334 is output to the source signal line.

  For example, in the case of data D (2), D (3), and D (8), since the Pcntl signal is at the H level, a voltage is output from the voltage gradation circuit 371 to the source signal line 18 (A period). . When Pcntl is at L level, a voltage is first output to the source signal line 18 and then a program current is output. A period in which the voltage is output is indicated by A, and a period in which the current is output is indicated by B. The period A during which the voltage is output is controlled by the Ptc signal. The Ptc signal is a signal for controlling on / off of the switch 221 in FIG.

  It has been described that when the Pcntl signal is at the H level, only the voltage driving mode is set, and when the Pcntl signal is at the L level, the voltage + current driving mode is set. The period during which the voltage is applied is preferably changed according to the lighting rate or gradation. When the gradation is low, the program current cannot be completely written to the pixel by current driving. Therefore, it is preferable to implement voltage driving. By extending the voltage application period, even in the voltage + current driving mode, the voltage driving mode becomes dominant, and a low gradation state can be satisfactorily written in the pixel. In the case of a low lighting rate, there are many pixels in a low gradation state. Therefore, even in the low gradation state (low lighting rate), by extending the voltage application period, the voltage driving mode becomes dominant even in the voltage + current driving mode, and the pixel is satisfactorily reduced. The gradation state can be written.

  As described above, even in the voltage + current drive mode, it is preferable to change the period of the voltage drive state according to the lighting rate or the gradation data (video data) written to the pixel. That is, when the current flowing through the EL element 15 is reduced (in the present invention, the low lighting rate range), the voltage drive mode period is lengthened, and when the current flowing through the EL element 15 is increased (in the present invention, the high lighting rate range). ), Or control or adjust or configure the device to shorten the voltage drive mode period or make it “none”. Note that the meaning of the lighting rate or the lighting rate state has been described in detail in the present specification, and will be omitted. In addition, it goes without saying that the device may be configured or configured to control or adjust the duty ratio, reference current ratio, etc., in the voltage + current drive mode in the voltage drive mode (operation) period. It goes without saying that the above matters can be applied to other embodiments of the present invention.

  In FIG. 45, the voltage output period A and the current output period B are switched, but the present invention is not limited to this. Needless to say, the switch 221 (see FIG. 37) may be turned on and the voltage of the voltage gradation circuit 371 may be applied to the output terminal 93 in the state where the program current is output. Alternatively, the program current may be output from the current gradation circuit 334 in a state where the switch 221 is closed and a voltage is applied to the output terminal 93. The switch 221 is opened after the period A. As described above, since the current gradation circuit 334 has high impedance, there is no problem in terms of circuit even if it is short-circuited with the voltage circuit.

  In FIG. 46, the period during which the voltage is output to the source signal line 18 is varied by changing the H period of the Ptc signal. The H period is changed depending on the gradation number. For example, in D (7), the Ptc signal is at the L level during the 1H period. Therefore, the switch 221 in FIG. 37 is open for a period of 1H. Therefore, no voltage is applied during the 1H period, and the current programming state is always maintained. In D (5), the Ptc period is longer than the other 1H periods. Therefore, the period A during which the voltage is applied is set to be long.

  In the above embodiment, the current drive state and the voltage drive state are switched. However, the present invention is not limited to this. In the embodiment of FIG. 47, there is no Ptc signal. Therefore, it is controlled by the Pcntl signal. Therefore, voltage driving is performed during the H period, and current driving is performed during the L period.

  The voltage program needs to change the voltage value output to the source signal line 18 depending on the light emission efficiency of the RGB EL elements 15. This is because the voltage (program voltage) applied to the gate terminal of the driving transistor 11a varies depending on the current output from the driving transistor 11a in the pixel configuration of FIG. The output current of the driving transistor 11 a needs to be different depending on the light emission efficiency of the EL element 15. In order to make the source driver IC 14 of the present invention versatile, even if the pixel size of the EL display panel is different or the luminous efficiency of the EL element 15 is different, it is necessary to cope with the setting or adjustment. There is.

  The voltage gradation circuit 371 outputs a voltage with the anode voltage (Vdd) as the origin. This state is shown in FIG. The anode voltage (Vdd) is the operation origin of the driving transistor 11a. For ease of explanation, it is assumed that the driving transistor 11a as shown in FIG. 1 has a P-channel configuration. Also in the case where the driving transistor 11a is an N-channel, only the origin position changes, so that the description is omitted. Therefore, for ease of explanation, the case where the driving transistor 11a is a P channel will be described as an example.

  In FIG. 48, the horizontal axis is gradation. In the present invention, description will be made assuming that the output gradation of the voltage gradation circuit 371 is 256 (8 bits) gradation. The vertical axis represents the output voltage to the source signal line 18. In FIG. 48, the potential of the source signal line 18 decreases in proportion to the gradation number.

  The voltage of the source signal line 18 is the gate terminal voltage of the driving transistor 11a. The output current of the driving transistor 11a changes nonlinearly with the gate terminal voltage. In general, when a voltage is applied to the source signal line 18 as shown in FIG. 48, the output current of the driving transistor 11a changes with a square characteristic with respect to the applied voltage. That is, in FIG. 48, the potential of the source signal line 18 is proportional to the gradation, but the output current of the driving transistor 11a (current flowing through the EL element 15) has a substantially square characteristic.

  The circuit configuration of FIG. 48 is easy in circuit configuration. However, the current flowing through the EL element 15 is not proportional to the gradation number. This is because when a linearly changing voltage is applied to the driving transistor 11a (such as in the case of the embodiment of FIG. 48), the output current is output in proportion to the square of the applied voltage due to the square characteristics of the transistor 11a. . Therefore, when the gradation number is small, the change in the output current of the transistor 11a is small, and increases rapidly as the gradation number increases. Therefore, the accuracy of the output current with respect to the gradation number changes.

  FIG. 49 shows a configuration for solving this problem. In FIG. 49, when the gradation number is small, the change in the output voltage to the source signal line 18 is large. Further, the smaller the gradation number, the greater the voltage change rate to the source signal line 18. On the other hand, when the gradation number increases (approaching 256th), the change in the output voltage to the source signal line 18 is reduced. Therefore, the relationship between the source signal line output current and the gradation number is non-linear. This non-linear characteristic is made linear by combining with the output current characteristic to the EL element 15 with respect to the gate terminal voltage of the driving transistor 11a. That is, the output current to the EL element 15 of the driving transistor 11a with respect to the change of the gradation number is adjusted to be linear.

  In the current programming method, the current flowing through the EL element 15 with respect to the gradation number has a linear relationship. The configuration (method) in FIG. 49 is a voltage program method. In FIG. 49, the voltage programming method is used, but the current flowing through the EL element 15 with respect to the gradation number has a linear relationship. Therefore, matching is good in the configuration (method) in which the current program method and the voltage program method are combined as shown in FIG.

  In FIG. 49, the output current Ie of the driving transistor 11a with respect to the gradation number is changed substantially linearly. Therefore, the relationship of the source signal line output voltage with respect to the gradation number is not small when the gradation number is small, but is finely changed as the gradation number increases. When the gradation number is K and the source signal line is Vs, the change curve equation is such that the source signal line voltage Vs = A / (K · K) as shown in FIG. A is a proportionality constant. Alternatively, the source signal line voltage Vs = A / (B · K · K + C · K + D) or Vs = A / (B · K · K + C). D, B, C, and A are constants.

  As described above, by forming the change curve equation, when the change curve equation is multiplied by the output current Ie of the driving transistor with respect to the source signal line voltage Vs, Ie with respect to Vs can be in a linear relationship.

  In FIG. 49, the change curve equation is a curve. Therefore, it is relatively difficult to create a change curve. For this problem, it is appropriate to form a change curve equation with a plurality of straight lines as shown in FIG. That is, a change curve is formed by two or more straight lines having an inclination.

  In FIG. 49, the increment of the output voltage of the source signal line 18 is increased (indicated by A) in the range where the gradation number is small, and the increment of the output voltage of the source signal line 18 is decreased in the range where the gradation number is large. (Indicated by B). In the change curve of FIG. 49, the output current Ie of the driving transistor 11a with respect to the gradation number K has a non-linear relationship, and a plurality of non-linear outputs are combined. However, the relationship between the output current Ie and the gradation number K increases in a nearly linear range. Therefore, the combination with current program driving is also easy.

  In FIG. 49, the voltage gradation circuit 371 and the current gradation circuit 334 are illustrated as being formed in one source driver circuit (IC) 14, but the present invention is not limited to this. The present invention is characterized by having a voltage gradation circuit 371 and a current gradation circuit 334. Therefore, a voltage gradation circuit (IC) 371 is arranged or formed or mounted at one end of one source signal 18, and a current gradation circuit (use IC) 334 is arranged or formed at the other end of the source signal line. May be implemented. In other words, the present invention may have any configuration as long as it is a configuration or method capable of executing current programming and voltage programming on an arbitrary pixel.

  The driver circuit (IC) 14 that executes the voltage program has a gamma characteristic of 1.5 to 3.0 power. That is, the current increase at equal intervals can be realized corresponding to the step of changing the gate voltage of the driving transistor 11a. This is because the VI characteristic of the driving transistor 11a is a substantially square characteristic (because the output current I changes with a substantially square characteristic with respect to a change in voltage V). Furthermore, it is preferable that the gamma characteristic of the driver circuit (IC) for executing the voltage program is a reverse gamma characteristic of 1.8 to 2.4.

  It is preferable that the gamma characteristic of the driver circuit (IC) for executing the voltage program is configured to be programmable. When the driving transistor 11a is a P-channel transistor, the origin of the gamma characteristic curve is the anode voltage Vdd or near Vdd. When the driving transistor 11a is an N-channel transistor, the origin of the gamma characteristic curve is the cathode voltage Vss, the ground of the circuit 14, or a potential near them.

  The change in the voltage gradation circuit 371 (precharge circuit) and the current gradation circuit 334 are synchronized. That is, the voltage gradation circuit 371 (precharge circuit) is changed so as to correspond to the change in the current gradation circuit 334. If the target value (expected value) of the output current of the driving transistor 11a of the pixel 16 by the voltage gradation circuit 371 is 1 μA, the target value (expected value) of the driving transistor 11a of the pixel 16 by the current gradation circuit 334 is The gradation is controlled so as to be 1 μA. Therefore, it is preferable that the gradation data value of the current gradation circuit 334 and the gradation data of the voltage gradation circuit (precharge circuit) 371 coincide with each other. Needless to say, the above matters can be applied to other embodiments of the present invention. Moreover, it is preferable to synchronize.

  The present invention is not limited to performing both voltage programming (precharge) and current programming on all source signal lines 18. Any one of them may be implemented. For example, a voltage program (precharge) may be implemented for odd pixel columns and a current program may be implemented for even pixel columns. Even with such a configuration, there is almost no deterioration in image quality. Needless to say, the above matters can be applied to other embodiments of the present invention.

  In the example of FIG. 48, when the gradation number is 0, the potential of the source signal line 18 is not the anode potential (Vdd). The output current of the driving transistor 11a is 0 or almost 0 until the rising voltage. The range up to this rising voltage is the C region. Accordingly, since the area C is blank, when the number of gradation numbers is constant, the output voltage increment of the source signal line can be made relatively fine as compared with FIG.

  When the gradation number is 0, the potential of the source signal line 18 is not the origin (anode potential), the non-linear relationship of FIG. 49, the combination of a plurality of relational expressions of FIG. 50, the straight line relationship of FIG. Needless to say, they may be combined with each other.

  The voltage program needs to change the voltage value output to the source signal line 18 depending on the light emission efficiency of the R, G, and B EL elements 15. This is because the voltage (program voltage) applied to the gate terminal of the driving transistor 11a varies depending on the current output from the driving transistor 11a in the pixel configuration of FIG. The output current of the driving transistor 11 a needs to be different depending on the light emission efficiency of the EL element 15. In order to make the source driver IC 14 of the present invention versatile, even if the pixel size of the EL display panel is different or the luminous efficiency of the EL element 15 is different, it is necessary to cope with the setting or adjustment. There is.

  FIG. 44 shows a circuit configuration utilizing the point that the voltage reference is Vdd in voltage driving. The voltage magnitude Vdd, which is the vertical axis in FIG. 48, is fixed and changed. Therefore, even when the gradation number range (256 gradations = 256 increments) is made constant, the magnitude of the voltage on the vertical axis can be adjusted, and the source driver circuit (IC) 14 can be generalized. it can.

  In FIG. 44, the voltage range of the electronic volume 291 is from Vdd to Vbv. Therefore, the output voltage Vad of the operational amplifier 231a is output from Vdd to Vbv. Vbv is input from outside the source driver circuit (IC) 14. Further, it may be generated inside the IC (circuit) 14. The switch S of the electronic volume 291 decodes 8-bit control data (gradation number) by the decoder circuit 532, the corresponding switch S is closed, and the voltage between the voltage Vdd and Vbv is output from Vad.

  In FIG. 44 and the like, the anode voltage Vdd is the origin. FIG. 81 enables adjustment of the voltage corresponding to the anode potential. The voltage from the operational amplifier 231c is applied to the terminal Vdd of the electronic volume 291. The applied voltage is Vbvh. The lower limit voltage of the electronic regulator 291 is Vbvl. Therefore, the voltage range applied to the source signal line 18 is Vbvh or less and Vbvl or more as shown in FIG. Since other matters are the same as or similar to those of the other embodiments, description thereof will be omitted.

  FIG. 39 is a block diagram showing in more detail the components of the current gradation circuit 334 and the voltage gradation circuit 371 of FIGS. The shift register circuit (selector circuit) 352 sequentially shifts in response to a start signal (ST1) and a clock (CLK1). The 9-bit holding position of DATA is designated to the first latch circuit (holding circuit) 351a by the shift operation. The DATA 9 bits are a total of 9 bits including an image signal 8 bits and a precharge signal 1 bit. The latch circuit 351a sequentially holds DATA in one horizontal period.

  DATA held in the first latch circuit is loaded into the second latch circuit 351b in the second stage by the load signal (LD). DATA held in the latch circuit 351b becomes an input of the voltage gradation circuit 371 and an input of the current gradation circuit 334. One bit of the precharge signal is a switching signal between the program voltage of the voltage gradation circuit 371 and the program current of the current gradation circuit 334. The precharge signal temporally controls the switching circuit 391 (corresponding to the switch 221 in FIG. 37, etc.). When the precharge signal is turned on from the output terminal 93, the precharge voltage is output first, and then the program current is output. Output.

  Since the sample and hold circuit of the voltage gradation circuit operates only at a relatively low speed, a one-stage rat circuit may be added for the sample and hold of the latch voltage gradation circuit to form a three-stage latch circuit. Needless to say. The switching circuit 391 may be formed on the substrate 30 by polysilicon technology.

  FIG. 40 shows a configuration in which outputs (for example, Vpa, Vpb, Vpc) from the precharge voltage generation circuit are transmitted through the wiring of the IC chip 15. The wiring is formed in the longitudinal direction of the IC chip (perpendicular to each output stage 251). Precharge voltage (synonymous with or similar to program voltage) Vp (Vpa, Vpb, Vpc, open) precharge voltage (synonymous with or similar to program voltage) wiring PS (PSa, PSb, PSc, PSd) is a source signal line 18 is wired so as to be orthogonal to 18. The precharge voltage (synonymous with or similar to the program voltage) wiring PS and the internal wiring 222 are orthogonal to each other, and a switch Sp is disposed at each intersection. The switch Sp is switched by a SEL signal (including a precharge voltage selection signal and open). When open is selected by the switch Sp0a, the precharge voltage is not output. The switch Sp can be freely set for each output terminal 93. An appropriate switch Sp is selected and controlled depending on the magnitude and change of the video signal.

  The difference between FIG. 38 and FIG. 40 is the configuration in which FIG. 38 samples and holds a precharge voltage corresponding to each video signal. The sampled and held precharge voltage is determined and applied for each output terminal by a precharge bit (a bit for determining whether to apply a precharge voltage). FIG. 39 shows a configuration in which a plurality of precharge voltages are generated and one precharge voltage is selected. The precharge voltage to be selected is determined by a precharge bit (SEL signal: a bit for specifying which precharge voltage is applied. However, there is a case where the precharge voltage is not applied (open) in some cases). Applied.

  Note that the precharge voltage (synonymous with or similar to the program voltage) is applied to all the source signal lines 18 simultaneously in the first period of 1H. Therefore, it is necessary to latch and hold the SEL signal.

  In the above embodiment, the precharge voltage (synonymous with or similar to the program voltage) is applied via the source driver IC 14, but the present invention is not limited to this. For example, a precharge voltage (synonymous or similar to program voltage) transistor element formed on the array 30 substrate is formed, and this transistor element is turned on / off to be applied to a precharge voltage (synonymous or similar to program voltage) line. It goes without saying that the precharge voltage (synonymous with or similar to the program voltage) applied may be applied to the source signal line 18.

  In FIG. 40 and the like, an open function (open selection) is provided. However, this is for ease of explanation, and is not necessarily limited to the configuration or formation. For example, as shown in FIG. 90, a switch 221b (selector circuit) is arranged or formed on the output side of a voltage output circuit 371 for a program voltage (precharge voltage), and a precharge voltage or the like is output from an output terminal 93. In the case of (driving method), the switch 221b may be set to the a terminal side, and in other modes, the switch 221b may be set to the b terminal side (the a terminal is not selected).

  In the above embodiments, the precharge voltage (synonymous with or similar to the program voltage) is described as being close to the anode voltage. However, depending on the pixel configuration, the precharge voltage (synonymous with or similar to the program voltage) is the cathode. May be close to voltage. For example, when the driving transistor 11a is formed of an N channel transistor, the current transistor is executed by the driving transistor 11a being discharged by the P channel transistor (the pixel configuration in FIG. 1 is a sink (sink) current). It is. In this case, the precharge voltage (synonymous with or similar to the program voltage) needs to be a voltage close to the cathode voltage.

  FIG. 51 shows another embodiment of the present invention. As the precharge voltage (program voltage) V0 corresponding to the 0th gradation of the electronic volume, a fixed voltage is applied in RGB as shown in FIG. Of course, you may change by RGB. The resistor R may be external to the electronic volume 291 as shown in the figure. By changing or replacing the resistor R, each Vpc voltage can be changed freely.

  In addition, it comprises so that the relationship of resistance value R1> R2> ...> Rn may be maintained. Further, at least the relationship of R1> Rn is maintained (Rn is a resistor that determines the Vpc voltage output from the last switch. R1 is on the low gradation side and Rn is on the high gradation side. R1 is for generating a voltage in the vicinity of the rising voltage of the driving transistor 11a, and Rn is for generating a white display voltage). In particular, it is preferable to maintain the relationship of R1> R2 (voltage between terminals of R1> voltage between terminals of R2). This is because, due to the characteristics of the driving transistor 11a, the difference between the V0 voltage and the voltage of the next first gradation is large between the voltages of the first gradation and the second gradation.

  The switch S (S1 to S7 in FIG. 51) is designated by decoding VDATA. Note that the number of selectable Vpc voltages is preferably 1/8 or more of the number of gradations of the display device when the display device is 6 inches or more (32 gradations or more in the case of 256 gradations). . In particular, it is preferably 1/4 or more (in the case of 256 gradations, 64 gradations or more). This is because the program current is insufficiently written to a relatively high gradation region. In a relatively small display panel (display device) of 6 inches or less, the number of selectable Vpc voltages is preferably 2 or more. This is because even if Vpc is one of V0, good black display can be realized, but it may be difficult to perform gradation display in a low gradation region. If Vpc is 2 or more, a plurality of gradations can be generated by FRC control, and good image display can be realized.

  SDATA that determines the potential at the point b correlates with the reference current Ic. Preferably, control is performed so that Ic is proportional to 1 / 1.5 or higher and 1/3. When the reference current Ic is large, the b-point potential is controlled to drop, and when the reference current Ic is small, the b-point potential is high. Therefore, when the reference current Ic is large, the potential difference between the resistors R increases, and the difference between the Vpc increases (the step change of the program voltage increases). Conversely, when the reference current Ic is small, the potential difference between the resistors R is small, and the difference between the Vpc is small.

  As shown in FIG. 52, when the voltage terminals are configured to correspond to the V2 voltage, V8 voltage, V32 voltage, V128 voltage and four times the gradation, as shown in FIG. A charge voltage circuit can be configured. The potential difference between the V2 voltage and the V8 voltage, the potential difference between the V8 voltage and the V32 voltage, the potential difference between the V32 voltage and the V128 voltage, and the potential difference between the V128 voltage and the V255 voltage are substantially equal. The broken line gamma in FIG. 52 matches the VI characteristic of the driving transistor 11a.

  From the above, good precharge drive (precharge voltage + program current drive, etc.) can be realized by configuring as in the embodiments of FIGS. The precharge voltage output from the circuit configuration of FIG. 58 changes to the vicinity of the target source signal line 18 potential, and a slight shift amount can be corrected by the program current, so that an image display with very good uniformity can be realized. .

  The configuration of FIG. 58 is an example in which the voltage terminals are seven terminals of V0, V1, V2, V8, V32, V128, and V255. However, the present invention is not limited to this. For example, the terminal positions may be 0, 8, 32, 128, 512. That is, this is an embodiment in which a V0 voltage terminal, a V8 voltage terminal, a V32 voltage terminal, a V128 voltage terminal, and a V512 voltage terminal are formed. The terminal positions may be 0, 1, 2, 8, 32, and 128. That is, a V0 voltage terminal, a V1 voltage terminal, a V2 voltage terminal, a V8 voltage terminal, a V32 voltage terminal, and a V128 voltage terminal may be formed. Of course, it may be in the vicinity, and may be, for example, a V0 voltage terminal, a V1 voltage terminal, a V3 voltage terminal, a V7 voltage terminal, a V31 voltage terminal, a V127 voltage terminal, or the like.

  As described above, according to the present invention, at least one set of voltage terminals is a multiple of 4 or the vicinity thereof. Even if it is 4 times, it differs depending on whether it starts from 0 gradation or 1 gradation. For example, V0, V1, V2, V8, V32, and V128 may be V1, V2, V7, V31, V127, and the like. That is, Vn / Vn-1 only needs to be in the vicinity of 4. For example, V127 / V31 is also in the vicinity of 4, which is a technical category of the present invention. Even in the case of V1, V3, V12, V31, V255, etc., the relationship between V12 and V3, which is one combination, that is, V12 / V3 is 4, which is a technical category of the present invention.

  It is preferable that the potential difference between the voltage terminals can be changed according to a reference current ratio or the like. FIG. 60 shows an embodiment in which the voltage terminals can be varied with a volume VR. Of course, a DA converter may be used instead of VR. Resistors R0 to R6 are arranged between the voltage Vdd and GND. Along with the change of the reference current ratio, the terminal voltage of the resistor R6 is changed by the volume VR. The voltage at each of the resistance terminals R0 to R6 is changed by the volume VR, and this change changes the voltage at the voltage terminals V1 to V256. Since the V0 voltage is a voltage of gradation 0, it is fixed at a predetermined voltage Va. The potentials of the voltage terminals V <b> 1 to V <b> 256 are commonly applied to a plurality of source driver circuits (IC) 14.

  In the above embodiment, the voltage terminals V1 to V256 are changed corresponding to the reference current ratio, but it is needless to say that the voltage terminals V1 to V256 may be changed due to other fluctuations such as the lighting rate.

  The embodiment of FIG. 60 is configured to change the voltage applied to the voltage terminal by the external resistor R of the source driver circuit (IC) 14. However, the present invention is not limited to this. For example, as shown in FIG. 55, the internal resistance Ra of the source driver circuit (IC) 14 is predetermined between the voltage terminals (between the V2 voltage and the V8 voltage, between the V8 voltage and the V32 voltage, and between the V32 voltage and the V128 voltage). You may comprise so that a voltage may be applied.

  In FIG. 55 and the like, the V1 voltage and the V2 voltage are separated, but as shown in FIG. 56, the V1 voltage is used as the precharge voltage Vpc1, and the precharge voltage Vpc2 and subsequent voltages are generated via the operational amplifier 231c. Needless to say, it may be configured as above.

  In FIG. 54 and the like, it is assumed that the resistance R of the electronic volume 291 is the same. By making the resistance value of the resistor R the same, the size of the IC chip can be reduced. However, the present invention is not limited to this. The resistance R may be changed. For example, the resistance value on the low gradation side is increased (as shown in FIG. 52, the potential difference of the potential corresponding to the gradation is large in the V0 to low gradation region), and the resistance value on the high gradation side. May be relatively small or absolute. Further, the resistance value of the resistor may be composed of two types or a plurality of types of low gradation side and high gradation side.

  For example, in order to generate the gamma curve shown in FIG. 52, the resistance value arranged between the precharge voltage Vpc terminals is set to a square characteristic. This embodiment is illustrated in FIG. The precharge voltage Vpc terminal voltage changes the resistance value to 1, 3, 5, 7, 9,...

  In FIG. 57 and the like, an appropriate precharge voltage can be generated by changing the V1 voltage, the V2 voltage, and the like. A DA circuit may be used to change the voltage. The DA circuit is controlled by the 8-bit data ID output from the controller circuit (IC).

  Although the above embodiment has been described as an embodiment of the precharge driving system, the present invention is not limited to this. Needless to say, the present invention can also be applied to a voltage driving method (for example, a driving method of an EL display panel having a pixel configuration shown in FIG. 2). In the voltage drive, the gamma curves of the RGB EL elements are different, so that an RGB independent gamma circuit is required.

  The configuration of FIG. 58 and the configuration of FIG. 57 may be combined. In FIG. 58, for example, the resistance value between taps between the V1 voltage and the V2 voltage is not a constant resistance, but 4R, 2R, R, and the like are changed. As a result of the change, the curve of FIG. 52 becomes a curve and more closely matches the VI characteristics of the transistor 11a.

  As described above, in the source driver circuit (IC) 14 of the present invention, the circuit configuration for generating the precharge voltage includes various configurations. Further, it goes without saying that the above matters can be applied to a circuit configuration for generating a precharge current or an overvoltage Id.

  FIG. 61 shows an embodiment in which the previously described precharge voltage circuit of the present invention is applied to a voltage drive system. The RGB V0 voltage is common. The electronic volume 291R is an R voltage generation circuit. The electronic volume 291G is a G voltage generation circuit. The electronic volume 291B is a B voltage generation circuit. With the configuration shown in FIG. 61, an RGB independent gamma curve can be generated, and a good white balance can be realized.

  As described above, it goes without saying that the circuit configuration and driving method of the present invention for generating the precharge voltage can also be applied to the voltage driving method. That is, the present invention is not limited to voltage + current driving.

  In FIG. 54, the precharge voltage Vpc is made to correspond in the entire gradation range, but the present invention is not limited to this. The precharge voltage Vpc generation circuit may be configured or arranged only in a region where the write current or the write voltage is insufficient. For example, in FIG. 54, current driving is performed, and writing shortage occurs in the low gradation region (assumed to be). Therefore, it goes without saying that the precharge voltage generation circuit is configured from V0 to V128 corresponding to the low gradation, and the rest can be omitted. Needless to say, the corresponding gradation may be intermittent so that the precharge generation circuit is configured only for the 0th gradation and the even gradation. Further, the precharge voltage of gradation 128 or higher may be only Vpc255. This is because the program current operates dominantly. It goes without saying that the above matters can be applied to other embodiments of the present invention.

  It is also preferable to configure as shown in FIG. FIG. 54 is a modification (also a simplified embodiment) of FIG. FIG. 54 shows an example of a four-point broken gamma, but this is for ease of explanation, and may be a four-point broken gamma or less or a four-point broken gamma or less.

  The feature of FIG. 54 is that the number of precharge voltages Vpc among V0 to V1, V1 to V2, and V2 to V4 is not constant. As an example, V0 to V1 are two of Vpc0 and Vpc1, V1 to V2 are 32-1 = 31 precharge voltages Vpc, V2 to V3 are 128-32 = 96 precharge voltages Vpc, and V3 to V4 are 255. −32 = 223 precharge voltages Vpc. That is, the number of precharge voltages is increased as the gray level is increased.

  The precharge voltage V0 corresponding to gradation 0 is common to RGB and is close to the anode voltage Vdd. Further, the precharge voltage V1 corresponding to the gradation 1 is different for RGB, and the potential difference between the V1 and V0 voltages is large. In addition, since the V1 voltage has a low gradation, writing deficiency is likely to occur in the current programming method, and the light emission efficiency of the EL element is low, so that the voltage drive needs to be dominant. For this reason, in FIG. 54, the V0 voltage and the V1 voltage are input from the outside of the source driver circuit (IC) 14.

  On the other hand, the range from the V3 voltage to the V4 voltage is close to the ground (GND) voltage. Further, since the program current is large, the current drive becomes dominant, and therefore it is basically not necessary to apply the precharge voltage Vpc. On the high gradation side, the output current with respect to the source signal line potential (the gate potential of the driving transistor 11a) has a linear relationship, and the output current increases with a slight potential change. Also, the current value is large. Therefore, the accuracy of the precharge voltage Vpc is not necessary. For this reason, there is no problem even if the number of gradations corresponding to the V3 voltage and the V4 voltage is increased.

  Preferably, the potential difference between V0 and V1, the potential difference between V1 and V2, the potential difference between V2 and V3, and the potential difference between V3 and V4 are preferably the same or in the vicinity. The potential difference in the vicinity is within 1V. By setting the potential difference in the vicinity in this way, the circuit for generating the voltages V0 to V4 can be facilitated, and the configuration of the electronic volume 291 can be simplified.

  As described above, the present invention is characterized in that the number of precharge voltages corresponding to each of the voltages V0 to V4 applied from the outside (which may be generated inside) is different.

  The V0 voltage may be fixed even if the reference current ratio changes. However, the V1 voltage position greatly depends on the change in the reference current ratio. This is because since the rising current of the driving transistor 11a of the pixel 16 is small, it is necessary to largely change the gate terminal potential (the source signal line 18 potential during programming) of the driving transistor 11a in accordance with the reference current ratio. When the driving transistor 11a is a P-channel transistor, it is necessary to lower the potential of the source signal line 18 as the reference current ratio increases. In addition, the voltage change due to the reference current ratio needs to be larger for the V4 voltage than for the V2 voltage.

  As described above, in the present invention, when driving to change the reference current ratio, the V0 voltage is fixed or the potential after the V1 voltage or the V2 voltage is changed while the potential near the predetermined voltage is maintained. There is a feature. When the driving transistor 11a is an N-channel transistor, the V0 voltage (rising voltage) is located on the GND potential side.

  Therefore, the potential relationship in FIG. 54 may be changed for the N channel. Since the change is easy for those skilled in the art, the description is omitted. As described above, the present invention will be described assuming that the driving transistor 11a is a P-channel transistor, but the present invention is not limited to this. Needless to say, it may be an N-channel transistor.

  FIG. 54 shows a configuration in which a built-in resistor of the source driver circuit (IC) 14 is formed or arranged between the voltages V0 and V1. Of course, the resistor R may be an external resistor. Further, the resistance value of the resistor R may be adjusted by trimming.

  If the V0 voltage is fixed and does not link with the V1 or V2 voltage, it is not necessary to form the resistor R as shown in FIG. Further, since the potential difference between the V0 voltage and the V1 voltage is relatively large, it is necessary to form a large resistance between the V0 voltage and the V1 voltage. A large resistor increases the number of parts of the resistor and directly leads to an increase in the size of the source driver circuit (IC) 14 chip.

  In FIG. 58, the V0 voltage and the V1 voltage are made independent in order to solve this problem. That is, no resistor is formed between the V0 voltage terminal and the V1 voltage terminal. Further, no resistor is formed between the V1 voltage terminal and the V2 voltage terminal. On the other hand, a resistor R is arranged between the V2 voltage terminal and the V8 voltage terminal, and a resistance of 8 times the resistance R is provided between one precharge voltage terminal such as between Vpc2 and Vpc3, between Vpc3 and Vpc4, and between Vpc4 and Vpc5. (8R) is formed. This is because there is a relatively large potential difference between the V2 voltage terminal and the V3 voltage terminal, and if the number of resistors R is small, a large amount of through current flows and power consumption increases.

  A resistor R is arranged between the V8 voltage terminal and the V32 voltage terminal, and a resistance four times the resistance R (8R) is provided between one precharge voltage terminal such as between Vpc8 and Vpc9, between Vpc9 and Vpc10, between Vpc10 and Vpc11. ) Is formed. This is because there is a relatively large potential difference between the V8 voltage terminal and the V32 voltage terminal, and if the number of resistors R is small, a large amount of through current flows and power consumption increases. A resistor R is arranged between the Vpc terminal between the V32 voltage terminal and the V128 voltage terminal. The reason why it can be configured by one part of the resistor is that the number of precharge voltage terminals formed between the V32 voltage terminal and the V128 voltage terminal is large, so that the number of the resistors R is large and no through current flows. The above matters are the same between the V128 voltage terminal and the V255 voltage terminal.

  It is preferable that the potential difference between the voltage terminals can be changed according to a reference current ratio or the like. FIG. 60 shows an embodiment in which the voltage terminals can be varied with a volume VR. Of course, the DA converter 291 may be used instead of VR. Resistors R0 to R6 are arranged between the voltage Vdd and GND. Along with the change of the reference current ratio, the terminal voltage of the resistor R6 is changed by the volume VR. The voltage at each of the resistance terminals R0 to R6 is changed by the volume VR, and this change changes the voltage at the voltage terminals V1 to V256. Since the V0 voltage is a voltage of gradation 0, it is fixed at a predetermined voltage Va. The potentials of the voltage terminals V <b> 1 to V <b> 256 are commonly applied to a plurality of source driver circuits (IC) 14.

  In the above embodiment, the voltage terminals V1 to V256 are changed corresponding to the reference current ratio, but it is needless to say that the voltage terminals V1 to V256 may be changed due to other fluctuations such as the lighting rate.

  The embodiment of FIG. 60 is configured to change the voltage applied to the voltage terminal by the external resistor R of the source driver circuit (IC) 14. However, the present invention is not limited to this. For example, as shown in FIG. 55, the internal resistance Ra of the source driver circuit (IC) 14 is predetermined between the voltage terminals (between the V2 voltage and the V8 voltage, between the V8 voltage and the V32 voltage, and between the V32 voltage and the V128 voltage). You may comprise so that a voltage may be applied.

  In FIG. 55 and the like, the V1 voltage and the V2 voltage are separated, but as shown in FIG. 56, the V1 voltage is used as the precharge voltage Vpc1, and the precharge voltage Vpc2 and subsequent voltages are generated via the operational amplifier 231c. Needless to say, it may be configured as above.

  In FIG. 54 and the like, it is assumed that the resistance R of the electronic volume 291 is the same. By making the resistance value of the resistor R the same, the size of the IC chip can be reduced. However, the present invention is not limited to this. The resistance R may be changed. For example, the resistance value on the low gradation side may be increased and the resistance value on the high gradation side may be decreased relatively or in absolute value. Further, the resistance value of the resistor may be composed of two types or a plurality of types of low gradation side and high gradation side.

  For example, in order to generate the gamma curve shown in FIG. 52, the resistance value arranged between the precharge voltage Vpc terminals is set to a square characteristic. This embodiment is illustrated in FIG. The precharge voltage Vpc terminal voltage changes the resistance value to 1, 3, 5, 7, 9,...

  Although the above embodiment has been described as an embodiment of the precharge driving system, the present invention is not limited to this. Needless to say, the present invention can also be applied to a voltage driving method (for example, a driving method of an EL display panel having a pixel configuration shown in FIG. 2). In the voltage drive, the gamma curves of the RGB EL elements are different, so that an RGB independent gamma circuit is required.

  As described above, in the source driver circuit (IC) 14 of the present invention, the circuit configuration for generating the precharge voltage includes various configurations. Further, it goes without saying that the above matters can be applied to a circuit configuration for generating a precharge current or an overvoltage Id.

  FIG. 61 shows an embodiment in which the previously described precharge voltage circuit of the present invention is applied to a voltage drive system. The RGB V0 voltage is common. The electronic volume 291R is an R voltage generation circuit. The electronic volume 291G is a G voltage generation circuit. The electronic volume 291B is a B voltage generation circuit. With the configuration shown in FIG. 61, an RGB independent gamma curve can be generated, and a good white balance can be realized.

  As described above, it goes without saying that the circuit configuration and driving method of the present invention for generating the precharge voltage can also be applied to the voltage driving method. That is, the present invention is not limited to voltage + current driving.

  In FIG. 54, the precharge voltage Vpc is made to correspond in the entire gradation range, but the present invention is not limited to this. The precharge voltage Vpc generation circuit may be configured or arranged only in a region where the write current or the write voltage is insufficient. For example, in FIG. 54, current driving is performed, and writing shortage occurs in the low gradation region (assumed to be). Therefore, it goes without saying that the precharge voltage generation circuit is configured from V0 to V128 corresponding to the low gradation, and the rest can be omitted. Needless to say, the corresponding gradation may be intermittent so that the precharge generation circuit is configured only for the 0th gradation and the even gradation. Further, the precharge voltage of gradation 128 or higher may be only Vpc255. This is because the program current operates dominantly. It goes without saying that the above matters can be applied to other embodiments of the present invention.

  The embodiment of FIG. 60 is configured to change the voltage applied to the voltage terminal by the external resistor R of the source driver circuit (IC) 14. However, the present invention is not limited to this. For example, as shown in FIG. 59, the internal resistance Ra of the source driver circuit (IC) 14 is predetermined between the voltage terminals (between the V2 voltage and the V8 voltage, between the V8 voltage and the V32 voltage, and between the V32 voltage and the V128 voltage). You may comprise so that a voltage may be applied.

  In FIG. 59 and the like, the V1 voltage and the V2 voltage are separated, but as shown in FIG. 496, the V1 voltage is used as the precharge voltage Vpc1, and the precharge voltage Vpc2 and subsequent voltages are generated via the operational amplifier 231c. Needless to say, it may be configured as above.

  The precharge voltages (V0, V1,...) Shown in FIG. 63 are preferably changed according to the temperature of the display panel. This is because the driving transistor 11a has temperature dependency on the driving voltage. In order to cope with this temperature dependency, as shown in FIG. 63, elements (posisters, thermistors) Rb, Rb2, Rc2, etc. that change with temperature are added, and V0, V1, and V2 voltages are appropriate voltages depending on the temperature. What is necessary is just to comprise so that it may change.

  The EL display device requires a cathode wiring and an anode wiring which are not found in the liquid crystal display device. Further, as shown in FIG. 8, the gate driver circuit requires two gate driver circuits: a gate driver circuit 12a (for driving the gate signal line 17a) and a gate driver circuit 12b (for driving the gate signal line 17b). is there. Therefore, the EL display device has a large number of wirings and complicated connection. For this reason, the frame of the panel becomes large for routing the wiring. The size of the flexible substrate for inputting signal lines to the panel increases, which directly leads to higher costs.

  FIG. 65 is an explanatory diagram of a configuration for solving this problem. For ease of explanation, in FIG. 65 and the like, the control signal line of the gate driver circuit 12 is ST (signal line for applying or transmitting a start pulse) and CLK (signal line for applying or transmitting a clock (shift) pulse. ), Only ENBL (signal line for applying or transmitting an enable pulse). In practice, it goes without saying that there are UD (signal lines for applying or transmitting signals in the up / down direction), signal lines for transmitting or supplying Vgh voltage or Vgl voltage, and the like.

  For ease of explanation, ST (signal line for applying or transmitting a start pulse), CLK (signal line for applying or transmitting a clock (shift) pulse), ENBL (signal line for applying or transmitting an enable pulse) , A signal line for transmitting a control signal such as UD (signal line for applying or transmitting a signal in an up / down direction) is called a control signal line, and a signal line for transmitting or supplying a Vgh voltage or a Vgl voltage is a voltage signal line. Call it.

  The source driver IC 14 is formed or configured by a silicon chip, and is mounted on the array substrate 30 by COG (chip on glass) technology. On the other hand, the gate driver circuit 12 is directly formed on the array substrate 30 by polysilicon technology such as low-temperature polysilicon, high-temperature polysilicon, or CGS.

  The control signal line (or power signal line) is connected to the gate driver circuit 12 or the like via the back surface of the source driver IC 14 or the wiring pattern of the source driver IC 14. As described above, the control signal line and the power signal line are supplied via the source driver IC 14, whereby the width of the flexible substrate to which the signal line and the like are connected can be reduced to the chip width of the source driver IC 14. Therefore, the cost can be reduced.

  In order to realize the configuration of FIG. 65, the source driver IC 14 of the present invention is configured (formed) as shown in FIG. FIG. 64 is a view of the source driver IC 14 of the present invention as seen from the back side. Wiring 645 and the like are formed at both ends of the chip 14. In FIG. 64, the wiring is a normal aluminum wiring and is formed in the IC manufacturing process. However, the formation method of the wiring 645 and the like is not limited to this, and may be formed by a screen printing technique after the IC 14 is completed. Needless to say, the wiring 645 and the like may be formed only on one side of the chip 14.

  The IC 14 is formed with an input terminal 643 such as a control signal line and a terminal 644 connected to the source signal line 18. A terminal 641a for connecting a control signal line is formed or arranged at the end of the chip 14. In addition, a wiring 645 is connected to the terminal 641a, and the other end of the wiring 645 is connected to the terminal 641b. Therefore, the control signal line connected to the range of G1a is connected to the terminal 641b on the side of the chip. The power signal line connected to the terminal 642a is connected to the terminal 642b through the wiring 645. It is assumed that the terminal 642 is connected to an anode or a cathode wiring. Therefore, the power signal line bridges the IC chip and is output to the output side of the IC 14 (the connection side with the source signal line 18).

  The reason why the wiring 645 is bridged on the IC 14 in this way is that the anode wiring 1815 and the like are often formed on the back surface of the IC 14 as a light shielding film of the IC 14. By forming the anode wiring 1815 on the back surface of the IC as a light shielding film, the IC does not operate due to the photoconductor phenomenon. By connecting the control signal line or the power signal line with the wiring 645, it is not necessary to cross the wiring on the array substrate 30, and a short circuit or the like at the crossing portion can be reduced and the manufacturing yield can be improved.

  In the embodiment of FIG. 64, the wiring 645 and the like are formed on the back surface of the IC chip 14 (the surface facing the array substrate 30 during mounting), but the present invention is not limited to this. The wiring 645 and the like may be formed or arranged on the surface of the IC chip 14. Needless to say, a flexible printed circuit having wiring 645 and the like may be disposed in the gap between the IC chip 14 and the array substrate 30.

  In the above embodiments, the wiring 645 and the like are formed in the source driver IC 14 and the signal lines are bridged. However, the present invention is not limited to this, and it goes without saying that the gate driver circuit 12 may be formed of a silicon chip (gate driver IC 12) or the like, and the wiring 645 or the like may be formed on the back surface of the gate driver IC 12 or the like. .

  A thin film (thick film) made of an inorganic material or an organic material is preferably formed over the wiring 645. The thickness of the thin film (thick film) needs to be at least 0.1 μm or more. However, it is preferably 3 μm or less. By forming a thin film (thick film), the wiring 645 is protected, and problems such as corrosion do not occur. The relative dielectric constant of the thin film (thick film) is preferably 3.5 or more and 6.0 or less.

  FIG. 65 shows a state in which the source driver IC 14 of the present invention is mounted on the array substrate 30. The power signal line (anode wiring in the embodiment) is output to the terminal 642b via the wiring 645 and branched to the pixel 16 portion of the display area 64. It is output from the terminal 642b at the right end of the IC chip of the cathode wiring and is connected to the cathode electrode 36 at the cathode connection point. The control signal line is also output from the terminal 641 b via the wiring 645 of the IC 14 and input to the gate driver circuit 12.

  66 is a cross-sectional view of the IC 14 mounted on the array substrate 30. FIG. A wiring 645 is formed on the back surface of the IC chip 14 to connect between the terminal 642a and the terminal 642b. A gold bump 664 is formed on the terminal 642. The gold bump 664 connects the terminal 662 of the array substrate 30 and the terminal 642 of the IC 14. Therefore, since the signal applied to the signal line 661 is electrically connected to the signal line 622 via the wiring 645 of the IC 14, the signal lines 661 intersect even if conductor lines such as the anode wiring 663 are formed on the array substrate 30. There is nothing.

  As shown in FIG. 64, the output terminal position is set so that the wiring 622 delivered from the source driver circuit (IC) 14 to the gate driver circuit (IC) 12 does not intersect. With the configuration described above, the back surface portion of the IC chip 14 can be used effectively, and the panel can be narrowed.

As described above, by bridging the power signal line or the control signal line via the wiring 645 of the IC 14, the effect that it does not intersect with the wiring formed on the substrate 30 is exhibited. As another great effect, as shown in FIG. 67, an effect that the size of the flexible substrate 671 for applying a signal line or the like to the panel can be reduced is also exhibited. In general, since the flexible substrate 671 is expensive, the smaller the size, the greater the cost merit.
As shown in FIG. 67, a signal or the like is input straight from the flexible substrate 671 to the input signal line to the IC 14. If the wiring 645 of the IC 14 is not provided, the control signal line needs to be bent by avoiding the IC 14 on the input surface of the substrate 30. If it bends, the frame of a panel will become large. By connecting via the wiring 645 of the IC chip 14 as in the present invention, the frame can be reduced.

  The embodiment described in FIG. 64 and the like is an embodiment in which the terminal 641a and the terminal 641b are connected by a wiring 645 or the like. That is, the signal input from the terminal 641a is output to the terminal 641b as it is. However, the present invention is not limited to this. For example, it goes without saying that a circuit or a wiring for branching, delaying or changing the input signal may be formed or arranged between the terminals 641.

  FIG. 68 shows a configuration in which a conversion circuit 681 is formed or arranged between the terminals 641a and 641b as an example. The conversion circuit 681 in the embodiment of FIG. 68 is an inverted output generation circuit. An inverted output generation circuit 681 generates an inverted signal of the input signal. For example, if it is an ST signal, a negative ST signal is generated. This negative ST signal is referred to as NST. More specifically, if ST is 1V in the period of one frame and becomes 3V, and the other periods are 0V, the NST signal becomes 0V in the period of 1H in one frame period and 3V in the other periods. Become. The above items also apply to the CLK and ENBL signals.

  That is, in FIG. 68, the signal input to the terminal 641a is converted into a positive signal and a negative signal by the inverting output circuit 681 and output from the terminal 681b. Therefore, input signals can be reduced in the source driver IC 14.

  Although FIG. 68 shows a circuit that generates an inverted output, the present invention is not limited to this. In FIG. 69, a delay circuit 691 composed of a flip-flop circuit (FF circuit) is formed in the source driver IC 14.

  In FIG. 69, as an example, the FF circuit 691 is disposed between the terminal 641a and the terminal 641b. The ST signal and the like are delayed by the FF circuit 691. The control signal (ST, CLK, etc.) of the gate driver circuit 12 is synchronized with the latch circuit 381 of the source driver circuit (IC) 14, and the timing of the program current applied to the source signal line 18 and the gate signal line 17a. It is necessary to adjust the timing of applying the on-voltage. This timing adjustment is performed by the FF circuit 691 or the like. With the above configuration, the timing adjustment of the control signal output from the controller circuit (IC) 722 is facilitated.

  In addition to the above embodiment, as shown in FIG. 70, control signals (ST, CLK, ENBL, etc.) may be generated from HD (horizontal scanning signal) and VD (vertical scanning signal). That is, the signal generation circuit 701 is formed or arranged in the source driver circuit (IC) 14. A signal generation circuit 701 generates control signals (ST, CLK, ENBL, etc.) from HD (horizontal scanning signal), VD (vertical scanning signal), and the like. With the above configuration, the number of signal lines to the source driver IC 14 can be further reduced.

  By supplying a video signal or the like as a differential signal to the source driver circuit (IC) 14, the number of signal lines can be reduced. Moreover, it can also be strong against noise. Similarly, as shown in FIG. 71, a gate signal (control signal (ST, ENBL, etc.) of the gate driver circuit 12) may be applied to the source driver IC 14 as a differential signal. The differential signal is converted into a parallel signal by a differential-parallel signal conversion circuit 621.

  In the embodiment of FIG. 71, the anode voltage and cathode voltage as power signals are input to the terminal 642a, and the gate signal (differential) for controlling the gate driver circuit 12 is input to the terminal 641a. The video signal (differential) and the control signal (differential) are input to the terminal 643. Needless to say, the gate signal, the video signal, and the control signal may be twisted pair differential signals. Further, the gate signal or the like may be transmitted by a thin coaxial cable.

  It goes without saying that the above embodiment can be applied to other terminals (643, 644, 642, etc.).

  The number of signal lines can be reduced by applying a differential signal to FIG. By forming the wiring 645 in the IC 14 as shown in FIGS. 64 and 66, signal lines and the like can be prevented from crossing. The above configuration is an effect that can be exhibited by forming the gate driver circuit 12 or the like on the array substrate 30 using polysilicon technology, forming the source driver IC 14 using a silicon chip or the like, and mounting the array driver 30 on the array substrate 30 using COG technology. is there.

  The above embodiment is an embodiment in which one IC 14 is used for the panel. However, the present invention is not limited to this. For example, as shown in FIG. 76, two (plural) IC chips 14 may be mounted on the array substrate 30 to constitute the display panel 1334. A power signal line or a control signal line or both signal lines are formed or arranged at both ends of the IC 14, and a differential-parallel signal conversion circuit 621 is formed or disposed at both ends of the IC 14. Has been placed.

  Which differential-parallel signal conversion circuit 621 is operated is switched by a logic signal (voltage level) applied to the selector signal GSEL. In FIG. 76, the differential-parallel signal conversion circuit 621a1 operates in the IC chip 14a, and a control signal for the gate driver circuit 12a is output from the differential-parallel signal conversion circuit 621a1. In the IC chip 14b, the differential-parallel signal conversion circuit 621b2 operates, and a control signal for the gate driver circuit 12b is output from the differential-parallel signal conversion circuit 621b2.

  As shown in FIG. 73, the differential signal is output in synchronization with H and L of the A signal (discrimination signal) of the main circuit. When the A signal is L, the program voltage (VR, VG, VB) is output, and when the A signal is H, the program current (IR, IG, IB) is output.

  In addition, program currents (IR, IG, IB) and program voltages (VR, VG, VB) as data signals and data signals DM, DS are transmitted. That is, the differential signal is multiplexed in four phases of R video signal, G video signal, B video signal, and D data signal (VR, IR, VG, IG, VB, IB, DM, DS, VR, IR,・ ・ ・ ・ ・ ・). Note that during the video blanking period, DM and DS signals are continuously transmitted.

  It goes without saying that the precharge time may be applied from the controller circuit (IC) 722 or the like to the source driver circuit (IC) 14 by a TTL or CMOS logic waveform signal or the like. For example, the precharge voltage (precharge current) is applied to the source signal line 18 during the H level period of the logic waveform signal, and the precharge voltage (precharge current) is applied during the L level period of the logic waveform signal. It is controlled or configured not to be output to the source signal line 18. Needless to say, the precharge time may be controlled (variable) according to the lighting rate. When the lighting rate is low, it means that there are many low gradation pixels. Therefore, the precharge time is lengthened. Conversely, when the lighting rate is high, it means that there are many high gradation pixels. In this case, lack of programming current writing does not occur or is inconspicuous (not recognized). Therefore, the precharge time may be short.

  FIG. 74 describes the relationship with the start (ST) signal. CLK, ST, and RGB or (RGBD) of the video signal are also transmitted (transmitted) with the amplitude of the Diff voltage centered on 0 V (GND). Note that the Diff voltage as the amplitude is set, variable, or adjusted by a terminating resistor or the like.

  As shown in FIG. 74, CLK that synchronizes with RGB as a video signal has the same frequency. That is, the DATA contents are identified by the rising edge and falling edge of CLK. By maintaining such a relationship between DATA and CLK, the frequency is made steady and unnecessary radiation is reduced. On the other hand, the St signal has twice the width of CLK and is detected at the rising or falling edge of CLK. The phase of CLK is controlled by the PLL circuit 721. As described above, the differential signal is transmitted and transmitted / received.

  In the present invention, as illustrated in FIG. 79, a differential signal is output from the controller circuit (IC) 722 and received by the source driver circuit (IC) 14 as an example. A constant current circuit Icon is formed in the controller circuit (IC) 722, and the transistors M1 and M2 are controlled, whereby TxV + and TxV− signals are output from the terminal 643c. The signal output from the terminal 643c is transmitted through the wiring of the flexible board, the wiring of the printed board, the cable line, the coaxial wiring, and the like, and is applied to the input terminal 643a of the source driver circuit (IC) 14.

  The signal applied to the terminal 643a is applied to the comparator 791 as a differential signal (RxV +, RxV−) and restored to the logic signal TDATA. Resistors RT1 and RT2 are external resistors of the source driver circuit (IC) 14. Terminate the Icon current path.

  The resistors RT1 and RT2 may be built in the source driver circuit (IC) 14. It goes without saying that the source driver circuit (IC) 14 may be formed directly on the substrate 30 by polysilicon technology (low temperature polysilicon technology, high temperature polysilicon technology, CGS technology) or the like.

  The value of the resistor RT1 or the like is selected according to the impedance of the transmission line. In the configuration of the present invention, the value of the resistance RT is set to 100Ω or more and 300Ω or less.

  The switches (ST1, ST2) built in the source driver circuit (IC) 14 are exemplified by analog switches. Whether the switch ST is turned on or off is controlled by a logic level applied to a switching input terminal (not shown) of the source driver circuit (IC) 14.

  The switch ST is not limited to a switch. In the IC process, it may be selected and short-circuited by aluminum wiring according to the signal specification input to the display panel. This is because the differential input configuration described with reference to FIG. 80 or the CMOS level input configuration described with reference to FIG. 81 is determined in advance according to the signal specifications applied to the display panel. That is, it is rare that the switch ST needs to switch between the CMOS level signal and the differential signal in a timely manner.

  Of course, as shown in FIG. 80, it goes without saying that the terminal ST may be connected to the path of the input terminal of the comparator 791 or the output terminal of the controller circuit (IC) 722 without providing the switch ST. As for the termination resistor RT, even if there are a plurality of source driver circuits (IC) 14, one termination resistor RT may be arranged, installed, or configured in one wiring. The termination resistor RT may be composed of a volume so that the resistance value can be changed or changed. Further, the resistance value may be adjusted to a target value by trimming the resistance RT.

  In the configuration of FIG. 79, when the switches ST (ST1, ST2) are turned on (closed), the input to the source driver circuit (IC) 14 becomes a differential signal input. When the switch ST is turned off (opened), it becomes a CMOS or TTL logic signal input. In the case of CMOS level or TTL level input, as shown in FIG. 81, a constant DC voltage for determining the logic level is applied to the negative terminal of the comparator 791, and a logic signal is applied to the positive terminal. When the signal level applied to the + terminal is equal to or higher than the DC voltage applied to the − terminal, it is determined as H level logic, and when the signal level applied to the + terminal is equal to or lower than the DC voltage applied to the − terminal, L Judged as level logic. However, the comparator 791 is preferably configured to have a hysteresis characteristic for logic determination. In the present invention, for ease of explanation, it is assumed that the signal is a CMOS level signal.

  In the configuration of FIG. 79, the output signal from the controller circuit (IC) 722 is shown to be applied to one source driver circuit (IC) 14. However, in practice, the output signal from the controller circuit (IC) 722 is applied to a plurality of source driver circuits (IC) 14 as shown in FIGS.

  FIG. 80 shows the case of differential signal input. A termination resistor RT is disposed on the output wiring from the controller circuit (IC) 722 (for example, 8 bits of differential signals D0 + / D0−, D1 + / D1−D7 + / D7−). The controller circuit (IC) 722 drives a plurality of source driver circuits (IC) 14. A comparator 791 in the source driver circuit (IC) 14 converts the differential signal of each bit into a logic signal (TDATA) of each bit. TDATA is input to the drive (processing) circuit 811. A signal processed or controlled by the drive circuit 811 is output from the output terminal 93 and applied to the source signal line 18 of the display panel.

  FIG. 81 shows a case of a CMOS level signal (logic signal). A DC voltage (DC voltage) V 0 is applied to the − terminal (which may be a + terminal) of the comparator 791. When the signal level of the logic signals D0 to D7 is equal to or higher than the V0 voltage, it is determined as the H level. When the signal level of the logic signals D0 to D7 is equal to or lower than the V0 voltage, it is determined as the L level. Therefore, in the configuration of FIG. 81, the comparator 791 functions as a buffer.

  79 and 80, the source driver circuit (IC) 14 includes both a differential interface (differential IF) 621a and a CMOS (TTL) interface (CMOS IF) 621b as shown in FIG. is doing. Therefore, the IF specification can be selected according to the use state. In FIG. 82A, the controller circuit (IC) 722 outputs a CMOS level signal. The source driver circuit (IC) 14 uses a CMOS-IF having the configuration shown in FIG.

  Also in FIG. 82B, the controller circuit (IC) 722 outputs a CMOS level signal. In the configuration of FIG. 82B, a mode conversion circuit (IC) 821 is provided. The mode conversion circuit (IC) 821 has a function of converting a CMOS signal into a differential signal. The controller circuit (IC) 722 outputs a CMOS signal from the CMOS-IF 621b, and the mode conversion circuit 821 converts the signal received by the CMOS-IF 621b into a differential signal and outputs it from the differential IF 621a. The differential signal output from the differential IF 621a is input to the differential IF 621a of the source driver circuit (IC) 14.

  As shown in FIG. 75, the output terminal position is set so that the wiring 622 delivered from the source driver circuit (IC) 14 to the gate driver circuit (IC) 12 does not intersect.

  As described above, the source driver circuit (IC) 14 can receive both the differential signal and the CMOS (TTL) level signal by providing the circuit configuration of FIG.

  FIG. 75 shows a configuration using one source driver circuit (IC) 14. FIG. 76 shows a configuration using a plurality of source driver circuits (ICs) 14.

  75 and 76 show that the differential-parallel signal conversion circuit 621 is disposed at both ends of the IC chip 14, but the present invention is not limited to this. One differential-parallel signal conversion circuit 621 may be provided, and the control signal line or the like may be branched to both ends of the chip 14 by the wiring 701. What is important is that a power signal line or a control signal line can be output at both ends of the IC chip 14, and when a plurality of IC chips 14 are mounted on the array substrate 30 as shown in FIG. It is possible to switch whether or not the output of the signal line or the control signal line is output (or to prevent the image display from being affected even if a signal or the like is output from both). Switching is performed by a GESL signal.

  The cascade wiring 771 is not limited to being formed on the array substrate 71. For example, as shown in FIG. 77, a cascade wiring pattern 771 may be formed with a flexible substrate 671 or a printed substrate, and cascade connection may be performed via the flexible substrate 671 or the like.

  As shown in FIG. 78, the output signal 622 to the gate driver 12 may be controlled for each source driver circuit (IC) 14 by the Gcntl signal. In FIG. 78, by setting the Gcntl1a signal of the source driver circuit (IC) 14a to the H level, a control signal to the gate driver circuit 12a is output from the output terminal 641b1 of the source driver circuit (IC) 14a.

  By setting the Gcntl1a signal of the source driver circuit (IC) 14a to L level, the output terminal 641b1 of the source driver circuit (IC) 14a becomes high impedance. Further, by setting the Gcntl1b signal of the source driver circuit (IC) 14a to the L level, the output terminal 641b2 of the source driver circuit (IC) 14a becomes a high impedance state. In FIG. 78, since there is no signal to be output to the output terminal 641b2 of the source driver circuit (IC) 14a, the Gcntl1b signal is fixed at the L level.

  The source driver circuit (IC) 14b outputs a control signal to the gate driver circuit 12b from the output terminal 641b2 of the source driver circuit (IC) 14b by setting the Gcntl2b signal of the source driver circuit (IC) 14b to the H level. The Note that by setting the Gcntl2a signal of the source driver circuit (IC) 14b to L level, the output terminal 641b1 of the source driver circuit (IC) 14b becomes high impedance. In FIG. 78, since there is no signal to be output at the output terminal 641b1 of the source driver circuit (IC) 14b, the Gcntl2a signal is fixed at the L level.

  In the above embodiment, two source driver circuits (IC) 14 are used in one display panel. However, the present invention is not limited to this. Three or more source driver circuits (IC) 14 may be used. In the case of three or more, at least two output terminals 641b of the source driver circuit (IC) 14 are in a high impedance state. Needless to say, the high impedance state can be realized by manipulating the GSEL signal and the Gcntl signal.

  Accordingly, the same source driver IC 14 can be used regardless of whether one source driver IC 14 of the present invention is mounted on the array 30 or a plurality of source driver ICs 14 are mounted. In addition, when one is used, the present invention can be applied even when the gate driver circuit 12 is formed or arranged at one end of the screen 64.

  In some cases, it may be in the input direction. For example, the output pulse of the start pulse (ST) from the gate driver circuit 12 may be input to the terminal 2821b and output from the terminal 2821a. This output pulse is input to the control IC 722. With this output pulse, the control IC 722 can monitor the operation of the gate driver circuit 12 or determine its normality.

  In the present invention, the source driver IC 14 is formed of silicon or the like and mounted on the substrate 30 using COG technology or the like. However, the present invention is not limited to this. You may mount using TAB or COF technology. The circuit 14 of the source driver IC may be directly formed on the array substrate 30 using polysilicon technology. This is particularly effective for the configuration shown in FIG. In addition, the IC chip 14 is mounted on the array substrate 30 (the substrate on which the pixel electrode or the like is formed). However, the present invention is not limited to this. The source signal is formed on the counter substrate side and formed on the array substrate 30 or the like. You may connect with the line 18 etc. It goes without saying that the above matters can be applied to other embodiments of the present invention.

  In the current driving method, the problem is that the program current becomes small in the low gradation region, resulting in insufficient writing. In order to deal with this problem, the present invention implements precharge driving, voltage + current driving, reference current control, and the like.

  The cause of insufficient writing in current driving is greatly influenced by the parasitic capacitance Cs of the source signal line 18 as shown in FIG. The parasitic capacitance Cs is generated at the intersection of the gate signal line 17 and the source signal line 18.

  In the following description, for ease of explanation, it is assumed that the driving transistor 11a of the pixel 16 is a P-channel transistor and that current programming is performed with a sink current (a current sucked into the source driver circuit (IC) 14). Explain. When the driving transistor 11a of the pixel 16 is an N-channel transistor or when the current program is executed with the discharging current (current discharged from the source driver IC 14) from the driving transistor 11a, the relation is reversed. Since it is easy for those skilled in the art to change or read the reverse relationship, the description is omitted.

  In the following description, the driving transistor 11a of the pixel 16 is not limited to the P channel. Further, the pixel configuration will be described by exemplifying the pixel configuration in FIG. 1, but the pixel configuration is not limited to this, and it is needless to say that any other current-driven pixel configuration may be used. Needless to say, the above matters are applied to the present invention described before or after.

  As shown in FIG. 83A, when changing from black display (low gradation display) to white display (high gradation display), the source driver circuit (IC) 14 is mainly driven by a sink current. is there. The source driver circuit (IC) 14 absorbs the charge of the parasitic capacitance Cs with the program current Id1 (Iw). By sinking the current, the charge of the parasitic capacitance Cs is discharged, and the potential of the source signal line 18 is lowered. Accordingly, the gate terminal potential of the driving transistor 11a of the pixel 16 is lowered, and current programming is performed so that the program current Iw flows.

  When the white display (high gradation display) is changed to the black display (low gradation display), the operation of the driving transistor 11a of the pixel 16 is mainly performed. The source driver circuit (IC) 14 outputs a black display current, but does not operate effectively because it is very small. The driving transistor 11a operates and charges the parasitic capacitance Cs so as to match the potential of the program current Id2 (Iw). By charging the parasitic capacitance Cs with a charge, the potential of the source signal line 18 rises. Therefore, the gate terminal potential of the driving transistor 11a of the pixel 16 rises and current programming is performed so that the program current Iw flows.

  However, in the driving shown in FIG. 83A, the current Id1 is small in the low gradation region, and because of the constant current operation, a very long time is required for discharging the charge of the parasitic capacitance Cs. In particular, since it takes a long time to reach the white luminance, the luminance of the upper side in the white window display is lower than the predetermined luminance. Therefore, it is visually noticeable. In FIG. 83B, the current Id2 is relatively large because the driving transistor 11a operates in a non-linear manner. For this reason, the power reception time of Cs is relatively short. In particular, since the time until the black luminance is reached is short, the luminance of the lower side tends to be lowered in the white window display, which is visually inconspicuous.

  In order to solve the problem of insufficient programming current writing, voltage + current driving, punch-through voltage driving, duty driving, and precharge driving are performed. However, with this method alone, if the panel is large, it may be difficult to realize the black to white display in FIG. As a countermeasure, in the present invention, the program current from the source driver circuit (IC) 14 is increased in the first half of 1H. In the second half, the regular program current Iw is output. That is, under a predetermined condition, a current larger than a predetermined program current is supplied to the source signal line 18 at the beginning of 1H, and a regular program current is supplied to the source signal line 18 in the second half. This embodiment will be described below.

  The drive method (drive device or drive system) described below is called overcurrent (precharge current or discharge current) drive. In addition, overcurrent (precharge current or discharge current) driving can be combined with other driving methods or driving devices (voltage + current driving, punch-through voltage driving, duty driving, precharge driving, etc.) of the present invention. Needless to say. Needless to say, it can be combined with other embodiments such as the differential signal IF of FIG.

  FIG. 84 is an explanatory diagram of the source driver circuit (IC) 14 that implements the overcurrent (precharge current or discharge current) driving system of the present invention. The basic configuration is the configuration shown in FIGS. 22, 23, 24, 26, 27, 28, 28, and the like. However, for ease of illustration, a current circuit having one unit transistor 224 is referred to as a transistor group 841a and is indicated by '1'. Similarly, a current circuit having two unit transistors 224 is referred to as a transistor group 841b and is indicated by '2'. Further, a current circuit having four unit transistors 224 is a transistor group 841c and is indicated by '4'. A current circuit having eight unit transistors 224 is referred to as a transistor group 841d and is indicated by '8'. One output stage of the transistor group 841 is a current output circuit 251c. In order to facilitate drawing, RGB has 6 bits each.

  In the configuration of FIG. 84, the transistor group 841f is a transistor group that supplies an overcurrent (precharge current or discharge current) program current. That is, an overcurrent (pre-charge current or discharge current) is caused to flow through the source signal line 18 by turning on / off the switch D5 of the most significant bit of the gradation data. By flowing an overcurrent (precharge current or discharge current), the charge of the parasitic capacitance Cs can be discharged in a short time.

  The most significant bit is used for overcurrent (precharge current or discharge current) control for the following reason. First, for ease of explanation, it is assumed that the gradation is changed from 1 gradation to 4 gradations. The number of gradations is 256 gradations (8 bits for each RGB).

  Even when the gradation is changed from one gradation to the white gradation, when the gradation is changed from one gradation to a halftone or more (128 gradations or more), the program current is not insufficiently written. This is because the program current is relatively large and the parasitic capacitance Cs is charged and discharged relatively quickly.

  However, when the gradation level changes from 1 gradation to halftone or less, the program current is small, and the parasitic capacitance Cs cannot be sufficiently charged / discharged during the 1H period. Therefore, it is necessary to improve the gradation change to a halftone or less, such as 1 gradation to 4 gradations. In this case, the overcurrent (precharge current or discharge current) driving of the present invention is performed.

  Since the gradation changing as described above is equal to or lower than the halftone, the most significant bit is not used to specify the program current. In other words, when changing from one gradation, the target gradation is '011111' or less (the most significant bit switch D5 is constantly in the off state. The present invention constantly controls the most significant bit in the off state. Overcurrent (pre-charge current or discharge current) drive is performed.

  If the first gradation (gradation before change) is 1, the switch D0 is on and one unit transistor 224c operates. If the target gradation is 4, the switch D2 operates and four unit transistors 224c operate. However, if the number of unit transistors 224c is four, the charge of the parasitic capacitance Cs cannot be sufficiently discharged to the target value. Therefore, the switch D5 is closed and the transistor group 841f is operated. The operation of the D5 switch may be performed in addition to the operation of the D2 switch (the first half of 1H turns on the D5 and D2 switches and the second half turns on only the D2 switch), and the first half of 1H takes the switch D5. Only the switch D2 may be turned on in the latter half.

  When the switch D5 is turned on, 32 unit transistors 224c operate. Therefore, 32/4 = 8 compared to the operation of only the D2 switch, so that the charge of the parasitic capacitance Cs can be discharged at a speed eight times higher. Therefore, the programming current can be improved.

  Whether or not the switch D5 is turned on is determined by the controller circuit (IC) 722 for each RGB video data. A judgment bit KDATA is applied from the controller circuit (IC) 722 to the source driver circuit (IC) 14. KDATA is 4 bits as an example. When KDATA = 0, overcurrent (precharge current or discharge current) driving is not performed. When KDATA = 1, precharge driving (voltage + current driving) is performed. When KDATA = 2 to 15 performs overcurrent (precharge current or discharge current) driving, the magnitude of KDATA indicates a time for turning on the D5 bit.

KDATA is held in the latch circuit 331 for 1H period. The counter circuit 332 is reset by HD (1H synchronization signal) and counted by the clock CLK. The data of the counter circuit 332 and the latch circuit 331 are compared, and when the count value of the counter circuit 332 is smaller than the data value (KDATA) of the latch circuit 331, the AND circuit 333 continues to output the ON voltage to the internal wiring 222b. The on state of the switch D5 is maintained. Therefore, the current of the unit transistor 224c of the transistor group 841f flows through the internal wiring 222a and the source signal line 18. Note that the switch 222b is closed during current programming, and the switch 221a is closed and the switch 221b is open during precharge driving.
FIG. 91 is an explanatory diagram of the operation of the controller IC (circuit) 722. However, it is explanatory drawing of the process of 1 pixel row (RGB group). Video data DATA (8 bits × RGB) is latched in two stages in latch circuits 351a and 351b in synchronization with the internal clock. Therefore, the previous 1H video data is held in the latch circuit 351b, and the current video data is held in the latch circuit 351a.

  The comparison circuit 911 compares the video data before 1H with the current video data, and derives the value of KDATA. The video data DATA is transferred to the source driver circuit (IC) 14. Further, the controller circuit (IC) 722 transfers the upper limit count value CNT of the counter 332 to the source driver circuit (IC) 14.

  KDATA is determined by the comparison circuit 911. The determination is made based on the video data before the change (data before 1H) and the video data after the change (current data). The data before 1H indicates the current potential of the source signal line 18. The current data indicates the target potential of the source signal line 18 to be changed.

  As shown in FIG. 83, it is important to write the program current in consideration of the potential of the source signal line 18. The write time t can be expressed by T = ACV / I (A: proportionality constant, C: magnitude of parasitic capacitance, V: changing potential difference, I: program current). Therefore, if the potential difference V that changes is large, the writing time becomes long. On the other hand, if the program current I = Iw is increased, the write time is shortened.

  In the present invention, I is increased by overcurrent (precharge current or discharge current) driving. However, in any case, if I is increased, the target source signal line 18 potential may be exceeded. Accordingly, when overcurrent (precharge current or discharge current) driving is performed, it is necessary to consider the potential difference V. From the current potential of the source signal line 18 and the next video data (current video data (video data to be applied next = (after change: vertical direction in FIG. 92)), the target source signal line 18 potential. Find KDATA.

  KDATA may be the time to turn on the D5 switch, but it may be the magnitude of current in overcurrent (precharge current or discharge current) driving. Further, the ON time of the D5 switch (the longer the time is, the longer the overcurrent (precharge current or discharge current) application time applied to the source signal line 18 is, and the effective value of the overcurrent (precharge current or discharge current) is larger. And the magnitude of the overcurrent (precharge current or discharge current) (the larger the magnitude, the larger the effective value of the overcurrent (precharge current or discharge current) applied to the source signal line 18). You may combine. For ease of explanation, KDATA is first described as being the D5 switch on time.

  The comparison circuit 911 compares the video data before 1H and after the change (see FIG. 92) to determine the size of KDATA. The case where 0 or more data is set in KDATA is the case where the following conditions are met.

  When the video data before 1H is in a low gradation region (preferably in the region of 0 gradation or more and 1/8 or less of all gradations. For example, in the case of 64 gradations, 0 gradation or more and 8 gradations. And the video data after the change is less than or equal to the halftone area (preferably an area that is greater than or equal to 1 gradation and less than or equal to 1/2 of all gradations).

  For example, in the case of 64 gradations, the area is from 1 gradation to 32 gradations. ) Is set to KDATA. The data to be set is determined in consideration of the VI characteristic curve of the driving transistor 11a. The potential difference from the Vdd voltage of the source signal line 18 to V0 (complete black display) which is the voltage of the 0th gradation is large. Further, the potential difference from the V0 voltage to V1 of the first gradation is large. The potential difference between the V2 voltage and the V1 voltage, which is the next second gradation, is considerably smaller than the potential difference from the V0 voltage to the V1 voltage. Thereafter, the potential difference decreases as V3 and V2, and V4 and V3. As described above, the potential difference becomes smaller as the gray scale level is increased. This is because the VI characteristic of the driving transistor 11a is nonlinear.

  The potential difference between the gradations is proportional to the amount of discharge of the parasitic capacitance Cs. Accordingly, the application time of the program current, that is, the overcurrent (precharge current or discharge current) driving is linked to the application time and magnitude of the overcurrent (precharge current or discharge current) Id. For example, the application time of the overcurrent (precharge current or discharge current) Id is shortened just because the gradation difference between V0 (gradation 0) before 1H and V1 (gradation 1) after the change is small. I can't. This is because the potential difference is large.

  On the contrary, there are cases where it is not necessary to increase the overcurrent (pre-charge current or discharge current) even if the gradation difference is large. For example, in the gradation 10 and the gradation 32, the potential difference between the potential V10 of the gradation 10 and the potential 32 of the gradation 32 is small and the program current Iw of the gradation 32 is also large, so that the parasitic capacitance Cs can be charged and discharged in a short time. Because.

  In FIG. 92, the horizontal axis indicates the gradation number of the video data before 1H (before the change, that is, the current potential of the source signal line 18). The vertical axis indicates the gradation number of the current video data (after the change, that is, the target source signal line 18 potential to be changed).

  The change from the 0th gradation (1H before) to the 0th gradation (after the change) has no potential change, so KDATA may be zero. This is because the potential of the source signal line 18 does not change. The change from the 0th gradation (before 1H) to the 1st gradation (after the change) needs to be changed from the V0 potential to the V1 potential as shown in FIG. Since the V1-V0 voltage is large, KDATA is set to a maximum value of 15 (example). This is because the potential change of the source signal line 18 is large. To change from the first gradation (before 1H) to the second gradation (after change), it is necessary to change from the V1 potential to the V2 potential. Since the V2-V1 voltage is relatively large, KDATA is near the maximum value. 12 (which is an example). This is because the potential change of the source signal line 18 is large. To change from the third gradation (before 1H) to the fourth gradation (after change), it is necessary to change from the V3 potential to the V4 potential. However, since the V4-V3 voltage is relatively small, KDATA is set to a small value of 2. This is because the potential change of the source signal line 18 is small, charging / discharging of the parasitic capacitance Cs can be performed in a short time, and a target program current can be written into the pixel 16.

  Even if the gradation before the change is a low gradation area, the value of KDATA is 0 when the gradation after the change is halftone or higher. This is because the program current corresponding to the changed gradation is large, and the potential of the source signal line 18 can be changed to the target potential or a nearby potential within the 1H period. For example, when changing from the second gradation to the 38th gradation, KDATA = 0.

  When the gradation after the change is lower than that before the change, overcurrent (pre-charge current or discharge current) driving is not performed. When changing from the 38th gradation to the second gradation, KDATA = 0. This is because FIG. 83B corresponds to this case, and the program current Id is mainly supplied from the driving transistor of the pixel 16 to the parasitic capacitance Cs. In the case of FIG. 83 (b), it is preferable not to implement the overcurrent (precharge current or discharge current) drive method, but to implement the voltage + current drive method or the precharge voltage drive.

  In the overcurrent (precharge current or discharge current) driving method of the present invention, it is effective to combine with a driving method for increasing the reference current or a driving method for controlling the reference current ratio and duty. This is because the overcurrent (pre-charge current or discharge current) can also be increased in the configuration of FIG. 84 due to the increase in the reference current. Therefore, the charge / discharge time of the parasitic capacitance Cs is also shortened. It is also possible to control the magnitude of the overcurrent (precharge current or discharge current) of the overcurrent (precharge current or discharge current) driving method by controlling the magnitude of the reference current or the reference current ratio. It is a characteristic configuration.

  As described above, KDATA is determined by the control IC (circuit) 722, and KDATA is transmitted to the source driver circuit (IC) 14 as a differential signal. The transmitted KDATA is held by the latch circuit 331 in FIG. 84, and the D5 switch is controlled.

  The table in FIG. 92 may be set such that KDATA may be set using a matrix ROM table, but KDATA may be calculated (derived) using a multiplier of the controller circuit (IC) 722 using a calculation formula. Good. In addition, KDATA may be determined by a change in the external voltage of the controller circuit (IC) 722. Further, the present invention is not limited to being implemented by the controller circuit (IC) 722, but may be implemented by the source driver circuit (IC) 14.

  In the present invention, the magnitude of the program current Iw varies in proportion to the reference current depending on the magnitude of the reference current. Therefore, the magnitude of the overcurrent (precharge current or discharge current) for driving the overcurrent (precharge current or discharge current) shown in FIG. 84 also changes in proportion to the magnitude of the reference current. It goes without saying that the magnitude of KDATA described in FIG. 92 also needs to be linked to the change in the magnitude of the reference current. That is, it is preferable that the magnitude of KDATA is linked to the magnitude of the reference current or the magnitude of the reference current is taken into consideration.

  The technical idea of the overcurrent (precharge current or discharge current) driving method of the present invention is that the overcurrent (precharge current or discharge current) corresponds to the magnitude of the program current, the output current from the driving transistor 11a, etc. The size, the application time, and the effective value are set.

  The comparison circuit 911 or the comparison means performs comparison for each RGB video data, but it goes without saying that KDATA may be calculated by obtaining the luminance (Y value) from the RGB data. That is, instead of simply comparing each RGB, KDATA is calculated, determined, or calculated in consideration of chromaticity change and luminance change, and in consideration of continuity, periodicity, and change rate of gradation data. Needless to say, KDATA may be derived in consideration of video data of peripheral pixels or data similar to video data, not in units of pixels. For example, there is exemplified a method in which the screen 64 is divided into a plurality of blocks, and KDATA is determined in consideration of video data in each block.

  Further, it goes without saying that the above items can be applied in combination to other embodiments such as a display device and a display panel of the present invention. Further, an N-fold pulse drive method (such as FIG. 6), an N-fold current drive pixel method (such as FIG. 19), a non-display area division drive method (such as FIG. 14), and a field sequential drive method (such as FIG. 9 and FIG. 12), voltage + current driving method (for example, FIG. 33, FIG. 34, etc.), punch-through voltage driving method (see the matters relating to punch-through voltage in the specification), precharge driving method (for example, FIG. 84, etc.), It goes without saying that the present invention can be implemented in combination with other driving methods such as a multiple line simultaneous selection driving method (for example, FIG. 16).

  In FIG. 84 and the like, the time for selecting the D5 switch is preferably set to 3/4 period or less of 1H (one horizontal scanning period) and 1/32 period or more. More preferably, it is set to be not more than 1/2 period of 1H (one horizontal scanning period) and not less than 1/16 period. If the period for applying the overcurrent (pre-charge current or discharge current) is long, the period for applying the regular program current is shortened, and current compensation may not be good.

  If the period during which the overcurrent (precharge current or discharge current) is applied is short, the target potential of the source signal line 18 cannot be reached. In overcurrent (pre-charge current or discharge current) driving, it goes without saying that it is preferable to perform up to the potential of the source signal line 18 of the target gradation. However, it is not necessary to completely set the target source signal line potential only by overcurrent (precharge current or discharge current) driving. After the first half overcurrent (precharge current or discharge current) drive, normal current drive is performed, and the error caused by overcurrent (precharge current or discharge current) drive is the program current due to normal current drive. This is because it is compensated.

  FIG. 85 illustrates the potential change of the source signal line 18 when the overcurrent (precharge current or discharge current) driving method is performed. FIG. 85A shows the case where the D5 switch is turned on for 1 / (2H). The D5 switch is turned on from t1 which is the first of one horizontal scanning period (1H), and unit currents of 32 unit transistors 224c are sucked from the output terminal 93. The D5 switch is kept on until 1 / (2H) t2, and an overcurrent (pre-charge current or discharge current) Id2 flows to the source signal line 18. Therefore, the potential of the source signal line 18 is lowered to the Vm potential in the vicinity of the target potential Vn potential. Thereafter (after t2), the D5 switch is turned off, and the normal program current Iw flows to the source signal line 18 until the end of 1H (t3), and the potential of the source signal line 18 becomes the target Vn potential.

  The source driver circuit (IC) 14 operates at a constant current. Therefore, a constant program current Iw flows during the period from t2 to t3. When the program current Iw is charged / discharged until the parasitic capacitance Cs reaches the target potential, the current I flows from the driving transistor 11a of the pixel 16, and the potential of the source signal line 18 is maintained so that the target program current Iw flows. Is done. Therefore, the driving transistor 11a is held so that the predetermined program current Iw flows. As described above, the accuracy of overcurrent (precharge current or discharge current) for driving overcurrent (precharge current or discharge current) is not required. Even if there is no accuracy, it is corrected by the driving transistor 11a of the pixel 16.

  FIG. 85B shows the case where the D5 switch is turned on for 1 / (4H) period. The D5 switch is turned on from t1 which is the first of one horizontal scanning period (1H), and unit currents of 32 unit transistors 224c are sucked from the output terminal 93. The D5 switch is kept on until 1 / (4H) t4, and an overcurrent (pre-charge current or discharge current) Id2 flows through the source signal line 18. Therefore, the potential of the source signal line 18 is lowered to the Vm potential in the vicinity of the target potential Vn potential. Thereafter (after t4), the D5 switch is turned off, and the normal program current Iw flows to the source signal line 18 until the end of 1H (t3), and the potential of the source signal line 18 becomes the target Vn potential.

  The source driver circuit (IC) 14 operates at a constant current. Therefore, a constant program current Iw flows during the period from t4 to t3. When the program current Iw is charged / discharged until the parasitic capacitance Cs reaches the target potential, the current I flows from the driving transistor 11a of the pixel 16, and the potential of the source signal line 18 is maintained so that the target program current Iw flows. Is done. Therefore, the driving transistor 11a is held so that the predetermined program current Iw flows. As described above, the accuracy of overcurrent (precharge current or discharge current) for driving overcurrent (precharge current or discharge current) is not required. Even if there is no accuracy, it is corrected by the driving transistor 11a of the pixel 16.

  FIG. 85C shows the case where the D5 switch is turned on for 1 / (8H). The D5 switch is turned on from t1 which is the first of one horizontal scanning period (1H), and unit currents of 32 unit transistors 224c are sucked from the output terminal 93. The D5 switch is kept on until 1 / (8H) t5, and an overcurrent (pre-charge current or discharge current) Id2 flows to the source signal line 18. Therefore, the potential of the source signal line 18 is lowered to the Vm potential in the vicinity of the target potential Vn potential. Thereafter (after t5), the D5 switch is turned off, and the normal program current Iw flows to the source signal line 18 until the end of 1H (t3), and the potential of the source signal line 18 becomes the target Vn potential.

  As described above, the number of operating unit transistors 224c and the unit current of one unit transistor 224c are fixed values. Therefore, the charge / discharge time of the parasitic capacitance Cs can be proportionally controlled by the ON time of the D5 switch, and the potential of the source signal line 18 can be controlled. For ease of explanation, the parasitic capacitance Cs is charged / discharged by an overcurrent (pre-charge current or discharge current). However, since there is a leak of the switch transistor of the pixel 16, the parasitic capacitance Cs is limited to charging / discharging of Cs. It is not something.

  As described above, the characteristic feature of the present invention of FIG. 84 is that the magnitude of the overcurrent (pre-charge current or discharge current) can be grasped by the number of operating unit transistors 224. The write time t can be expressed by T = ACV / I (A: proportionality constant, C: magnitude of parasitic capacitance, V: potential difference that changes, I: program current), so that KDATA and value are both parasitic capacitance ( The value of KDATA can be determined as a theoretical value from the VI characteristics of the driving transistor 11a (which can be grasped at the time of array design).

  The embodiment of FIG. 85 controls the magnitude and application time of overcurrent (precharge current or discharge current) Id for overcurrent (precharge current or discharge current) driving by operating the most significant bit D5 switch. It was a thing. The present invention is not limited to this. Needless to say, switches other than the most significant bit may be operated or controlled.

  FIG. 86 shows a configuration in which the most significant bit switch D7 and the second most significant bit switch D6 are controlled by KDATA when the source driver circuit (IC) 14 has an RGB 8-bit configuration. For ease of explanation, it is assumed that 128 unit transistors 224c are formed or arranged in the D7 bit, and 64 unit transistors 224c are formed or arranged in the D6 bit.

  FIG. 86 (a1) shows the operation of the D7 switch. FIG. 86 (a2) shows the operation of the D6 switch. FIG. 86 (a3) shows the potential change of the source signal line. In FIG. 86A, since the switches D7 and D6 are simultaneously operated, 128 + 64 unit transistors 224c are simultaneously operated and flow into the source driver circuit (IC) 14 from the output terminal 93. Therefore, the potential of the source signal line 18 can be changed at high speed from the V0 voltage of gradation 0 to the V3 voltage of gradation 3. After t2, the normal switch D is closed, and the normal program current Iw is sucked into the source driver circuit (IC) 14 from the output terminal 93.

  Similarly, FIG. 86 (b1) shows the operation of the D7 switch. FIG. 86 (b2) shows the operation of the D6 switch. FIG. 86 (b <b> 3) shows the potential change of the source signal line 18. In FIG. 86B, since only the D7 switch operates, 128 unit transistors 224c operate simultaneously, and flow into the source driver circuit (IC) 14 from the output terminal 93. Therefore, the potential of the source signal line 18 can be changed at high speed from the V0 voltage of gradation 0 to the V2 voltage of gradation 2. The rate of change is smaller than in FIG. However, since the changing potential is from V0 to V2, it is appropriate. After t2, the normal switch D is closed, and the normal program current Iw is sucked into the source driver circuit (IC) 14 from the output terminal 93.

  Similarly, FIG. 86 (c1) shows the operation of the D7 switch. FIG. 86 (c2) shows the operation of the D6 switch. FIG. 86 (c <b> 3) shows the potential change of the source signal line 18. In FIG. 86 (c), since only the D6 switch operates, 64 unit transistors 224c operate simultaneously and flow into the source driver circuit (IC) 14 from the output terminal 93. Therefore, the potential of the source signal line 18 can be changed at high speed from the V0 voltage of gradation 0 to the V1 voltage of gradation 1. The rate of change is smaller than in FIG. 86 (b). However, since the changing potential is from V0 to V1, it is appropriate. After t2, the normal switch D is closed, and the normal program current Iw is sucked into the source driver circuit (IC) 14 from the output terminal 93.

  As described above, an appropriate source signal line potential can be achieved by operating or operating a plurality of switches and changing the number of unit transistors 224c to be operated by KDATA as well as the switch ON period.

  In FIG. 86, the switch D (D6, D7) driven by the overcurrent (pre-charge current or discharge current) is operated during the period from t1 to t2. However, the present invention is not limited to this and is shown or described in FIG. As described above, it goes without saying that it may be changed or changed according to the value of KDATA, such as t2, t3, t4. Also, control or change the size of the reference current or reference current while applying the overcurrent (precharge current or discharge current), and adjust the size of the overcurrent (precharge current or discharge current). Also good. Note that the reference current or the magnitude of the reference current is set to a normal value during the period in which the normal program current is applied.

  The switches to be operated are not limited to D7 and D6, but it goes without saying that other switches such as D5 may be operated or controlled simultaneously or selected. For example, FIG. 88 shows an embodiment. In the example of the period a, overcurrent (precharge current or discharge current) is driven, and the D7 switch is turned on for a period of 1 / (2H), and the overcurrent (precharge current or discharge current) is made up of 128 unit currents. Is applied to the source signal line 18.

  In the example of period b, the overcurrent (precharge current or discharge current) is driven, and the switches D7 and D6 are turned on for 1 / (2H) and the overcurrent (precharge current or discharge current) consisting of 128 + 64 unit currents is turned on. Current) is applied to the source signal line 18.

  In the example of the period c, the overcurrent (precharge current or discharge current) driving is performed by turning on the switches D7, D6, and D5 of 1 / (2H) and turning on the overcurrent (precharge current) of 128 + 64 + 32 unit currents. Alternatively, a discharge current) is applied to the source signal line 18.

  In the example of the d period, the overcurrent (precharge current or discharge current) drive is a 1 / (2H) period D7, D6, D5 switch and a switch of video data not corresponding to the switch (for example, if the video data is 4) In other words, the D2 switch) is turned on, and an overcurrent (precharge current or discharge current) consisting of 128 + 64 + 32 + α unit currents is applied to the source signal line 18.

  In the embodiment described above, the period during which the overcurrent (pre-charge current or discharge current) flows is from the beginning of 1H, but the present invention is not limited to this. In FIG. 87, (a1) and (a2) are methods in which the switch is operated from the first t1 of 1H to t2 of 1 / (2H). In FIG. 87, (b1) and (b2) are methods in which the switch is operated from t4 to t5 of 1 / (2H). The application time of the overcurrent (precharge current or discharge current) is the same as that in FIG. Since the potential of the source signal line 18 is defined by charging / discharging of the parasitic capacitance Cs, the effective value becomes equal regardless of the application period of the overcurrent (precharge current or discharge current). However, the end of 1H needs to be a regular program current application period. This is because, by applying a normal program current, it can be set to an accurate target potential (the driving transistor 11a can pass a highly accurate program current).

  87 (c1) and 87 (c2), the switch is operated from the first t1 of 1H to t4 of 1 / (4H), and the switch is operated from t2 of 1H to t5 of 1 / (4H). The effective value of the application time of the overcurrent (precharge current or discharge current) is the same as that in FIG. As described above, in the present invention, the application time of the overcurrent (pre-charge current or discharge current) may be dispersed in a plurality. Further, the application start time of the overcurrent (precharge current or discharge current) is not limited to the beginning of 1H.

  As described above, the overcurrent (precharge current or discharge current) driving method of the present invention is not limited to the application timing of the overcurrent (precharge current or discharge current). However, it is necessary to set a period during which the program current is applied at the time when the current program of the pixel 16 is completed. However, it goes without saying that the present invention is not limited to this when the current program of the pixel 16 does not require accuracy. That is, the 1H period may be ended in an overcurrent (precharge current or discharge current) application state.

  In the overcurrent (precharge current or discharge current) driving of the present invention, it is important to operate the overcurrent (precharge current or discharge current) through the source signal line 18, and the overcurrent (precharge current or discharge current) is generated. What is generated is not limited to the unit transistor 224c. For example, it goes without saying that, for example, a constant current circuit or a variable current circuit may be formed or configured by being connected to the output terminal 93, and these current circuits may be operated to generate an overcurrent (precharge current or discharge current). .

  In FIG. 84, the structure or structure used for gradation display (used for current program driving) of the source driver circuit (IC) 14 is used for overcurrent (precharge current or discharge current) driving. The present invention is not limited to this. As shown in FIG. 89, an overcurrent (precharge current or discharge current) transistor 891 for generating an overcurrent (precharge current or discharge current) used for overcurrent (precharge current or discharge current) driving is separately formed or It may be configured.

  The overcurrent (pre-charge current or discharge current) transistor 891 may have the same size as the unit transistor 224c, and a plurality of unit transistors 224 may be formed. The unit transistor 224c may have a different size, WL ratio, or WL shape. However, it is the same for all output stages.

  In FIG. 89, the gate terminal potential of the overcurrent (precharge current or discharge current) transistor 891 is the same as the gate terminal potential of the unit transistor 224c. By making them the same, the magnitude of the overcurrent (precharge current or discharge current) output from the overcurrent (precharge current or discharge current) transistor 891 can be easily controlled by the reference current control. Further, since the output overcurrent (precharge current or discharge current) such as the size of the overcurrent (precharge current or discharge current) transistor 891 can be predicted, the design becomes easy. However, the present invention is not limited to this. The gate terminal potential of the overcurrent (pre-charge current or discharge current) transistor 891 may be configured to be a terminal potential different from that of the unit transistor 224c. The magnitude of the overcurrent (precharge current or discharge current) can be controlled by manipulating the gate terminal potential of an overcurrent (precharge current or discharge current) transistor 891 that is configured separately.

  The applied voltage may be controlled or adjusted by separating the drain terminal (D) of the overcurrent (precharge current or discharge current) transistor 891 from the drain (D) terminal of the unit transistor 224c. The magnitude of the overcurrent (precharge current or discharge current) output from the overcurrent (precharge current or discharge current) transistor 891 can also be adjusted or controlled by adjusting or controlling the drain terminal potential.

  The above can be applied to other embodiments of the present invention. For example, also in FIG. 84, the magnitude of the overcurrent (pre-charge current or discharge current) can be adjusted or controlled by controlling or adjusting the potential of the drain terminal.

  In FIG. 89, the switch Dc is controlled to be turned on / off by a signal applied to 222b, thereby realizing the overcurrent (precharge current or discharge current) driving of the present invention. By adopting the configuration of FIG. 89, overcurrent (pre-charge current or discharge current) driving can be performed regardless of the size of video data.

  In particular, the overcurrent (precharge current or discharge current) driving described with reference to FIGS. 84 and 89 is preferably performed in combination with voltage + current driving (precharge driving). FIG. 93 is an explanatory diagram of this embodiment. In FIG. 93, the video data indicates a change in gradation (change in video data) written to the pixel 16. The source signal line potential indicates a potential change of the source signal line 18. The number of gradations is 256.

  When the video data changes from 255 (white) gradation to 0 gradation, the state is as shown in FIG. 83 (b). In this case, first, a precharge voltage is applied to the source signal line 18. Since the program current Iw of the driving transistor 11a of the pixel 16 is 0, the gate terminal potential rises in the Vdd voltage direction so that no current flows. At the 0th gradation, the display is completely black by driving through voltage. Overcurrent (pre-charge current or discharge current) drive is not performed.

  When the video data changes from 0 (black) gradation to 2 gradations, the state is as shown in FIG. In this case, first, an overcurrent (precharge current or discharge current) is applied to the source signal line 18 during a period from t3 to t4. In general, the driving transistor 11a of the pixel 16 does not operate. Program current driving is performed in the period from t4 to t5. When the potential of the source signal line 18 is too low due to overcurrent (pre-charge current or discharge current) driving, the driving transistor 11a of the pixel 16 operates, and as shown in FIG. The potential is raised to the anode voltage side to become the V2 voltage.

  With the above operation, the gate terminal voltage of the driving transistor 11a becomes the V2 voltage, and an accurate program current can be passed through the EL element 15.

  The program current is small in a relatively low gradation region when the video data changes from 2 gradations to 16 gradations. The operation is as shown in FIG. In this case, first, an overcurrent (precharge current or discharge current) is applied to the source signal line 18 during a period from t5 to t6. In general, the driving transistor 11a of the pixel 16 does not operate. Program current driving is performed in the period from t6 to t7. When the potential of the source signal line 18 is appropriate due to overcurrent (precharge current or discharge current) driving, the potential of the source signal line 18 does not change as shown in FIG. That is, the driving transistor 11a of the pixel 16 does not operate. When the potential of the source signal line 18 is lower than the target value, the source driver circuit (IC) 14 draws the program current during the period from t6 to t7, and becomes the target source signal line 18 potential.

  With the above operation, as shown in FIG. 93, the potential of the source signal line 18 becomes the gate terminal voltage of the driving transistor 11a becomes the V16 voltage, and an accurate program current can be supplied to the EL element 15.

  When the video data changes from 16 gradations to 90 gradations, the program current is large. The operation is as shown in FIG. In this case, the program current drive is performed over the entire period from t7 to t8. That is, precharge voltage drive and overcurrent (precharge current or discharge current) drive are not performed. As described above, according to the present invention, the KDATA value is changed according to the change rate of the gradation data and the size before the change, and the driving method is changed.

  Hereinafter, another embodiment of the present invention will be described with reference to the drawings. FIG. 96 shows another embodiment of the overcurrent (precharge current or discharge current) driving system of the present invention. In FIG. 89, there is one overcurrent transistor 891. In FIG. 96, a plurality of overcurrent transistors 891 are formed or arranged, and the gate terminal of the overcurrent transistor 891 is connected to the transistor 251c and another gate wiring.

  With the configuration as shown in FIG. 96, the magnitude of the overcurrent (pre-charge current or discharge current) can be freely set or adjusted without being restricted by the magnitude of the reference current Ic. In addition, the configuration of a plurality of overcurrent (precharge current or discharge current) transistors 891 allows the magnitude of the overcurrent (precharge current or discharge current) to be freely set by the switch DC.

  The overcurrent transistor 891 is shared by the RGB circuit. R reference current Icr, which is changed or adjusted by a set value IRDATA of R (red) reference current. Similarly, it is the G reference current Icg, and Ic is changed or adjusted by the set value IGDATA of the G (green) reference current. The reference current Icb for B is changed or adjusted by the set value IBDATA for the reference current for B (blue).

  On the other hand, the overcurrent (pre-charge current or discharge current) Id is common to RGB. That is, the Id of the R output stage circuit (see FIG. 96 and the like) is the same as the Id of the G output stage circuit and the Id of the B output stage circuit. The magnitude of Id and / or the change timing of Id is set by the controller circuit (IC) 722 by setting data IKDATA4 bits of overcurrent (precharge current or discharge current). As shown in FIG. 96, this Id flows through a parent circuit of a current mirror composed of a transistor group composed of one transistor 228d or a plurality of transistors 228d. In FIG. 96, the number of transistors 228d is one, but it is needless to say that a plurality of transistors 228d may be used.

  In FIG. 89, the magnitude of the program current can be individually set in the RGB circuit. However, it is not preferable to set the overcurrent (precharge current or discharge current) individually for RGB. This is because the overcurrent (pre-charge current or discharge current) controls charging / discharging of the parasitic capacitance Cs as described with reference to FIG. The parasitic capacitance Cs is the same in the source signal line 18 in RGB. Therefore, if the RGB overcurrent (precharge current or discharge current) is different, the overcurrent (precharge current or discharge current) writing speed is different as shown in FIG. The signal line potential is different.

  In FIG. 98, the overcurrent (precharge current or discharge current) of B of the alternate long and short dash line is the largest. Therefore, the voltage V2 corresponding to gradation 2 is reached from the voltage V0 corresponding to gradation 0 in the period of 1H. The dotted overcurrent G (precharge current or discharge current) is the smallest. Therefore, in the period of 1H, the V2 voltage corresponding to the gradation 2 does not reach from the V0 voltage corresponding to the gradation 0. R is indicated by a solid line. As shown in FIG. 98, this is an intermediate state between G and B. In the above state, the white balance is shifted after 1H. However, since FIG. 98 is a low gradation region, there is no practical problem even if the white balance is shifted.

  It goes without saying that the problem described with reference to FIG. 98 can be solved by making the parasitic capacitances different for RGB. That is, in the state of FIG. 98, the parasitic capacitance Cs of the R source signal line 18 is made larger than the parasitic capacitance Cs of the G source signal line 18. Further, the parasitic capacitance Cs of the B source signal line 18 is made larger than the parasitic capacitance Cs of the R source signal line 18. As a method of increasing the parasitic capacitance Cs, a method of forming or configuring a capacitor with a polysilicon circuit at the end of the source signal line 18 for each of RGB is exemplified.

  Further, a configuration in which the parasitic capacitance of the source signal line 18 is reduced in RGB is also exemplified. The parasitic capacitance Cs of the G source signal line 18 is made smaller than the parasitic capacitance Cs of the R source signal line 18. Further, the parasitic capacitance Cs of the R source signal line 18 is made smaller than the parasitic capacitance Cs of the B source signal line 18. As a method of reducing the parasitic capacitance Cs, a configuration in which the wiring width of the source signal line 18 is changed for each RGB is exemplified.

  If the width of the source signal line 18 is reduced, the parasitic capacitance Cs is reduced. In the current driving method, the current flowing through the source signal line 18 is on the order of μA. Therefore, there is no problem in realizing the current driving method even if the width of the source signal line 18 is narrow and the resistance value of the source signal line 18 is high.

  As described above, in the present invention, one or more parasitic capacitances Cs of the RGB source signal lines 18 are different from the parasitic capacitances Cs of the other source signal lines 18. In addition, the configuration is exemplified by changing the line width of the source signal line 18. A configuration in which a capacitor serving as a capacitor is manufactured or arranged and electrically connected to the corresponding source signal line 18 is exemplified.

  The V0 voltage corresponding to the 0th gradation is determined by the driving transistor 11a of the pixel 16. Usually, the driving transistor 11a has the same size or size for RGB. Therefore, the V0 voltages are the same in RGB. The charge / discharge of the parasitic capacitance Cs is often based on the V0 voltage.

  By making the overcurrent (pre-charge current or discharge current) Id common in the RGB circuit, the charge / discharge curve of the source signal line 18 is not different for each RGB as shown in FIG. That is, it is preferable that the overcurrent (precharge current or discharge current) Id is the same for RGB.

  The adjustment circuit for the overcurrent (pre-charge current or discharge current) Id is performed by the electronic volume circuit 291b. The electronic volume 291b can be changed or changed for each frame or each pixel row by IKDATA. Further, a configuration in which the screen 64 is divided into a plurality of areas, an electronic volume 291b is arranged for each divided area, and the current Id is changed or adjusted for each divided area is also exemplified. Needless to say, the above matters can be applied to the electronic volume circuit 291a of the reference current Ic.

  FIG. 95 (a) is a configuration example of an overcurrent (pre-charge current or discharge current) circuit in the source driver circuit (IC) 14 of the present invention. The transistor 228d and the overcurrent transistor 891 constitute a current mirror circuit. The magnitude of the overcurrent (precharge current or discharge current) Ik is controlled by two switches Dc. The switch Dc0 is connected to one overcurrent transistor 891, and the switch Dc1 is connected to two overcurrent transistors 891.

  The overcurrent transistor 891 has the same configuration as the unit transistor 224 described with reference to FIG. 15 (formed or configured with the same technical idea). Accordingly, in the configuration or description of the overcurrent transistor 891, the matters described in the unit transistor 224 are applied as they are or correspondingly. Therefore, the description is omitted.

  Control of the switch Dp for applying the precharge voltage Vpc to the output terminal 93 and control of the switch Dc for applying an overcurrent (precharge current or discharge current) to the output terminal 93 are controlled by 2 bits. These bits are K bits (first bit) and P bits (0th bit: LSB). Therefore, four states can be controlled.

  The four states are illustrated in the table of FIG. When (K, P) = 0, it is controlled to (Dp, Dc0, Dc1) = (0, 0, 0). Note that 0 indicates that the switch is open, and 1 indicates that the switch is closed.

  When (K, P) = 0, the precharge voltage (program voltage) control switch Dp is open, and the overcurrent control switch Dc is also open. Therefore, neither the precharge voltage nor the overcurrent (precharge current or discharge current) is output (applied) from the output terminal 93.

  When (K, P) = 1, it is controlled to (Dp, Dc0, Dc1) = (1, 0, 0). The precharge voltage (program voltage) control switch Dp is in a closed state, and both overcurrent control switches Dc are in an open state. Therefore, the precharge voltage Vpc is output from the output terminal 93, but the overcurrent (precharge current or discharge current) is not output (applied).

  When (K, P) = 2, it is controlled to (Dp, Dc0, Dc1) = (0, 1, 0). The precharge voltage (program voltage) control switch Dp is in an open state, the overcurrent control switch Dc is in a closed state Dc0, and Dc1 is in an open state. Therefore, the precharge voltage Vpc is not output from the output terminal 93. Further, as for the overcurrent (precharge current or discharge current), the output current of one overcurrent transistor 891 is applied to the source signal line 18.

  When (K, P) = 3, (Dp, Dc0, Dc1) = (0, 0, 1) is controlled. The precharge voltage (program voltage) control switch Dp is in an open state, and the overcurrent control switch Dc has Dc0 and Dc1 in a closed state. Therefore, the precharge voltage Vpc is not output from the output terminal 93. Further, as for the overcurrent (precharge current or discharge current), the output current of two overcurrent transistors 891 is applied to the source signal line 18.

  As described above, the precharge voltage and overcurrent (precharge current or discharge current) can be controlled by the 2-bit signals (K, P).

  In FIG. 95 (b), the decoding circuit of (K, P) is necessary. FIG. 94 shows a configuration table that eliminates the need for a decoding circuit. In FIG. 94, K0 and K1 are switch signals for controlling overcurrent (precharge current or discharge current). K0 is a bit that controls opening and closing of Dc0. K1 is a bit for controlling the opening and closing of Dc1 (see FIG. 95A). In FIG. 94, P is a switch signal for controlling the precharge voltage. Dp is a bit for controlling opening and closing (see FIG. 95A).

  When (P, K0, K1) = (0, 0, 0), it is controlled to (Dp, Dc0, Dc1) = (0, 0, 0). The precharge voltage (program voltage) control switch Dp is in an open state, and the overcurrent control switches Dc0 and Dc1 are also in an open state. Therefore, the precharge voltage Vpc is not output from the output terminal 93. Also, no overcurrent (pre-charge current or discharge current) is output.

  When (P, K0, K1) = (1, 0, 0), it is controlled to (Dp, Dc0, Dc1) = (1, 0, 0). The precharge voltage (program voltage) control switch Dp is in a closed state, and the overcurrent control switches Dc0 and Dc1 are also in an open state. Therefore, although the precharge voltage Vpc is output from the output terminal 93, no overcurrent (precharge current or discharge current) is output.

  For example, when (P, K0, K1) = (1, 1, 1), it is controlled to (Dp, Dc0, Dc1) = (1, 1, 1). The precharge voltage (program voltage) control switch Dp is in a closed state, and the overcurrent control switches Dc0 and Dc1 are also in a closed state. Therefore, the precharge voltage Vpc and the overcurrent (precharge current or discharge current) are output from the output terminal 93.

  Similarly, Dc0 and Dc1 of the precharge voltage (program voltage) control switch Dp and the overcurrent control switch are controlled independently according to the values of (P, K0, K1). Therefore, precharge voltage application and overcurrent (precharge current or discharge current) application can be performed simultaneously.

  In FIGS. 94 and 95, by adding a bit for closing the switches (Dp, Dc0, Dc1), the overcurrent (precharge current or discharge current) and the precharge voltage can be controlled with higher accuracy. Needless to say.

  FIG. 96 shows an embodiment in which the switch for controlling the overcurrent (pre-charge current or discharge current) is 3 bits. When the Dc0 switch is turned on (closed), the current of one overcurrent transistor 891 is applied to the source signal line 18. When the Dc1 switch is turned on (closed), the currents of the two overcurrent transistors 891 are applied to the source signal line 18. When the Dc2 switch is turned on (closed), the currents of the four overcurrent transistors 891 are applied to the source signal line 18. Similarly, the currents of the seven overcurrent transistors 891 are applied to the source signal line 18 by turning on (closing) the Dc0, Dc1, and Dc2 switches.

  In FIG. 96, the period during which the overcurrent (pre-charge current or discharge current) is applied to the output terminal 93 is controlled by the td period of the signal applied to the terminal 643 of the source driver circuit (IC) 14. The td period is a period during which the switch 221c is turned on (closed).

  The d period control may be performed by a counter circuit (not shown) configured or formed in the source driver circuit (IC) 14.

  In FIG. 95, FIG. 96, and FIG. 89, each switch Dc is composed of a plurality of overcurrent transistors that pass a unit overcurrent (precharge current or discharge current). However, the present invention is not limited to this. For example, as shown in FIG. 97B, it goes without saying that one overcurrent transistor 891 may be formed or arranged for each switch Dc. In FIG. 97 (b), one overcurrent transistor 891a is arranged or formed in the switch Dc0. One overcurrent transistor 891b is also arranged or formed in the switch Dc1. In addition, one overcurrent transistor 891c is arranged or formed in the switch Dc2. The overcurrent transistors 891a to 891c have different levels of output overcurrent (precharge current or discharge current). The magnitude of the overcurrent (pre-charge current or discharge current) can be easily adjusted or designed according to the WL ratio, size, or shape of the overcurrent transistor 891. Of course, as shown in FIG. 97A, the number of overcurrent transistors 891 corresponding to the number of bits may be formed or arranged.

  In FIG. 101, the reference current Ic and the reference current Id of the overcurrent (pre-charge current or discharge current) change according to IDATA input to the electronic volume 291. The ratio between the reference current Ic and the reference current Id of the overcurrent (precharge current or discharge current) is such that the transistor 228a that supplies the reference current Ic and the transistor that supplies the reference current Id of the overcurrent (precharge current or discharge current). This is realized by making the shape of 228c different.

  In FIG. 101, there is one transistor 228a for supplying the reference current Ic and four transistors 228c for supplying the overcurrent (precharge current or discharge current) reference current Id. Therefore, the transistor 228a and the transistor 228c have the same shape. Even in this case, the relationship of reference current Ic × 4 = reference current Id can be configured.

  In FIG. 101, four overcurrent transistors 891 corresponding to the switch Dc are formed or arranged. By configuring the output stage with a plurality of overcurrent transistors 891 that pass a small overcurrent (precharge current or discharge current), output variation can be reduced. Since the above has been described with reference to FIG.

  In FIG. 101, as shown in FIG. 96, the switch Dc is time-controlled by an on / off signal applied to the internal wiring 222b, and the effective current output from the output terminal 93 is controlled. Further, the switches 221a and 221b have an on / off state opposite to each other. Therefore, when the precharge voltage Vpc is applied to the output terminal 93, the overcurrent (precharge current or discharge current) is controlled not to be applied to the output terminal 93.

  FIG. 102 shows an 8-bit source driver circuit (IC) 14 having a program current Iw (generated by the on / off state of switches D0 to D7) and an overcurrent (precharge current or discharge current) Id (for ease of explanation). The transistor 228d and the overcurrent transistor 891 constitute a current mirror circuit having a current mirror ratio of 1, and the same overcurrent (precharge current or discharge current) as the reference current Id of the overcurrent (precharge current or discharge current). ) Is applied to the output terminal 93), or its state or driving method.

  FIG. 102A shows a state where an overcurrent (pre-charge current or discharge current) Id is applied. Overcurrent (pre-charge current or discharge current) Id is applied for a certain period such as 1 / (2H) period of 1H. However, the 1 / (2H) period of 1H is an example, and the present invention is not limited to this. It is preferable that the 1H 1 / (2H) period, 1H 1 / (4H) period, 1H 2 / (3H) period, 1H 1 / (8H) period, and the like can be switched by a control signal or the like. Needless to say. FIG. 102B shows a state after the application time of overcurrent (pre-charge current or discharge current). FIG. 102B shows, as an example, the output state of the program current Iw when the data D (D7 to D0) is “10000001”, that is, the D7 bit and the D0 bit are on (closed).

  As described above, in the embodiment of FIG. 102, the state in which the overcurrent (precharge current or discharge current) Id is applied and the output state of the program current Iw are independent.

  FIG. 103A shows a state where an overcurrent (pre-charge current or discharge current) Id is applied. Overcurrent (pre-charge current or discharge current) Id is applied for a certain period such as 1 / (2H) period of 1H.

  However, as described in FIG. 102, the 1 / (2H) period of 1H is an example, and the present invention is not limited to this. It is preferable that the 1H 1 / (2H) period, 1H 1 / (4H) period, 1H 2 / (3H) period, 1H 1 / (8H) period, and the like can be switched by a control signal or the like. Needless to say.

  Also, depending on the size of the video data, the total size of the video data of one screen, the size of the source signal line 18 potential before 1H, the change in the image state of each frame, the nature of the image such as a still image or a moving image Needless to say, the application time of the overcurrent (precharge current or discharge current) Id may be changed, changed or controlled. Needless to say, the above matters can be applied to other embodiments of the present invention.

  In FIG. 103 (a), all the switches D0 to D7 that generate the program current Iw are turned on (closed). Therefore, the overcurrent (precharge current or discharge current) output from the output terminal 93 is obtained by adding the maximum program current Iw to the original overcurrent (precharge current or discharge current) Id. As described above, a large overcurrent (precharge current or discharge current) Id can be applied to the source signal line 18 by controlling the switches D0 to D7 and Dc as shown in FIG. Therefore, the charge discharge time of the parasitic capacitance Cs can be shortened.

  FIG. 103 (b) shows a state after the application time of an overcurrent (precharge current or discharge current). FIG. 103B shows an example of the output state of the program current Iw when the data D (D7 to D0) is “10000001”, that is, the D7 bit and the D0 bit are on (closed), as in FIG. Show.

  As described above, in the embodiment of FIG. 103, a large overcurrent (precharge current or discharge current) can be applied during a period in which the overcurrent (precharge current or discharge current) flows. In FIG. 103 (a), it is not limited to turning on (closing) all the switches D0 to D7. It goes without saying that the on / off states of the switches D0 to D7 may be changed or controlled in accordance with the potential of the source signal line 18, the length of the horizontal scanning period, the size of the parasitic capacitance Cs, and the like.

  102 and 103, the overcurrent transistor 891 is controlled to apply an overcurrent (precharge current or discharge current) to the source signal line 18. However, the present invention is not limited to this. This embodiment is illustrated in FIG.

  In FIG. 104A, all the switches D0 to D7 that generate the program current Iw are turned on (closed). However, the switch Dc that controls the overcurrent transistor 891 is open. Therefore, Id that is an overcurrent (pre-charge current or discharge current) is not applied to the output terminal 93. FIG. 104 (a) shows an embodiment generated by controlling the currents equal to or higher than the program current Iw based on the video data and the switches D7 to D0. In general, insufficient writing occurs in an area where video data is small (low gradation area). Accordingly, in this region, the switch such as the D7 bit is not turned on. A switch (such as D7) that is not turned on in this video data is turned on to generate a large program current (= overcurrent (pre-charge current or discharge current)), and the potential of the source signal line 18 is increased by this current. Control or operate.

  As described above, the overcurrent (precharge current or discharge current) output from the output terminal 93 is the maximum program current Iw. As described above, a large overcurrent (precharge current or discharge current) Id can be applied to the source signal line 18 by controlling the switches D0 to D7 and Dc as shown in FIG. Therefore, the charge discharge time of the parasitic capacitance Cs can be shortened.

  FIG. 104B shows a state after the application time of overcurrent (pre-charge current or discharge current). FIG. 104B is an example similar to FIGS. 102B and 103B. As an example, the program in which the data D (D7 to D0) is “10000001”, that is, the D7 and D0 bits are on (closed). The output state of current Iw (corresponding to the size of regular video data) is shown.

  As described above, in the embodiment of FIG. 104, a large overcurrent (precharge current or discharge current) can be applied during a period in which the overcurrent (precharge current or discharge current) flows. In FIG. 104 (a), it is not limited to turning on (closing) all the switches D0 to D7. It goes without saying that the on / off states of the switches D0 to D7 may be changed or controlled in accordance with the potential of the source signal line 18, the length of the horizontal scanning period, the size of the parasitic capacitance Cs, and the like.

  Although an overcurrent transistor 891 is provided in FIG. 103, the present invention is not limited to this. The overcurrent transistor 891 may not be formed or arranged.

  In FIG. 103 and the like, when the precharge current is applied, all the switches D0 to D7 are closed, but the present invention is not limited to this. When the precharge current is applied, only the upper bit D7 may be turned on. Further, the D4 to D7 bits corresponding to the upper bits may be turned on. That is, according to the present invention, the switch Dn is operated so that the output current is larger than when the video data corresponds to the predetermined video data.

  In FIG. 104A, all the switches D0 to D7 that generate the program current Iw are turned on (closed). However, the switch Dc that controls the overcurrent transistor 891 is open. Therefore, Id that is an overcurrent (pre-charge current or discharge current) is not applied to the output terminal 93.

  FIG. 104 (a) shows an embodiment generated by controlling the currents equal to or higher than the program current Iw based on the video data and the switches D7 to D0. In general, insufficient writing occurs in an area where video data is small (low gradation area). Accordingly, in this region, the switch such as the D7 bit is not turned on. A switch (such as D7) that is not turned on in this video data is turned on to generate a large program current (= overcurrent (pre-charge current or discharge current)), and the potential of the source signal line 18 is increased by this current. Control or operate.

  As described above, the overcurrent (precharge current or discharge current) output from the output terminal 93 is the maximum program current Iw. As described above, a large overcurrent (precharge current or discharge current) Id can be applied to the source signal line 18 by controlling the switches D0 to D7 and Dc as shown in FIG. Therefore, the charge discharge time of the parasitic capacitance Cs can be shortened.

  FIG. 104B shows a state after the application time of overcurrent (pre-charge current or discharge current). FIG. 104B is an example similar to FIGS. 102B and 103B. As an example, the program in which the data D (D7 to D0) is “10000001”, that is, the D7 and D0 bits are on (closed). The output state of current Iw (corresponding to the size of regular video data) is shown.

  As described above, in the embodiment of FIG. 104, a large overcurrent (precharge current or discharge current) can be applied during a period in which the overcurrent (precharge current or discharge current) flows. In FIG. 104 (a), it is not limited to turning on (closing) all the switches D0 to D7. It goes without saying that the on / off states of the switches D0 to D7 may be changed or controlled in accordance with the potential of the source signal line 18, the length of the horizontal scanning period, the size of the parasitic capacitance Cs, and the like.

  101 to 104 and the like are configurations or methods for generating an overcurrent (pre-charge current or discharge current) Id in the direction of suction from the output terminal 93. However, the present invention is not limited to this. The configuration may be such that overcurrent (pre-charge current or discharge current) is discharged from the output terminal 93.

  Further, both a circuit that sucks an overcurrent (precharge current or discharge current) from the output terminal 93 and a circuit that discharges an overcurrent (precharge current or discharge current) from the output terminal 93 may be formed, configured, or arranged. Needless to say.

  A difference from FIGS. 101 to 104 is that a circuit for discharging an overcurrent (precharge current or discharge current) is provided. An overcurrent (pre-charge current or discharge current) discharge circuit is formed of a current mirror circuit including a transistor 228d2 and an overcurrent transistor 891. An overcurrent (pre-charge current or discharge current) Id2 (when the current mirror ratio is 1) is applied to the output terminal 93 by this current mirror circuit.

  103, 104, and the like, in the first period of 1H (one horizontal scanning period), it is determined from video data or the like, and when necessary, the switch 221a is closed and the precharge voltage Vpc is applied to the output terminal 93. And applied to the source signal line 18. Basically, when the precharge voltage Vpc is applied, the switch 221b is controlled to be in an open state.

  Further, it is judged from video data or the like after the first 1H or after the application of the precharge voltage. When necessary, the switch Dn is closed, the precharge current is applied to the output terminal 93, and applied to the source signal line 18. The After the precharge current is applied, the switch D corresponding to the regular video data is closed and the program current Iw is applied to the source signal line 18.

  103 and 104, the potential change of the source signal line 18 can be increased as the period for applying the precharge current Id is lengthened. That is, the potential change of the source signal line 18 can be increased by controlling the period during which the precharge current is applied.

  103 and 104, the precharge current is generated in the sink current direction. The present invention is not limited to this. For example, a program current output stage 251ca for sink current and a program current output stage 251cb for outputting discharge current may be formed or configured in the source driver circuit (IC) 14. When the precharge current of the sink current is generated, the switch Dn of the output stage 251ca is controlled or operated. When the discharge current is generated, the output stage 251cb switch Dn is controlled or operated. Either precharge current is realized by controlling the switch 221b1 and the switch 221b2.

  FIG. 99 is an explanatory diagram for explaining a driving method (driving method) of the display panel (display device) of the present invention. The potential state is shown in the source signal line 18 by the voltage precharge and the program current. In the embodiment of FIG. 99, the precharge voltages generated by the source driver circuit (IC) 14 are the gradation V 0 potential (black voltage precharge) and the maximum gradation 255 potential V 255 (white voltage precharge). And generate.

  In FIG. 99, the period for applying the precharge voltage is 1 μsec as an example. Therefore, 1H time-1 μsec is the current program period. However, the present invention is not limited to this. Needless to say, other configurations, states, or times may be used.

  The embodiment in FIG. 99 and the like will be described assuming that RGB is 8 bits each (256 gradation display). The present invention is not limited to RGB as described before. It may be a single color, may be cyan, yellow, magenta, or the like, and may be four colors of white (W) in addition to RGB. FIG. 99A shows an embodiment in which the gradation is changed from gradation 0 to gradation 255. FIG. When the potential difference between gradation 0 and gradation 255 is large, white voltage precharge (V255 voltage is applied) is performed. As shown in FIG. 99A, the white voltage precharge is performed from the first period of 1H (not limited to the first period of 1H) to 1 μsec. By performing the white voltage precharge, a voltage is applied to the source signal line 18 and the potential of the source signal line 18 becomes V255. Thereafter, current programming is performed, and the potential of the source signal line 18 is corrected in accordance with the characteristics of the driving transistor 11a of the pixel 16. As an example, in FIG. 99A, the potential of the source signal line 18 increases in the direction of the anode potential Vdd.

  FIG. 99B shows an embodiment in which the gradation 255 is changed to gradation 0. FIG. When the potential difference between gradation 255 and gradation 0 is large, black voltage precharge (application of V0 voltage) is performed. As shown in FIG. 99 (b), the black voltage precharge is performed from the first period of 1H (not limited to the first period of 1H) to 1 μsec. By performing the black voltage precharge, the voltage V0 is applied to the source signal line 18, and the potential of the source signal line 18 becomes V0 close to the GND voltage. Thereafter, current programming is performed, and the source signal line 18 is corrected so that a current equal to the target programming current flows according to the characteristics of the driving transistor 11a of the pixel 16. As an example, in FIG. 99B, the potential of the source signal line 18 drops in the direction of the ground (GND) potential.

  FIG. 99C shows an embodiment in which the gradation is changed from 0 to 200. When the potential difference between the gradation 0 and the gradation 200 is relatively large, white voltage precharge (V255 voltage is applied) is performed. Note that the black voltage precharge is performed when changing to a gradation region lower than ¼ of all gradations. The white voltage precharge is performed when the gradation changes to a gradation area higher than ½ of all gradations. As shown in FIG. 99 (c), the white voltage precharge is performed from the first period of 1H (not limited to the first period of 1H) to 1 μsec. By performing the white voltage precharge, a voltage is applied to the source signal line 18 and the potential of the source signal line 18 becomes V255. Thereafter, current programming is performed, and the driving transistor 11a of the pixel 16 mainly operates to correct the potential of the source signal line 18 corresponding to the target gradation current 200.

  FIG. 100 is an explanatory diagram of a drive method for performing both overcurrent drive (precharge current drive) and voltage drive (precharge voltage drive). As an example of the circuit configuration, the switch 221 is turned on to be in a closed state and turned off to be in an open state. The switch 221a is turned on and the precharge voltage Vpc is applied to the output terminal 93 (applied to the source signal line 18). The switch 221b is turned on and the program current Iw is applied to the output terminal 93 (applied to the source signal line 18). Further, the switch Dc is turned ON, and an overcurrent (precharge current or discharge current) Iw is applied to the output terminal 93 (applied to the source signal line 18).

  As shown in FIG. 100A, the state in which the switch 221a is ON and the precharge voltage Vpc is applied to the output terminal 93 and the state in which the switch 221b is ON and the program current Iw is applied to the output terminal 93 are simultaneous. Even if it occurs, there is no problem in operation. This is because the constant current circuit 251c and the like have high internal impedance, and can operate normally even when short-circuited with a constant voltage circuit (precharge voltage circuit). However, as illustrated in FIGS. 100B and 100C, when the switch Dc is in the ON state, the switch 221a is preferably in the OFF state. This is because the current from the overcurrent (precharge current or discharge current) circuit may flow as an inrush current to the constant voltage circuit. As shown in FIG. 100A, when the switch Dc is in the OFF state, there is no problem even if the switch 221a is in the ON state.

  As shown in FIGS. 100B and 100C, the period during which the overcurrent (pre-charge current or discharge current) is applied to the output terminal 93 can be adjusted by controlling the period during which the switch Dc is turned on. it can. In FIG. 100B, the period during which the overcurrent (precharge current or discharge current) is applied is 1 / (3H), and in FIG. 100C, the overcurrent (precharge current or discharge current) is applied. The period of time is 1 / (4H). The potential change of the source signal line 18 can be made larger in FIG. 100C than in FIG.

  103 and 104, the configuration for operating the D0 to D7 switches for controlling the program current Iw has been described. FIG. 105 shows a more detailed embodiment or another embodiment.

  The switch Dc for supplying an overcurrent (pre-charge current or discharge current) can control the ON period by an ON / OFF signal applied to the internal wiring 222b. In the embodiment of FIG. 105, control can be performed in four periods of 0, 82/4, and 3/4 of 1H. Similarly, the period during which the switches D0 to D for forcibly controlling the program current Iw are operated (controlled) (referred to as “forced control”) is 1H of 0, 82/4, 3/4 in the embodiment of FIG. Can be controlled in four periods. In FIG. 105, the period during which the normal program current is supplied is described as data control, and is described from gradation 4 to gradation 5 (described as 4 → 5). In the embodiment of FIG. 105, a period of at least 1/2 of 1H is a period in which a normal program current is passed.

  The period during which the normal program current is passed (the state in which the switches D0 to D7 corresponding to the video signal are set (operated or controlled) so as to be the normal program current) may be all 1H periods. That is, any period may be used as long as it is 1H or less 1 / (4H) or more.

  The operation (control) of the D7 to D0 switches by the Dc switch and the forcing is performed according to the change in gradation. The operation (control) of the Dc switch and the D7 to D0 switch by the forcibility is determined by the controller IC (circuit) 722 based on the change of the video signal for every 1H or the change of the video signal in 1F (one frame) or the change rate. Is done. The determined data or control signal is converted into a differential signal or the like and transmitted to the source driver circuit (IC) 14.

  In FIG. 105 (a), the switch Dc for supplying an overcurrent (precharge current or discharge current) is turned on (closed) for a period of 1 / (4H) from the beginning of 1H. Therefore, an overcurrent (precharge current) is applied to the source signal line 18 for a 1 / (4H) period from the beginning of 1H. Further, the switches D0 to D7 for supplying the program current are forcibly (closed) for a period of 1 / (2H) from the beginning of 1H. Therefore, it is added to the overcurrent (precharge current or discharge current) Id flowing by the operation of the Dc switch, and the precharge current by the switches D0 to D7 is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Applied.

  The period added to the overcurrent (precharge current or discharge current) Id is a 1 / (4H) period from the beginning of 1H and is relatively short. The period during which the normal program current is passed (the state in which the switches D0 to D7 corresponding to the video signal are set (operated or controlled) so as to be the normal program current) is implemented in the 1 / (2H) period of the second half of 1H. Is done. With the above operation, the potential of the source signal line 18 changes from the gradation 4 to the gradation 5 level in the 1 / (2H) period from the beginning of 1H, and the normal program is generated in the 1 / (2H) period in the latter half of 1H. The current program is executed so that the driving transistor 11a of the pixel 16 passes the target program current Iw after being corrected by the current.

  In FIG. 105 (b), the switch Dc for supplying an overcurrent (pre-charge current or discharge current) is turned on (closed) for a period of 1 / (2H) from the beginning of 1H. Therefore, an overcurrent (precharge current) is applied to the source signal line 18 for a 1 / (2H) period from the beginning of 1H. Further, the switches D0 to D7 for supplying the program current are forcibly (closed) for a period of 1 / (2H) from the beginning of 1H. Therefore, it is added to the overcurrent (precharge current or discharge current) Id flowing by the operation of the Dc switch, and the precharge current by the switches D0 to D7 is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Applied.

  The period during which the normal program current is passed (the state in which the switches D0 to D7 corresponding to the video signal are set (operated or controlled) so as to be the normal program current) is implemented in the 1 / (2H) period of the second half of 1H. Is done.

  With the above operation, the potential of the source signal line 18 changes from the gradation 1 to the gradation 2 level in the 1 / (2H) period from the beginning of 1H, and the normal program is generated in the 1 / (2H) period in the latter half of 1H. The current program is executed so that the driving transistor 11a of the pixel 16 passes the target program current Iw after being corrected by the current. As described above, when the potential of the source signal line 18 to start operation is at the gradation 1 level, the period during which the Dc switch is turned on is lengthened, and the overcurrent (precharge current or discharge current) Id is increased for a long time. It is necessary to apply to the signal line 18.

  In FIG. 105 (c), the switch Dc for supplying an overcurrent (pre-charge current or discharge current) is turned on (closed) for a period of 3 / (4H) from the beginning of 1H. Therefore, an overcurrent (precharge current) is applied to the source signal line 18 for a 3 / (4H) period from the beginning of 1H. Further, the switches D0 to D7 for supplying the program current are forcibly (closed) for a period of 1 / (4H) from the beginning of 1H. Therefore, it is added to the overcurrent (precharge current or discharge current) Id flowing by the operation of the Dc switch, and the precharge current by the switches D0 to D7 is applied to the source signal line 18 in the 1 / (4H) period from the beginning of 1H. Applied.

  The period during which the normal program current is passed (the state where the switches D0 to D7 corresponding to the video signal are set (operated or controlled) so as to be the normal program current) is implemented in the 1 / (4H) period of the second half of 1H. Is done.

  With the above operation, the potential of the source signal line 18 changes from the gradation 0 to the gradation 1 level in the 3 / (4H) period from the beginning of 1H, and the normal program is generated in the 1 / (4H) period of the latter half of 1H. The current program is executed so that the driving transistor 11a of the pixel 16 passes the target program current Iw after being corrected by the current. As described above, when the potential of the source signal line 18 for starting operation is at the gradation 0 level, the period during which the Dc switch is turned on is the longest, and the overcurrent (pre-charge current or discharge current) Id is increased for a long time. It is necessary to apply to the source signal line 18.

  In FIG. 105 (d), the switch Dc for supplying an overcurrent (pre-charge current or discharge current) does not operate. The switches D0 to D7 for supplying a program current are forcibly (closed) for a period of 1 / (2H) from the beginning of 1H. Therefore, it is added to the overcurrent (precharge current or discharge current) Id flowing by the operation of the Dc switch, and the precharge current by the switches D0 to D7 is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Applied.

  The period during which the normal program current is passed (the state in which the switches D0 to D7 corresponding to the video signal are set (operated or controlled) so as to be the normal program current) is implemented in the 1 / (2H) period of the second half of 1H. Is done. With the above operation, the potential of the source signal line 18 changes substantially from the gradation 0 to the gradation 1 level in the 1 / (2H) period from the beginning of 1H, and in the 1 / (2H) period in the latter half of 1H. The current program is executed so that the driving transistor 11a of the pixel 16 passes the target program current Iw after being corrected by the program current. As described above, the Dc switch through which an overcurrent (pre-charge current or discharge current) is not operated is because the gradation before the change is relatively low, such as the gradation change from the 16th gradation to the 18th gradation. This is because it is large (the potential of the source signal line 18 is high) and the change from the 16th to the 18th gradation is relatively small.

  In the above embodiment, the Dc switch is continuously kept on, but the present invention is not limited to this. In FIG. 105 (e), the Dc switch is kept on for 1H period continuously, but the present invention is not limited to this. FIG. 105 (e) shows an example in which the Dc switch is turned on a plurality of times (twice) in the 1H period. In FIG. 105 (e), the switch Dc for supplying an overcurrent (pre-charge current or discharge current) has a period of 1 / (4H) from the beginning of 1H and a period of 1 / (4H) after 1 / (2H) has elapsed. Is turned on (closed). Accordingly, an overcurrent (precharge current) is applied to the source signal line 18 as a whole for 1 / (2H) period of 1H. Further, the switches D0 to D7 for supplying the program current are forcibly (closed) for a period of 1 / (2H) from the beginning of 1H.

  Therefore, it is added to the overcurrent (precharge current or discharge current) Id flowing by the operation of the Dc switch, and the precharge current by the switches D0 to D7 is supplied to the source signal line 18 in the 1 / (4H) period from the beginning of 1H. Is applied. The period during which the normal program current is passed (the state where the switches D0 to D7 corresponding to the video signal are set (operated or controlled) so as to be the normal program current) is implemented in the 1 / (4H) period of the second half of 1H. Is done.

  With the above operation, the potential of the source signal line 18 changes from the gradation 2 to the gradation 3 level in the 3 / (4H) period from the beginning of 1H, and in the 1 / (4H) period in the latter half of 1H, the normal program The current program is executed so that the driving transistor 11a of the pixel 16 passes the target program current Iw after being corrected by the current. As described above, constant current can be added in current driving. Therefore, the overcurrent (pre-charge current or discharge current) Id may be applied in any period other than the second half of 1H (other than the final). Moreover, you may divide and apply in multiple times. Needless to say, the above items can be applied to the forced control of the D0 to D7 switches.

  In the above embodiment, the Dc switch is turned on from the beginning of 1H, but the present invention is not limited to this. FIG. 105 (f) shows an embodiment in which the Dc switch is turned on after the lapse of 1 / (4H) period from the beginning. Further, the switches D0 to D7 for supplying the program current are forcibly (closed) for a period of 3 / (4H) from the beginning of 1H.

  Therefore, it is added to the overcurrent (precharge current or discharge current) Id flowing by the operation of the Dc switch, and the precharge current by the switches D0 to D7 is supplied to the source signal line 18 in the 1 / (4H) period from the beginning of 1H. Is applied.

  The period during which the normal program current is passed (the state where the switches D0 to D7 corresponding to the video signal are set (operated or controlled) so as to be the normal program current) is implemented in the 1 / (4H) period of the second half of 1H. Is done. With the above operation, the potential of the source signal line 18 changes from the gradation 5 to the gradation 6 level in the 3 / (4H) period from the beginning of 1H, and the normal program is generated in the 1 / (4H) period in the latter half of 1H. The current program is executed so that the driving transistor 11a of the pixel 16 passes the target program current Iw after being corrected by the current. As described above, constant current can be added in current driving. Therefore, the overcurrent (precharge current or discharge current) Id is not limited to being applied from the beginning of 1H. You may apply in any period other than the latter half of 1H (except the last). Moreover, you may divide and apply in multiple times. Needless to say, the above items can be applied to the forced control of the D0 to D7 switches.

  Although the control period or the operation period in the above embodiment is 1H, the present invention is not limited to this. Needless to say, it may be performed within a specific period of 1H or more. Needless to say, overcurrent (precharge current or discharge current) driving and precharge voltage (program voltage) driving may be combined. Needless to say, the above matters can be applied to other embodiments of the present invention.

FIG. 106 shows an embodiment in which overcurrent (precharge current or discharge current) driving and precharge voltage (program voltage) driving are combined. Further, this is an embodiment in which the overcurrent (precharge current or discharge current) Id application period is also changed.
FIG. 106 shows a case where the precharge voltage is a V0 voltage corresponding to 0 gradation. First, FIGS. 106 (a1), (a2), and (a3) will be described. In FIG. 106 (a1), the precharge voltage is applied for 1 μsec at the beginning of 1H. Further, as shown in FIG. 106 (a2), an overcurrent (pre-charge current or discharge current) Id is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Therefore, as shown in FIG. 106 (a3), the potential of the source signal line 18 is the voltage potential V0 of 0 gradation during the period from t1 to t0. In the period from t0 to t3, the source signal line potential 18 drops due to an overcurrent (pre-charge current or discharge current) Id (intake current direction). During the period from t3 to t2 (the end of 1H), current programming with video data is performed.

  Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16. In the embodiment shown in FIG. 106 (a), after the potential of the source signal line 18 is set to a predetermined value by applying the precharge voltage V0, the current precharge by the overcurrent (precharge current or discharge current) Id is performed. carry out. Therefore, the controller IC (circuit) 722 (not shown) predicts theoretically the appropriate magnitude of the overcurrent (precharge current or discharge current) Id and the application time of the overcurrent (precharge current or discharge current). It is easy to control or set with. As a result, a good and accurate current program can be implemented.

  Next, a driving method in another embodiment of the present invention will be described with reference to FIGS. 106 (b1), (b2), and (b3). In FIG. 106 (b1), the precharge voltage is applied for a time of tx μsec from the beginning of 1H. Further, as shown in FIG. 106 (b2), an overcurrent (pre-charge current or discharge current) Id is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Therefore, as shown in FIG. 106 (b3), during the period from t1 to t0, the potential of the source signal line 18 is the voltage potential V0 of 0 gradation. In the period from t0 to t3, the source signal line potential 18 drops due to an overcurrent (pre-charge current or discharge current) Id (intake current direction). During the period from t3 to t2 (the end of 1H), current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment shown in FIG. 106 (b), the application period of the current precharge by the overcurrent (precharge current or discharge current) Id can be adjusted by controlling the period tx during which the precharge voltage V0 is applied. it can. Therefore, the controller IC (circuit) 722 (not shown) predicts theoretically the appropriate magnitude of the overcurrent (precharge current or discharge current) Id and the application time of the overcurrent (precharge current or discharge current). It is easy to control or set with. As a result, a good and accurate current program can be implemented.

  FIGS. 106A and 106B show the case where the precharge voltage is applied once. However, according to the present invention, the period for applying the precharge voltage is not limited to once. By applying the precharge voltage, the potential of the source signal line 18 can be reset, and the potential control (adjustment) of the source signal line 18 by overcurrent (precharge current or discharge current) Id driving is facilitated by the reset. Because.

  106 (c1), (c2), and (c3) are examples in which the precharge voltage is applied to the source signal line 18 a plurality of times in the 1H period (predetermined time interval). In FIG. 106 (c1), the precharge voltage is applied 1 μsec twice from the beginning of 1H and t3 time. Further, as shown in FIG. 106 (c2), an overcurrent (pre-charge current or discharge current) Id is applied to the source signal line 18 in a period of 4 / (5H) from the beginning of 1H. Therefore, as shown in FIG. 106 (c3), the potential of the source signal line 18 is the voltage potential V0 of 0 gradation during the period from t1 to t0. During the period from t0 to t3, the potential of the source signal line 18 drops due to an overcurrent (precharge current or discharge current) Id. However, in order to apply the precharge voltage during the period from t3 to t4, the potential of the source signal line 18 is reset to V0. During the period from t4 to t5, the potential of the source signal line 18 drops again due to the overcurrent (precharge current or discharge current) Id. During a period from t5 to t2 (the end of 1H), current programming is performed using video data. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment shown in FIG. 106 (c), the potential of the source signal line 18 is reset to a predetermined value by applying the precharge voltage V0, and the current program operation is started from the time when the final precharge voltage is applied. The Therefore, by controlling or adjusting the timing of applying the precharge voltage, the appropriate overcurrent (precharge current or discharge current) Id and the application time of the overcurrent (precharge current or discharge current) can be theoretically determined. It is possible to control. Therefore, it is easy to control or set with a controller IC (circuit) 722 (not shown), and a current program with good accuracy can be implemented.

  FIG. 106 shows an example in which a constant precharge voltage (program voltage) is applied. FIG. 107 shows an embodiment in which the precharge voltage is changed. As an example, it is assumed that an overcurrent (precharge current or discharge current) Id in FIG. 107 is applied for a period of 1 / (2H) from the beginning of 1H (period t1 to t3).

  FIG. 107 (a1) shows a case where the precharge voltage is a V0 voltage corresponding to 0 gradation. FIG. 107 (b1) shows a case where the precharge voltage is a V1 voltage corresponding to one gradation. FIG. 107 (c1) shows a case where the precharge voltage is a V2 voltage corresponding to two gradations.

  107 (a1), (a2), and (a3) will be described. In FIG. 107 (a1), the precharge voltage V0 is applied for 1 μsec at the beginning of 1H. Further, as shown in FIG. 107 (a2), an overcurrent (pre-charge current or discharge current) Id is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Therefore, as shown in FIG. 107 (a3), during the period from t1 to t0, the potential of the source signal line 18 is the voltage potential V0 of 0 gradation.

  In the period from t0 to t3, the source signal line potential 18 drops due to an overcurrent (pre-charge current or discharge current) Id (intake current direction). During the period from t3 to t2 (the end of 1H), current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment of FIG. 107 (a), the potential of the source signal line 18 is set to a predetermined value by applying the precharge voltage V0, and then the current precharge with the overcurrent (precharge current or discharge current) Id is performed. . Therefore, the controller IC (circuit) 722 (not shown) predicts theoretically the appropriate magnitude of the overcurrent (precharge current or discharge current) Id and the application time of the overcurrent (precharge current or discharge current). It is easy to control or set with. As a result, a good and accurate current program can be implemented.

  Next, FIG. 107 (b1) (b2) (b3) will be described. In FIG. 107 (b1), the precharge voltage V1 corresponding to the first gradation is applied for 1 μsec at the beginning of 1H. Further, as shown in FIG. 107 (b2), an overcurrent (pre-charge current or discharge current) Id is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Therefore, as shown in FIG. 107 (b3), during the period from t1 to t0, the potential of the source signal line 18 is the voltage potential V1 of one gradation. In the period from t0 to t3, the source signal line potential 18 drops due to an overcurrent (pre-charge current or discharge current) Id (intake current direction). During the period from t3 to t2 (the end of 1H), current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment of FIG. 107 (b), after the potential of the source signal line 18 is set to a predetermined value by applying the precharge voltage V1, the current precharge with the overcurrent (precharge current or discharge current) Id is performed. . The precharge voltage V1 is lower in potential written to the source signal line 18 than V0. On the other hand, the application time of the overcurrent (precharge current) is constant, and the magnitude of the overcurrent (precharge current or discharge current) Id is also constant at Id0. Therefore, since the potential of the source signal line 18 can be lowered as compared with FIG. 107A, higher luminance display can be realized.

  Also, a controller IC (circuit) 722 (not shown) predicts theoretically an appropriate overcurrent (precharge current or discharge current) Id and application time of the overcurrent (precharge current or discharge current). It is easy to control or set with. As a result, a good and accurate current program can be implemented.

  Further, FIGS. 107 (c1) (c2) (c3) will be described. In FIG. 107 (c1), the precharge voltage V2 corresponding to the second gradation is applied for 1 μsec at the beginning of 1H. Further, as shown in FIG. 107 (c2), an overcurrent (pre-charge current or discharge current) Id is applied to the source signal line 18 in the 1 / (2H) period from the beginning of 1H. Therefore, as shown in FIG. 107 (c3), the potential of the source signal line 18 is the voltage potential V2 of the second gradation during the period from t1 to t0.

  In the period from t0 to t3, the source signal line potential 18 drops due to an overcurrent (pre-charge current or discharge current) Id (intake current direction). During the period from t3 to t2 (the end of 1H), current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment of FIG. 107 (c), the precharge voltage V2 is applied to set the potential of the source signal line 18 to a predetermined value, and then the current precharge with the overcurrent (precharge current or discharge current) Id is performed. . The precharge voltage V2 has a lower potential for writing to the source signal line 18 than V1. On the other hand, the application time of the overcurrent (precharge current) is constant, and the magnitude of the overcurrent (precharge current or discharge current) Id is also constant at Id0. Accordingly, since the potential of the source signal line 18 can be lowered as compared with FIG. 107B, higher luminance display can be realized.

  Also, a controller IC (circuit) 722 (not shown) predicts theoretically an appropriate overcurrent (precharge current or discharge current) Id and application time of the overcurrent (precharge current or discharge current). It is easy to control or set with. As a result, a good and accurate current program can be implemented.

  As described above, by changing the magnitude or potential of the precharge voltage Vpc, the potential of the source signal line 18 when 1H has elapsed can be easily controlled.

  FIG. 107 shows an example in which a constant precharge voltage (program voltage) is changed. FIG. 108 shows an embodiment in which the overcurrent (precharge current) is changed. Note that changing the precharge current can be realized by controlling the Dc0 and Dc1 switches in FIGS. 92, 93, and 94. 108 (a1) and 108 (b1), the precharge voltage is fixed at V0. FIG. 108 (c1) shows an embodiment in which no precharge voltage is applied.

  108 (a1) (a2) (a3) will be described. In FIG. 108 (a1), the precharge voltage V0 is applied for 1 μsec (period t1 to t0) at the beginning of 1H. Further, as shown in FIG. 108 (a2), an overcurrent (pre-charge current or discharge current) Id0 is applied to the source signal line 18 in the first (t1) to t4 period of 1H. Overcurrent (pre-charge current or discharge current) Id1 is applied to the source signal line 18 during the period from t4 to t3.

  As shown in FIG. 108 (a3), the potential of the source signal line 18 is the voltage potential V0 of 0 gradation during the period from t1 to t0. Further, during the period from t0 to t4, the source signal line potential 18 rapidly drops due to a large overcurrent (pre-charge current or discharge current) Id0 (intake current direction). During the period from t4 to t3, the source signal line potential 18 drops relatively slowly due to an overcurrent (precharge current or discharge current) Id1 (intake current direction) smaller than the overcurrent (precharge current or discharge current) Id0. To do. During the period from t3 to t2 (the end of 1H), current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment of FIG. 108 (a), after the potential of the source signal line 18 is set to a predetermined value by applying the precharge voltage V0, first, the current caused by the first overcurrent (precharge current or discharge current) Id0. Precharge is performed to suddenly change the potential of the source signal line. Next, current precharge with a second overcurrent (precharge current or discharge current) Id1 is performed to bring the potential of the source signal line close to the target potential. Finally, current programming is performed so that the driving transistor 11a flows a predetermined current with a program current corresponding to the target video signal. As described above, a plurality of overcurrents (precharge current or discharge current) Id are used for control, the magnitude of these overcurrents (precharge current or discharge current), and application of overcurrent (precharge current or discharge current). An accurate current program can be realized by adjusting the time.

  Further, since the potential change of the source signal line 18 can be theoretically predicted or estimated, it is easy to control or set by the controller IC (circuit) 722 (not shown). As a result, a good and accurate current program can be implemented.

  Next, FIG. 108 (b1) (b2) (b3) will be described. In FIG. 108 (b1), the precharge voltage V0 is applied for 1 μsec (period t1 to t0) at the beginning of 1H. Further, as shown in FIG. 108 (b2), an overcurrent (pre-charge current or discharge current) Id1 is applied to the source signal line 18 in the first (t1) to t3 period of 1H.

  As shown in FIG. 108 (b3), during the period from t1 to t0, the potential of the source signal line 18 is the voltage potential V0 of 0 gradation. In the period from t0 to t3, the source signal line potential 18 drops due to an overcurrent (pre-charge current or discharge current) Id1 (in the sink current direction). During the period from t3 to t2, current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment of FIG. 108B, after the potential of the source signal line 18 is set to a predetermined value by applying the precharge voltage V0, the current precharge with a relatively small overcurrent (precharge current or discharge current) Id1. To change the potential of the source signal line. Finally, current programming is performed so that the driving transistor 11a flows a predetermined current with a program current corresponding to the target video signal.

  As described above, the overcurrent (precharge current or discharge current) Id having an appropriate magnitude is used for control from the target program current or the source signal line 18 potential, and the application time of the overcurrent (precharge current or discharge current) is set. An accurate current program can be realized by adjusting. Further, since the potential change of the source signal line 18 can be theoretically predicted or estimated, it is easy to control or set by the controller IC (circuit) 722 (not shown). As a result, a good and accurate current program can be implemented.

  Further, FIGS. 108 (c1) (c2) (c3) will be described. In FIG. 108 (c1), the precharge voltage is not applied. Therefore, the potential of the source signal line 18 is 1H before. Further, as shown in FIG. 108 (c2), the second overcurrent (pre-charge current or discharge current) Id1 is applied to the source signal line 18 during the first (t1) to t4 period of 1H. A second overcurrent (pre-charge current or discharge current) Id0 is applied to the source signal line 18 during the period from t4 to t3.

  As shown in FIG. 108 (c3), during the period from t0 to t4, the source signal line potential 18 changes due to a relatively small overcurrent (pre-charge current or discharge current) Id1 (intake current direction). During the period from t4 to t3, the source signal line potential 18 rapidly drops due to an overcurrent (precharge current or discharge current) Id0 (in the sink current direction) larger than the overcurrent (precharge current or discharge current) Id1. During the period from t3 to t2 (the end of 1H), current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the embodiment of FIG. 108 (c), first, current precharge with a second overcurrent (precharge current or discharge current) Id1 is performed to change the potential of the source signal line. Next, a current precharge with a first overcurrent (precharge current or discharge current) Id0 is performed to bring the potential of the source signal line close to the target potential. Finally, current programming is performed so that the driving transistor 11a flows a predetermined current with a program current corresponding to the target video signal.

  As described above, a plurality of overcurrents (precharge current or discharge current) Id are used for control, the magnitude of these overcurrents (precharge current or discharge current), and application of overcurrent (precharge current or discharge current). An accurate current program can be realized by adjusting the time. Further, since no precharge voltage is applied, the potential can be changed relatively from the potential applied to the previous pixel row. The potential of the source signal line 18 applied to the previous pixel row can be theoretically predicted or estimated. It is easy to control or set with a controller IC (circuit) 722 (not shown). As a result, a good and accurate current program can be implemented.

  In FIG. 108, the overcurrent (precharge current or discharge current) (precharge current) is changed in the 1H period (predetermined period), but the present invention is not limited to this. For example, the precharge voltage may be changed during the 1H period (predetermined period). Needless to say, both the precharge current and the precharge voltage may be changed. Needless to say, the application time of both the precharge current and the precharge voltage may be changed.

  FIG. 109 shows an embodiment in which the application timing of the precharge voltage is changed. The overcurrent (precharge current) is assumed to be the same. In FIGS. 108 (a1), (b1), and (c1), the precharge voltage is fixed at V0.

  109 (a1), (a2), and (a3) will be described. In FIG. 109 (a1), the precharge voltage V0 is applied for 1 μsec (period t1 to t0) at the beginning of 1H. Further, as shown in FIG. 109 (a2), an overcurrent (pre-charge current or discharge current) Id0 is applied to the source signal line 18 in the first (t1) to t5 period of 1H.

  As shown in FIG. 109 (a3), during the period from t1 to t0, the potential of the source signal line 18 is the voltage potential V0 of 0 gradation. In addition, during the period from t0 to t5, the source signal line potential 18 rapidly drops due to Id0 (as an example, the direction of the suction current. The above matters are the same in other embodiments of the present invention). During a period from t5 to t2 (the end of 1H), current programming is performed using video data. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  As described above, an overcurrent (precharge current or discharge current) Id having an appropriate magnitude is used for control from the target program current or the source signal line 18 potential, and the application time of the overcurrent (precharge current or discharge current) or An accurate current program can be realized by adjusting the size. Further, since the potential change of the source signal line 18 can be theoretically predicted or estimated, it is easy to control or set by the controller IC (circuit) 722 (not shown). As a result, a good and accurate current program can be implemented.

Similarly, FIGS. 109 (b1) (b2) (b3) will be described. In FIG. 109 (b1), the precharge voltage V0 is applied from t0 to 1 μsec (period t0 to t3). Further, as shown in FIG. 109 (b2), an overcurrent (pre-charge current or discharge current) Id0 is applied to the source signal line 18 in the first (t1) to t5 period of 1H.
As shown in FIG. 109 (b3), during the period from t1 to t0, the potential of the source signal line 18 changes from the potential of 1H before (the potential of the source signal line 18 applied for current programming in the previous pixel row). Start. Thereafter, the precharge voltage V0 is applied for 1 μsec (t0 to t1 period) from t0 at t0. Accordingly, the potential of the source signal line 18 is reset to the V0 voltage.

  During the period from t3 to t5, the source signal line potential 18 rapidly drops due to Id0 (as an example, the direction of the sink current. The above matters are the same in other embodiments of the present invention). During a period from t5 to t2 (the end of 1H), current programming is performed using video data. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  As described above, by applying a precharge voltage at an arbitrary time, an overcurrent (precharge current or precharge current or an appropriate magnitude) is generated from the potential of the source signal line 18 (V0 voltage in FIG. 109) defined at an arbitrary timing. An accurate current program can be realized by using the discharge current) Id for control and adjusting the application time or magnitude of the overcurrent (pre-charge current or discharge current). Further, since the potential change of the source signal line 18 can be theoretically predicted or estimated, it is easy to control or set by the controller IC (circuit) 722 (not shown). As a result, a good and accurate current program can be implemented.

  FIG. 109 (c) is the same as FIG. 109 (b). In FIG. 109 (c1), the precharge voltage V0 is applied for 1 μsec from t3 (period from t3 to t4). Further, as shown in FIG. 109 (b2), an overcurrent (pre-charge current or discharge current) Id0 is applied to the source signal line 18 in the first (t1) to t5 period of 1H.

  As shown in FIG. 109 (c3), during the period from t1 to t3, the potential of the source signal line 18 is changed from the potential of 1H before (the potential of the source signal line 18 applied for current programming in the previous pixel row). Start. Thereafter, at t3, the precharge voltage V0 is applied for 1 μsec from t3 (period t3 to t4). Accordingly, the potential of the source signal line 18 is reset to the V0 voltage.

  During the period from t4 to t5, the source signal line potential 18 drops rapidly due to Id0 (as an example, the direction of the sink current. The above matters are the same in other embodiments of the present invention). During a period from t5 to t2 (the end of 1H), current programming is performed using video data. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  As described above, the potential of the source signal line 18 can be changed to a constant value by applying a precharge voltage at an arbitrary time. The magnitude of the overcurrent (pre-charge current or discharge current) Id is the same. Therefore, the change curve due to the overcurrent (pre-charge current or discharge current) Id has a constant inclination angle. An overcurrent (precharge current or discharge current) Id of an appropriate size is used for control from the source signal line 18 potential (V0 voltage in FIG. 109) defined at an arbitrary timing. The potential of the source signal line 18 can be changed to near the target potential by adjusting the application time or magnitude of the current or discharge current. After the potential has become close, it is only necessary to correct by the program current, so that an accurate current program can be realized. Further, since the potential change of the source signal line 18 can be theoretically predicted or estimated, it is easy to control or set by the controller IC (circuit) 722 (not shown).

  In FIGS. 106 to 109 and the like, the direction of the overcurrent (precharge current) has been described by exemplifying the current (sink current) in the direction sucked into the source driver circuit (IC) 14. However, the present invention is not limited to this, and the overcurrent (precharge current) may be in the discharge direction. Further, the overcurrent (pre-charge current or discharge current) may have both a discharge current and a sink current.

  FIG. 111 is an explanatory diagram of a driving method when an overcurrent (precharge current or discharge current) uses both a discharge current and a sink current. As the circuit configuration, the configuration of FIG. 110 is exemplified. In FIG. 111, a switch 221a is used for on / off control of a precharge voltage. When on, a precharge voltage is applied to the output terminal 93. The switch Dc2 is used for on / off control of the precharge current in the discharge direction. When on, a precharge current in the discharge direction is applied to the output terminal 93. The switch Dc1 is used for on / off control of the precharge current in the suction direction. When on, a precharge current in the suction direction is applied to the output terminal 93.

  In the period a in FIG. 111, the precharge voltage V0 is applied for 1 μsec at the beginning of 1H. Also, the Dc1 switch in FIG. 111 is on for the period t1 to ta. Therefore, an overcurrent Id1 in the suction direction flows. During the period from t1 to 1 μsec, the potential of the source signal line 18 is the voltage potential V0 of 0 gradation. Thereafter, during the period up to ta, the source signal line potential 18 rapidly drops due to the overcurrent (precharge current) Id0. During the period from ta to t2, current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the period b in FIG. 111, no precharge voltage is applied. In addition, the Dc2 switch in FIG. 111 is on for a period of t2 to tb. Therefore, an overcurrent Id2 in the discharge direction flows. Due to the overcurrent (precharge current) Id2, the source signal line potential 18 rises rapidly. During the period from tb to t3, current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the period c of FIG. 111, the precharge voltage V0 is applied for 1 μsec at the beginning of 1H for writing in the low gradation region. The Dc1 and Dc2 switches in FIG. 111 are in an off state. During a period of 1 μsec from t3, the potential of the source signal line 18 is the voltage potential V0 of 0 gradation. Thereafter, during the period up to t4, the current program is executed by the video data. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the period d of FIG. 111, the precharge voltage V0 is applied for 1 μsec at the beginning of 1H. Further, the Dc1 switch in FIG. 111 is on for a period from t4 to td. Therefore, an overcurrent Id1 in the suction direction flows. During a period of 1 μsec from t4, the potential of the source signal line 18 is the voltage potential V0 of 0 gradation.

  Thereafter, during the period up to td, the source signal line potential 18 rapidly drops due to the overcurrent (precharge current) Id0. During the period from td to t5, current programming with video data is performed. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  In the period e of FIG. 111, no precharge voltage is applied. In addition, the Dc2 switch in FIG. 111 is on for a period of t5 to te. Therefore, an overcurrent Id2 in the discharge direction flows. Due to the overcurrent (precharge current) Id2, the source signal line potential 18 rises rapidly. During the period from te to t6, the current program is executed by the video data. Therefore, the potential of the source signal line 18 decreases so that a current that matches the program current flows through the driving transistor 11a of the pixel 16.

  As described above, an overcurrent (precharge current or discharge current) Id having an appropriate magnitude is used for control from the target program current or the source signal line 18 potential, and the application time of the overcurrent (precharge current or discharge current) or An accurate current program can be realized by adjusting the size. Further, since the potential change of the source signal line 18 can be theoretically predicted or estimated, it is easy to control or set by the controller IC (circuit) 722 (not shown). As a result, a good and accurate current program can be implemented.

  The above embodiment is an embodiment of overcurrent (precharge current or discharge current) driving or / and precharge voltage driving within the 1H period. However, overcurrent (precharge current or discharge current) drive and / or precharge voltage drive is performed not only in the 1H period but also in consideration of the potential state of the source signal line 18 in one frame or a plurality of horizontal scanning periods. preferable.

  In the present invention, the precharge voltage is also made FRC as shown in FIG. For example, FIG. 130B shows a 4FRC driving method. In FIG. 130 (b), a white circle (white circle) indicates that a precharge voltage (synonymous with or similar to the program voltage) is applied (output), and a black circle (black circle) indicates the precharge voltage (program voltage and (Synonymous or similar) is not applied. That is, FIGS. 130B and 130A indicate that the precharge voltage (synonymous with or similar to the program voltage) is applied only once in 4 frames (fields).

  Similarly, FIGS. 130 (b) and (2) show that the precharge voltage (synonymous with or similar to the program voltage) is applied only twice in 4 frames (fields), and FIGS. 130 (b) and (3). This shows that the precharge voltage (synonymous with or similar to the program voltage) is applied three times in four frames (fields). FIGS. 130 (b) and (4) show that a precharge voltage (synonymous with or similar to the program voltage) is applied to all four frames (fields).

  By performing the above operation (method), gradation display can be increased with a precharge voltage (synonymous with or similar to the program voltage). Therefore, the number of gradations is increased and better image display can be realized. That is, gradation display is realized mainly by a precharge voltage (synonymous with or similar to the program voltage) in the low gradation area, and gradation display is realized by the program current in the high gradation area.

  In the present invention, precharge current or precharge voltage driving is performed. For example, in order to realize 1024 gradations with an 8-bit (256 gradations) source driver circuit (IC) 14, it is combined with 4FRC as described in FIG. Therefore, in the 1024 gradations, the second gradation is displayed in combination with the output of the 0th gradation and the output of the 1st gradation in the source driver circuit (IC) 14 of 256 gradations. Therefore, in the FRC drive, the 0th gradation voltage (precharge voltage and first gradation program voltage or program current) is alternately applied to the source signal line 18 every 1H. Since this region is a low gradation region, precharge driving is always performed for the first gradation. Precharge driving is also performed in raster display. When precharge driving is performed, even in current driving, a voltage driving state is set and display uniformity is deteriorated. On the other hand, in raster display, even if it is a low gradation region, insufficient writing does not occur, so that uniform display can be realized only with a program current. It is not preferable that uniformity is lowered by performing precharge driving.

  In order to solve this problem, according to the present invention, when FRC driving is performed, in the case of adjacent gradation outputs (in the 256 gradation source driver circuit (IC) 14, the output of the 0th gradation and the 1 gradation) The first output is the adjacent output, and the first gradation output and the second gradation are the adjacent output), the precharge drive is not performed. That is, when the output applied to the source signal line 18 has a difference of only one gradation, precharge driving (voltage precharge, current precharge, etc.) is not performed. This is because it is determined that there is no change in raster display or image by FRC, and uniform display is realized only by current drive. Since one gradation difference is subjected to FRC, when precharge driving is performed, voltage driving is performed on the entire screen, and the characteristic variation of the driving transistor 11a of each pixel 16 can be displayed on the screen 64. It is because the nature is high.

  Note that FRC is a technology that realizes gradation display between adjacent gradations by combining them. For example, when 4FRC is performed with 6-bit display (64 gradations), approximately 256 gradation display can be realized. In this display method, for example, a combination of the first gradation and the second gradation (adjacent gradation) can realize display of seven gradations between the first gradation and the second gradation. Similarly, a combination of the second gradation and the third gradation (adjacent gradation) can realize a display of seven gradations between the first gradation and the second gradation.

  When there is a difference of two or more gradations, precharge driving (voltage precharge, current precharge, etc.) is performed (particularly in the low gradation region). For example, in the 256-level source driver circuit (IC) 14, the output applied to the source signal line 18 changes from the 0th gradation to the 2nd gradation. This is also when the output changes from the first gradation to the third gradation. When the gradation changes by two or more gradations, it is determined that the gradation changes more than FRC, and insufficient writing is solved by precharge driving. The above determination is performed by the controller circuit (IC) 722. In other words, the FRC drive is not performed at a difference of two gradations or more.

  Further, the sixth gradation of 1024 gradations is displayed by the output of the first gradation and the output of the second gradation in the 256-gradation source driver circuit (IC) 14. The source signal line 18 is supplied with an output of the first gradation and an output of the second gradation alternately or at a constant cycle from the source driver circuit (IC) 14 of 256 gradations.

  Thus, when the video data applied to the source signal line 18 is for one gradation, the precharge drive is not performed. That is, when the output applied to the source signal line 18 has a difference of only one gradation at a gradation not considering FRC (in this embodiment, 256 gradations), precharge driving (voltage precharge, current precharge). Etc.) This is because it is determined that there is no change in raster display or image by FRC, and uniform display is realized only by current drive.

  When there is a difference of two gradations or more, precharge driving (voltage precharge, current precharge, etc.) is performed. Particularly, it is performed in a low gradation region. For example, in the 256 gradation source driver circuit (IC) 14, the output applied to the source signal line 18 changes from the first gradation to the third gradation or more. Note that it is not necessary to perform precharge driving in the high gradation region. This is because the write current is large.

  As described above, when FRC is performed, precharge driving is performed as necessary when the number of gradations applied to the source signal line 18 changes by two or more gradations at this gradation (256 gradations in the embodiment). Then. However, the present invention is not limited to this. Even when the FRC is not performed, it goes without saying that the precharge drive may be performed as necessary when the number of gradations applied to the source signal line 18 changes by two or more gradations.

  However, precharge driving may be performed even when the change in the adjacent pixel row (change in the signal level applied to the source signal line 18) is a difference of one gradation. For example, when displaying a natural image, even if precharge driving is performed, the characteristic variation of the driving transistor 11a of each pixel 16 is not significant (in the case of a pattern display such as whitewashing, the driving transistor 11a Dispersion of characteristics is remarkable). Therefore, the controller circuit (IC) 722 may determine the display image and determine whether to perform precharge driving.

  Needless to say, if the number of gradations changing in gradations after nFRC is C, precharge driving may be performed as necessary when C / n is greater than 1. For example, when displaying 1024 gradations with 4FRC, if the number of gradations changing in 1024 gradations is 4 (C = 4), precharge driving is not performed with 4/4 = 1. If the number of gradations changing in 1024 gradations is 5 or more (C = 5 or more), 5/4> 1 and precharge driving is performed as necessary.

  In the above embodiments, it has been described that precharge driving is performed as necessary when C / n is larger than 1, but precharge driving is performed as necessary when C / n is larger than K. You may do that. The value of K is changed depending on the lighting rate. For example, when displaying 1024 gradations with 4FRC, if the lighting rate is 70% or more, K = 4, and if the number of gradations changing in 1024 gradations is 16 (C = 16) or more, 334 = Precharge driving may be performed with 4 = K. When C is less than 16, precharge driving is not performed. In addition, when 1024 gradation display is performed with 4FRC, K = 2 when the lighting rate is 20% or more, and when the number of gradations changing with 1024 gradations is 8 (C = 8) or more, 8 / Precharge driving may be performed with 4 = 2 = K. When C is less than 8, precharge driving is not performed.

  In the above-described embodiment, when the output applied to the source signal line 18 changes from the first gradation to the third gradation or higher, such as when the gradation changes from the low gradation to the high gradation, the third gradation to the first gradation. Needless to say, the precharge drive may be performed when the gradation changes from high to low, such as the first and the tenth to the eighth to the eighth. Note that it is not necessary to perform precharge driving in a high gradation region having a predetermined gradation or more. This is because the write current is large.

  Hereinafter, a driving method of the EL display device of the present invention will be described. The EL display panel of the present invention is mainly driven by current. There are mainly two distinct image display control methods. One is control of the reference current. The other is duty ratio control. By combining the reference current control and the ratio control singly or in combination, a wide dynamic range, high image quality display, and high contrast can be realized.

  In the specification of the present invention, the ratio of the display area 63 to the entire display area 64 on the display screen 64 is called a duty ratio. That is, the duty ratio is the area of the display area 63 / the area of the entire display area 64. Alternatively, the duty ratio is also the number of gate signal lines 17b to which an ON voltage is applied / the number of all gate signal lines 17b. Further, the ON voltage is applied to the gate signal line 17b, and the number of selected pixel rows connected to the gate signal line 17b / the total number of pixel rows in the display area 64 is also obtained.

  In this specification, description will be made assuming that duty ratio control or the like is changed in accordance with the lighting rate. However, the lighting rate does not have a certain meaning. For example, the low lighting rate means that the current flowing through the screen 64 is small, but also means that there are many low gradation display pixels constituting the image. That is, the image constituting the screen 64 has many dark pixels (low gradation pixels).

  Therefore, the low lighting rate can be paraphrased as a state where there is a large amount of low gradation video data when the histogram processing of the video data constituting the screen is performed. The high lighting rate means that the current flowing through the screen 64 is large, but also means that there are many high gradation display pixels constituting the image. That is, the image constituting the screen 64 has many bright pixels (high gradation pixels). The high lighting rate can be paraphrased as a state in which there is a lot of high gradation video data when the histogram processing of the video data constituting the screen is performed. In other words, the control corresponding to the lighting rate may mean a state that is synonymous or similar to the control corresponding to the gradation distribution state or the histogram distribution of the pixel.

  From the above, the control based on the lighting rate is based on the gradation distribution state of the image (low lighting rate = many low tone pixels, high lighting rate = many high tone pixels) depending on the case. In other words, it can be controlled. For example, increasing the reference current ratio as the lighting rate decreases and decreasing the duty ratio as the lighting rate increases increases the reference current ratio as the number of low gradation pixels increases. In other words, the duty ratio decreases as the number of pixels in the key increases. Alternatively, increasing the reference current ratio as the lighting rate decreases and decreasing the duty ratio as the lighting rate increases increases the reference current ratio as the number of low gradation pixels increases. This means the same or similar meaning, operation or control as decreasing the duty ratio as the number of pixels increases.

  Also, for example, if the reference current ratio is increased N times below a predetermined low lighting rate and the number of selection signal lines is increased to N, the reference current ratio is increased N times when the number of low gradation pixels is equal to or greater than a certain value. In addition, this means the same or similar meaning, operation, or control to setting the number of selection signal lines to N.

  For example, normally, driving with a duty ratio of 1/1 and lowering the duty ratio stepwise or smoothly above a predetermined high lighting rate means that the number of low gradation or high gradation pixels is within a certain range. When the ratio is within the range, the duty ratio is 1/1, and when the number of high gradation pixels exceeds a certain value, the meaning or operation or control is the same as or similar to the stepwise or smooth reduction of the duty ratio. It is.

  In order to realize full color display on an EL display panel, it is necessary to form (create) a reference current for each of RGB. White balance can be adjusted by the ratio of RGB reference currents. The reference current determines the current value that the unit transistor 224 passes. Therefore, if the magnitude of the reference current is determined, the current that the unit transistor 224 flows can be determined. For this reason, if R, G, and B reference currents are set, white balance can be obtained in all gradations. The above items are the effects that are exhibited because the source driver circuit (IC) 14 is current output (current drive).

  In the present invention, by forming or arranging an electronic volume inside the source driver circuit (IC) 14, the reference current can be varied or changed by digital data control from the outside of the source driver circuit (IC) 14. . This matter is an important matter in the current drive driver. In current driving, video data is proportional to the current flowing through the EL element 15. Therefore, the current flowing through all the EL elements can be controlled by performing logic processing on the video data. Since the reference current is also proportional to the current flowing through the EL elements 15, the current flowing through all the EL elements 15 can be controlled by digitally controlling the reference current. From the above, by performing the reference current control based on the video data, it is possible to easily realize the expansion of the dynamic range of display luminance. Further, white balance can be maintained even when the display luminance is changed.

  In the reference current control, as shown in FIGS. 29 and 30, the source driver circuit (IC) 14 includes a circuit 291 for adjusting the reference current Ic of each RGB. The program current Iw from the source driver circuit (IC) 14 is determined by the number of unit transistors 224.

  The current output from one unit transistor 224 is proportional to the magnitude of the reference current. Therefore, by adjusting the reference current, the current output by one unit transistor 224 is determined, and the magnitude of the program current is determined. Since the reference current and the output current of the unit transistor 224 have a linear relationship, and the program current and the luminance have a linear relationship, if the white balance is adjusted by adjusting the reference current of each RGB in white raster display , White balance is maintained in all gradations.

  6, FIG. 7, FIG. 12, FIG. 13, FIG. 14 and FIG. 15 are duty ratio control methods. FIG. 6 shows a method of inserting the non-display area 62 continuously. Suitable for video display. The duty ratio can be freely changed by controlling the gate driver circuit 12a and applying an ON or OFF voltage to the gate signal line 17b. If the duty ratio is changed while the reference current is kept constant, the brightness of the screen 62 can be changed.

  FIG. 14 shows a method of inserting the non-display area 62 by dividing it into a large number. Particularly suitable for still image display. The duty ratio can be freely changed by controlling the gate driver circuit 12b and periodically applying an on / off voltage to the gate signal line 17b.

  As described above, the duty ratio control is a method for realizing brightness control of the screen 64 by controlling the current flowing through the EL element 15 without changing the program current Iw applied to the source signal line 18. is there. That is, this is a method for realizing brightness control of the screen 64 in a state where the reference current is constant (without changing). Of course, the duty ratio may be changed while changing the reference current.

  In this method, the brightness of the screen 64 is controlled without changing the current flowing through the driving transistor 11a. In addition, the brightness of the screen 64 is controlled without changing the gate terminal (G) voltage of the driving transistor 11a. In addition, by changing the scanning state of the gate driver 12b, the gate signal line 17b and the like are controlled, and brightness control of the screen 64 is realized.

  The dispersion of the display area 63 is 220/4 = 55 if the number of pixel rows of the display panel is 220 and the 1/4 duty ratio is 1 to 55 (from 1 brightness to 55 times the brightness). Can be adjusted). Further, if the number of pixel rows of the display panel is 220 and the 1/2 duty ratio is 220/2 = 110, 1 to 110 (the brightness can be adjusted from 1 brightness to 110 times the brightness). Therefore, the adjustment range of the brightness of the screen brightness 64 is very wide (the dynamic range of image display is wide). Further, there is a feature that the number of gradations that can be expressed can be maintained regardless of the brightness. For example, in the case of 64-gradation display, 64-gradation display can be realized regardless of whether the brightness of the display screen 64 in white raster is 300 nt or 3 nt.

As described before, the duty ratio can be easily changed by controlling the start pulse to the gate driver circuit 12b. Therefore, various duty ratios such as 1/2 duty ratio, 1/4 duty ratio, 3/4 duty ratio, and 3/8 duty ratio can be easily changed.
The duty ratio driving in units of one horizontal scanning period (1H) may be performed by applying an on / off signal of the gate signal line 17b in synchronization with the horizontal synchronizing signal. Furthermore, the duty ratio can be controlled even in units of 1H or less.

  The main reason that it is necessary to perform duty ratio control within 1H when the duty ratio is equal to or less than ¼ duty ratio is that the amount of change per step is large. Moreover, since the image is halftone, even a minute change is easily recognized visually. Human vision has a low ability to detect changes in brightness on dark screens above a certain level. In addition, even on a bright screen above a certain level, the detection capability for brightness change is low. This seems to be because human vision depends on the square characteristic.

  If the number of pixel rows in the panel is 200, on / off control within 1H is performed at a ratio of 20/200 duty ratio or less (1/200 or more and 20/200 or less), and duty ratio control for a period of 1H or less is performed. When the 1/200 duty ratio is changed to the 2/200 duty ratio, the difference between the 1/200 duty ratio and the 2/200 duty ratio is 1/200, which is a change of 100%. This change is completely visually recognized as flicker. Therefore, on / off control is performed within 1H, and current supply to the EL element 15 is controlled in a period equal to or shorter than 1H (one horizontal scanning period). Although the duty ratio control is performed in the 1H period or less (within 1H period), the present invention is not limited to this. As can be seen in FIG. 6, the non-display area 62 is continuous. That is, control such as the 10.5H period is also within the scope of the present invention. In other words, the present invention is not limited to the 1H period (a decimal part is generated), and performs duty ratio driving.

  When the 40/200 duty ratio is changed to the 41/200 duty ratio, the difference between the 40/200 duty ratio and the 41/200 duty ratio is 1/200, and the change is 2.5% at (1/200) / (40/200). It becomes. Whether or not this change is visually recognized as flicker is highly likely to depend on the screen brightness 64. However, since the 40/200 duty ratio is halftone display, it is visually sensitive. Therefore, it is desirable to perform OEV2 control (see FIG. 40 and the like) and to control current supply to the EL element 15 in a period of 1H (one horizontal scanning period) or less.

  As described above, the driving method and the display device according to the present invention can store the current value flowing through the EL element 15 in the pixel 16 (corresponding to the capacitor 19 in FIG. 1), the driving transistor 11a, and the light emitting element (EL 6 is a display panel having a configuration capable of turning on and off a current path with respect to the element 15 (the pixel configuration shown in FIGS. 1, 18, 19 and the like corresponds), and at least in a display state of a display image. 14 is generated (the display screen 64 is a display area 63 (may be a duty ratio of 1/1) depending on the luminance of the image) and a duty ratio drive (at least one of the display screens 64). If the driving method or driving state in which the portion becomes the non-display area 63 is equal to or less than a predetermined duty ratio, the EL element is limited to one horizontal scanning period (1H period) or to 1H period unit 5 to control the current flowing, and performs brightness control of the display screen 64.

  It is carried out when the ratio is below. Conversely, if the duty ratio is equal to or higher than the predetermined duty ratio, duty ratio control is performed in units of 1H. Or, OEV2 control is not performed. The duty ratio control other than the 1H period is performed when the change of one step changes from before the change to 1/20 (5%) or more after the change. More preferably, it is desirable to perform minute duty ratio drive control by performing OEV2 control even with a change of 222 (2%) or less. Alternatively, it is carried out with a luminance of 1/4 or less of the maximum luminance of the white raster.

  According to the duty ratio control drive of the present invention, if the number of gradation representations of the EL display panel is 64 gradations, the display brightness (nt) of the display screen 64 is any brightness (regardless of whether the brightness is low or high). Even so, 64-gradation display is maintained. For example, even when the number of pixel rows is 220 and only one pixel row is in the display area 63 (display state) (duty ratio 1/220), 64-gradation display can be realized. This is because an image is sequentially written in each pixel row by the program current Iw of the source driver circuit (IC) 14, and this one pixel row is sequentially displayed by the gate signal line 17b. Even when all the pixel rows are in the display area 63 (display state) (duty ratio 1/1), 64-gradation display can be realized.

  Of course, even when 20 pixel rows are in the display area 63 (display state) (duty ratio 20/220 = duty ratio 1/11), 64-gradation display can be realized. This is because images are sequentially written in the pixel rows by the program current Iw of the source driver circuit (IC) 14, and all the pixel rows are simultaneously displayed by the gate signal lines 17b. Even when only 20 pixel rows are in the display area 63 (display state) (duty ratio 20/220 = duty ratio 1/11), 64-gradation display can be realized. This is because an image is sequentially written to each pixel row by the program current Iw of the source driver circuit (IC) 14, and the 20 pixel rows are sequentially scanned and displayed by the gate signal line 17b.

  The same applies to the reference current control of the present invention (see the circuit configurations of FIGS. 29 and 30), and 64-gradation display can be realized regardless of whether the reference current is small or large.

  Since the duty ratio control drive of the present invention is a control of the lighting time of the EL element 15, the brightness of the display screen 64 with respect to the duty ratio has a linear relationship. Therefore, it is very easy to control the brightness of the image, the signal processing circuit is simple, and the cost can be reduced. As shown in FIG. 29, the RGB reference current is adjusted to achieve white balance. As a method for adjusting the reference current, there are a method of changing the electronic volume 291 of each RGB and a method of adjusting the value of the resistance R1 (R1r, R1g, R1b) of each RGB. In the duty ratio control, white balance is maintained at any gradation and brightness of the display screen 64 in order to simultaneously control the brightness of R, G, and B.

  In the duty ratio control, the luminance of the display screen 64 is changed by changing the area of the display region 63 with respect to the display screen 64. Naturally, the current flowing through the EL display panel changes in proportion to the display area 63. Therefore, by obtaining the sum of the video data, it is possible to calculate the total consumption current flowing through the EL element 15 of the display screen 64. Since the anode voltage Vdd of the EL element 15 is a DC voltage and is a fixed value, if the total current consumption can be calculated, the total power consumption can be calculated in real time according to the image data. When the calculated total power consumption is predicted to exceed the prescribed maximum power, the reference current Ic in FIG. 29 and the like may be adjusted by an adjustment circuit such as an electronic volume, and the RGB reference current may be controlled to be suppressed.

  In addition, a predetermined luminance in white raster display is set, and this time is set so as to minimize the duty ratio. For example, the duty ratio is 1/8. For natural images, the duty ratio is increased. The maximum duty ratio is 1/1. For example, a natural image in which an image is displayed only 1/100 of the display screen 64 is set to a duty ratio 1/1. The duty ratio 1/1 to the duty ratio 1/8 is smoothly changed depending on the display state of the natural image on the display screen 64.

  As described above, as an example, in white raster display (all pixels are lit 100% in a natural image), the duty ratio is 1/8, and 1/100 pixel of the display screen 64 is lit. The duty ratio is 1/1. The approximate power consumption can be calculated by the number of pixels × the ratio of the number of lit pixels × duty ratio.

  For ease of explanation, assuming that the number of pixels is 100, the power consumption in white raster display is 100 × 1 (100%) × duty ratio 1/8 = 80. On the other hand, the power consumption of a natural image in which 1/100 is lit is 100 × (1/100) (1%) × duty ratio 1/1 = 1. The duty ratio 1/1 to the duty ratio 1/8 is gently controlled so that flicker does not occur in accordance with the number of lighting pixels of the image (actually, the total current of the lighting pixels = the total sum of the program currents of one frame). Is implemented.

  As described above, the power consumption ratio of white raster is 80, and the power consumption ratio of a natural image in which 1/100 is lit is 1. Therefore, the maximum current can be suppressed by setting a predetermined luminance in white raster display and setting this time so as to minimize the duty ratio.

  In the present invention, the sum of the program currents for one screen is S, the duty ratio is D, and drive control is performed with S × D. In addition, the total program current in the white raster display is Sw, the maximum duty ratio is Dmax (usually the duty ratio 1/1 is the maximum), the minimum duty ratio is Dmin, and any natural This is a drive method and a display device that realizes the drive method in which the relationship of Sw × Dmin> = Ss × Dmax is maintained when the total program current in the image is Ss.

  Note that the maximum duty ratio is 1/1. The minimum is preferably a duty ratio of 1/16 or more (such as 1/8). That is, the duty ratio is set to 1/16 or more and 1/1 or less. Needless to say, the use of 1/1 is not restricted. Preferably, the minimum duty ratio is 1/10 or more. This is because if the duty ratio is too small, the occurrence of flicker is conspicuous, and the change in screen brightness due to the image content becomes too large, making it difficult to see the image.

  As described above, the program current is proportional to the video data. Therefore, the sum of program currents is synonymous with the sum of video data. Although the sum of program currents for one frame (one field) period is obtained, the present invention is not limited to this. In one frame (one field), the pixels to which the program current is added may be sampled at a predetermined interval or a predetermined cycle, and the total of the program current (video data) may be obtained. Further, the sum data before and after the frame (field) to be controlled may be used, or the duty ratio control may be performed using the sum data by estimation or prediction.

  FIG. 112 is a block diagram of the drive circuit of the present invention. Hereinafter, the drive circuit of the present invention will be described. In FIG. 112, a Y / UV video signal and a composite (COMP) video signal can be input from the outside. The switch circuit 1121 selects which video signal is input to.

  The video signal selected by the switch circuit 1121 is decoded and AD converted by a decoder and an A / D circuit, and converted into digital RGB image data. RGB image data is 8 bits each. The RGB image data is subjected to gamma processing by a gamma circuit 1124. At the same time, a luminance (Y) signal is obtained. The RGB image data is converted into 10-bit image data by gamma processing.

  After the gamma processing, the image data is subjected to FRC processing or error diffusion processing by the processing circuit 1129. RGB image data is converted into 6 bits by FRC processing or error diffusion processing. This image data is subjected to AI processing or peak current processing by an AI processing circuit 1126. The moving image detection circuit 1127 performs moving image detection. At the same time, color management processing is performed by the color management circuit 1128.

  The processing results of the AI processing circuit 1126, the moving image detection circuit 1127, and the color management circuit 1128 are sent to the arithmetic circuit 1129, and the arithmetic processing circuit 1129 converts them into control arithmetic, duty ratio control, and reference current control data. The data is sent to the source driver circuit (IC) 14 and the gate driver circuit 12 as control data.

  Duty ratio control, reference current ratio control, peak current control, and the like are preferably not applied to OSD (on-screen display or on-screen demand). In OSD, a menu screen is displayed on a video camera or the like. Even in OSD, when peak current control or the like is performed, the screen becomes darker or brighter depending on the display state of the menu, and a visual defect occurs.

  To deal with this problem, OSD data (OSDDATA) and video data (moving image data) are processed by separate control circuits 1126. Basically, OSD data is not subjected to luminance modulation.

  Note that the controller circuit (IC) 722 is not limited to one chip. For example, a controller circuit (IC) 722G that controls the gate driver circuit 12 and a controller circuit (IC) 722S that controls the source driver circuit (IC) 14 may be separated. The processing contents become clear by the separation, and the controller IC can be reduced in size.

  The duty ratio control data is sent to the gate driver circuit 12b, and duty ratio control is performed. On the other hand, the reference current control data is sent to the source driver circuit (IC) 14 and the reference current control is performed. Image data that has been subjected to gamma correction and subjected to FRC or error diffusion processing is also sent to the source driver circuit (IC) 14.

  The image data conversion needs to be performed by gamma processing of the gamma circuit 1124. The gamma circuit 1124 performs gradation conversion using a multipoint broken gamma curve. The 256-gradation image data is converted to 1024 gradations by a multipoint broken gamma curve. Although the gamma circuit 1124 performs gamma conversion with a multipoint broken gamma curve, the present invention is not limited to this.

  In the above description, the duty ratio is controlled. However, the duty ratio is a predetermined period (usually one field or one frame. That is, in general, a cycle or time at which image data of an arbitrary pixel is rewritten. It is a lighting period of the EL element 15 in (A). That is, a duty ratio of 1/8 means that the EL element 15 is lit during a 1/8 period (1F / 8) of one frame. Therefore, the duty ratio can be read as duty ratio = Ta / Tf, where Tf is the period when the pixel 16 is rewritten and the lighting period Ta of the pixel.

  In addition, although the period time in which the pixel 16 is rewritten is Tf and is based on Tf, the present invention is not limited to this. The duty ratio control drive of the present invention does not need to complete the operation in one frame or one field. That is, the duty ratio control may be performed with several fields or several frame periods as one cycle. Therefore, Tf is not limited to the cycle of rewriting pixels, and may be one frame or one field or more. For example, if the lighting period Ta is different for each field or frame, the repetition period (period) may be Tf and the total lighting period Ta of this period may be employed. That is, Ta may be the average lighting time of several fields or several frame periods. The same applies to the duty ratio. When the duty ratio differs for each frame (field), an average duty ratio of a plurality of frames (fields) may be calculated and used.

  Therefore, the sum of program currents in white raster display is Sw, the sum of program currents in an arbitrary natural image is Ss, the minimum lighting period is Tas, and the maximum lighting period is Tam (usually Tam = Tf). To Tam / Tf = 1), a driving method for maintaining a relationship of Sw × (Tas / Tf)> = Ss × (Tam / Tf) and a display device that realizes the driving method.

  As shown in FIGS. 29 and 30, the program current can be linearly adjusted by controlling the reference current. This is because the output current of one unit transistor 224 changes. When the output current of the unit transistor 224 is changed, the program current Iw is also changed. The larger the current programmed in the pixel capacitor 19 (actually, the voltage corresponding to the program current) is, the larger the current flowing through the EL element 15 is. The current flowing through the EL element 15 and the light emission luminance are linearly proportional. Therefore, the light emission luminance of the EL element 15 can be linearly changed by changing the reference current.

  The source driver circuit (IC) 14 of the present invention changes the program current Iw by controlling the number of unit transistors 224 connected to the output terminal 93. The program current Iw is realized by changing the reference current Ic as described with reference to FIGS.

  However, the reference current control or the like of the present invention is not limited, and a constant reference (voltage, current, setting data, etc.) is changed, and the current Iw output from the output terminal 93 can be changed by this change. Any one can be used. However, it is important to change the program current Iw of each output terminal 93 at the same rate due to a change in the reference. Note that the present invention is not limited to changes in the program current Iw. It may be a program voltage. This is because the luminance of the display screen 64 can be adjusted by changing the program voltage of each output terminal 93 at the same rate. Further, the white balance can be adjusted by changing the RGB terminal.

  The present invention controls screen brightness and the like using at least one of the reference current control method and the duty ratio control method described above. Preferably, the reference current control method and the duty ratio control method are combined and implemented.

  Further, the driving method of the present invention will be described. One object of the driving method of the present invention is to limit the upper limit of current consumption consumed by the EL display panel. In the EL display panel, the luminance is proportional to the current flowing through the EL element 15. Therefore, if the current flowing through the EL element 15 is increased, the luminance of the EL display panel can be increased. The current consumed (= power consumption) increases in proportion to the luminance.

  When used for a mobile device such as a portable device, the capacity of a battery or the like is limited. Further, the scale of the power supply circuit increases as the current consumed increases. Therefore, it is necessary to provide a limit for the consumed current. Providing this limit (peak current suppression) is one object of the present invention.

  The display is improved by increasing the contrast of the image. Display is improved by converting an image (such as a wide dynamic range, a high contrast ratio, and a large gradation expression power) so that the image is displayed with an edge. The second object of the present invention is to improve the image display as described above. The present invention that achieves the above object will be referred to as AI driving.

  For ease of explanation, it is assumed that the IC chip 14 of the present invention has a 64-gradation display. In order to realize AI driving, it is desirable to expand the gradation expression range. For ease of explanation, the source driver circuit (IC) 14 of the present invention has 64 gradation display and the image data has 256 gradation. This image data is subjected to gamma conversion so as to match the gamma characteristic of the EL display device. The gamma conversion is performed by expanding the input 256 gradations to 1024 gradations. The gamma-converted image data is subjected to error diffusion processing or frame rate control (FRC) processing so as to conform to the 64 gradations of the source driver IC 14 and is applied to the source driver IC 14.

  When the image data of one screen is large as a whole, the total sum of the image data becomes large. For example, since the white raster has 63 gradations as image data in the case of 64-gradation display, the number of pixels of the display screen 64 × 63 is the sum of the image data. In the white window display of 1/100 and the white display portion displaying white with the maximum luminance, the number of pixels of the display screen 64 × (1/100) × 63 is the sum of the image data.

  In the present invention, a value capable of predicting the total sum of image data or the current consumption amount of the screen is obtained, and the duty ratio control or the reference current control is performed based on this sum or value.

  Although the sum of the image data is obtained, the present invention is not limited to this. For example, an average level of one frame of image data may be obtained and used. In the case of an analog signal, the average level of the video signal can be obtained by filtering the analog image signal with a capacitor. A direct current level may be extracted from an analog video signal through a filter, and the direct current level may be AD converted to be a sum of image data. In this case, the image data can also be referred to as an APL level.

  It is preferable to obtain the sum of the image data from 30 frames to 300 frames or data that can estimate the sum, and perform duty ratio control based on the size of this data. The total data changes slowly according to image changes. The longer the frame period for obtaining the total data, the slower the brightness change of the image.

  It is not necessary to add all the data of the image constituting the display screen 64, and 1 / W (W is a value larger than 1) of the display screen 64 may be picked up and extracted to obtain the sum of the picked up data. . For example, a method of sampling video data by skipping one pixel and obtaining the sum from the sampled video data is exemplified. Further, there is exemplified a method of sampling video data of one or a plurality of pixels for each pixel row and obtaining a sum from the sampled video data.

  In order to facilitate the description, the description will be made assuming that the sum of the image data is also obtained in the above case. In many cases, the sum of the image data coincides with the determination of the APL level of the image. The sum total of image data includes means for digital addition, but the method for obtaining the sum total of digital and analog image data is hereinafter referred to as an APL level for ease of explanation.

  Since the APL level is 6 bits for each of RGB in the white raster, 63 (indicated by 63 as data representation because it is the 63rd gradation) × number of pixels (176 × RGB × for the QCIF panel) 220). Therefore, the APL level is maximized. However, since the current consumed by the RGB EL elements 15 is different, it is preferable to calculate the image data separately for RGB.

  For this problem, the arithmetic circuit shown in FIG. 113 is used. In FIG. 113, reference numerals 1311, 1132 denote multipliers. Reference numeral 1131 denotes a multiplier for weighting the emission luminance. R, G, and B have different visibility. The visibility in NTSC is R: G: B = 3: 6: 1. Therefore, the R multiplier 1131R performs a multiplication of 3 times on the R image data (Rdata). Further, the G multiplier 1131G performs 6 times multiplication on the G image data (Gdata). Further, the B multiplier 1131B performs multiplication of 1 time on the B image data (Bdata). However, this description is conceptual. This is because EL elements have different efficiencies in RGB.

  The EL element 15 has different luminous efficiencies for RGB. Usually, the luminous efficiency of B is the worst. Next, G is bad. R has the best luminous efficiency. Therefore, the multiplier 1132 weights the light emission efficiency. The R multiplier 1132R multiplies the R image data (Rdata) by the R light emission efficiency. The G multiplier 1132G multiplies the G image data (Gdata) by the G light emission efficiency. The B multiplier 1132B multiplies the B image data (Bdata) by the B light emission efficiency.

  The results of the multipliers 1131 and 1132 are added by the adder 1133 and accumulated in the summation circuit 1134. Based on the result of the summation circuit 1134, duty ratio control and reference current control are performed.

  In the embodiment described above, data is obtained by multiplying video data by a predetermined value in consideration of the efficiency of the EL element 15 and the like. The present invention obtains the current flowing from the video data to the anode or cathode terminal of the display panel.

  Usually, the RGB EL element 15 has a known luminous efficiency for each EL material, and the relationship between current and luminance is known. In addition, the target color temperature when the EL display panel is produced is determined. Therefore, if the display size and the target luminance of the EL display panel are determined, the ratio and the magnitude of the RGB current that flows through the EL display panel to obtain the target color temperature can be known. Therefore, the target luminance and color temperature can be obtained by setting the current flowing through the anode terminal or cathode terminal of the EL display panel to a predetermined value.

  The current flowing through the anode terminal or the cathode terminal is proportional to the sum of the video data. From the above, the anode current (cathode current) can be obtained from the sum of the video data. The anode current is a current that flows into the anode terminal connected to the display area. The cathode current is a current that flows out from the cathode terminal connected to the display area. Since the anode voltage or the cathode voltage is a fixed value, the power consumption of the EL display panel can be controlled from the video data.

  In other words, the cathode (anode) current required for the EL display panel can be obtained by monitoring (calculating) the size of the video data (the sum) or a change in the size in real time. If it is known to which size the current should be suppressed, the current can be controlled by reference current control and duty ratio control.

  Of course, by converting the magnitude of the anode current or cathode current from analog to digital (AD), the magnitude of the current can be controlled from the converted digital data by reference current control and duty ratio control. Further, by performing feedback control of amplification factor by using an operational amplifier directly using analog data, the magnitude of current can be controlled by reference current control and duty ratio control. That is, the control method may be digital or analog.

  The input data is RGB data (red is RDATA, green is GDATA, and blue is BDATA), but is not limited thereto. It may be YUV (luminance data and chromaticity data). In the case of YUV, weighting processing is performed by directly converting to Y (luminance) data or Y data and UV (chromaticity) data, or by converting into luminance data or the like in consideration of light emission efficiency with respect to chromaticity.

  Needless to say, the duty ratio of the current operation state is taken into consideration when this operation is performed. This is because, if the duty ratio is small, even if the weighted data is large, the current flowing into the panel is small, and the panel does not enter an overheated state.

  RDATA is multiplied by a constant Ra. GDATA is multiplied by a constant Ga. BDATA is multiplied by a constant Ba. From the multiplied data, a summation circuit (SUM) 1134 obtains current data (or similar data) for one screen. In order to facilitate the following description, Ry, Gy, and By are set to 1. The summation circuit 1134 sends it to a comparison circuit (not shown). The comparison circuit compares with preset comparison data (a value or data set to indicate an overheat condition above a predetermined current data). When the current data is equal to or higher than the comparison data, a counter circuit (not shown) To increase the counter value of the counter circuit by one. When the current data is smaller than the comparison data, the counter value of the counter circuit is decreased by one.

  When the above operation is continued and the counter value of the counter circuit reaches a predetermined value or more, the controller circuit (IC) 722 controls the gate driver 12b to reduce the duty ratio and suppress the current flowing through the panel. Therefore, the panel is not overheated and deteriorated.

  Needless to say, the constants Ra, Ga, and Ba are preferably configured to be rewritten by a command by the controller circuit (IC) 722. Of course, it goes without saying that it may be configured so that the user can manually rewrite. Needless to say, it is preferable that the comparison data of the comparison circuit is also rewritable. In addition, since the EL element 15 has temperature dependence, it is preferable that the constant is rewritten depending on the panel temperature. Also, the light emission efficiency varies depending on the lighting rate (also depending on the magnitude of the current flowing through the EL element 15). Therefore, it is preferable that the constant is rewritten depending on the lighting rate. The above matters also apply to Ry, Gy, and By.

  As described above, the present invention calculates or controls the power (current) consumed by the EL display panel from the size (or data that can be estimated) of the video data (or data proportional thereto), and controls the duty ratio. Reference current control is performed.

  Calculation of the power (current) consumed by the EL display panel from the size (or data that can be estimated) of the video data (or data proportional thereto) is limited to being performed for each frame (one field). Needless to say, it may be performed for each of a plurality of frames (fields), or may be performed a plurality of times in one frame (one field). Needless to say, the reference current control and the duty ratio control are not limited to being performed in real time, and may be performed with delay, hysteresis, or skipping.

  The magnitude of the anode current or cathode current of the EL display panel is controlled by reference current control and duty ratio control. However, the present invention is not limited to this, and by controlling the anode voltage or cathode voltage, the EL display panel can also be controlled. Needless to say, the power consumption can be controlled.

  If the control is performed as shown in FIG. 113, duty ratio control and reference current control for the luminance signal (Y signal) can be performed. However, when a luminance signal (Y signal) is obtained and duty ratio control is performed, a problem may occur. For example, a blue back display. In the blue back display, the current consumed by the EL display panel is relatively large. However, the display brightness is low. This is because the visibility of blue (B) is low. Therefore, the sum (APL level) of the luminance signal (Y signal) is calculated to be small, and the duty ratio control becomes a high duty ratio. Accordingly, flicker occurs.

  For this problem, the multiplier 1131 may be used as through. This is because the sum (APL level) with respect to the current consumption is obtained. It is desirable to obtain the total APL level by taking both the sum (APL level) based on the luminance signal (Y signal) and the sum (APL level) based on the current consumption into consideration. Depending on the total APL level, duty ratio control, reference current control, precharge control, etc. are performed.

  Since the black raster is the 0th gradation in the case of the 64 gradation display, the APL level is 0 and becomes the minimum value. In the current driving method, power consumption (current consumption) is proportional to image data. The image data need not count all the bits of the data constituting the display screen 64. For example, when the image is represented by 6 bits, only the upper bits (MSB) may be counted. In this case, the number of gradations is 32 or more and one count is made. Therefore, the APL level changes depending on the image data constituting the display screen 64. In other words, the sum total of video data is not a complete sum but may be any method that can estimate the sum.

  From the analog concept, the term “APL level” is used as the sum of video data or an index similar to the sum. However, in the latter half, the driving method of the present invention will be described using the term lighting rate. The lighting rate will be described later.

  In order to facilitate understanding, specific numerical values will be exemplified. However, this is virtual, and it is actually necessary to determine control data and a control method by experiment and image evaluation.

  The maximum current that can be passed through the EL display panel is 100 (mA). In the case of white raster display, the total (APL level) is assumed to be 200 (no unit). When the APL level is 200, it is assumed that 200 (mA) flows in the EL display panel when applied to the panel as it is. When the APL level is 0, the current flowing through the EL display panel is 0 (mA). When the APL level is 100, the duty ratio is ½.

  Therefore, when the APL is 100 or more, it is necessary to make the limit 100 (mA) or less. Most simply, when the APL level is 200, the duty ratio is (1/2) × (1/2) = 1/4, and when the APL level is 100, the duty ratio is 1/2. When the APL level is 100 or more and 200 or less, the duty ratio is controlled to be between 1/4 and 1/2. The duty ratio of 1/4 to 1/2 can be realized by controlling the number of gate signal lines 17b to be simultaneously selected by the gate driver circuit 12b on the EL selection side.

  However, if the duty ratio control is performed considering only the APL level, the luminance of the display screen 64 changes according to the average luminance (APL) of the display screen 64 according to the image, and flicker occurs. In order to solve this problem, the APL level to be calculated is held for a period of at least 2 frames, preferably 10 frames, more preferably 60 frames or more, and the APL level is used to calculate the duty ratio by duty ratio control based on the APL level. calculate. In addition, it is preferable to perform duty ratio control by extracting image features such as maximum luminance (MAX), minimum luminance (MIN), luminance distribution state (SGM) of the display screen 64. Needless to say, the above items also apply to the reference current control.

  It is also important to perform black stretching and white stretching by extracting image features. This may be performed in consideration of maximum luminance (MAX), minimum luminance (MIN), luminance distribution state (SGM), and scene change state. That is, it is preferable to correct the total (APL level or lighting rate) in consideration of not only the addition of video data but also the distribution state of the image display. Examples of the circuit configuration include a configuration in which the correction amount of a correction circuit (not shown) of the adder 1133c in FIG. 113 is added.

  In FIG. 118, the horizontal axis represents the lighting rate. The maximum value is 100%. The vertical axis represents the duty ratio. The lighting rate = 100% is the maximum white display state in all pixel rows. When the lighting rate is small, the screen is dark or has a small display (lighting) area. At this time, the duty ratio is increased. Therefore, the luminance of the pixel displaying the image is high. For this reason, the dynamic range of the image is expanded and high-quality display is performed. When the lighting rate is high (the maximum value is 100%), the screen is a bright screen or a wide display (lighting) area. At this time, the duty ratio is reduced. Therefore, the luminance of the pixel displaying the image is low. Therefore, power consumption can be reduced. Since the amount of light emitted from the screen is large, the image does not feel dark.

  In FIG. 118, the duty ratio value reached when the lighting rate is 100% is changed. For example, when the duty ratio is 1/2, 1/2 of the screen is in the image display state. Therefore, the image is bright. When the duty ratio is 1/8, 1/8 of the screen is in the image display state. Therefore, the brightness is 1/4 compared to the duty ratio = 1/2.

  In the drive system of the present invention, the image brightness is controlled by the lighting rate, duty ratio, reference current, data sum, etc., and the dynamic range is expanded. In addition, high contrast display is realized.

  In the liquid crystal display panel, white display and black display are determined by the transmittance from the backlight. Even when a non-display area is generated on the screen as in the driving method of the present invention, the transmittance in black display is constant. On the contrary, when the non-display area is generated, the white display luminance in one frame period is lowered, so that the display contrast is lowered.

  In the EL display panel, black display is a state in which the current flowing through the EL element is zero. Therefore, even when a non-display area is generated on the screen as in the driving method of the present invention, the luminance of black display is zero. When the area of the non-display area is increased, the white display luminance is lowered. However, since the luminance of black display is 0, the contrast is infinite. Therefore, a good image display can be realized.

  In the driving method of the present invention, the number of gradations is maintained over the entire gradation range, and white balance is maintained over the entire gradation range. Further, the luminance change of the screen can be changed nearly 10 times by the duty ratio control. Further, since the change has a linear relationship with the duty ratio, the control is easy. Further, R, G, and B can be changed at the same ratio. Therefore, the white balance is maintained at any duty ratio.

  The relationship between the lighting rate and the duty ratio is preferably set according to the content of the image data, the image display state, and the external environment. Further, it is preferable that the user can set or adjust freely.

  The above switching operation displays the display screen very brightly when the power of a mobile phone, a monitor, etc. is turned on. After a certain period of time, the display brightness is reduced to save power. Use. In order to reduce the display luminance, the duty ratio is reduced or the reference current is reduced. Alternatively, either the duty ratio or the reference current is reduced. The power consumption of the EL display panel can be reduced by reducing the reference current or the duty ratio.

  The above control can also be used as a function for setting the brightness desired by the user. For example, when outdoors, the screen is very bright. This is because the surroundings are bright outdoors and the screen cannot be seen at all. That is, outdoors, the curve a in FIG. 118 is selected. However, if display is continued with high luminance, the EL element deteriorates rapidly. For this reason, when it is very bright, it is configured to return to normal luminance in a short time. For example, normally, the curve of c is selected. Further, in the case of displaying with high brightness, the display brightness can be increased by the user pressing the button.

  Therefore, it is preferable that the user can be switched with a button, can be automatically changed in a setting mode, or can be switched automatically by detecting the brightness of external light. Further, it is preferable that the display brightness is set to 50%, 60%, and 80% and can be set by the user. Further, it is preferable that the duty ratio curve, inclination, etc. are rewritten by an external microcomputer or the like. Further, it is preferable that one can be selected from a plurality of stored duty ratio curves.

  Needless to say, the selection of the duty ratio curve or the like is preferably performed in consideration of one or more of the APL level, maximum luminance (MAX), minimum luminance (MIN), and luminance distribution state (SGM).

  As described above, for example, a is an outdoor curve. c is an indoor curve. b is a curve for an intermediate state between indoor and outdoor. Switching between the curves a, b, and c is performed by the user operating the switch. Alternatively, the brightness of outside light may be detected by a photo sensor and automatically switched. Although the gamma curve is switched, the present invention is not limited to this. It goes without saying that a gamma curve may be generated by calculation.

  The duty ratio in FIG. 118 is a straight line, but is not limited to this. As shown in FIG. 119, a single-point bending curve may be used. That is, the slope of the duty ratio is changed according to the lighting rate. Of course, the duty ratio curve may be a curved line or a multipoint broken curve. Further, the duty ratio curve may be changed in real time depending on the external light or the type of image. The above matters are the same in the reference current change control.

  When it is necessary to reduce the power consumption of the display panel, the c curve in FIG. 119 is selected. The effect of reducing power consumption is exhibited. Although the display brightness decreases, there is no decrease in image display such as the number of gradations. When high display luminance is required, the a curve in FIG. 119 is selected. The image display becomes brighter and the occurrence of flicker is reduced. Although power consumption increases, there is no decrease in image display such as the number of gradations.

  In another embodiment of the present invention, the duty ratio is changed in a range where the lighting rate is 1/10 or more (see FIG. 120). This is because an image with a lighting rate close to 1 is rarely generated, and when the lighting rate is changed to 100 and the duty ratio is changed as shown in FIG. 118, the image display is felt dark. More preferably, the duty ratio is changed in the range where the lighting rate is 8/10 or more.

  Many natural images have a lighting rate of 20% to 40%. Therefore, it is preferable that the duty ratio is large in this range. On the other hand, when the lighting rate is high (60% or more), the power consumption is large and the EL display panel tends to generate heat and deteriorate. Therefore, the duty ratio is controlled to be 1/1 or in the vicinity when the lighting rate is in the range of 20% to 40% or in the vicinity thereof, and the duty ratio is controlled to be smaller than 1/1 when the lighting rate is 60% or in the vicinity thereof. It is preferable.

  In FIG. 120, when the lighting rate is 0.9 or less, the duty ratio is changed from 1/1 to 1/5. Therefore, a dynamic range of 5 times is realized. In FIG. 120, when the lighting rate is 0.9 or more, the duty ratio is 1/5. Therefore, the display luminance is 1/5 of the maximum luminance. A lighting rate of 100% is a white raster display. That is, in white raster display, the display brightness is reduced to 1/5 of the maximum brightness.

  When the lighting rate is 10% or less, the duty ratio is 1/1. 1/10 of the screen is a display area (in the case of a white window or the like). Of course, natural images are images with many dark areas. When the duty ratio is 1/1, since there is no non-lighting area 62, the light emission luminance of the EL element becomes the display luminance of the pixel as it is.

  The lighting rate of 10% is a state where most of the image display is black display and an image is displayed in part. For example, an image display with a lighting rate of 10% or less is an image in which the moon appears in a completely dark night sky (this is a reference image example for explanation. A white window is a 1/10 white window display. ). Setting the duty ratio to 1/1 in this image means that the moon portion is displayed with a luminance that is five times the luminance of the white raster (the luminance at the lighting rate of 100% in FIG. 120). Therefore, an image display with a wide dynamic range can be realized. Since the image is displayed in the 1/10 area, even if the brightness of the 1/10 area is increased 5 times, the increase in power consumption is slight.

  As described above, in the present invention, the duty ratio is 1/1 or relatively large for an image with a low lighting rate. At a duty ratio of 1/1, a current always flows through a pixel that emits light. Therefore, the current consumption is large when viewed from one pixel. However, since there are few pixels emitting light in the EL display panel, there is almost no increase in power consumption when viewed from the entire EL display panel. In the EL display panel, the black portion is completely black (non-light emitting). Therefore, if the maximum luminance can be displayed with a duty ratio of 1/1, the dynamic range can be expanded, and a good and clear image display can be realized.

  On the other hand, in the present invention, in an image with a high lighting rate, the duty ratio is relatively small, such as 1/5. Further, control is performed so that the duty ratio becomes small in accordance with the lighting rate. When the duty ratio is small, intermittent current flows through the light-emitting pixels. Therefore, the current consumption of one pixel is small. In an EL display panel, many pixels emit light, but since current consumption per pixel is small, an increase in power consumption is small when viewed from the entire EL display panel.

  As described above, the driving method of the present invention for controlling the duty ratio with respect to the lighting rate is an optimal driving method for a self-luminous display panel such as an EL display panel. If the duty ratio decreases, the image brightness decreases. However, since the generated light flux is large on the entire screen, the impression that it has become dark cannot be felt.

  As described above, by performing one or both of duty ratio control and reference current control, the contrast ratio of the image can be expanded, the dynamic range can be expanded, and low power consumption can be realized.

  The above control is performed using the lighting rate. As described above, the lighting rate is the magnitude of the current that flows into (flows out) the anode or cathode in normal driving (duty ratio 1/1). As the lighting rate increases, the current at the anode or cathode terminal increases in proportion. The current increases / decreases in proportion to the magnitude of the reference current, and increases / decreases in proportion to the duty ratio. The present invention is characterized in that the duty ratio and the reference current are changed depending on the lighting rate. That is, the duty ratio and the reference current are not fixed. The state is changed to at least a plurality of states according to the display state of the image.

  In an image with a lighting rate close to 0, most pixels are in low gradation display. In terms of a histogram, the majority of data is distributed in the low gradation area of the histogram. In this image display, the image is blacked out and there is no sharpness. Therefore, the dynamic range of the black display part is widened by controlling the gamma curve.

  In the above embodiment, when the lighting rate is 0, the duty ratio is set to 1/1, but the present invention is not limited to this. Needless to say, the duty ratio may be smaller than 1. The duty ratio curve may be a curve. Examples of the curve include a sine curve shape, an arc shape, and a triangular shape.

  When a maximum value is provided for the duty ratio, it is preferable that the maximum value is set at any position within a range of at least a lighting rate of 20% to 50%. This range often appears in image display. Therefore, by making the duty ratio larger than other lighting rate ranges such as 1/1, it is recognized that the image is displayed with high brightness. For example, a control method in which the duty ratio is 1/1 at a lighting rate of 35%, and the duty ratio is 1/2 at a lighting rate of 20% and 60% is exemplified.

  You may control in step shape according to a lighting rate. For example, when the lighting rate is 0% to 20%, the duty ratio is 1/1, and when the lighting rate is greater than 20% and 60% or less, the duty ratio is 1/2 and the lighting rate is When it is greater than 60% and less than or equal to 100%, it refers to a control method in which the duty ratio is ¼.

  As shown in FIG. 117, the duty ratio curve may be changed for red (R), green (G), and blue (B) pixels. In FIG. 117, the slope of the change in the duty ratio of blue (B) is the largest, the slope of the change in the duty ratio of green (G) is the next largest, and the slope of the change in the duty ratio of red (R) is the largest. It is small. If driven as described above, RGB white balance adjustment can be optimized. Of course, one color may be constant (not changed even when the lighting rate changes), and the other two colors may be controlled to change according to the lighting rate.

  The relationship between the lighting rate and the duty ratio is preferably set according to the content of the image data, the image display state, and the external environment. Further, it is preferable that the user can set or adjust freely. Further, it is preferable that the duty ratio, the reference current ratio, etc. can be automatically adjusted by the output from the photo sensor or the temperature sensor. For example, when the ambient temperature (panel temperature) is high, by reducing the duty ratio (such as 1/4), current consumption flowing into the panel can be suppressed, and the self-heating of the panel is reduced. The temperature can be lowered. Therefore, it is possible to prevent the panel from being thermally deteriorated.

  The temperature change may be controlled so that the temperature change is integrated, and when the integrated value exceeds a predetermined value, current suppression means such as duty ratio control is operated. At the time of integration, it is preferable to consider a decrease in panel temperature due to heat radiation from the panel. Therefore, it is not controlled simply by the integral value, but is controlled by subtracting the amount of heat release. The amount of heat release can be easily derived through experiments.

  From the above, the panel temperature can be estimated or predicted by obtaining the sum of the video data, integrating the sum, and subtracting the heat release from the integrated value. As a result of the prediction, when the panel temperature rises or exceeds a specified value, duty ratio control, reference current ratio control, etc. are performed to suppress panel power consumption. Further, when it is predicted that the panel has fallen below the specified temperature due to the suppression, normal duty ratio control, reference current ratio control, and the like are performed.

  When a bright screen and a dark screen are alternately repeated at a high speed, flicker occurs when the duty ratio, the reference current, and the like are changed according to the change. Therefore, when changing from a certain duty ratio to another duty ratio, it is preferable to provide a hysteresis (time delay). For example, if the hysteresis period is 1 sec, the previous duty ratio is maintained even if the screen brightness is bright and dark but is repeated a plurality of times within the 1 sec period. That is, the duty ratio does not change. Needless to say, the above items can also be applied to reference current control and the like. The change may be made different between R, G, and B.

  This hysteresis (time delay) time is called Wait time. Further, the duty ratio before the change is called the pre-change duty ratio, and the duty ratio after the change is called the post-change duty ratio. Although referred to as hysteresis (time delay), the hysteresis includes the meaning of slowly changing. For example, when the duty ratio is changed from 1/1 to 1/2, an example in which the duty ratio is changed slowly over a time of 2 seconds is exemplified (almost, control is this method).

  When the duty ratio before change is small and changes to another duty ratio, flicker is likely to occur due to the change. The state where the duty ratio before change is small is a state where the data sum of the screen is small or a state where there are many black display portions on the screen.

  In particular, when the halftone or lighting rate is around the median, the change is slow. This is probably because the screen is halftone and the visibility is high. Further, in a region where the duty ratio is small, the difference from the change duty ratio tends to increase. Of course, when the difference in duty ratio increases, control is performed using OEV. However, OEV control also has a limit. From the above, when the duty ratio before change is small, it is necessary to lengthen the wait time.

  As described above, the duty ratio control of the present invention changes the wait time in accordance with the duty ratio. When the duty ratio is small, the wait time is lengthened, and when the duty ratio is large, the wait time is shortened. That is, in the driving method that varies at least the duty ratio, the duty ratio before the first change is smaller than the duty ratio before the second change, and the wait time of the first before-change duty ratio is the second The duty ratio is set to be longer than the wait time of the duty ratio before change.

  In the above embodiment, the wait time is controlled or defined based on the duty ratio before change. However, the difference between the pre-change duty ratio and the post-change duty ratio is slight. Therefore, in the above-described embodiment, the duty ratio before change may be read as the duty ratio after change.

  In the above embodiment, the pre-change duty ratio and the post-change duty ratio have been described. Needless to say, when the difference between the pre-change duty ratio and the post-change duty ratio is large, it is necessary to increase the wait time. Needless to say, when the duty ratio difference is large, it is preferable to change the duty ratio to the post-change duty ratio via the intermediate duty ratio.

  The duty ratio control method of the present invention is a driving method that takes a longer wait time when the difference between the pre-change duty ratio and the post-change duty ratio is large. That is, this is a driving method in which the wait time is changed according to the difference in duty ratio. Further, this is a driving method in which the wait time is lengthened when the difference in duty ratio is large. As described above, the wait time or hysteresis means to change slowly. Needless to say, in a broad sense, it also means delaying the start of change.

  The duty ratio method according to the present invention is a driving method characterized in that when the duty ratio difference is large, the duty ratio is changed to the post-change duty ratio via the intermediate duty ratio.

  In the above embodiment, the Wait time with respect to the duty ratio has been described as different for R (red), G (green), and B (blue). However, needless to say, the present invention may change the wait time by R, G, and B. This is because the visibility is different between RGB. By setting the wait time according to the visibility, a better image display can be realized.

  The above embodiment is an embodiment related to duty ratio control. It is preferable to set the wait time for the reference current control.

As described above, in the driving method of the present invention, the duty ratio and the reference current are not changed rapidly. This is because the change state is recognized as flicker if it is suddenly changed. Usually, it is changed with a delay time of 0.2 seconds or more and 10 seconds or less. Needless to say, the above items can also be applied to anode voltage change control, precharge voltage change control, change control based on ambient temperature (to change the duty ratio and reference current depending on the panel temperature), and the like.
When the reference current is small, the display screen 64 is dark, and when the reference current is large, the display screen 64 is bright. That is, when the reference current magnification is small, it can be rephrased as a halftone display state. When the reference current magnification is high, the image display state is high brightness. Therefore, when the reference current magnification is low, the wait time needs to be increased because the visibility to changes is high. On the other hand, when the reference current magnification is high, the wait time may be short because the visibility to the change is low.

  The duty ratio control as described above need not be completed in one frame or one field. The duty ratio control may be performed in a period of several fields (several frames). In this case, the duty ratio is an average value of several fields (several frames) as the duty ratio. Even when the duty ratio control is performed in several fields (several frames), the number field (several frames) period is preferably 6 fields (six frames) or less. This is because flicker may occur when the value exceeds this value. Also, the number field (several frames) is not an integer, and may be 2.5 frames (2.5 fields). That is, it is not limited to a field (frame) unit.

  The above items can be applied not only to the current driving method but also to the voltage driving method. Needless to say, the present invention can be applied to a general self-luminous display device.

  The duty ratio pattern is changed between the moving image and the still image. When the duty ratio pattern is suddenly changed, an image change may be recognized. Also, flicker may occur. This problem occurs due to the difference between the duty ratio of the moving image and the duty ratio of the still image. In the moving image, a duty ratio pattern in which the non-display area 62 is inserted at once is used. The still image uses a duty ratio pattern in which the non-display area 62 is inserted in a distributed manner. The ratio of the area of the non-display area 62 / the screen area 64 is the duty ratio. However, even if the duty ratio is the same, human visibility varies depending on the dispersion state of the non-display area 62. This is thought to be due to the dependence on human video response.

  In the intermediate moving image, the non-display area 62 is in a distributed state between the moving image distributed state and the still image distributed state. Note that a plurality of intermediate moving images may be prepared, and selected from a plurality of intermediate moving images corresponding to the moving image state or the still image state before the change. Examples of the plurality of intermediate moving image states include a configuration in which the non-display area is distributed in a manner similar to the moving image display, and the non-display area 62 is divided into three parts, for example. On the contrary, a state in which the non-display area is dispersed in a large number like a still image is illustrated.

  Some still images are bright and some are dark. The same applies to videos. Therefore, it is only necessary to determine which intermediate moving image state is to be changed according to the state before the change. In some cases, a moving image may be transferred to a still image without going through an intermediate moving image. You may transfer from a still image to a moving image without going through an intermediate moving image. For example, an image whose display screen 64 has a low luminance does not feel strange even if the moving image display and the still image display are moved directly. Further, the display state may be shifted via a plurality of intermediate moving image displays. For example, it is possible to shift from the duty ratio state of the moving image display to the duty ratio state of the intermediate moving image display 1, and further shift to the duty ratio state of the intermediate moving image display 2 and then shift to the duty ratio state of the still image display.

  When moving from the movie display to the still image display, the intermediate movie state is passed. Also, the display is shifted from the still image display to the moving image display via the intermediate moving image display. It is preferable to set a wait time for the transition time of each state. Further, when shifting from a still image to a moving image or an intermediate moving image, the non-display area 62 changes slowly.

  FRC (frame rate control) and moving image display are related. The number of frames used in FRC (for example, in 4FRC, 4 frames are used to make gradation display for 2 bits (4 times the number of gradations). In 16FRC, 16 frames are used for gradation of 4 bits. However, if nFRC (n is an integer of 2 or more) n (number of frames) increases, there is no problem with still images, but moving image performance deteriorates with moving images. Therefore, it is desirable that n of the NFRC is smaller in moving image display, and more than a certain number of gradations is not necessary in moving image display, and in most cases, 256 gradations or less is sufficient, whereas in still images, A large number of gradations are necessary.

  For example, a difference between pixel data at the same position between the first frame and the next second frame is obtained, and if the difference value is greater than or equal to a certain value, it is determined as a moving image pixel. If the number of pixels in one panel is 100,000 pixels, the ratio of moving picture pixels is 25% if the ratio of pixels determined to be moving picture pixels by the difference calculation is 25,000 pixels.

  The ratio of moving picture pixels is 0% to 25% or less, and it is determined that the picture is a complete still picture or close to it, and 16FRC (n = 16) is set. Further, it is determined that the moving image pixel ratio is 25% to 50% or less and is an intermediate image close to a moving image, and is set to 12 FRC (n = 12). In addition, the ratio of moving image pixels is 50% to 75% or less, and it is determined as an intermediate image close to a still image, and is set to 8FRC (n = 8). The ratio of moving picture pixels is 75% or more, and it is determined that it is a complete moving picture or close to it, and 1 FRC (n = 1, that is, FRC control is not performed).

  As described above, it is possible to realize a more optimal image display by changing the FRC based on the content of the display image. The FRC is changed by a controller circuit (IC) 722.

  It is preferable to change the FRC when the scene of the image changes suddenly. The state in which the image scene changes suddenly is exemplified when the screen changes to commercial, when the channel is switched, or when the drama scene changes. It should be noted that when a scene changes suddenly, the peak current suppression and duty ratio control of the present invention are also described.

  Therefore, if the number of FRCs of nFRC is changed in real time when the ratio of the moving image is changed, the screen is in a flicker-like display state. Therefore, it is preferable to change the number of FRCs when a scene changes suddenly.

  The application of the precharge voltage is preferably linked to the lighting rate or the duty ratio. It is preferable not to apply the precharge voltage to a place where it is not necessary. This is because a decrease in brightness of white display may occur. Therefore, it is preferable that application of the precharge voltage is limited.

  The precharge drive is performed in order to eliminate the phenomenon of crosstalk under the white display portion, particularly in the current drive method. Therefore, this crosstalk is conspicuous in an image having a lot of black display portions on the screen and partly displaying white. In terms of the lighting rate, precharge is necessary in a region where the lighting rate is small. This is because if the entire display screen 64 is white, it will not be visually recognized even if crosstalk occurs. Therefore, it is not necessary to perform precharge driving.

  The present invention reduces the duty ratio when the lighting rate is high (the display screen 64 has many white display portions as a whole). That is, n of the duty ratio 1 / n is increased. When the lighting rate is low (the display screen 64 has a large number of black display portions as a whole), the duty ratio is increased. That is, the duty ratio approaches 1/1. Therefore, there is a correlation between the duty ratio and the lighting rate. Naturally, the lighting rate (lighting rate) is obtained from the video data, and the duty ratio control is performed from the lighting rate. The lighting rate is also related to the precharge control.

  As shown in FIG. 126 (a), it is assumed that there is a relationship between the duty ratio and the lighting rate (%). FIG. 126 (b) shows the precharge on / off state. In FIG. 126 (b), precharge driving is set at a duty ratio of 20% or less. However, even if the precharge drive is used, the precharge drive of the present invention includes an all precharge mode, an adaptive precharge mode, a 0 grayscale precharge mode, and a selective grayscale precharge mode. Therefore, in FIG. 126 (b), the point is that the precharge drive is set to be performed, and the drive state differs depending on which precharge is performed. What is important is to change whether or not to perform precharge driving depending on the duty ratio or the lighting rate.

  There is also a correlation between the duty ratio or lighting rate (%) and gamma control. FIG. 127 is an explanatory diagram thereof. In an image with a high lighting rate, there are many images with high overall brightness. Therefore, the image becomes whitish. Therefore, it is preferable to increase the coefficient of the gamma constant (usually the coefficient is 2.2) to increase the area of the black gradation region. By increasing the area of the black gradation area, the image is sharpened.

  FIG. 114 shows the duty ratio with respect to the lighting rate. In the control of FIG. 114, when the lighting rate of the display image is close to 100%, the duty ratio is set to almost 1/4. The gradation is proportional to the luminance. In an image with a high lighting rate, the gradation display of the image is crushed and the image has no resolution, so it is necessary to change the gamma curve. That is, it is necessary to increase the coefficient, which is a multiplier of the gamma curve, to make the gamma curve steep.

  From the above, in the present invention, the coefficient of the gamma curve is changed according to the lighting rate or the duty ratio. FIG. 127 is an explanatory diagram thereof.

The present invention reduces the duty ratio when the lighting rate is high (the entire display screen 64 has many white display portions). That is, n of the duty ratio 1 / n is increased. When the lighting rate is low (the display screen 64 has a large number of black display portions as a whole), the duty ratio is increased. That is, the duty ratio approaches 1/1. Therefore, there is a correlation between the duty ratio and the lighting rate. Naturally, the lighting rate (lighting rate) is obtained from the video data, and the duty ratio control is performed from the lighting rate.
As shown in FIG. 127A, it is assumed that there is a relationship between the duty ratio and the lighting rate (%). In the graph of FIG. 127 (b), the vertical axis indicates the coefficient of the gamma curve. In FIG. 127B, the gamma curve coefficient is set to be large when the duty ratio is 70% or more. That is, the gradation expression is increased in the high gradation region so that the gamma curve becomes steep. Therefore, the whiteout image is improved.

  There is a close relationship between duty ratio control and power supply capacity. The power supply size increases as the maximum power supply capacity increases. In particular, when the display device is mobile, a large power source becomes a serious problem. EL has a proportional relationship between current and luminance. In black display, no current flows. The maximum current flows in the white raster display. Therefore, the change in current due to the image is large. When the change in current is large, the power supply size increases and the power consumption increases.

  In the present invention, when the lighting rate is high, 1 / n of duty ratio control is increased to reduce current consumption (power consumption). Conversely, when the lighting rate is low, the duty ratio is set to 1/1 = 1 or close to 1/1 so that the maximum luminance is displayed. This control method will be described below.

  First, the relationship between the lighting rate (lighting rate) and the duty ratio is illustrated in FIG. It is assumed that the lighting rate is converted by the current flowing through the panel as described above. This is because, in the EL display panel, the light emission efficiency of B is poor, and thus when the display of the sea is displayed, the power consumption increases at a stretch. Therefore, the maximum value is the maximum value of the power supply capacity. The data sum is not a simple addition value of video data, but video data converted into current consumption. Therefore, the lighting rate is also obtained from the current used for each image with respect to the maximum current.

  FIG. 114 shows an example in which the duty ratio is 1/1 when the lighting rate is 0%, and the minimum duty ratio is 1/4 when the lighting rate is 100%. FIG. 115 shows the result of multiplying the power and the lighting rate. If the lighting rate is 0 to 100% in FIG. 114 and the duty ratio is constantly 1/1, a curve indicated by a in FIG. 115 is obtained. The vertical axis in FIG. 115 is the ratio of power used to the power supply capacity (power ratio). That is, in the curve a, the lighting rate and the power consumption are in a proportional relationship. Therefore, when the lighting rate is 0%, the power consumption is 0 (power ratio 0), and when the lighting rate is 100%, the power consumption is 100 (power ratio 100%).

  A curve b in FIG. 115 is an example in which power limitation is performed with the duty ratio curve in FIG. 114. Since the duty ratio is 1/4 when the lighting rate is 100%, the power ratio is 25% of 1/4 compared to the curve a. The curve b is operating in a range smaller than the electric power 1/3. Therefore, when duty ratio control is performed as shown in FIG. 114, 1/3 of the power supply capacity is sufficient as compared with the conventional case (curve a). That is, in the present invention, the power supply size can be reduced as compared with the conventional one.

  If the state of high lighting rate continues in the prior art (curve a), the current flowing through the panel is large, and the panel is deteriorated due to heat generation. However, in the present invention in which the duty ratio control is performed, an average current flows through the panel regardless of the lighting rate, as can be seen from the curve b. Therefore, there is little heat generation and the panel does not deteriorate.

  In the duty ratio curve of FIG. 114, an example in which the lowest duty ratio is halved is a curve c. Further, the curve d is an example in which the minimum duty ratio is 1/3. Similarly, the example is curve e with a minimum duty ratio of 1/8.

  In FIG. 114, the duty ratio curve is a straight line. However, the duty ratio curve can be generated by a wide variety of straight lines or curves. The duty ratio curve changes the power ratio with respect to the lighting rate as indicated by b, c, d, and e in FIG. As described above, the duty ratio curve or the reference current ratio curve is preferably configured to be variable by programming such as a microcomputer or external control.

  The duty ratio control curve allows the user to freely switch the duty ratio curve with a button according to the external environment. In a bright external environment, a curve with a large duty ratio is selected. When the external environment is dark, a curve with a small duty ratio is selected in order to suppress power more. Further, it is preferable that the duty ratio control curve is configured to be freely changed.

  As shown in FIG. 116, the duty ratio is decreased in the low lighting rate region (lighting rate of 20% or less in FIG. 116) (FIG. 116 (a)), and the reference current ratio is increased as the duty ratio decreases. (FIG. 116 (b)) may be used. As described above, by performing the duty ratio control and the reference current ratio control at the same time, the luminance does not change as illustrated in FIG. At a low lighting rate, insufficient writing of the program current in the low gradation region is conspicuous. However, since the program current can be increased in proportion to the reference current by increasing the reference current in the low lighting rate region as shown in FIG. 116, there is no shortage of current writing. Moreover, since the luminance is constant, a good image display can be realized.

  In FIG. 116, in the region where the lighting rate is high (40% or more in FIG. 116), the duty ratio is decreased, but the reference current ratio remains constant at 1. Therefore, since the luminance decreases as the duty ratio decreases, the power consumption of the panel can be controlled (basically reduced). In the driving method in which the maximum duty ratio is 1/1, it is preferable to insert the non-display area 62 all at once.

  The relationship between the reference current ratio, the duty ratio, and the lighting rate is preferably kept constant as will be described below. This is because the increase in flicker generation or the panel deterioration due to self-heating is accelerated. According to the result of the study, it is preferable that the duty ratio × reference current ratio (A) is 0.7 or more and 1.4 or less in a region where the lighting rate is 30% or less. More preferably, it is 0.8 or more and 1.2 or less. In the region where the lighting rate is 80% or less, it is preferable to control or set the duty ratio × reference current ratio (A) to be 0.1 or more and 0.8 or less. Further, it is preferable to control or set so as to be 0.2 or more and 0.6 or less.

  Alternatively, when the duty ratio × reference current ratio when the lighting rate is 50% is A, the duty ratio × reference current ratio × A is set to 0.7 or more and 1.4 or less in the region where the lighting rate is 30% or less. Or it is preferable to control. More preferably, it is set or controlled at 0.8 or more and 1.2 or less. Further, in a region where the lighting rate is 80% or less, it is preferable that duty ratio × reference current ratio × A is set or controlled to be 0.1 or more and 0.8 or less. More preferably, it is set or controlled to be 0.2 or more and 0.6 or less.

  In the present invention, the first lighting rate (the anode current of the anode terminal, the ratio to the sum of the data may be described previously) or the lighting rate range (the anode current range of the anode terminal, the range of the ratio to the sum of the data) In the first FRC, the lighting rate, the current flowing through the anode (cathode) terminal, the reference current, the duty ratio, the panel temperature, the product of the reference current ratio and the duty ratio, or the like. These are changed as a combination.

  Further, in the second lighting rate (which may be the anode current of the anode terminal) or the lighting rate range (which may be the anode current range of the anode terminal), the current flowing through the second FRC, the lighting rate, or the anode (cathode) terminal. Alternatively, the reference current or the duty ratio, the panel temperature, the product of the reference current ratio and the duty ratio, or a combination thereof is changed. Or, depending on the lighting rate (which may be the anode current of the anode terminal) or the lighting rate range (which may be the anode current range of the anode terminal) (adapted), it flows to the FRC or the lighting rate or the anode (cathode) terminal. The current, the reference current, the duty ratio, the panel temperature, the product of the reference current ratio and the duty ratio, or a combination thereof is changed. Also, when changing, the hysteresis is changed, delayed or changed slowly.

  FIG. 122 shows a relationship between the lighting rate and the anode voltage as an example. Vdd + 2 and Vdd + 4 do not indicate absolute voltages, but are relatively illustrated for ease of explanation.

  In FIG. 122, the reference current (program current) is increased when the lighting rate is 25% or less. In this state, since the anode voltage needs to be increased, the anode voltage is increased as the reference current increases. The reference current is increased when the lighting rate is 75% or more. As the reference current increases, the anode voltage increases.

  FIG. 122 shows a relationship between the lighting rate and the anode voltage as an example. The present invention is not limited to this. For example, it goes without saying that the potential difference between the anode terminal voltage and the cathode terminal voltage may be changed according to the lighting rate or the like. For example, if the anode terminal voltage is 6 (V) and the cathode terminal voltage is −9 (V), the potential difference is 6 − (− 9) = 15 (V). That is, the absolute value of the anode voltage and the cathode voltage is changed according to the lighting rate, the reference current, the current flowing through the anode terminal, or the like.

  In FIG. 123, the reference current (program current) is changed stepwise according to the lighting rate. As the reference current changes, the anode voltage also changes.

  The anode voltage with respect to the magnitude of the program current (the magnitude of the reference current) may be changed as shown in FIG. A solid line a in FIG. 124 is an example in which the anode voltage is changed in proportion to the program current (reference current). A dotted line b in FIG. 124 is an embodiment in which the anode voltage is changed when the current is equal to or higher than a predetermined program current (reference current). In the dotted line b, since the change point of the anode voltage with respect to the reference current is one point, the circuit configuration is easy.

  In the above embodiment, the anode voltage is changed according to the magnitude of the reference current or the program current. However, a change in the magnitude of the reference current or the program current is synonymous with changing the potential of the source signal line 18. In the case where the driving transistor 11a shown in FIG. 1 is a P channel, increasing the program current Iw or the reference current is to lower the potential of the source signal line 18 (close to the GND potential). Conversely, to reduce the program current Iw or the reference current is to increase the potential of the source signal line 18 (closer to the anode Vdd).

  From the above, control may be performed as shown in FIG. That is, when the potential of the source signal line 18 is 0 (GND), the anode voltage is set highest (the reference current and the program current are the maximum values). When the potential of the source signal line 18 is the Vdd potential, the anode voltage is made the lowest (the reference current and the program current are the minimum values). By configuring or controlling as described above, the period during which a high voltage is applied to the EL element 15 can be shortened, and the life of the EL element 15 can be extended.

  The duty ratio or the like may be changed according to the panel or the ambient temperature of the panel. FIG. 121 shows an example. In FIG. 121, the solid line indicates the case where the panel temperature is 40 ° C. or lower. In the solid line, when the lighting rate is 40% or less, the duty ratio is 1/1, and when it is 40% or more, the duty ratio is decreased. In the dotted line, when the lighting rate is 20% or less, the duty ratio is halved, and when the lighting rate is 20% or more, the duty ratio is decreased. A curve between a dotted line and a solid line is drawn between 40 ° C and 60 ° C.

  FIG. 128 is a configuration diagram of a power supply circuit of a display device of the present invention in another embodiment. An output voltage Vin from the battery or the DC power supply is applied to the booster circuit 1281a and the voltage inverting circuit 1282. The booster circuit 1281 is exemplified by a DCDC converter circuit and a charge pump circuit. The DCDC converter circuit includes a switching element and a coil. The DC voltage Vin voltage is converted into a rectangular wave by the switching element, and the voltage is boosted by the resonance action of the coil. The boosted voltage is smoothed by the capacitor of the booster circuit 1281a to obtain the anode voltage Vdd. On the other hand, the voltage Vin input to the voltage inverting circuit 1282 is inverted in polarity. The voltage whose polarity is inverted is input to the booster circuit 1281b and boosted to become the cathode voltage Vss.

   In FIG. 128 and the like, the voltage inverting circuit 1282 and the booster circuit 1281b are illustrated as separate blocks. However, the present invention is not limited to this, and the voltage inverting circuit 1282 and the booster circuit 1281b have one circuit configuration (one block). Needless to say, it may be produced or configured. As described above, the present invention generates the positive voltage Vdd and the negative voltage Vss mainly by two coils. The voltage inverting circuit 1282 and the booster circuit 1281 operate with reference to the ground potential (GND). The same applies to Vin. The ground potential (GND) is also the GND of the source driver circuit (IC) 14.

  For ease of explanation, the voltage Vin in the embodiment of the present invention is set to 2.7 (V) to 4.5 (V). The anode voltage Vdd is 6 (V), and the cathode voltage Vss is −9 (V).

  FIG. 129 shows a relationship between output voltages of the power supply circuit and the like of the display device of the present invention. In the present invention, the ground potential (GND) of the source driver circuit (IC) 14 and the ground potential (GND) of the booster circuit 1281 are common. The power supply voltage Vcc of the source driver circuit (IC) 14 is generated (generated) by regulating the Vdd voltage, or is generated (generated) from the Vin voltage by a DCDC converter configured separately.

  In the EL display device, as described in FIG. 1, the current Ie flows from the anode voltage Vdd to the cathode voltage Vss. Further, the current flowing through the anode terminal and the current flowing through the cathode terminal are characterized by being equal. That is, there is a relationship of Ie = Idd = Iss. This is a characteristic feature of EL display devices.

  In the embodiment of FIG. 129, the absolute value of the anode voltage Vdd indicated by A and the absolute value of the cathode voltage Vss indicated by B are configured such that A <B. Specifically, the anode voltage Vdd is 6 (V), and the cathode voltage Vss is −9 (V). That is, 1.5 × A = B.

  The present invention includes a power generation capacity (referred to as anode power capacity = anode voltage Vdd × anode current Idd) of the boost circuit 128a and a power generation capacity (referred to as cathode power capacity = cathode voltage Vdd × cathode) of the boost circuit 128b of FIG. The current Idd) is configured (produced) substantially the same. By setting the anode power capacity = the cathode power capacity, the power module size can be reduced. In particular, the effect of being able to design the cathode power source capacity to be smaller than the required capacity is great. Further, since the coil L used in the booster circuit 128a and the coil L used in the booster circuit 128b can be the same, the cost can be reduced.

  If 1.5 × A = B, Idd = Iss, and anode power source capacity = cathode power source capacity, then cathode current Iss = (1 / 1.5) × anode current Idd. As described above, the EL display device has a relationship of Idd = Iss. Therefore, in the configuration of FIG. 129, when the anode power source capacity is fully used, the cathode power source capacity becomes insufficient. If 1.5 × A = B, about 50% of the cathode power supply capacity is insufficient with respect to the required power supply capacity. Although the anode current Idd and the cathode current Iss are described with reference to FIG. 1, Idd and Iss are not the meaning of the current for each pixel in the following specification, but the current flowing into the entire display region 64. It is. In other words, the current changes corresponding to the lighting rate.

  In the present invention, the cathode power supply capacity is configured not to output more than a specified value. Therefore, when the cathode power source capacity becomes insufficient, the cathode voltage Vss rises, and is controlled at the specified power source capacity. Even if the cathode voltage Vss increases (for example, −9 V → −6 V), the Iss current maintains the maximum current. The cathode current Iss can be increased by the amount of increase in the cathode voltage. That is, the maximum value of the cathode power source capacity standard is maintained. Further, the relationship of Idd = Iss is maintained. In other words, the booster circuit 1281b constituting the cathode power source capacity is controlled so as to increase the cathode voltage Vss and not to exceed the upper limit value of the cathode power source capacity so as to maintain the relationship of Idd = Iss.

  In FIG. 128 and the like, Idd and Iss are DC currents, but in the booster circuit 1281, a rectangular wave or a triangular wave is generated and an AC operation is performed. In the present invention, the cathode power source capacity or the anode power source capacity is controlled so as not to exceed a certain capacity. However, in order not to exceed a certain capacity, it is necessary to consider not the DC level but the maximum value of a rectangular wave or a triangular wave. This is because the maximum voltage is defined by the IC breakdown voltage in the booster circuit 1281.

  128 and 129, Idd = Iss and A <B. Therefore, in the conventional example, the power generation capacity (cathode voltage Vss × cathode current Iss) of the booster circuit 128b is larger than the power generation capacity (anode voltage Vdd × anode current Idd) of the booster circuit 128a.

  In the present invention, A <B, and the power generation capacity of the booster circuit 128b corresponding to B is made smaller than the originally required power capacity. Therefore, Idd = Iss is maintained, and when Iss becomes larger than the power generation capacity of the booster circuit 128b, the cathode voltage Vss is increased to maintain the specified upper limit value of the power capacity.

  As described above, even when the cathode power source capacity is made smaller than the specified value and the cathode voltage Vss is increased, the display image of the display screen 64 is deteriorated (for example, flicker occurs or the luminance is visually recognized). Does not occur). The present invention takes advantage of these EL display panel features.

  In the present invention, as shown in FIG. 1, the driving transistor 11a is constituted (formed) by a P-channel transistor. The operation starting point of the driving transistor 11a is the anode voltage Vdd. Further, the Vdd voltage is also a starting voltage when viewed from the source driver circuit (IC) 14. That is, when the potential of the source signal line 18 is the Vdd voltage, no current flows through the EL element 15. When the source driver circuit (IC) 14 operates and the program current Iw flows from the Vdd voltage to the source signal line 18, the potential of the source signal line 18 decreases. As the potential of the source signal line 18 moves away from Vdd, the current flowing through the EL element 15 increases. From the above, it is necessary to keep the Vdd voltage stably at a predetermined value as the starting voltage.

  On the other hand, the cathode voltage Vss is not a starting voltage. The potential difference between the Vdd voltage and the Vss voltage only affects the saturation voltage of the EL element 15. Therefore, even if the Vss voltage changes, the image display is hardly affected. The present invention is a driving method or driving circuit or driving method for maintaining the cathode voltage Vss at a specified value when the Iss current is small and increasing the cathode voltage when the Iss current is large.

  When the Iss current is large, the lighting rate is high. Image display with a high lighting rate is an image display state in which white display (high luminance display) occupies a high ratio on the screen. In such an image display state, even if the luminance is somewhat lowered or display unevenness occurs, it is not visually recognized. When the lighting rate is low, the cathode voltage is maintained at a specified value, and of course there is no image display deterioration.

  As described above, according to the present invention, the driving transistor 11a of the pixel 16 is configured by the P channel, and the source driver circuit (IC) 14 operates in the sink current mode (the unit transistor 224 of the source driver circuit (IC) 14 is operated). The cathode power supply capacity is smaller than the specified value power supply capacity (originally required power supply capacity). To make it small, it is preferable to be in the range of 10% to 60%. If it is smaller than 10%, it is difficult to obtain the cost merit and the power size merit. If it is larger than 60%, when the lighting rate is slightly increased, the cathode voltage rises and the image display is affected.

  In particular, the present invention relating to the cathode power supply capacity and the like exhibits a synergistic effect when used in combination with duty ratio control and reference current ratio control. For example, duty ratio control is a method of controlling the lighting rate by processing such as addition.

  For example, consider an example in which an image display (scene) with a high lighting rate suddenly changes in an image display with a low lighting rate near a duty ratio of 1/1. In this case, an operation for suppressing the peak current is performed by reducing the duty ratio (close to 0 such as ¼). When the duty ratio is suddenly changed from 1/1 to 1/4, flicker occurs. In order to suppress the occurrence of this flicker, the duty ratio is slowly changed over several frames or several tens of frames. However, if the duty ratio is changed slowly, a current exceeding the specified value of the power supply capacity may flow during the change period. The period in which the duty ratio is suddenly changed is a sudden change of the image scene, and the chance of occurrence is extremely small.

  In order to cope with a sudden change in the image scene, it is inefficient to produce a large cathode power source capacity. The present invention is configured to increase the Vss voltage and maintain the cathode power supply capacity below a specified value for a large Iss current that is generated when the image scene changes suddenly. Therefore, the use efficiency of the power source is high. In addition, both the booster circuits 1281a and 1281b are used with relatively high power. Therefore, a high efficiency design can be realized by setting a portion where the maximum efficiency is exhibited in the booster circuit 128 at a relatively high power.

  When duty ratio control is performed, the Idd current with respect to the lighting rate changes. For example, in a driving method in which control is performed so that the duty ratio is 1/4 when the lighting rate is 100%, Idd is 1/4 as compared with the conventional driving method where the lighting rate is 100% and the duty ratio is 1/1. The power ratio indicates the change rate of the anode current.

  Needless to say, the above items are not limited to the current driving method, and can be applied to a pixel structure of a voltage driving method, a display panel, a display device, or the like. In addition, matters relating to the power supply configuration of the booster circuit and the like of the present invention can be combined with other matters of the present invention. For example, the reference current, the duty ratio, the precharge voltage (synonymous with or similar to the program voltage), the gate signal line voltage (Vgh, etc.) depending on image (video) data, lighting rate, current flowing through the anode (cathode) terminal, panel temperature, etc. Vgl), gamma curve, etc. may be changed or linked or combined with adjustment. Further, it goes without saying that image (video) data, lighting rate, current flowing through the anode (cathode) terminal, change rate or change in panel temperature may be predicted or predicted, and adjusted, changed, variable, or controlled.

  The above embodiment is a case where the driving transistor 11a is a P-channel transistor. However, the present invention is not limited to this. For example, the present invention can be applied even when the driving transistor 11a is an N channel. When the driving transistor 11a is N-channel, the operation starting point of the driving transistor 11a is the cathode voltage Vss. The Vss voltage is almost always the starting voltage even when viewed from the source driver circuit (IC) 14. That is, no current flows through the EL element 15 when the potential of the source signal line 18 is the Vss voltage. When the source driver circuit (IC) 14 operates and the program current Iw flows from the Vss voltage to the source signal line 18, the potential of the source signal line 18 rises. As the potential of the source signal line 18 moves away from Vdd, the current flowing through the EL element 15 increases. From the above, it is necessary to keep the Vss voltage stable at a predetermined value as the starting voltage.

  On the other hand, when the driving transistor 11a is an N-channel transistor, the anode voltage Vdd is not a starting voltage. The potential difference between the Vdd voltage and the Vss voltage only affects the saturation voltage of the EL element 15. Therefore, even if the Vdd voltage changes, the image display is hardly affected. The present invention is a driving method or driving circuit or driving method that maintains the anode voltage Vdd at a specified value when the Idd = Iss current is small and reduces the anode voltage when the Idd current is large.

  That is, according to the present invention, at least one of the anode power supply capacity and the cathode power supply capacity is formed (configured) smaller than a specified value (current flowing through the maximum current used by the display panel × anode voltage or cathode voltage). Then, when the Idd or Iss current flows at a predetermined value or more, the driving method or driving device or driving method changes at least one of the cathode voltage and the anode voltage. Further, it is particularly preferable to combine duty ratio control or reference current control.

  In the present invention, one of the anode voltage and the cathode voltage with respect to the GND voltage is increased, and the output voltage (anode voltage or cathode voltage) of the larger power capacity (anode power capacity or cathode power capacity) is set to the lighting rate or The driving method, the driving method, or the driving device is changed in accordance with the magnitude of the lighting rate, the predetermined lighting rate range, or the lighting rate change. It is particularly preferable to combine duty ratio control or reference current control.

  The present invention provides a driving method, driving method or driving apparatus for changing the cathode voltage in accordance with the magnitude of the lighting rate, the change in the lighting rate, or the amount of change in the lighting rate when the pixel driving transistor is constituted by a P channel. It is. Further, according to the present invention, when the pixel driving transistor is composed of N channels, the anode voltage is changed according to the magnitude of the lighting rate, the change in the lighting rate, or the amount of change in the lighting rate. It is a drive device. The above items are particularly preferably combined with duty ratio control or reference current control.

  In the above embodiments, it is needless to say that the change in the cathode voltage or the anode voltage is preferably changed or changed slowly with a hysteresis (with a delay time).

  The cathode current is preferably configured to increase according to the lighting rate. In the present invention, as a result of investigation, it is preferable that the cathode voltage be lowered in a range where the lighting rate ranges from 30% to 80%. It is preferable that the cathode voltage be reduced when the lighting rate is in the range of 30% to 80%. More preferably, the power supply capacity of the booster circuit 1281b is preferably configured (driven) so as to lower the cathode voltage at 40% to 70% of the lighting rate 100%. That is, in the method of the present invention, the power supply capacity of the booster circuit 1281b does not need a power supply capacity with a lighting rate of 100%, and can be a capacity size of about 50%. Therefore, low cost and downsizing of the power supply size can be realized. Note that the relationship between the inductance L1 (μ Henry) of the coil used in the booster circuit 1281a and the inductance L2 (μ Henry) of the coil used in the booster circuit 1281b is L2 = L1 × ± 1.2 (depending on accuracy) It is preferable to set it to exclude variation, that is, comparison of type values. More preferably, it is preferable to set L2 = L1 × ± 1.1. The characteristics are stable and the mounting area can be reduced. Also, cost reduction can be realized.

  The present invention described above exhibits a great effect when used in mobile devices (DVC, DSC, DVD TV, portable TV, mobile phone, etc.) whose power supply capacity is limited.

  128 and 129, the cathode voltage is changed according to the lighting rate. The cathode voltage is assumed to change automatically from the power supply capacity, but may be changed intentionally. That is, changing the cathode voltage or the like of the present invention includes both the concepts of automatic control and manual control.

  It is preferable that the maximum value of the cathode current Iss or the anode current Idd is configured to be variable depending on the setting. The variable can be easily realized because a limiter function is provided in the switching element of the booster circuit 1281 so that one can be set from a plurality of limiter values.

  FIG. 130 shows an embodiment in which the cathode voltage is changed in accordance with the lighting rate. In FIG. 130, the example of the solid line changes the cathode voltage linearly between the first lighting rate (20% as an example in FIG. 130) and the second lighting rate (80% as an example in FIG. 130). As the lighting rate increases, the cathode voltage increases. In this range, the cathode current Iss increases the cathode current Iss as much as the cathode voltage increases. One anode current Idd has an anode voltage magnitude A (see FIG. 129) smaller than a cathode voltage magnitude B. If the anode power source capacity = the cathode power source capacity, the cathode voltage increases and the anode voltage does not decrease until A = B. The anode current Idd and the cathode current Iss are kept the same.

  In the example of the solid line in FIG. 130, the cathode voltage is kept constant when the lighting rate is 80% or more. This is because, as described above, unless a certain limit is set for the increase in the cathode voltage, the image display will break down. Since the cathode voltage Vss is controlled to be constant when the lighting rate is 80% or more, the cathode current Idd is kept constant when the lighting rate is in the range of 80% to 100%. Therefore, there is no increase in the total light speed generated from the display panel (the screen brightness does not change). However, the above description assumes that the booster circuit 1281b operates at the maximum power supply capacity when the lighting rate is 80% or more. Of course, the cathode current Iss increases as the lighting rate increases if there is a margin in power supply capacity even when the lighting rate is 80% or more.

  In the solid line in FIG. 130, the cathode voltage is kept constant even when the lighting rate is 20% or less. This is because the IC withstand voltage used in the booster circuit 1281b exceeds the upper limit unless a certain limit is set for the rise of the cathode voltage as described above. Since the cathode voltage Vss is controlled to be constant when the lighting rate is 20% or less, the cathode current Idd decreases as the lighting rate decreases when the lighting rate ranges from 0% to 20%.

  The dotted line in FIG. 130 is an example in which the cathode voltage is linearly changed according to the lighting rate. The lighting rate is high, that is, the cathode voltage increases as the Idd current increases. At a lighting rate of 100%, the cathode voltage rises to -5V, but there is no deterioration in image quality. Further, the lighting rate of normal video display is 20% to 40%. A lighting rate of 80% or more hardly occurs. Therefore, even if image quality deterioration occurs in an area where the lighting rate is high, it is extremely rare and is not visually recognized. The present invention also makes good use of the feature that the occurrence of a high lighting rate in video display is rare. In the present invention, duty ratio control is performed, and the anode current Idd is suppressed in the high lighting rate region. Therefore, the power supply capacity is reduced. Therefore, even if the lighting rate is high, there is almost no situation where the cathode voltage is raised.

  Increasing the cathode voltage occurs when the image display has a low lighting rate, and when the duty ratio is 1/1 or close to it, the video display scene changes suddenly and the lighting rate is high. This is the case. Of course, if the lighting rate is increased, the duty ratio is lowered (for example, close to ¼), and after a certain period of time, the state shifts to a high lighting rate and low duty ratio state. Therefore, the cathode voltage drops to a normal voltage. From the above, it is very rare that a driving state in which the cathode voltage is raised occurs.

  According to the present invention, the power supply capacity is reduced, and the rarely generated Idd current increase state raises the cathode voltage and suppresses the deterioration of the image display. The above is a configuration unique to a self-luminous display device such as an EL display device and is extremely effective.

  Depending on the temperature of the display panel, the change in the cathode voltage with respect to the lighting rate may be varied or changed. FIG. 131 shows an example thereof. As shown in FIG. 131, when the display panel is as high as 50 ° C., the cathode voltage is held at a constant value from a relatively low lighting rate state with a lighting rate of 60% or more. Since it is held at a constant value, the Idd current does not increase in a state where the lighting rate is higher than 60%. That is, the Idd current limiter function works. Therefore, heat generation at the display panel is suppressed. This is because when the display panel is in a high temperature state and further heat is generated, deterioration of the display panel is promoted. It goes without saying that heat generation can also be suppressed by raising the cathode voltage and reducing it to a voltage applied to the EL element 15.

  When the temperature of the display panel is as low as 10 ° C., the cathode voltage is kept in a low state until the lighting rate is 60% or less and a relatively high lighting rate. Therefore, the anode current Idd increases as the lighting rate increases (when the duty ratio control is not performed). When the lighting rate is 60% or more, the cathode voltage is increased. Heat generated by the display panel due to the rise is also suppressed.

  When the display panel is hot, the cathode voltage may be relatively high. This is because the Vt voltage (rising voltage) of the EL element 15 is lowered, and the absolute value of the voltage applied to both ends of the EL element 15 for obtaining the same luminance is also lowered. In other words, changing the cathode voltage according to the temperature of the display panel is advantageous for reducing power consumption. In the dotted line in FIG. 131 (when the panel temperature is high), the cathode voltage is −8V. In the case of a solid line (when the panel temperature is low), the cathode voltage is set to -9V. Further, in the case of a one-dot chain line with a lower panel temperature, the cathode voltage is set to -9.5V. In the present invention, the display panel or the ambient temperature of the display panel is detected (measured), and the cathode voltage or the anode voltage is changed depending on the temperature.

  In FIGS. 130 and 131, the cathode voltage is changed linearly corresponding to the lighting rate. However, the present invention is not limited to this, and it may be changed (corresponding) nonlinearly such as a square curve. Needless to say. Further, it is not limited to the two-point broken line as shown by the solid line in FIG. 130, and it goes without saying that the broken line may be three or more points.

  As described above, the present invention changes the cathode voltage in accordance with or in accordance with the lighting rate. The present invention is preferably implemented in combination with duty ratio control and reference current ratio control. FIG. 143 shows an embodiment in which cathode voltage control (FIG. 130, FIG. 131, etc.) and reference current control are combined.

  In FIG. 143, the reference current is increased at a lighting rate of 75% or more. The change in the reference current ratio is a change in the program current. Therefore, the program current increases in proportion to the reference current ratio, and the luminance of the EL element 15 also increases. In FIG. 143, the cathode voltage is kept constant in the range where the reference current is increased (lighting rate is 75% or more). When the lighting rate is 25% or more, the cathode voltage is increased.

  FIG. 144 shows an embodiment in which cathode voltage control (FIG. 130, FIG. 131, etc.) and duty ratio control are combined.

  In FIG. 143, the duty ratio is lowered to 1/2 = 0.5 when the lighting rate is 75% or more. The change in the duty ratio is a change in the Idd (Iss) current. Therefore, the luminance of the display screen 64 decreases corresponding to the duty ratio. In FIG. 144, the cathode voltage is kept constant at −4 V when the lighting rate is 75% or more. When the lighting rate is 25% or more, the cathode voltage is increased. Further, the duty ratio is lowered according to the lighting rate.

  As described above, the cathode current control is performed to suppress the cathode (anode) power supply power. Further, the present invention is combined with duty ratio control to suppress peak current and suppress cathode (anode) power supply power. FIG. 147 is an explanatory diagram of this embodiment.

  FIG. 147 (a) shows the case of the conventional example (constant cathode voltage, duty ratio control). The horizontal axis is the elapsed time. In FIG. 147 (a), the duty ratio is varied in accordance with the lighting rate of the image. However, the duty ratio is changed slowly to suppress flicker that occurs when the lighting rate changes. The time when the duty ratio changes suddenly is the time of a and b in FIG. 147 (a). At this time, a large cathode current flows. Therefore, the cathode power source capacity is also required to be close to 160%. The state in which the cathode current is increased continues for a certain period. However, by slowly reducing the duty ratio, the cathode current is reduced, and the cathode power source capacity is not within a specified range within 100%.

  FIGS. 147 (b1) and 147 (b2) are examples in which cathode current control (see FIGS. 128, 129, etc.) and duty ratio control are combined. The time when the duty ratio changes suddenly is the time of a and b as in FIG. 147 (a). At this time, as shown in FIG. 147 (b2), the cathode voltage rises. Therefore, the voltage applied to the EL element 15 decreases. Although the cathode current Iss increases, the cathode voltage increases, and as a result, the cathode power supply power is kept constant. Therefore, as illustrated in FIG. 147 (b1), the cathode power supply power ratio does not exceed 100%. The duty ratio slowly decreases starting from the times a and b, and the cathode voltage returns to a normal voltage (becomes −9 V) as the duty ratio changes.

  Although FIG. 147 has been described as a driving method combining cathode current control (see FIGS. 128, 129, etc.) and duty ratio control, the present invention is not limited to this. For example, cathode current control and reference current ratio control may be combined. This is because the program current can be increased or decreased and the anode (cathode) current can be increased or decreased by increasing or decreasing the reference current ratio. Further, cathode current control, duty ratio control and reference current ratio control may be combined.

  In the above embodiment, the cathode voltage is changed according to the lighting rate. The example of FIG. 145 shows the relationship between the change rate of the cathode current Iss (the cathode current ratio, expressed in%) and the cathode voltage. The cathode current ratio of 100% is the maximum current of the cathode current Iss that can be extracted from the booster circuit 1281b in the case of the initial value voltage of the cathode voltage (voltage in the region where the lighting rate is low; cathode voltage = −9V in FIG. 145). . The transition point is a cathode current ratio of 100%. When the cathode current ratio is 100% or more, the cathode voltage is increased.

  For ease of explanation, specific numbers are described as an example. In FIG. 145, it is assumed that the cathode current Iss = 0.1 A when the cathode current ratio is 100%. Therefore, when the cathode current ratio is 150%, the cathode current Iss = 0.15A. The power supply capacity of the booster circuit 1281b is 0.1 A × (−9) V = 0.9 W when the cathode current ratio is 100%. When the cathode current ratio is 150%, the cathode current Iss = 0.15 A and the cathode voltage is −6V. Therefore, the necessary power supply capacity is 0.15 A × (−6) = 0.9 W. In other words, even if the cathode current becomes 1.5 times (cathode current ratio 150%), it is not necessary to increase the power supply capacity of the booster circuit 1281b by increasing the cathode voltage (−9V → −6V). When the cathode current ratio is in the range of 100% to 150%, the power supply capacity of the booster circuit 1281b is kept within the maximum usable range (inside) by linearly changing the cathode voltage.

  As described above, the present invention changes the cathode voltage in response to an increase in the cathode current. Therefore, the power supply circuit can be reduced in size.

  In FIG. 146, the horizontal axis represents the power ratio of the booster circuit 1281b. The power ratio of 100% is the maximum power that can be used by the booster circuit 1281b. The vertical axis represents the cathode current ratio. In the embodiment of FIG. 146, the cathode current ratio is lowered at a power ratio of 100% or more. That is, the cathode current Iss is decreased. When the power ratio is 150%, the cathode current ratio is reduced to 66.7%.

  For ease of explanation, specific numbers are described as an example. In FIG. 146, the cathode current Iss = 0.1 A when the cathode current ratio is 100%. Therefore, when the cathode current ratio is 66.7%, the cathode current Iss = 0.0667A. The power supply capacity 100% of the booster circuit 1281b is 0.1 A × (−9) V = 0.9 W when the cathode current ratio is 100%. When the power supply capacity of the booster circuit 1281b is 150%, the cathode current Iss = 0.0667A. Therefore, the power output from the booster circuit 1281b is 1.5 × 0.0667A × (−9) = 0.9W. That is, it is not necessary to increase the power supply capacity of the booster circuit 1281b by suppressing the cathode current to 0.667 times. When the power ratio of the booster circuit 1281b is in the range of 0% to 100%, the maximum output current of the cathode current ratio is changed linearly.

  FIG. 148 shows another embodiment of the present invention. FIG. 148 shows a power supply circuit composed of a booster circuit 1281 that boosts the Vin voltage and generates a Vdd voltage, and a voltage inverter circuit 1282 that generates a Vss voltage whose polarity is inverted with the boosted Vdd voltage as the center of the GND voltage. It is a block diagram.

  With the configuration as shown in FIG. 148, the circuit configuration is simplified and the cost can be reduced. However, in the generated voltage, as shown in FIG. 149, the magnitude A of the Vdd voltage and the magnitude B of the Vss voltage are A = B. As shown in FIG. 149, by making the Vcc voltage and the Vdd voltage common (the same voltage), the cost of the power supply circuit can be further reduced.

  Even in the configuration of FIG. 149, cathode (anode) voltage control (when the driving transistor is a P-channel transistor, the cathode voltage control that mainly changes the cathode voltage is performed, and when the driving transistor is an N-channel transistor) Needless to say, it is possible to apply an anode voltage control mainly for changing the anode voltage.

  In FIGS. 130 and 131, it has been described that the change in the cathode voltage is continuously changed, but the present invention is not limited to this. For example, as shown in FIG. 150, the cathode voltage may be digitally changed to Vss0, Vss1, Vss2, and Vss3 (may be changed with a jump value). Moreover, a part may be changed continuously and a part may be changed digitally. For example, when switching between the high luminance display mode and the normal luminance display mode, the change may be made digitally, and the change due to temperature may be changed continuously. Further, as shown in FIG. 152, the Vin voltage may be inverted after the booster circuit 1281b.

  In the above embodiment, the anode voltage is lowered or the cathode voltage is raised by the operation of the booster circuit 1281. However, the present invention is not limited to this. For example, as shown in FIG. 151, a resistor R is arranged at the output terminal of the cathode voltage. When the Iss current flows through the resistor R, the voltage across the resistor R increases in proportion to the Iss current. Therefore, the cathode terminal voltage increases as the Iss current increases. Since the Iss current is proportional to the lighting rate, the cathode voltage can be increased (changed) in accordance with the lighting rate. Instead of the resistance R, a non-linear element such as a body or a thyristor may be used.

  Hereinafter, an EL display panel or an EL display device of the present invention or a device using the driving method thereof will be described. The following apparatus implements the previously described apparatus or method of the present invention. FIG. 133 is a plan view of a mobile phone as an example of an information terminal device. An antenna 1331, a numeric keypad 1332, and the like are attached to the housing 1333. 1332 and the like are display color switching keys, power on / off, and frame rate switching keys.

  If the key 1332 is pressed once, the display color is set to the 8-color mode, then the same key 1332 is pressed, the display color is set to 4096 color mode, and if the key 1332 is pressed, the display color is set to the 260,000 color mode. But you can. The key is a toggle switch that changes the display color mode each time it is pressed. In addition, you may provide the change key with respect to a display color separately. In this case, there are three (or more) keys 1332.

  The key 1332 may be a push switch, another mechanical switch such as a slide switch, or may be switched by voice recognition or the like. For example, when 4096 colors are input to the receiver by voice input, for example, “high quality display”, “4096 color mode” or “low display color mode” is input to the receiver, the display screen 64 of the display panel displays. The display color is changed. This can be easily realized by adopting the current speech recognition technology. The display color can be switched by FRC, precharge driving, or the like. Embodiments of FRC or precharge driving have been described before and will not be described.

  Note that in the case where the efficiency of the RGB EL elements is different and it is difficult to achieve white balance, a color filter 1681 may be disposed on the light exit surface as shown in FIG. In FIG. 168, when the luminous efficiency of R is high, in order to attenuate the emission ratio of R light, red (R) for the purpose of improving color purity by cutting a part of R light or narrowing the band. ) A filter 1681 is arranged.

  In addition, the display color may be switched by an electrical switch or a touch panel that is selected by touching a menu displayed on the display unit 64 of the display panel. Further, it may be configured to be switched by the number of times the switch is pressed, or to be switched by rotation or direction like a click ball.

  Although 1332 is a display color switching key, it may be a key for switching the frame rate. Moreover, it is good also as a key etc. which switch a moving image and a still image. A plurality of requirements such as a moving image, a still image, and a frame rate may be switched at the same time. Alternatively, the frame rate may be changed gradually (continuously) as long as the pressure is kept pressed. This case can be realized by making the resistor R of the capacitor C and the resistor R constituting the oscillator a variable resistor or an electronic volume. The capacitor can be realized by using a trimmer capacitor. Alternatively, a plurality of capacitors may be formed on the semiconductor chip, one or more capacitors may be selected, and these may be connected in parallel in a circuit.

  In the display panel (display device) of the present invention, brightness adjustment is performed by duty ratio control or reference current ratio control. Particularly, the configuration of the reference current ratio control circuit is preferable because the brightness of the display screen 64 can be linearly controlled or adjusted while maintaining the white balance. Brightness adjustment may be software control by the controller circuit (IC) 722, or may be adjustment by a touch switch that is selected by touching a menu displayed on the display unit 64 of the display panel. Further, a method in which the intensity of outside light is detected by a photosensor and is adjusted automatically may be used. Needless to say, the above items can also be applied to contrast adjustment and the like. Needless to say, the present invention can also be applied to duty ratio control.

  FIG. 134 is a cross-sectional view of the viewfinder in the embodiment of the present invention. However, it is schematically drawn for easy explanation. In addition, there are parts that are partially enlarged or reduced, and some parts are omitted. For example, in FIG. 134, the eyepiece cover is omitted. The above also applies to other drawings.

  The back surface of the body 1333 is dark or black. This is because stray light emitted from the EL display panel (display device) 1334 is diffusely reflected on the inner surface of the body 1333 to prevent a decrease in display contrast. Further, a phase plate (λ / 4 plate or the like) 38, a polarizing plate 39, or the like is disposed on the light emission side of the display panel. This is also explained in FIG. 3 and FIG.

  A magnifying lens 1342 is attached to the eyepiece ring 1341. The observer adjusts the eyepiece ring 1341 so that the display screen 64 of the display panel 1334 is in focus by changing the insertion position of the eyepiece ring 1341 in the body 1333.

  Further, if a positive lens 1343 is disposed on the light exit side of the display panel 1334 as necessary, the principal ray incident on the magnifying lens 1342 can be converged. Therefore, the lens diameter of the magnifying lens can be reduced, and the viewfinder can be miniaturized.

  FIG. 135 is a perspective view of the video camera. The video camera includes a photographing (imaging) lens unit 1352 and a video or melody body 1333, and the photographing lens unit 1352 and the viewfinder unit 1333 are back to back. An eyepiece cover is attached to the viewfinder (see also FIG. 134) 1333. An observer (user) observes the display screen 64 of the display panel 1334 from the eyepiece cover portion.

  On the other hand, the EL display panel of the present invention is also used as a display monitor. The display unit 64 can freely adjust the angle at a fulcrum 1351. When the display unit 64 is not used, it is stored in the storage unit 1353.

  The switch 1354 is a changeover or control switch that performs the following functions. A switch 1354 is a display mode switching switch. The switch 1354 is preferably attached to a mobile phone or the like. The display mode changeover switch 1354 will be described.

  As one of the driving methods of the present invention, there is a method in which an N-fold current is supplied to the EL element 15 to light it for a period of 1 / M of 1F. The brightness can be changed digitally by changing the lighting period. For example, assuming that N = 4, a current that is four times as large as the EL element 15 is passed. If the lighting period is set to 1 / M and M = 1, 2, 3, and 4 are switched, the brightness can be switched from 1 to 4 times. In addition, you may comprise so that it can change with M = 1, 1.5, 2, 3, 4, 5, 6, etc.

  In the above switching operation, the display screen 64 is displayed very brightly when a power source of a mobile phone, a monitor, or the like is turned on, and the display brightness is reduced to save power after a certain period of time has elapsed. Used for. It can also be used as a function for setting the brightness desired by the user. For example, when outdoors, the screen is very bright. This is because the surroundings are bright outdoors and the screen cannot be seen at all. However, if the display is continued with high luminance, the EL element 15 deteriorates rapidly. For this reason, when it is very bright, it is configured to return to normal luminance in a short time. Further, in the case of displaying with high brightness, the display brightness can be increased by the user pressing the button.

  Therefore, it is preferable that the user can be switched by the button 1354, can be automatically changed in the setting mode, or can be automatically switched by detecting the brightness of external light. Further, it is preferable that the display brightness is set to 50%, 60%, and 80% and can be set by the user.

  The display screen 64 is preferably a Gaussian distribution display. The Gaussian distribution display is a method in which the brightness at the center is bright and the periphery is relatively dark. Visually, if the central part is bright, it is felt bright even if the peripheral part is dark. According to the subjective evaluation, if the peripheral part keeps 70% of brightness compared to the central part, it is visually inferior. Even if the brightness is further reduced to 50% luminance, there is almost no problem. In the self-luminous display panel of the present invention, the above-described N-fold pulse drive (a method in which an N-fold current is supplied to the EL element 15 and the light is lit for a period of 1 / M of 1F) is used. A Gaussian distribution is generated in the direction.

  Specifically, the value of M is increased at the top and bottom of the screen, and the value of M is decreased at the center. This is realized by modulating the operation speed of the shift register of the gate driver circuit 12 or the like. The left and right brightness modulation of the screen is generated by multiplying the table data and the video data. With the above operation, when the peripheral luminance (angle of view 0.9) is 50%, the power consumption can be reduced by about 20% compared to the case of 100% luminance. When the peripheral luminance (angle of view 0.9) is 70%, the power consumption can be reduced by about 15% compared to the case of 100% luminance.

  Gaussian distribution means changing the reference current (for example, increasing the reference current ratio at the center of the screen and decreasing the reference current ratio at the top and bottom of the screen), and changing the duty ratio (for example, the center of the screen). Needless to say, this can also be realized by increasing the duty ratio at the portion and decreasing the duty ratio at the upper and lower portions of the screen) and changing the precharge current or precharge voltage.

  It is preferable to provide a changeover switch or the like so that the Gaussian distribution display can be turned on and off. This is because, for example, when the Gaussian display is used outdoors, the periphery of the screen cannot be seen at all. Therefore, it is preferable that the user can be switched with a button, can be automatically changed in a setting mode, or can be switched automatically by detecting the brightness of external light. In addition, it is preferable that the peripheral brightness is set to 50%, 60%, and 80% so that the user can set it.

  In a liquid crystal display panel, a fixed Gaussian distribution is generated by a backlight. Therefore, the Gaussian distribution cannot be turned on / off. The fact that the Gaussian distribution can be turned on / off is an effect peculiar to a self-luminous display device.

  The EL display device and the like of this embodiment can be applied not only to a video camera but also to an electronic camera, a still camera, or the like as shown in FIG. The display device is used as a monitor 64 attached to the camera body 1361. In addition to the shutter 1363, a switch 1354 is attached to the camera body 1361.

  The EL display panel of the present invention can also be employed in a 3D (stereoscopic) display device. 141 and 142 are explanatory diagrams of the 3D display device of the present invention. As shown in FIG. 141, the two EL display panels (EL display arrays) 30a and 30b are arranged facing each other. Further, the pixel electrode 15a of the display panel 30a and the pixel electrode 15b of the display panel 30b are arranged at facing positions. The distance between the two EL display panels is held by a separation column 1411. The isolation column 1411 is disposed around the display area 64 and has a ring shape. It is composed of an inorganic material such as glass. The isolation column 1411 (height) may be formed or configured by a pressure film technique, a coating technique, a printing technique, or the like. Alternatively, the array substrate 30 may be formed by digging up the display region 64 or the like using an etching technique or a polishing technique.

  The isolation column 1411 has a thickness of 1 mm or more and 8 mm or less. In particular, it is preferable that the separation column 1411 has a thickness of 3 mm to 7 mm (corresponding to d in FIG. 165). The isolation column 1411 is attached to the panels 30 a and 30 b with a sealing resin 6332. In the space 6333, a desiccant is disposed, formed, or configured as necessary.

  In FIG. 142, the display panels 30a and 30b are illustrated as being integrated by two substrates, but the present invention is not limited to this. The display panels 30a and 30b may each be configured to have an array substrate and a counter substrate (sealing substrate). In other words, the independent display panels 30a and 30b may be arranged using an isolation means (a means for maintaining a constant interval) such as the isolation column 1411.

  The pixel electrode 15a of the display panel 30a and the pixel electrode 15b of the display panel 30b display different images or the same image. The image is observed from the A direction. Therefore, the EL display panel 30a needs to be a transmissive type. This is because it is necessary to observe an image displayed on the pixel electrode 15b of the display panel 30b via the pixel electrode 15a. Both electrodes of the EL element 15 of the display panel 30b need to have transparency. A liquid crystal display device requires a backlight for image display. Therefore, it cannot be configured as a transmission type. Since the EL display panel is a self-luminous panel, the display image can be configured to be seen from both sides. That is, the image of the display panel 30a can be observed from the A side. In addition, the display panel needs to be configured so that the image of the display panel 30b can be observed from the A side. The display panel 30b may be a transmissive type or a reflective type.

  The display panel 30b may be a liquid crystal display panel. In that case, a backlight 1414 is arranged as shown in FIG. 141 so that the image on the display panel 30b can be observed from the A side. The screen sizes of the display panels 30a and 30b are preferably matched, but the present invention is not limited to this. The screen size of one display panel 30 may be increased or decreased.

  If the video processing circuits for supplying video signals to the display panels 30a and 30b are made common, cost reduction can be expected. Further, it is preferable that the brightness of one of the display images of the display panels 30a and 30b can be changed or changed with respect to the brightness of the other.

  The display image 64a of the display panel 30a is displayed brighter (higher brightness) than the display image layer 64b of the display panel 30b. By generating a luminance difference between the display image 64a and the display image 64b, the image viewed from the A side can be seen three-dimensionally. The luminance difference is preferably 10% or more and 80% or less. In particular, it should be 20% or more and 60% or less.

  142 is an explanatory diagram of image display states of the two display panels 30. FIG. The controller circuit (IC) 722 controls the image by controlling the source driver circuit (IC) 14a and the like of the display panel 30a and the source driver circuit (IC) 14b and the like of the display panel 30b, and the display images 64a and 64b 3D Realize the display.

  FIG. 165 shows an embodiment in which a transmissive self-luminous display panel 30a and a non-luminous liquid crystal display panel 1653 are combined. A backlight 1651 is disposed on the back surface of the liquid crystal display panel 1653. A polarizing plate (polarizing film) 39 a is disposed between the backlight 1651 and the liquid crystal display panel 1653, and a polarizing plate (polarizing film) 39 b is also disposed on the light exit surface side of the liquid crystal display panel 1653. The liquid crystal display panel 1653 is in a normally white mode, and the polarizing axes of the polarizing plate 39a and the polarizing plate 39b are orthogonal to each other. The liquid crystal display panel 1653, the backlight 1651, and the EL display panel 30a are attached to a holder (housing) 1652 so as to be integrated. Therefore, the image display position of the liquid crystal display panel 1653 and the distance d between the image display positions of the EL display panel 30a are kept constant with high accuracy.

  The term “orthogonal” as used herein means that when no voltage is applied to the liquid crystal layer of the liquid crystal display panel, light incident on the polarizing plate 39a passes through the liquid crystal display panel 1653 and enters the polarizing plate 39b. It means that it is configured or arranged so as to be absorbed by the polarizing plate 39b and not to be transmitted through the polarizing plate 39b (a state in which light is hardly transmitted).

  On the other hand, a circularly polarizing plate 1654a is disposed between the EL display panel 30a and the liquid crystal display panel 1651. The circularly polarizing plate 1654 includes a λ / 4 plate (λ / 4 film) 38 and a polarizing plate (polarizing film) 39. A circularly polarizing plate 1654b is also disposed on the light exit surface of the EL display panel 30a. The polarizing axis of the polarizing plate 39c of the circularly polarizing plate 1654a and the polarizing axis of the polarizing plate 39d of the circularly polarizing plate 1654b are arranged so as to be orthogonal to each other.

  The term “orthogonal” as used herein means that linearly polarized light incident on the polarizing plate 39c is converted into circularly polarized light by the λ / 4 plate (λ / 4 film) 38c, passes through the EL display panel 30a, and is transmitted by the circularly polarizing plate 38d. This means that the light is converted to linearly polarized light having a phase difference of 90 degrees from that of the previous linearly polarized light, and is configured or arranged in a state of transmitting the polarizing plate 39d (a state of transmitting the most light).

  The above relationship is illustrated in FIG. The arrow shown on the polarizing plate 39 in FIG. 166 indicates the polarization axis. Light from the backlight 1651 enters the polarizing plate 39a and is converted into linearly polarized light. The linearly polarized light enters the liquid crystal display panel 1653, and the liquid crystal display panel 1653 modulates the linearly polarized light according to the video signal to which the linearly polarized light is applied. The modulated linearly polarized light is absorbed or transmitted by the polarizing plate 39b in accordance with the modulation rate. The linearly polarized light transmitted through the polarizing plate 39b has a phase rotated by 90 degrees with respect to the linearly polarized light transmitted through the polarizing plate 39a.

  The linearly polarized light that has passed through the polarizing plate 39b passes through the polarizing plate 39c as it is (partially attenuated). The linearly polarized light incident on the polarizing plate 39c is converted into circularly polarized light by the λ / 4 plate (λ / 4 film) 38c, passes through the EL display panel 30a, and the circularly polarizing plate 38d has a phase difference of 90 degrees from the previous linearly polarized light. It is converted into linearly polarized light and transmitted through the polarizing plate 39d. Therefore, the display image on the liquid crystal display panel 1653 can be observed through the EL display panel 30a. Of course, since the EL display panel 30a is self-luminous, the display image of the EL display panel can also be observed through the circularly polarizing plate 1654b. With the above configuration, as described in FIG. 141, the image viewed from the A side looks three-dimensional.

  FIG. 167 is an explanatory diagram illustrating suppression of external light. External light B enters from the EL display panel 30a side. External light B enters the polarizing plate 39d and becomes linearly polarized light. This linearly polarized light is converted into circularly polarized light by a λ / 4 plate (λ / 4 film) 38d and enters the EL display panel 30a. External light is mainly reflected by the cathode electrode 30. The reflected light C again enters the λ / 4 plate (λ / 4 film) 38d. The incident reflected light C is converted into linearly polarized light by a λ / 4 plate (λ / 4 film) 38d. This linearly polarized light is 90 degrees out of phase with the linearly polarized light in which external light B is transmitted through the polarizing plate 39d. Therefore, the light C is absorbed by the polarizing plate 39d. Therefore, the present invention is not affected by the external light B and can realize a good contrast display.

  The above is the case where the display area of the display panel is relatively small, but the display screen 64 tends to bend when the display area is larger than 30 inches. As a countermeasure, in the present invention, as shown in FIG. 137, an outer frame 1371 is attached to the display panel, and the outer frame 1371 is attached by a fixing member 1374 so that it can be suspended. The fixing member 1374 is used to attach to a wall or the like.

  However, as the screen size of the display panel increases, the weight increases. Therefore, a leg mounting portion 1373 is disposed on the lower side of the display panel so that the weight of the display panel can be held by the plurality of legs 1372.

  The leg 1372 can move left and right as shown in A, and the leg 1372 can be contracted as shown in B. Therefore, the display device can be easily installed even in a narrow place.

  In the television of FIG. 137, the surface of the screen is covered with a protective film (or a protective plate). This is for the purpose of preventing an object from hitting the surface of the display panel and damaging it. An AIR coat is formed on the surface of the protective film, and the surface is embossed to prevent external conditions (external light) from appearing on the display panel.

  A certain space is arranged by spreading beads or the like between the protective film and the display panel. Moreover, a fine convex part is formed in the back surface of a protective film, and space is hold | maintained between a display panel and a protective film with this convex part. By holding the space in this way, the impact from the protective film is suppressed from being transmitted to the display panel.

  It is also effective to place or inject an optical binder such as a liquid such as alcohol or ethylene glycol or a solid resin such as an epoxy resin between the protective film and the display panel. This is because interface reflection can be prevented and the optical binder functions as a buffer material.

  Examples of the protective film include a polycarbonate film (plate), a polypropylene film (plate), an acrylic film (plate), a polyester film (plate), and a PVA film (plate). Needless to say, other engineering resin films (ABS and the like) can be used. Moreover, what consists of inorganic materials, such as tempered glass, may be used. The same effect can be obtained by coating the surface of the display panel with an epoxy resin, a phenol resin, or an acrylic resin with a thickness of 0.5 mm or more and 2.0 mm or less instead of arranging the protective film. It is also effective to emboss the surface of these resins.

  It is also effective to coat the surface of the protective film or coating material with fluorine. This is because the dirt on the surface can be easily wiped off with a detergent or the like. Further, the protective film may be formed thick and may also be used as a front light.

  In the above embodiments, the display panel of the present invention is used as a display device. However, the present invention is not limited to this. FIG. 140 is used as an information generating apparatus. As described with reference to FIG. 8 and the like, the non-lighting region 62 and the lighting region 63 can be generated by a signal (particularly an ST signal) input to the gate driver circuit 12. The lighting region 63 is a region where the EL element 15 of the corresponding pixel 16 emits light. In other words, the ON voltage is applied to the gate signal line 17b, and in the pixel configuration of FIG. 1, the transistor 11d is in the ON state. The non-lighting area 62 is an area where no current flows through the EL element 15 of the pixel 16. That is, the off voltage is applied to the gate signal line 17b, and in the pixel configuration of FIG. 1, the transistor 11d is in the off state.

  It is assumed that a white raster display signal is applied from the source driver circuit (IC) 14 to the display area 64. By controlling the gate driver 12b, it is possible to generate the lighting region 63 and the non-lighting region 62 in the display region 64 in a stripe shape (because lighting and non-lighting control are performed in units of pixel rows). As shown in FIG. 140, barcode display can be realized by controlling the gate driver circuit 12b.

  A start pulse is applied once per frame to the ST1 terminal of the gate driver circuit 12a. A start pulse is applied to the ST2 terminal of the gate driver circuit 12b in correspondence with the bar code display. The difference from the bar code of a normal printed matter is that each bar code display position of the display area 64 moves in synchronization with the horizontal scanning signal.

  Accordingly, as shown in FIG. 139, if a photosensor 1391 capable of detecting the lighting state of one pixel row is arranged or formed in the display area 64 of the EL display panel, the photosensor 1391 is fixed and 1 / (1 second. Barcode display state can be detected at a rate of (frame number / pixel row number). Data detected by the photosensor 1391 is converted into an electrical signal by a decoder (barcode decoder) 1392 and decoded to become information. Since the EL display panel has high responsiveness, high-speed information can be displayed.

  The drive method and drive circuit of the present invention described in this specification such as duty ratio control drive, reference current control, N-fold pulse drive, source driver circuit (IC), gate driver configuration, etc. It is not limited to a drive circuit or the like. Needless to say, the present invention can be applied to other displays such as a field emission display (FED) and an SED (display developed by Canon and Toshiba) as shown in FIG. In particular, since the FED and SED are current driven, the technical idea of the source driver circuit (IC) 14 and the driving method of the present invention can be favorably applied.

  In the FED of FIG. 138, electron emission protrusions 1383 (corresponding to the pixel electrode 35 in FIG. 3) that emit electrons in a matrix are formed on the substrate 30. A holding circuit 1384 that holds image data from the video signal circuit 1382 (corresponding to the source driver circuit (IC) 14 in FIG. 1) is formed in the pixel (corresponding to a capacitor in FIG. 1). A control electrode 1381 is disposed on the front surface of the electron emission protrusion 1383. A voltage signal is applied to the control electrode 1381 by an on / off control circuit 1385 (which corresponds to the gate driver circuit 12 in FIG. 1).

  If a peripheral circuit is configured with the pixel configuration of FIG. 138, duty ratio control driving or N-fold pulse driving can be performed. An image data signal is applied from the video signal circuit 1382 to the source signal line 18. The pixel 16 selection signal is applied to the selection signal line from the on / off control circuit 1385a, the pixels 16 are sequentially selected, and image data is written.

  The configuration of FIG. 138 also includes the duty ratio control, reference current control, precharge control, lighting rate control, AI control, peak current suppression control, panel wiring routing, source driver circuit (IC) 14 configuration of the present invention or Various configurations or methods, configurations, methods, apparatus configurations, display methods, etc. described in the specification of the present invention, such as drive methods, gate driver circuit configurations or control methods, trimming methods, program voltage + program current drive methods, inspection methods, etc. Needless to say, is applicable. Needless to say, the above items can be similarly applied to other embodiments of the present invention.

  In the present invention, reference current, duty ratio, precharge voltage (synonymous with or similar to program voltage), gate signal line voltage (synonymous with or similar to program voltage) depending on image (video) data, lighting rate, current flowing through the anode (cathode) terminal, panel temperature, etc. Vgh, Vgl), gamma curve, etc. are changed, adjusted, changed or varied, but are not limited thereto. For example, by predicting or predicting image (video) data, lighting rate, current flowing through the anode (cathode) terminal, panel temperature change rate or change, reference current, duty ratio, precharge voltage (synonymous or similar to program voltage) Needless to say, the output current of the source signal line 18, the gate signal line voltages (Vgh, Vgl), the gamma curve, etc. may be changed, adjusted, changed, changed or controlled. Needless to say, the frame rate may be changed or changed. In addition, these technical ideas can be combined with each other regardless of part or all of them.

  The present invention flows to the first FRC or the lighting rate or the anode (cathode) terminal in the first lighting rate (which may be the anode current of the anode terminal) or the lighting rate range (which may be the anode current range of the anode terminal). The current, the reference current, the duty ratio, the panel temperature, or the like is changed.

  Further, in the second lighting rate (which may be the anode current of the anode terminal) or the lighting rate range (which may be the anode current range of the anode terminal), the current flowing through the second FRC, the lighting rate, or the anode (cathode) terminal. Alternatively, it is changed as a reference current, a duty ratio, a panel temperature, or a combination thereof. Or, depending on the lighting rate (which may be the anode current of the anode terminal) or the lighting rate range (which may be the anode current range of the anode terminal) (adapted), it flows to the FRC or the lighting rate or the anode (cathode) terminal. The current, the reference current, the duty ratio, the panel temperature, or the like, or a combination thereof is changed.

  Also, when changing, the hysteresis is changed, delayed or changed slowly. In addition, these technical ideas can be combined with each other regardless of part or all of them.

  The matters described in the driver circuit (IC) of the present invention can be applied to the gate driver circuit (IC) 12 and the source driver circuit (IC) 14, and only the organic (inorganic) EL display panel (display device). In addition, the present invention can be applied to a liquid crystal display panel (display device). In addition, these technical ideas can be combined with each other regardless of part or all of them.

  The pixel configuration, display panel (display device) or control method or technical idea thereof, drive method or control method of the display panel or display device or technical idea, source driver circuit (IC), gate driver IC described above (Circuit) and other drive circuits or controller ICs (circuits) or their control circuits and their adjustment or control methods (including gate driver circuits) or technical ideas may be combined with each other in part or in whole. Can do. Needless to say, they can be applied to each other or configured or formed. Needless to say, the technical idea of the inspection apparatus and the inspection method or adjustment method of the present invention can be applied to the display panel or display apparatus of the present invention. In addition, these technical ideas can be combined with each other regardless of part or all of them.

  It goes without saying that the display panel of the present invention may mean a display device. In addition, the display device includes a case where it means a device having other components such as a photographing lens. That is, a display panel or a display device is a device having some display means.

  The technical ideas such as the display device, driving method, control method or method described in the embodiments of the present invention are applied to video cameras, projectors, stereoscopic televisions, projection televisions, FEDs, SEDs (displays developed by Canon and Toshiba), etc. Applicable.

  The present invention can also be applied to a viewfinder, a main monitor and a sub monitor of a mobile phone, a clock display unit, a PHS, a portable information terminal and its monitor, a digital camera, a satellite TV, a satellite mobile TV and a monitor thereof.

  The present invention can also be applied to an electrophotographic system, a head mounted display, a direct view monitor display, a notebook personal computer, a video camera, and an electronic still camera.

  Further, the present invention can be applied to a monitor of an automatic cash drawer, a public telephone, a videophone, a personal computer, a wristwatch and a display device thereof. The present invention can also be applied to a device that generates information such as a barcode. These technical ideas and the like can be combined with each other regardless of part or all of them.

  The present invention relates to a display monitor for home appliances, a display unit for car audio, a car speedometer, a shaving display unit, a pocket game device and its monitor, a display monitor for telephone numbers, a train destination display monitor, a neon Needless to say, the present invention can be applied to and applied to a display device replacement, a display panel backlight or a lighting device such as a home or commercial lighting device, a ceiling light, a window glass, or a car headlight. The lighting device is preferably configured so that the color temperature can be varied. In this case, the color temperature can be changed by forming RGB pixels in a stripe or dot matrix and adjusting the current flowing through them.

  It can also be applied to display devices such as advertisements or posters, RGB traffic lights, warning indicator lights, and the like. These technical ideas and the like can be combined with each other regardless of part or all of them.

  Further, the self-luminous element, the display device or the organic EL display panel of the present invention is also effective as a light source for the scanner. Using an RGB dot matrix as a light source, the object is irradiated with light to read an image. Of course, it goes without saying that it may be monochromatic. Further, it goes without saying that the light output from the display device of the present invention may be configured to emit a single wavelength or a narrow-band wavelength and used as a laser display device or its application. The band narrowing can be realized by using an interference effect or an optical filter.

  Moreover, it is not limited to an active matrix, A simple matrix may be sufficient. If the color temperature can be adjusted, the image reading accuracy can be improved. In addition, these technical ideas can be combined with each other regardless of part or all of them.

  The organic EL display device is also effective for the backlight of the liquid crystal display device of the present invention. The RGB pixels of the EL display device (backlight) are formed in a stripe shape or a dot matrix shape, and the color temperature can be changed by adjusting the current passed through them, and the brightness can be easily adjusted. In addition, since it is a surface light source, a Gaussian distribution that brightens the central part of the screen and darkens the peripheral part can be easily configured.

  It is also effective as a backlight for a field sequential type liquid crystal display panel that alternately scans R, G, and B light. Of course, it is needless to say that the technical idea of the present invention may be used as a white or single color backlight or flon and light without forming the pixel 16 or the like. In addition, these technical ideas can be combined with each other regardless of part or all of them.

  The technical idea of the present invention may be used not only for an active matrix display panel but also for a simple matrix display panel. Further, even if the backlight blinks, it can be used as a backlight of a liquid crystal display panel for displaying moving images by inserting black. In addition, the apparatus or method of the present invention can realize white light emission and can be used as a backlight of a liquid crystal display device or the like. In addition, these technical ideas can be combined with each other regardless of part or all of them.

  The present invention is not limited to the above-described embodiments, and various modifications and changes can be made without departing from the scope of the invention when it is practiced. In addition, the embodiments may be implemented in an appropriate combination as much as possible, and in that case, the effect of the combination can be obtained.

  The EL display device according to the present invention can suppress the occurrence of display unevenness due to variations in transistor thresholds, compensates for the temperature dependence of the driving transistor elements, and has a dynamic range by duty ratio control. Self-luminous display panels such as EL display panels (display devices) using organic or inorganic electroluminescence (EL) elements, etc., and drive circuits (ICs) such as these display panels, which have the effect of realizing a wide image display And the driving method.

  The EL display device according to the present invention has effects such as high image quality, good moving image display performance, low power consumption, low cost, high luminance, and the like, and EL using an organic or inorganic electroluminescence (EL) element or the like. It is useful for a self-luminous display panel such as a display panel (display device), a driving circuit (such as an IC) and a driving method for these display panels.

  The EL display device according to the present invention does not consume electric power, does not consume resources, and thus has an effect of being friendly to the global environment and space environment, and uses an organic or inorganic electroluminescence (EL) element or the like. It is useful for self-luminous display panels such as EL display panels (display devices), drive circuits (such as ICs) for these display panels, and drive methods.

It is a block diagram of the display panel of this invention. It is a block diagram of the display panel of this invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 10 is an explanatory diagram representing a driving method of a display device of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. FIG. 46 is an explanatory diagram of a display panel of the present invention. It is explanatory drawing of the drive method of the display panel of this invention. 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Explanation of symbols

11 TFT (Thin Film Transistor)
12 Gate driver IC (circuit)
14 Source Driver Circuit (IC)
15 EL (element) (light emitting element)
16 pixel 17 gate signal line 18 source signal line 19 storage capacity (additional capacitor, additional capacity)
29 EL film 30 Array substrate (Self-luminous display panel)
31 Bank (rib)
32 Interlayer insulating film 34 Contact 35 Pixel electrode 36 Cathode electrode 37 Desiccant 38 λ / 4 plate (λ / 4 film, phase plate, phase film)
39 Polarizing plate 40 Sealing lid 41 Thin film sealing film 61 Writing row 62 Non-display area (non-lighting area, black display area)
63 Display area (lighting area, image display area)
91 Current holding circuit 92 Polysilicon current holding circuit (Built-in current holding circuit)
93 Output terminal 16 Dummy pixel (row)
221 switch (on / off means)
222 Internal wiring (Output wiring)
223 Gate wiring 224 Current source (unit transistor)
232, 228 Transistor 321 Source terminal 322 Gate terminal 323 Drain terminal 324 Transistor 331 Matching circuit 332 Counter 333 AND circuit 334 Current output circuit 351 Latch circuit 352 Selector circuit 353 Precharge circuit 371 Voltage gradation circuit 381 Sample hold circuit (voltage holding means) )
382 Source signal line terminal 391 switching circuit 441 decoder 641 wiring pad (terminal) for gate driver
642 Wiring pad (terminal) for gate driver
643 Input signal line pad (terminal)
644 Output signal line pad (terminal)
661 Input signal line 662 Terminal electrode 663 Anode wiring 664 Gold bump 671 Flexible substrate 681 Inverted output generation circuit 691 Flip-flop (FF) circuit (selection circuit)
701 Signal generation circuit 622 Wiring 621 Differential-parallel signal conversion circuit 721 PLL circuit 791 Comparator circuit 811 Processing circuit 821 Mode conversion circuit (IC)
841 Unit transistor (Unit current output circuit)
891 Overcurrent transistor 911 Comparison circuit 1121 Switch circuit (switching means)
1122 Decoder circuit 1126 AI processing circuit (peak current suppression, dynamic range expansion processing, etc.)
1127 Video detection process (ID process)
1128 Color management processing circuit (color compensation / correction, color temperature correction circuit)
1129 Arithmetic circuit (MPU, CPU)
1131, 1132 Multiplier 1133 Adder 1134 Summation circuit (SUM circuit, data processing circuit, total current calculation circuit)
1281 Booster circuit 1282 Voltage inversion circuit 1331 Antenna 1332 Key 1333 Case 1334 Display panel 1341 Eyepiece ring 1342 Magnifying lens (positive lens)
1343 Convex lens (positive lens)
1351 Support point (rotating part)
1352 Photography lens (imaging means)
1353 Storage section 1354 Switch 1361 Main body 1362 Shooting section 1363 Shutter switch 1371 Mounting frame 1372 Leg 1373 Mounting base 1374 Fixing section 1381 Control electrode 1382 Video signal circuit 1383 Electron emission projection 1384 Holding circuit 1385 On-off control circuit 1391 Photo sensor 1392 Decoder (barcode decoding) vessel)
1393 EL display panel (Self-luminous display panel (device))
1411 Isolation pillar (Isolation wall (ring))
1412 Sealing resin (sealing means)
1413 Space 1414 Backlight 1531 Output selection circuit 1651 Backlight 1652 Holder (housing)
1653 Liquid crystal display panel (non-luminous display panel)
1654 circularly polarizing plate 1681 color filter

Claims (1)

A display area in which EL elements are arranged in a matrix;
Means for generating a reference current;
A transistor group to which the reference current is applied;
An output stage constituting the current mirror circuit with the transistor group;
An output terminal connected to the source signal line;
An EL display device comprising: an output selection circuit disposed between the output stage and the output terminal.

Images