JP2006013536A - Semiconductor storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively reduce an interference noise generated between adjacent bit lines in one cross (open bit line type) dynamic RAM. <P>SOLUTION: Sub-arrays 8, 8 are arranged at the right and left sides of a row of sense amplifiers 7 as a center. Each sub-array has a number of dynamic memory cells MC.... A pair of complementary bit lines is composed of bit lines (BL0, NBL0) to (BLn, NBLn) in the same row at the sub-arrays 8, 8 positioned at the left and right sides of the row of sense amplifiers 7 to become an open bit line type. A first wiring pattern SLD formed in parallel with these bit lines and in the same wiring layer is arranged between the bit lines BL0 to BLn, NBL0 to NBLn in the sub-arrays 8, 8. These wiring patterns SLD are all set at fixed potential, such as power source potential. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device such as a random access memory, and more particularly to a one-intersection type (open bit line type) in which a bit line connected to a dynamic memory cell extends left and right around a sense amplifier column.

  Conventionally, there are Patent Document 1 and Patent Document 2 as semiconductor memory devices. Both of the techniques of these patent documents are composed of a dynamic memory cell composed of one transistor and one capacitor, a word line, and a bit line, and two bit lines constituting a complementary bit line pair are composed of a sense amplifier array. 1-point intersection type (open bit line type) dynamic RAM, each extending left and right.

  In Patent Document 1, when an information storage capacitor using a MOS capacitor is used, when the power supply voltage fluctuates due to the operation of the peripheral circuit, the fluctuation is divided into two on the left and right sides of the sense amplifier row. The first wiring connected to the plate electrode at a plurality of positions is arranged in a direction perpendicular to the bit line for each plate electrode, and the first electrode connected to each plate electrode The first wiring is connected to each other by the second wiring, and the central portion of the second wiring is connected to the power supply line of the peripheral circuit by the third wiring. Correspondingly, the potential of the plate electrode is made uniform as a whole.

On the other hand, in Patent Document 2, when the information storage capacitor is a COB (Capacitor Over Bit-line) type, or when one electrode of the information storage capacitor has a cylinder shape formed on the inner wall of the hole of the interlayer insulating film. The common plate electrode of the capacitors of the plurality of dynamic memory cells provided on the left and right sides of the sense amplifier row so as to reduce the plate noise caused by the parasitic capacitance existing between the bit line and the plate electrode They are connected to each other.
JP 59-2365 A JP 2001-118999 A

  In recent years, a DRAM-embedded LSI in which a logic circuit and a dynamic RAM are mounted on a single chip has been actively commercialized. The memory capacity of the dynamic RAM mounted on the DRAM-embedded LSI is compared with that of a general-purpose DRAM. The transistor performance and cost reduction equivalent to standard CMOS are desired. For this reason, it is effective to incorporate a dynamic RAM using a planar memory cell that can be manufactured by a standard CMOS process. In order to reduce the size of the dynamic RAM, it is desirable that the operation method is a one-intersection method (open bit line type).

  However, the inventors of the present invention have examined noise interference in detail for the dynamic RAM of the one-intersection method. In recent miniaturization processes, interference noise between adjacent bit lines is dominant, and the plate electrode is also used. It turned out that there was a noise that could not be ignored. In order to reduce the plate noise, it is not sufficient to stabilize the plate potential using the techniques described in Patent Document 1 and Patent Document 2. Moreover, no countermeasure is taken against interference noise between adjacent bit lines. Further, each of the patent documents has a disadvantage that the manufacturing process is large and the wafer cost is increased because the plate electrode forming process is different from the transistor gate electrode forming process.

  Hereinafter, degradation of the operation margin of the memory array due to interference between adjacent bit lines will be described with reference to FIGS. 15 and 16.

  As shown in FIG. 15, in the one-intersection type memory array in which the memory arrays MATA and MATB are arranged on the left and right sides of the sense amplifier row, there is a parasitic capacitance between adjacent bit lines. As an example, the word line WL0A of the memory array MATA is selected, the data is read from the memory cell MC, the high level is read to the bit line BL1, and the low level is read from the other bit lines BL0 and BL2 to BLn. Explain the case.

  In this case, since the data of the bit lines BL0 and BL2 adjacent to the bit line BL1 is inverted data, the bit line BL1 receives coupling noise via the parasitic capacitances Cbs01A and Cbs12A between the adjacent bit lines. The read potential appearing on the line BL1 becomes small. On the other hand, there is no potential fluctuation of the bit lines NBL0 to NBLn on the memory array MATB side that becomes the reference potential. Therefore, regarding the potential difference between the complementary bit lines at the start of the amplification operation by the sense amplifier, the read potential difference of the complementary bit line pair (BL1, NBL1) is smaller than the other complementary bit line pairs. In this state, when the amplification operation by the sense amplifier is performed, since the high level read margin of the bit line BL1 is small, the data may be amplified erroneously when the sense amplifier is out of balance.

  Further, when the amplification operation is performed in a state where the high level signal of the bit line BL1 is small and the low level signals of the other bit lines BL0 and BL2 to BLn are large, the amplification operation of the bit lines BL0 and BL2 to BLn is fast. The amplification operation speed of the bit line BL1 is slow. Also at this time, negative phase noise is generated in the bit line BL1 via the parasitic capacitances Cbs01A and Cbs12A between the bit lines, and negative phase noise is also generated in the bit line NBL1 via the parasitic capacitances Cbs01B and Cbs12B on the memory array MATB side. Arise. Since these noises further delay the amplification speed of the complementary bit line pair (BL1, NBL1), the data of the complementary bit line pair (BL1, NBL1) may be inverted, resulting in erroneous reading.

  As described above, in the one-intersection type memory array, since there is a parasitic capacitance between adjacent bit lines, there is a possibility that data may be erroneously read depending on the data pattern read to the bit line. When the amount of signal charge stored in the memory cell is reduced due to leakage current or the like, the signal level read to the bit line is further reduced, and the possibility of erroneous reading is further increased.

  Further, in the conventional dynamic RAM, when the sense amplifier circuit is large, the high integration is reduced, and when the operation variation of the N-channel and P-channel pair transistors constituting the sense amplifier circuit is large. The operation is not stable, and there is a possibility of erroneous data reading.

  The present invention solves the above-described conventional problems, and an object of the present invention is to improve the layout configuration in the vicinity of the sense amplifier circuit and realize high integration in a dynamic RAM using planar memory cells. is there.

  In order to achieve the above object, in the present invention, the wiring layer forming the bit line is changed between the memory mat and the sense amplifier array.

  That is, the semiconductor memory device according to the first aspect of the present invention is the semiconductor memory device according to the first aspect of the present invention, wherein the plurality of word lines, the plurality of bit lines extending in the direction intersecting the word lines, and the word lines And a dynamic memory cell having one MOS transistor connected to the word line and the bit line and one capacitor having a storage node. A potential difference between a pair of complementary bit lines arranged between a memory mat and the bit line of the first memory mat and the bit line of the second memory mat, which is arranged between the first memory mat and the second memory mat. An open bit line type semiconductor memory device having a sense amplifier array for amplifying the bit line, wherein the bit line in the first and second memory mats is a predetermined wiring layer Is formed, said bit line extending in the sense amplifier row is being formed in different wiring layers from the predetermined layer level wiring layer.

  According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, in each of the complementary bit line pairs, a wiring length and a wiring width between two bit lines constituting the complementary bit line pair are substantially equal. It is characterized by being.

  According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the dynamic memory cell is a parallel plate type in which a capacitor is formed of a MOS transistor, and the plate electrode of the capacitor and the plurality of the plurality Are formed in the same process, and the plurality of bit lines are formed in the wiring layer above the capacitors and the plurality of word lines. Two sense amplifier circuits corresponding to two pairs of complementary bit line pairs are arranged side by side in the bit line direction.

  According to a fourth aspect of the present invention, in the semiconductor memory device according to the first, second, or third aspect, the odd-numbered bit lines of the first memory mat and the even-numbered bit lines of the second memory mat Constitutes a complementary bit line pair, and the even-numbered bit lines of the first memory mat and the odd-numbered bit lines of the second memory mat constitute a complementary bit line pair.

  According to a fifth aspect of the present invention, in the semiconductor memory device according to the third or fourth aspect, in the two sets of sense amplifier circuits corresponding to the two sets of complementary bit line pairs, the N-channel type constituting each of the sense amplifier circuits The pair transistors are arranged adjacent to each other, and the P-channel type pair transistors are also arranged adjacent to each other.

  According to a sixth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, two global bit lines corresponding to the complementary bit line pair are formed in an upper wiring layer of the complementary bit line pair. In the vicinity of the end of the complementary bit line pair, a switch circuit for connecting the complementary bit line pair to the two global bit lines is arranged in one place.

  As described above, according to the first to sixth aspects of the present invention, in the sense amplifier region, the two bit lines constituting the complementary bit line pair are parallel to each other and the wiring intervals are also equal in the sense amplifier column direction. Therefore, the layout of the sense amplifier circuit is facilitated and the chip area is reduced. In particular, in the invention described in claim 3, since two sets of sense amplifier circuits corresponding to two sets of complementary bit line pairs are arranged side by side in the bit line direction, the layout dimension in the sense amplifier column direction (word line direction) is Reduced. Furthermore, in the invention according to claim 5, since the N-channel type pair transistors and the P-channel type pair transistors constituting the two sets of sense amplifier circuits are arranged adjacent to each other, The isolation region from the channel pair transistor is reduced, and the layout dimension in the bit line direction is also reduced.

  As described above, according to the first to sixth aspects of the invention, in the sense amplifier region, the two bit lines constituting the complementary bit line pair are parallel to each other and the wiring interval is in the sense amplifier column direction. Since it can be made uniform, the layout of the sense amplifier circuit can be facilitated. In particular, according to the invention described in claim 3, the layout dimension in the word line direction is reduced, and according to the invention described in claim 5, the separation region between the N-channel type transistor and the P-channel type transistor is reduced. Each layout dimension in the bit line direction can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 14 shows an overall schematic layout of the semiconductor memory device according to the first embodiment of the present invention.

  In the figure, reference numeral 10 denotes a memory chip constituting a dynamic RAM. In the memory chip 10, 1 is a memory control circuit block arranged at the left end in the figure, and 2 is a right side of the memory control circuit block 1 in the figure. Read / write amplifier and column selection circuit block 3 arranged at the center, 3 is a row decoder and word line drive circuit block arranged in the longitudinal direction of the memory chip 10 at the center, and 4 is an internal power supply arranged at the right end in the figure. Circuit blocks 5, 5 and 5 are memory blocks arranged in two above and below the row decoder and word line driving circuit block 3 in the figure.

  Each memory block 5 has 16 memory arrays 6 arranged in the longitudinal direction of the memory chip 10. As shown in the enlarged view, the memory array 6 is arranged between a memory cell array (hereinafter referred to as a subarray) 8 arranged in two columns in the short direction of the memory chip 10 and two subarrays 8 and 8 in the same row. Sense amplifier row 7 and word line backing region 9 provided between upper and lower subarrays 8 and 8. Each sense amplifier circuit constituting the sense amplifier array 7 includes a CMOS latch circuit. The dynamic RAM according to the present embodiment is a so-called one-intersection system (open bit line) in which a complementary bit line pair is constituted by a bit line extending to the left and a bit line extending to the right with the sense amplifier row 7 as the center. System).

  A plurality of global bit lines (not shown) extending through the memory arrays 6 are formed on the memory blocks 5, and the global bit lines are switched in each memory array 6 (not shown). Are selectively connected to the bit lines of each memory array 6. Although not shown, the read / write amplifier and column selection circuit block 2 include a column selection circuit that selects the global bit line and a read amplifier that performs amplification operation of the global bit line pair selected by the column selection circuit. A circuit and a write amplifier circuit for performing a data write operation on the global bit line pair. Although not shown, the internal power generation circuit block 4 includes a step-down circuit, a plate potential generation circuit, and a bit line precharge potential generation circuit.

  One subarray 8 shown in the enlarged view is provided with, for example, 32 word lines, one redundant word line, and 32 bit lines extending in a direction crossing them, and each word line, bit line, Is connected to a dynamic memory cell having one transistor and one capacitor. Since 32 word lines and 32 bit lines are provided in one subarray 8, the number of memory cells is 32 × 32 = 1024. Since each memory array 6 is provided with 64 subarrays 8 and 16 memory arrays 6 are provided in the bit line direction, the storage capacity is 1024 × 64 × 16 = 1M. Since two memory blocks 5 are provided at the top and bottom, the entire memory block 5 has a storage capacity of 1M × 2 = 2M bits.

  FIG. 1A shows a specific configuration of the two subarrays 8 and 8 shown in an enlarged view of FIG. 14 and the sense amplifier array 7 arranged therebetween.

  In FIG. 5A, MATA is a subarray located on the left side of the sense amplifier row 7, MATB is a subarray located on the right side, WL0A to WLnA and WL0B to WLnB are word lines, and BL0 to BLn and NBL0 to NBLn are Complementary bit lines are constituted by a pair of bit lines (BL0, NBL0) to (BLn, NBLn) in the same column. MC is a dynamic memory cell composed of one transistor and one capacitor, and SA0 to SAn are sense amplifier circuits including a CMOS latch circuit. PLT is a common plate electrode of the capacitor of the memory cell MC, and serves as a common electrode between a plurality of memory cells including memory cells MC connected to one word line and adjacent memory cells MC. ing. WLDA and WLDB are word line drive circuits. The sense amplifier row 7 has a plurality of sense amplifier circuits SA0 to SAn.

  In FIG. 1A, SLD is a first wiring pattern arranged between adjacent bit lines BL0 to BLn and between adjacent bit lines NBL0 to NBLn for each of the subarrays MATA and MATB. A power supply potential VDD is supplied as a fixed potential to the first wiring pattern SLD. The bit lines BL0 to BLn and NBL0 to NBLn are formed in the first metal wiring layer, and the first wiring pattern SLD is also formed in the same wiring layer as the bit lines BL0 to BLn and NBL0 to NBLn. Cbs indicates a parasitic capacitance between the bit lines BL0 to BLn and NBL0 to NBLn and the first wiring pattern SLD.

  In the present embodiment, as described above, the bit lines BL0 to BLn adjacent in the subarray MATA and the bit lines NBL0 to NBLn adjacent to each other in the subarray MATB are formed in the same wiring layer. A first wiring pattern SLD is provided, and the potential of the first wiring pattern SLD is set to a fixed potential VDD. Accordingly, when the stored information is read from the memory cell MC to the complementary bit line pair, or when the minute potential difference read to the bit line is amplified by the corresponding sense amplifier circuits SA0 to SAn, the first wiring pattern SLD is shielded. Since it functions as a line, it is possible to significantly reduce interference noise to data reading that occurs through parasitic capacitance between adjacent bit lines, and it is possible to further stabilize the data reading operation.

  A circuit diagram of the memory cell MC is shown in FIG. In FIG. 4B, Q1 is a transfer gate made of a MOS transistor, and Q2 is a capacitor made of a MOS transistor, which is a parallel plate type memory cell. WL is a word line, BL is a bit line, and the word line WL is the gate of the transfer gate Q1, the bit line BL is one of the source and drain of the transfer gate Q1, and the other of the source and drain of the transfer gate Q1 is The plate electrode P of the MOS capacitor Q2 is connected to the storage node N of the MOS capacitor Q2 to the common plate electrode PLT which is the common electrode.

  FIG. 2 shows a more detailed configuration of a portion of the subarray MATA of FIG. In the sub-array MATA shown in the figure, BL0 to BL7 are bit lines formed in the first metal wiring layer, SASect0 and SAsct1 are sense amplifier rows, WL is a word line formed of polysilicon, and WLMT is a second metal layer. A word line backing wiring, PLT, formed in the wiring layer, is a common plate electrode, formed of polysilicon wiring, and a plurality of memory cells MC commonly connected to one word line WL and these memory cells A plate electrode is shared by a plurality of other memory cells MC adjacent to the MC.

  Further, PLTMT is a plate electrode backing wiring formed in the second metal wiring layer, and SLDM1 is the first wiring pattern, which is formed in the first metal wiring layer and adjacent to the bit line BL0. Located between ~ BL7. SLDM2 is a second wiring pattern formed in the second metal wiring layer, and is arranged in the direction in which the word line WL extends so as to intersect the first wiring pattern SLDM1, and a contact described later at each intersection. It is commonly connected to the first wiring pattern SLDM1 by VIA1 (indicated by black circles in the figure). The power supply potential VDD is supplied to the second wiring pattern SLDM2 as a fixed potential, and the power supply potential VDD is supplied to the first wiring pattern SLDM1 through the second wiring pattern SLDM2. JT is a word line backing region for connecting the word line WL and the word line backing wiring WLMT and for connecting the common plate electrode PLT and the plate electrode backing wiring PLTMT. Furthermore, VIA1 indicated by a black circle in the figure is a contact for connecting the first layer metal wiring and the second layer metal wiring, and CW indicated by a cross in the figure is for connecting the first layer wiring to the polysilicon and the active region. Contact.

  In the present embodiment, the first wiring pattern SLDM1 is formed of the same wiring layer as the bit lines BL0 to BL7 in parallel to each other, and the subarray MATA is formed by the contact CW at the left and right ends of the subarray MATA. It is connected to the MATA substrate. The second wiring pattern SLDM2 is arranged in parallel with the word line backing wiring WLMT in the same wiring layer as the word line backing wiring WLMT.

  3 is a cross-sectional view taken along the line III-III in the subarray MATA of FIG. 2, and FIG. 4 is a cross-sectional view taken along the line IV-IV in the word line backing region JT. In FIG. 3, the common plate electrode PLT and the word line WL are formed in the first metal wiring layer in the same manufacturing process. The first wiring pattern SLDM1 is connected by a contact VIA1 that connects the first-layer metal wiring and the second-layer metal wiring at each intersection with the second wiring pattern SLDM2, and at the left and right ends. A fixed potential VDD is supplied to the substrate NWELL by a contact CW connecting the first wiring pattern SLDM1 and the active region n +. In addition, a second wiring layer is formed above the first wiring pattern SLDM1, and a plate electrode backing wiring (fourth wiring pattern) is formed in a portion of the wiring layer located above the common plate electrode PLT. ) PLTMT is formed. The word line backing wiring WLMT is formed adjacent to the left and right of the plate electrode backing wiring PLMTT, and the second wiring pattern SLDM2 is formed adjacent to the left and right of the word line backing wiring WLMT. Yes.

  In FIG. 4, in the word line backing region JT, the plate electrode backing wiring PLTMT is connected to the common plate electrode PLT located immediately below by the contact VIA1 and the contact CW. Further, the word line backing wiring WLMT enters the first wiring layer by the contact VIA1, and then bends left or right so as to avoid both ends of the common plate electrode PLT, and the word line of the polysilicon layer by the contact CW. Connected to WL.

  5 is a cross-sectional view taken along the line VV of the common plate electrode PLT of FIG. 2, and FIG. 6 is a cross-sectional view taken along the line VI-VI of the second wiring pattern SLDM2. In FIG. 5, a plurality of bit lines BL and the first wiring pattern SLDM1 are alternately formed in the first metal wiring layer in the sub memory area. A plate electrode backing wiring PLTMT is formed in the second metal wiring layer, and this backing wiring PLTMT is connected to the common plate electrode PLT of the polysilicon layer by the contact VIA1 and the contact CW in the word line backing region JT.

  In FIG. 6, in the sub memory area, a plurality of bit lines BL and first wiring patterns SLDM1 are alternately formed in the first metal wiring layer. The second wiring pattern SLDM2 formed in the second metal wiring layer is connected to the first wiring pattern SLDM1 by the contact VIA1 at the intersection with the first wiring pattern SLDM1. 3 to 6, description of the cross-sectional structures of the memory cell transistor and capacitor is omitted.

  As can be seen from the above description and FIGS. 2, 3 and 6, the first wiring pattern SLDM1 and the second wiring pattern SLDM2 are arranged in a mesh pattern, and the fixed potential VDD is changed from the second wiring pattern SLDM2. Since the first wiring pattern SLDM1 is supplied, the fixed potential VDD can be supplied to the first wiring pattern SLDM1 with a low resistance. Therefore, the shielding function of the first wiring pattern SLDM1 formed between the adjacent bit lines BL can be more stably exhibited.

  Moreover, as shown in FIGS. 2 and 3, the fixed potential VDD of the first wiring pattern SLDM1 is also applied to the substrate NWELL so that the substrate potential is the same as the fixed potential of the first wiring pattern SLDM1. Therefore, it is possible to stabilize the substrate potential.

  Further, in the memory cell having the structure in which the word line WL and the common plate electrode PLT are formed in the polysilicon layer in the same manufacturing process as in the present embodiment, the common plate electrode PLT is formed by the word lines WL located on the left and right sides thereof. Due to the division and subdivision within the same memory array MATA, the resistance value of each subdivided common plate electrode PLT becomes high. However, in the present embodiment, the plate electrode backing wiring (fourth wiring pattern) PLTMT is formed on the upper layer of the common plate electrode PLT (the same wiring layer as the word line backing wiring WLMT and the second wiring pattern SLDM2). Since the plate electrode backing wiring PLTMT is commonly connected to the common plate electrode PLT of the polysilicon layer by the contacts VIA1 and CW in the word line backing region JT, the resistance of the common plate electrode PLT can be reduced. Therefore, it is possible to suppress the data reading interference noise from the common plate electrode PLT and stabilize the data reading operation.

  In addition, as can be seen from FIG. 4, since the plate electrode backing wiring PLTMT and the second wiring pattern SLDM2 are arranged on the left and right of the word line backing wiring WLMT, interference noise between the two word lines WL is obtained. And the data reading operation can be stabilized.

  In this embodiment, a memory cell using a planar type (parallel plate type) MOS capacitor shown in FIG. 1B is used. This planar memory cell has a larger memory cell area and a simple structure than a memory cell using a three-dimensional capacitor such as a stack capacitor or a trench capacitor. For this reason, the bit line pitch and the word line pitch are relaxed, and there is no need to add a special manufacturing process to the CMOS process. Therefore, when using a planar type memory cell, it becomes easy to adopt the above-described configuration, and the manufacturing cost can be reduced together with the stability of operation.

  In the present embodiment, the word line WL and the common plate electrode PLT are formed in the polysilicon layer. However, a structure represented by a laminated structure of polysilicon and tungsten may be used. The line and the plate electrode may be formed by the same manufacturing process. In this embodiment, the bit line BL and the first wiring pattern SLDM1 are formed in the first metal wiring layer. However, they may be formed in other wiring materials and other wiring layers. The bit line BL and the first wiring pattern SLDM1 may be formed in the same manufacturing process.

  FIG. 7 shows an example of a power supply method in the dynamic RAM of the present embodiment, and shows a configuration with a metal wiring layer for power supply.

  In the figure, BL0 to BL5 and NBL0 to NBL5 are bit lines, both of which are formed in the first metal wiring layer and bit lines (BL0, NBL0) to (BL5, NBL5) in the same row are connected to each other. Complementary bit line pairs are formed by. MBL0 to MBL3 are global bit lines extending in the same direction as the bit lines BL0 to BL5 and NBL0 to NBL5 and penetrating each memory array 6, and are formed in the third metal wiring layer. 6 is selectively connected to one of the bit lines by a predetermined switch means (not shown).

  SLDM1 is a first wiring pattern arranged between adjacent bit lines BL0 to BL5 and between adjacent bit lines NBL0 to NBL5, and is divided into a predetermined length in the first metal wiring layer. Is formed. The reason why the first wiring pattern SLDM1 is divided will be described later (described in FIG. 8). SLDM2 is a second wiring pattern formed so as to intersect with the first wiring pattern SLDM1, and is formed in a second metal wiring layer, and is formed in plural at an equal pitch. Each intersection with one wiring pattern SLDM1 is connected to the first wiring pattern SLDM1 by a contact VIA1 (indicated by a black circle in the drawing). The second wiring pattern SLDM2 is supplied with a fixed potential VDD as will be described later, and is connected to the substrate of the memory array 6 by the contact VIA1 in the word line backing region JT, thereby stabilizing the substrate potential. Let

  Further, SLDM3 is a third wiring pattern, which is formed in the third metal wiring layer and extends in parallel with the same wiring layer in the same direction (bit line direction) as the global bit lines MBL0 to MBL3. In addition, each intersection with the second wiring pattern SLDM2 is connected to each second wiring pattern SLDM2 by a contact VIA2 (indicated by x in the figure). Further, in this third wiring pattern, one SLDM3 is formed between two predetermined global bit lines (in the figure, MBL2 and MBL3), and as a whole, a plurality of SLDM3 are formed at an equal pitch. At the same time, the region of each memory array 6 passes through the subarrays 8 and 8 and the sense amplifier row 7 in the horizontal direction in FIG. 7 and reaches the internal power generation circuit block 4. In the internal power generation circuit block 4 and each sense amplifier row 7, each third wiring pattern SLDM3 is commonly connected to the power supply wiring VDD by a contact VIA3 (indicated by a Δ in the figure), so that the internal power generation The power supply is supplied from the power supply wiring VDD of the circuit block 4, and the received fixed potential is supplied to the sense amplifier circuits SA0 to SAn of the sense amplifier array 7 in common and the second wiring pattern SLDM2 is used for each of the first wirings. 1 is commonly supplied to one wiring pattern SLDM1. The third wiring pattern SLDM3 is commonly connected to the ground wiring VSS of the internal power generation circuit block 4 and the ground wiring of the sense amplifier circuits SA0 to SAn, and a ground potential (fixed potential) is supplied to the first wiring pattern SLDM1. May be.

  As described above, the supply of the fixed potential (power supply potential VDD) to the first wiring pattern SLDM1 has a three-layer structure having the second and third wiring patterns SLDM2 and SLDM3. A large number of the first and second wiring patterns SLDM1 and SLDM2 are formed in each layer, and a multi-mesh structure is formed in which the wiring layers intersect each other in a mesh pattern. Accordingly, by supplying the fixed potential VDD with such a wiring structure, the fixed potential VDD is supplied to the first wiring pattern SLDM1 evenly and with low resistance to the entire area of the memory array 6 including the sense amplifier array 7. As a result, interference noise between adjacent bit lines is effectively reduced in the data read and write operations in the memory array 6, so that stable operation with less location dependence is possible.

  Next, FIG. 7 will be described. In the figure, PLTMT is a plate electrode backing wiring (fourth wiring pattern), which is a wiring for supplying a plate potential VCP to the plate electrode P of the memory cell of FIG. It is formed in the second metal wiring layer and extends in a direction crossing the global bit lines MBL0 to MBL3.

  In FIG. 7, PLTMT2 is a fifth wiring pattern for supplying the plate potential VCP and extends in the direction intersecting the plate electrode backing wiring PLTMT, that is, in the bit line direction, and is the same as the global bit lines MBL0 to MBL0. They are formed in the same wiring layer in the direction (third metal wiring layer). The fifth wiring pattern PLTMT2 has a contact VIA2 at each intersection of the plate electrode backing wirings PLTMT of the subarrays (memory mats) 8 and 8 arranged on both sides with respect to the sense amplifier row 7 in the word line backing region JT. (Indicated by x in the figure).

  The fifth wiring pattern PLTMT2 is arranged so as to be sandwiched between two global bit lines (in FIG. 7, MBL3 and a global bit line (not shown) adjacent thereto). At least one is formed in the area of the sub memory 8 formed and sandwiched between the word line backing areas JT. Accordingly, since the plurality of fifth wiring patterns PLTMT2 are arranged in an intersecting manner with respect to the plurality of plate electrode backing wirings (fourth wiring pattern) PLTMT, the common plate electrodes PLT of both the memory mats MATA and MATB are arranged. The plate potential VCP is supplied in a mesh configuration. These fifth wiring patterns PLTMT2 pass through the regions of the respective subarrays 8 and reach the internal power generation circuit block 4. The plate potential VCP generated in this circuit block 4 is supplied to the plate electrode backing wiring PLTMT. To do. As shown in FIG. 2, the plate electrode backing wiring PLTMT supplies a plate potential VCP to the common plate electrode PLT in each word line backing region JT.

  Thus, in the present embodiment, a plurality of fifth wiring patterns PLTMT3 are provided with a plurality of plate electrode backing wirings (fourth fourth) of the memory mats 8 and 8 arranged on both sides with the sense amplifier row 7 as the center. Since the common plate electrodes PLT of the memory mats 8 and 8 are connected with a low resistance, noise generated in the common plate electrode PLT during operation can be made uniform. In addition, since the common plate electrodes PLT of the memory mats 8 and 8 can be commonly connected with low resistance in this way, other memory mats can be used against noise generated in the common plate electrode PLT of the memory mat 8 on the operating side. Since the eight common plate electrodes PLT function as a smoothing capacitor, noise generated in the common plate electrode PLT can be further reduced, and the operation can be further stabilized.

  Further, in FIG. 7, BP is a bit line precharge potential supply line, VSSL is a ground potential supply line, and these supply lines BP and VSSL are both extended in the same direction as the global bit lines MBL0 to MBL3, and A plurality of wires are formed in the same wiring layer (third metal wiring layer). Further, these supply lines BP and VSSL are each arranged so as to be sandwiched between two global bit lines, and are arranged at a predetermined pitch in each subarray 8, and two word line backing regions JT and JT are arranged. It arrange | positions so that at least 1 or more may be contained in between. The bit line precharge potential supply line BP and the ground potential supply line VSSL reach the internal power generation circuit block 4 through the sub memory arrays 8 and 8 and the sense amplifier row 7, and the bit line precharge from the circuit block 4. Charge potential VCP and ground potential VSS are received.

  In this embodiment, the dynamic RAM having the word line backing structure has been described. However, the present invention can be similarly applied to a dynamic RAM having a hierarchical word line structure having a sub word line and a main word line. . That is, in the dynamic RAM having the hierarchical word line structure, although not shown, the same effect can be obtained by replacing the word line backing area JT described in the present embodiment with the sub word line driving circuit area having the hierarchical word line structure. It is done.

(Specific configuration of memory cell)
FIG. 8 shows a specific layout configuration of the memory cell MC provided in the dynamic RAM according to the present embodiment.

  In the figure, WL is a word line, BL is a bit line, PLT is a common plate electrode, SLDM1 is a first wiring pattern arranged between adjacent bit lines BL and BL, and is the same as the bit line BL. 1 metal wiring layer. SLDM2 is a second wiring pattern and is formed in the second metal wiring layer. As shown in FIG. 1B, MC is a memory cell composed of a transfer gate Q1 composed of one MOS transistor and a MOS capacitor Q2 composed of one MOS transistor. When the memory cells MC are arranged in an array, as shown in FIG. 8, a total of eight cells arranged in the bit line direction and two in the word line direction are taken as one unit.

  In FIG. 8, OD is an active region of the memory cell MC, and an overlapping portion of the active region OD and the word line WL is formed as a transfer gate Q1. Further, an overlapping portion between the active region OD and the common plate electrode PLT is formed as a MOS capacitor Q2. VIA1 is a contact for connecting the first wiring pattern SLDM1 and the second wiring pattern SLDM2. As can be seen from FIG. 8, the common plate electrode PLT is formed between the memory cells MC including the memory cells MC connected to the common word line WL and the adjacent memory cells MC. It is common.

  In the present embodiment, the following configuration is employed in order to make the area of the MOS capacitor Q2 as large as possible in a limited region. Hereinafter, the memory cell MC surrounded by a thick line in the figure located at the lower left in the figure will be described as an example. In this memory cell MC, the lower half region of the common plate electrode PLT is configured as a so-called boot-type (step-shaped) MOS capacitor Q2 having an enlarged portion in that protrudes in the right bit line direction in the figure. Yes. In accordance with the protruding shape of the common plate electrode PLT, the word line WL running in the vicinity of the common plate electrode PLT is also bent in the right direction in the drawing at the protruding portion. In accordance with the projecting shape of the common plate electrode PLT, the position of the transfer gate Q1 is set not to be directly below the bit line BL but to a position biased in the upper word line direction in the figure. The bit line BL connected to Q1 also has a protruding portion ex extending upward in the drawing toward the transfer gate Q1, and a contact CW is formed near the tip of the protruding portion ex, and the protruding portion is formed by the contact CW. ex is connected to the transfer gate Q1. Further, the first wiring pattern SLDM1 is connected to the protruding portion ex of the bit line BL and the transfer gate Q1, that is, a contact so that the protruding portion ex of the bit line BL and the first wiring pattern SLDM1 are not short-circuited. The structure is divided near the CW.

  The memory cell MC (M0) located on the right side of the lower left memory cell MC (R0) in the figure is a horizontally inverted type of the memory cell MC (R0), and the memory cell MC (M0) on the right side in the figure. The memory cell MC (M180) located in the memory cell MC (R0) is an upside down type of the memory cell MC (R0), and the memory cell MC (R180) located on the right side of the memory cell MC (M180) is the memory cell MC (R0). ) Upside down / left / right inverted type. The four memory cells MC (R0), MC (M0), MC (M180), and MC (R180) in the same column in the bit line BL direction are used as sub-units, and the memory in the sub-unit is used in the word line WL direction. Another sub-unit composed of four memory cells MC that are vertically inverted is arranged.

  With the arrangement of the memory cells MC as described above, in the present embodiment, the wide MOS capacitor Q2 can be configured with a small area, and the first wiring pattern SLDM1 having a shielding effect against bit line interference noise is also effective. It is possible to configure. Therefore, it is possible to obtain a dynamic RAM that achieves both reduction in chip size and operational stability.

(Second Embodiment)
Subsequently, a semiconductor memory device according to a second embodiment of the present invention will be described. This embodiment relates to an improvement in the layout configuration of a sense amplifier circuit and a bit line in a dynamic RAM.

  First, before explaining the present embodiment, the layout configuration of FIG. 9 will be explained. In the figure, BL0, BL1, NBL0 and NBL1 are bit lines, respectively, and a bit line BL0 and a bit line NBL0 constitute a complementary bit line pair, and a bit line BL1 and a bit line NBL1 constitute a complementary bit line. Configure a pair. Each bit line BL0, BL1, NBL0, NBL1 is formed of the same metal wiring layer (first metal wiring layer) in both the sub-array 8 region and the sense amplifier region.

  NSA0, NSA1, PSA0, and PSA1 are paired transistors that form a pair in the sense amplifier circuit (CMOS type latch circuit). In each bit line pair (BL0, NBL0), (BL1, NBL1), one bit line BL0, BL1 and the other bit line NBL0, NBL1 are in opposite directions around the pair transistors NSA0, NSA1, PSA0, PSA1. Are arranged so as to form a one-intersection (open bit line type) memory array.

  In FIG. 9, an N-channel pair transistor NSA0 and a P-channel pair transistor PSA1 constituting a sense amplifier circuit for one bit line pair (BL0, NBL0) are arranged adjacent to each other, and the other bit line pair (BL1, NBL pair transistor NSA1 and P-channel pair transistor PSA1 constituting a sense amplifier circuit for NBL1) are arranged adjacent to each other, and the wiring lengths of bit lines BL0, NBL0, BL1, NBL1 forming complementary bit lines Is configured to be substantially uniform.

  Therefore, in FIG. 9, two sets of sense amplifier circuits are divided into two columns for two sets of complementary bit line pairs, and substantially one sense amplifier circuit is configured for each bit line pitch. The layout area of the sense amplifier circuit can be reduced. Further, since the balance of the capacitive load between the two bit lines constituting the complementary bit line pair can be kept uniform, the operation can be stabilized.

  Next, the semiconductor memory device of this embodiment will be described with reference to FIG.

  In the layout configuration of the sense amplifier circuit shown in the figure, the bit lines BL0, BL1, NBL0, and NBL1 are formed in the first metal wiring layer in the subarray (memory mat) region, and the portion extending to the sense amplifier region is the first. It is configured to be formed in a second metal wiring layer different from the first layer. Further, in the subarray region, the odd-numbered bit line NBL0 in the subarray region on the right side of FIG. 10 and the even-numbered bitline BL0 in the subarray region on the left side of FIG. To form a complementary bit line pair, and the even-numbered bit line NBL1 in the sub-array region on the right side of FIG. 10 and the odd-numbered bit in the sub-array region on the left side of FIG. A complementary bit line pair is constituted by the line BL1. In these complementary bit line pairs, the wiring length and the wiring width are the same between the two bit lines (BL0, NBL0), (BL1, NBL1) constituting the pair.

  Further, in the sense amplifier region, the N-channel type transistor NSA0 and the P-channel type transistor PSA0 that constitute a sense amplifier circuit for one set of bit line pairs (BL0, NBL0), and another set of bit line pairs ( BL1 and NBL1) N-channel pair transistor NSA1 and P-channel pair transistor PSA1 constituting a sense amplifier circuit are arranged side by side in the bit line direction at the same pitch of these two complementary bit line pairs. . Further, in these two sets of sense amplifier circuits, the N-channel type pair transistors NSA0 and NSA1 are arranged adjacent to each other and concentrated at one place, and the P-channel type pair transistors PSA0 and PSA1 are arranged adjacent to each other at one place. Are arranged. In FIG. 10, a cross indicates a contact connecting the first layer and the second layer.

  Therefore, in the present embodiment, the wiring length and the wiring interval between the two bit lines (BL0, NBL0) and (BL1, NBL1) constituting the complementary bit line pair can be configured equally. The load balance can be kept uniform, and the bit lines BL0, NBL0, BL1, and NBL1 in the sense amplifier region are parallel to each other and the wiring intervals are also uniform, so that the layout of the sense amplifier circuit is facilitated.

  Furthermore, since the four pair transistors NSA0, PSA0, NSA1, and PSA1 constituting the two sets of CMOS latches can be arranged in a straight line in the bit line direction, the pitch of the sense amplifier circuits arranged in the array is set to the second. The wiring pitch of the layer can be made four times, and the layout dimension in the word line direction can be reduced.

  In addition, the N-channel pair transistors NSA0 and NSA1 of the two sets of CMOS latch circuits and the P-channel pair transistors PSA0 and PSA1 are each concentrated on one region. And the P-channel pair transistor can be reduced, and the layout dimension can be reduced in the bit line direction.

  FIG. 11 shows a configuration in which global bit lines are added to the layout configuration of the sense amplifier circuit shown in FIG.

  In the figure, MBL0 and MBL1 are global bit lines, which penetrate each subarray 8 and are formed in the third wiring layer. Bit lines BL0, NBL0, BL1, and NBL1 are formed in the second wiring layer in the sense amplifier region and in the first wiring layer in the subarray region, respectively. The even bit line BL0 in the left subarray region in FIG. 11 and the odd bitline NBL0 in the right subarray region in FIG. 11 and the bit line NBL0 in the right subarray region in FIG. 11 and the odd-numbered bit line BL1 in the left sub-array region in FIG. 11 and the even-numbered bit line NBL1 in the right sub-array region in FIG. Complementary bit line pairs are formed.

  In FIG. 11, SG0 is a switch circuit for connecting the bit line pair (BL0, NBL0) to the global bit lines MBL0, MBL1, and SG1 is a switch for connecting the bit line pair (BL1, NBL1) to the global bit lines MBL0, MBL1. Circuit. The switch circuit SG0 is arranged on the right end side of the bit lines BL0 and BL1 extending to the left of the sense amplifier region in the drawing, and the switch circuit SG1 is connected to the bit lines NBL0 and NBL1 extending to the right of the sense amplifier region in the drawing. It is arranged on the left end side. These two switch circuits SG0 and SG1 selectively connect one of the two pairs of complementary bit lines to the global bit lines MBL0 and MBL1.

  In general, in order to connect the bit lines to the global bit lines MBL0 and MBL1, the switch circuits SG0 and SG1 require a second wiring layer that is a node different from the bit line on which global bit line side. In the sense amplifier region, since the second wiring layer is used as the wiring layer of the bit lines BL0, BL1, NBL0, NBL1, these switch circuits SG0, SG1 cannot be arranged in the sense amplifier region. When complementary bit line pairs are adjacent to each other in this sense amplifier area, it is necessary to divide this switch circuit on both sides of the sense amplifier area in order to place a switch circuit for this complementary bit line pair. And the layout efficiency is degraded. However, in the present embodiment, the switch circuit SG0 is collectively arranged at one place at the right end of the bit lines BL0 and BL1, and the switch circuit SG1 is arranged at one place at the left end of the other bit lines NBL0 and NBL1. Has been. Therefore, since the switch circuits SG0 and SG1 for the complementary bit line pairs (BL0, NBL0) and (BL1, NBL1) are laid out in the same region in this way, the layout area can be reduced. .

(Third embodiment)
Next, an embodiment of the present invention will be described with reference to FIG. This embodiment relates to an improvement of a latch circuit of a sense amplifier circuit.

  First, a conventional configuration will be described. FIG. 12 is a conventional general schematic layout diagram of a pair transistor constituting a latch circuit of a sense amplifier circuit. In the figure, OD is an active region, Q1 and Q2 are a paired transistor in a latch circuit, BL and NBL are complementary bit line pairs, and S is a common source of the paired transistors Q1 and Q2. One bit line BL is connected to the gate of one transistor Q1 and the drain of the other transistor Q2, and the other bit line NBL is connected to the gate of the other transistor Q2 and the drain of one transistor Q1. The pair transistors Q1 and Q2 have their gate electrodes G1 and G2 arranged in parallel with each other in the same active region OD, and arranged symmetrically with respect to the common source electrode S. Here, on the activation region OD, the gate lengths L1 of the gate electrodes G1, G2 of the pair transistors Q1, Q2 are the same length L1.

  In recent miniaturization processes, when the gate lengths and gate widths of the transistors Q1 and Q2 are set small in the conventional configuration, the relative variation of the threshold voltages of the pair transistors Q1 and Q2 becomes remarkable. When the relative variation of the threshold voltages of the pair transistors Q1 and Q2 increases, the operation margin of the sense amplifier circuit that amplifies a minute potential in the vicinity of several tens of mV of the bit line decreases, and erroneous data reading may occur. Can happen.

  FIG. 13 shows an embodiment of a layout configuration of a sense amplifier circuit for solving the above problem. In this figure, each component is the same as that in FIG. 12 showing the conventional example, but in the gate electrodes G1 and G2 extending in parallel with each other in the active regions OD of the transistors Q1 and Q2, the active regions of the pair transistors Q1 and Q2 The gate length L2 near the boundary between the OD and the isolation region (both ends of the active region OD) is set to be longer than the gate length L1 near the center (L2> L1). In this embodiment, L2> 2 · L1 is set. Further, with this configuration, the transistors Q1 and Q2 are configured symmetrically in the word line direction and symmetrical in the bit line direction with the common source S as the center.

  Therefore, this embodiment has the following effects. That is, in the vicinity of the boundary between the active region OD and the separation region, there is a relative variation in threshold voltage due to processing variations, concentration variations of implanted ions, and the like. Since the gate length L2 is long, the channel region in the vicinity of this becomes difficult to function as a transistor near the threshold voltage. As a result, since the relative variation between the pair transistors Q1 and Q2 is reduced, the operation stability of the sense amplifier circuit that amplifies a minute potential difference is greatly improved.

(A) is a figure which shows schematic structure of the dynamic RAM of the 1st Embodiment of this invention, The figure (b) is a block diagram of a memory cell. It is a figure which shows the detailed structure of the subarray of the dynamic RAM. It is the III-III sectional view taken on the line of FIG. FIG. 4 is a sectional view taken along line IV-IV in FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V in FIG. 2. It is the VI-VI sectional view taken on the line of FIG. It is a figure which shows the layout structure of the power supply wiring in the sense amplifier row | line | column of the same dynamic RAM, and the subarray located in the right and left. It is a figure which shows the layout structure of the memory cell of the same dynamic RAM. It is a figure which shows the layout structure of the sense amplifier circuit of dynamic RAM. It is a figure which shows the layout structure of the sense amplifier circuit of the dynamic RAM of the 2nd Embodiment of this invention. It is a figure which shows the other layout structure of the sense amplifier circuit of the same dynamic RAM. It is a figure which shows the conventional layout structure of the pair transistor which comprises the sense amplifier circuit of dynamic RAM. It is a figure which shows the layout structure of the pair transistor which comprises the sense amplifier circuit of the dynamic RAM of the 3rd Embodiment of this invention. 1 is a diagram illustrating an entire chip configuration of a dynamic RAM according to a first embodiment of the present invention. It is a figure which shows schematic structure of the conventional dynamic RAM. It is explanatory drawing of the erroneous read-out operation | movement of the data resulting from the noise mixing of the conventional dynamic RAM.

Explanation of symbols

MATA first memory mat MATB second memory mat MC memory cells BL0 to BLn,
NBL0 to NBLn bit line ex protruding portion WL0A to WLnA,
WL0B to WLnB Word lines SA0 to SAn Sense amplifier circuits SLD and SLDM1 First wiring pattern SLDM2 Second wiring pattern P Plate electrode PLT Common plate electrode N Storage node Q1 Transfer gate (MOS transistor)
Q2 MOS capacitor PLTMT2 Plate electrode backing wiring WLMT Word line backing wiring MBL0 to MBL3 Global bit line SLDM3 Third wiring pattern VSSL Ground potential supply line Nwell Substrate BP Bit line precharge potential supply line PLTMT, VCP2 Plate electrode backing wiring (fourth Wiring pattern)
PLTMT2 5th and 6th wiring pattern JT Backing area OD Activation area in Enlarged portion NSA0, NSA1 N-channel type pair transistor PSA0, PSA1 P-channel type pair transistor SG0, SG1 Switch circuit G1, G2 Gate electrode 4 Internal power generation circuit Block 5 Memory block 6 Memory array 7 Sense amplifier row 8 Subarray 10 Memory chip

Claims (6)

A plurality of word lines; a plurality of bit lines extending in a direction intersecting the word lines; and a MOS transistor disposed at each intersection of the word lines and the bit lines and connected to the word lines and the bit lines; First and second memory mats comprising dynamic memory cells having one capacitor having a storage node;
A sense arranged between the first memory mat and the second memory mat and amplifying a potential difference of a complementary bit line pair composed of a bit line of the first memory mat and a bit line of the second memory mat. An open bit line type semiconductor memory device comprising an amplifier array,
The bit lines in the first and second memory mats are formed in a predetermined wiring layer,
The bit line extending in the sense amplifier row is formed in a wiring layer different from the predetermined wiring layer. 2. The semiconductor memory device according to claim 1, wherein each complementary bit line pair has substantially the same wiring length and wiring width between two bit lines constituting the complementary bit line pair. The dynamic memory cell is a parallel plate type in which a capacitor is formed of a MOS transistor,
The plate electrode of the capacitor and the plurality of word lines are formed in the same process,
The plurality of bit lines are formed in a wiring layer above the capacitors and the plurality of word lines,
3. The two sets of sense amplifier circuits corresponding to the two complementary bit line pairs are arranged side by side in the bit line direction with respect to the pitch of two adjacent complementary bit pairs. The semiconductor memory device described. The odd-numbered bit lines of the first memory mat and the even-numbered bit lines of the second memory mat constitute a complementary bit line pair,
4. The semiconductor according to claim 1, wherein the even-numbered bit lines of the first memory mat and the odd-numbered bit lines of the second memory mat constitute a complementary bit line pair. Storage device. In two sets of sense amplifier circuits corresponding to two sets of complementary bit line pairs,
5. The semiconductor memory device according to claim 3, wherein the N-channel type pair transistors constituting each of the sense amplifier circuits are arranged adjacent to each other, and the P-channel type pair transistors are also arranged adjacent to each other. Two global bit lines corresponding to the complementary bit line pair are formed in the upper wiring layer of the complementary bit line pair,
5. The semiconductor according to claim 4, wherein a switch circuit for connecting the complementary bit line pair to the two global bit lines is arranged in one place near the end of the complementary bit line pair. Storage device.

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