JP2006013556A - Semiconductor apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent source offset in a semiconductor apparatus, having a FET with a trench gate structure in which a conductor layer serving as a gate is provided in a trench, extending in the main surface of a semiconductor substrate, and to prevent a gate insulator from being damaged. <P>SOLUTION: In the semiconductor apparatus, the top surface of the trench gate conductor layer is formed higher than the main surface of the semiconductor substrate. The trench gate conductor layer and the gate insulator are formed on the main surface of the semiconductor substrate in the trench and the periphery thereof. Additionally, in the method, a groove for forming a trench gate on the main surface of a semiconductor substrate is formed through an insulating film as a mask which is formed on the main surface of a semiconductor substrate. Next, the side surface of the insulating film is made to retract from the top of the trench through isotropic etching, and a gate insulator and a conductor layer serving as a trench gate are formed on the main surface of the semiconductor substrate in the trench and the periphery thereof. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a trench gate structure.

  Power transistors are used in power amplifier circuits, power supply circuits, converters, power supply protection circuits, and the like, but these power transistors are required to have a high breakdown voltage and a large current in order to handle a large amount of power.

  In the case of a MISFET (Metal Insulator Semiconductor Field Effect Transistor), as a method for achieving a large current, it can be easily achieved by increasing the channel width. In order to avoid an increase in the chip area due to such an increase in channel width, for example, a mesh gate structure is used.

In the mesh gate structure, the gates are arranged in a grid pattern in a plane, and therefore the channel width per unit chip area can be increased.
Conventionally, power FETs having a planar structure have been used because the process is simple and it is easy to form an oxide film to be a gate insulating film.

  However, in FETs, the channel length is determined by the gate length, so in a planar structure FET, when the gate is thinned, the channel length is shortened and the short channel effect occurs, or the gate has a wiring function at the same time. When the gate is thinned, there is a problem that the allowable current is reduced, and there is a limit to miniaturization. For this reason, FETs having a trench gate structure have been considered for the reason that the degree of cell integration can be further improved and the on-resistance can be reduced.

In the trench gate structure, a conductor layer serving as a gate is provided in a groove extending to the main surface of a semiconductor substrate via an insulating film, a deep layer portion of the main surface is used as a drain region, and a surface layer portion of the main surface is used as a source region. The semiconductor layer between the drain region and the source region is used as a channel formation region.
The mesh gate structure FET is described in Non-Patent Document 1 below. A MISFET having a trench gate structure is disclosed in, for example, Patent Document 1 below.

Ohm Publishing "Semiconductor Handbook" pages 429 to 430 JP-A-8-23092

  As the miniaturization of the device progresses, the source region is further shrunk. As the shallowing progresses, the source region becomes thinner, and it becomes difficult to accurately position the trench gate with respect to the thin source region. If a source offset occurs that causes the trench gate to deviate from the source region due to an error in the trench gate, the source offset does not function as an FET.

  As the miniaturization of the device progresses, the source region is further shrunk. As the shallowing progresses, the source region becomes thinner, and it becomes difficult to accurately position the trench gate with respect to the thin source region.

  In addition, since the end portion of the gate insulating film is located at the corner of the groove, it may be damaged in the process of forming the trench gate. May occur.

An object of the present invention is to provide a technique capable of solving such problems and preventing the occurrence of a source offset.
An object of the present invention is to provide a technique capable of solving such problems and preventing damage to a gate insulating film.
An object of the present invention is to provide an FET having a trench gate structure which is made shallow.
The above and other problems and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
In a semiconductor device having an FET having a trench gate structure in which a conductor layer serving as a gate is provided in a groove extending on a main surface of a semiconductor substrate, a trench gate conductor layer and a gate insulating film are formed on the main surface of the semiconductor substrate in the groove and at the periphery of the groove. Form.

  In the manufacturing method, an insulating film is formed on the main surface of the semiconductor layer, the insulating film is patterned into a pattern corresponding to the trench gate, and a trench gate is formed in the semiconductor substrate layer using the patterned insulating film as a mask. A trench is formed, and the side surface of the insulating film is made to recede from the upper end of the trench by isotropic etching, and a conductor layer that becomes a gate insulating film and a trench gate on the semiconductor substrate main surface in the trench and at the periphery of the trench Thereafter, a channel region and a source region in contact with the gate insulating film in the trench are formed.

(Function)
According to the above-described means, it is possible to prevent source offset by forming the upper surface of the trench gate conductor layer higher than the main surface of the semiconductor substrate. In addition, since the gate insulating film and the conductor layer serving as the trench gate and the gate conductive layer are formed on the main surface of the semiconductor substrate at the periphery of the groove, damage to the edge of the gate insulating film can be prevented. .

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the present invention, it is possible to prevent source offset by forming the upper surface of the trench gate conductor layer higher than the main surface of the semiconductor substrate.
(2) According to the present invention, there is an effect that the source can be made shallow by the effect (1).
(3) According to the present invention, there is an effect that the cell can be miniaturized by the effect (2).
(4) According to the present invention, there is an effect that the trench gate conductor layer and the gate insulating film can be formed on the main surface of the semiconductor substrate at the periphery of the groove where the trench gate is formed.
(5) According to the present invention, the effect (4) has an effect of preventing the gate insulating film from being damaged.
(6) According to the present invention, since the channel formation region and the source region are formed by independent heat treatment control after the trench gate is formed, there is an effect that the shallowing of these regions can be realized.

Embodiments of the present invention will be described below.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a plan view showing a power MISFET having a trench gate structure, which is a main part of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the MISFET shown in FIG. FIG. 3 is an enlarged plan view of the main part showing the a part in FIG. 1, and FIG. 4 is a longitudinal sectional view taken along the line aa in FIG. 3.

  The MISFET according to the present embodiment is formed on a semiconductor substrate in which an epitaxial layer 2 is formed by, for example, epitaxial growth on an n + type semiconductor substrate 1 made of, for example, single crystal silicon. This MISFET is provided in a rectangular ring shape along the outer periphery of the semiconductor substrate, and is surrounded by a plate-like field insulating film 3 having a rectangular portion inside the corner (indicated by double diagonal lines in FIG. 3). Is formed inside.

  In the region, a plurality of cells having a trench gate structure in which the planar shape is a hexagon or a flat octagon is regularly arranged, and each gate is arranged in a lattice pattern in a plane and the cells are connected in parallel. It consists of a gate structure.

  In each cell, the n − -type first semiconductor layer 2a formed on the semiconductor substrate 1 serves as a drain region, and the p-type second semiconductor layer 2b formed on the first semiconductor layer 2a forms a channel. A vertical FET in which the n + -type third semiconductor layer 2 c formed on the second semiconductor layer 2 b is the source region becomes the base region.

  The trench gate 4 is formed through a gate insulating film 5 in a groove reaching the n − -type second semiconductor layer 2a serving as a drain region from the main surface of the semiconductor substrate. The trench gate 4 is made of, for example, polycrystalline silicon into which impurities are introduced, and the gate insulating film 5 is made of, for example, a multilayer film in which a thermal oxide film of about 27 nm and a deposited film of about 50 nm are sequentially formed. ing.

  As shown in FIGS. 19 to 21 described later, the upper surface of the trench gate 4 of the present embodiment is formed higher than the surface of the third semiconductor layer 2c serving as the source region, that is, the main surface of the semiconductor substrate. With this configuration, even if the source region becomes shallow, a source offset in which the trench gate 4 deviates from the source region can be prevented. Further, it is desirable that the upper surface of the trench gate 4 is formed to be substantially flat or convex.

  A trench gate 4 and a gate insulating film 5 are also formed on the main surface of the semiconductor substrate at the periphery of the trench. With this configuration, defects in the gate insulating film 5 can be prevented.

  As described above, the trench gates 4 of the adjacent cells are connected to each other, and each trench gate 4 of the cell located on the outer periphery is connected to the gate wiring 6 using, for example, polycrystalline silicon in the vicinity of the outer peripheral portion of the semiconductor chip. Has been.

  The gate wiring 6 is formed in an upper layer via an interlayer insulating film 7 and is electrically connected to a gate guard ring 8 (partially indicated by a broken line in FIG. 3) using, for example, aluminum containing silicon. ing. The gate guard ring 8 is formed integrally with a rectangular gate electrode 9 (partially indicated by a broken line in FIG. 3) provided in a rectangular portion of the field insulating film 3, and the gate 4 is connected to the gate electrode 9. A region (indicated by a broken line in FIG. 1) is provided.

  The third semiconductor layer 2c serving as a source is formed as an upper layer on the main surface of the semiconductor substrate with an interlayer insulating film 7 interposed therebetween. For example, a source wiring 10 using aluminum containing silicon (indicated by a broken line in FIG. 3) Are partially connected). In the source wiring 10, a connection region (indicated by a broken line in FIG. 1) of the third semiconductor layer 2 c serving as a source is provided in the source wiring 10. In addition to the third semiconductor layer 2c serving as a source, the source wiring 10 is also electrically connected to a p + type contact layer 11 provided in the second semiconductor layer 2b in order to make the base potential constant. Yes.

  Further, as shown in FIG. 2, FIG. 3, or FIG. 4, a protection diode having a back-to-back configuration that prevents the gate insulating film 5 from being broken by a surge from the source between the gate and the source. 12 is provided. FIG. 5 is an enlarged vertical sectional view showing the protection diode 12. The protection diode 12 has n + type semiconductor regions 12a and p type semiconductor regions 12b alternately formed concentrically, and n + type semiconductor regions at both ends. The gate electrode 9 and the source line 10 are electrically connected to 12a, respectively.

  Further, on the outer periphery of the field insulating film 3, a wiring 13b using, for example, aluminum containing silicon in an n + type semiconductor region 13a provided on the main surface of the semiconductor substrate (partially indicated by a broken line in FIG. 3). The source guard ring 13 is connected, and the wiring 13 b of the source guard ring 13 is also connected to the n + -type semiconductor region 12 a of the protection diode 12, similarly to the source wiring 10.

  The gate wiring 6 and the gate guard ring 8 are provided on the field insulating film 3 provided in a rectangular ring shape, and the gate electrode 9 and the protection diode 12 are provided on a rectangular portion provided at the corner of the field insulating film 3. Is provided.

  A p-type well 14 is formed below the rectangular annular field insulating film 3, and the end of the trench gate 4 is connected to the p-type well 14 via the gate insulating film 5. Thus, the depletion layer can be gently extended under the field insulating film 3 to prevent discontinuity of the depletion layer, so that the p-type well 14 functions as an electric field relaxation portion for relaxing the electric field at the terminal end of the trench gate 4.

  The entire main surface of the semiconductor substrate covers the gate guard ring 8, the gate electrode 9, the source wiring 10, and the source guard ring 13, and is oxidized by, for example, plasma CVD using tetraethoxysilane (TEOS) gas as a main source gas. A protective insulating film 15 using a silicon film and polyimide is formed, and an opening for partially exposing the gate electrode 9 and the source wiring 10 is provided in the protective insulating film 15, and the gate electrode 9 and the source wiring exposed through the opening are provided. Reference numeral 10 denotes a connection region between the gate and the source, and electrical connection is performed to the connection region by wire bonding or the like.

  As the drain connection region, a drain electrode 16 that is electrically connected to the n + type semiconductor substrate 1 is formed on the entire back surface of the semiconductor substrate as a laminated film in which, for example, nickel, titanium, nickel, and silver are laminated. Electrical connection is made by connecting to the lead frame with a conductive adhesive.

Next, a method for manufacturing the semiconductor device described above will be described with reference to FIGS.
First, an n− type epitaxial layer 2 having a concentration lower than that of the semiconductor substrate 1 is formed to about 5 μm by epitaxial growth on an n + type semiconductor substrate 1 made of, for example, single crystal silicon into which arsenic (As) is introduced. Next, a silicon oxide film having a thickness of about 600 nm is formed on the main surface of the semiconductor substrate by, for example, a thermal oxidation method, a mask is formed on the silicon oxide film by photolithography, and the semiconductor substrate is etched by using the mask. A plate-like field insulating film 3 having a rectangular portion inside the corner is formed in a rectangular ring shape along the outer periphery of the substrate. Thereafter, a mask is formed by photolithography along the inner periphery of the field insulating film 3, and ion implantation of, for example, boron (B) using this mask is performed to diffuse the introduced impurities, thereby forming an electric field relaxation portion and A p-type well 14 is formed. This state is shown in FIG. The impurity concentration of the p-type well 14 is configured to be equal to or lower than that of the second semiconductor layer 2b, for example.

  Next, a relatively thick insulating film 17 having a thickness of about 600 nm is formed on the main surface of the semiconductor substrate by thermal oxidation, and each gate is planarly formed in a lattice shape on the insulating film 17 in the cell formation region surrounded by the field insulating film 3. A resist mask 18 of a trench gate pattern having a mesh gate structure disposed in the substrate is formed by photolithography, and an opening exposing the main surface of the semiconductor substrate of the pattern is provided by etching using the resist mask 18. FIG. 7 shows an enlarged view of the trench gate portion in this state.

  Next, using this insulating film 17 as a mask, a trench having a depth of, for example, about 1.6 μm is formed in the main surface of the semiconductor substrate by dry etching. This state is shown in FIG.

  Next, isotropic wet etching and chemical dry etching are performed on the groove formed by the dry etching, the corners of the bottom edge of the groove are relaxed, and at the same time, the side surface of the insulating film 17 is moved to the groove. Retract from the top. This state is shown in FIG.

  Next, a gate insulating film 5 is formed by laminating a silicon oxide film by CVD (Chemical Vapor Diposition) of about 50 nm on a thermal oxide film of about 27 nm. This state is shown in FIGS.

Next, a polycrystalline silicon film 4 ′ to be a conductive film for the trench gate 4 is formed by CVD on the entire main surface of the semiconductor substrate including the inside of the trench. Impurities (for example, phosphorus) for reducing the resistance value are introduced into the polycrystalline silicon film 4 'during or after the deposition. Impurity concentration and 1E18 / cm ³ to 1E21 / cm ³ order. This state is shown in FIGS.

  Subsequently, the polycrystalline silicon film 4 'is removed by etching to form a trench gate 4 in the groove. By this etching process, simultaneously, a gate wiring 6 connected to the trench gate 4 and a polycrystalline silicon film 9a serving as a base for the gate electrode 9 are formed on the rectangular portion of the field insulating film 3. This state is shown in FIGS.

  Next, the excess insulating film 17 remaining on the main surface of the semiconductor substrate is removed to expose the main surface of the semiconductor substrate. This state is shown in FIGS.

  In this state, since the insulating film 17 has receded by the isotropic etching described above, the third semiconductor layer 2c in which the gate insulating film 5 and the conductor film of the trench gate 4 serve as the source region at the periphery of the groove. On the surface of the semiconductor substrate, that is, on the main surface of the semiconductor substrate. In other words, the gate insulating film 5 and the conductor film of the trench gate 4 cover the periphery of the groove, and the trench gate 4 is provided with an eaves, and the eaves damages the gate insulating film 5 at the corner of the groove. Can be prevented. Further, since the insulating film 17 is retracted in a self-aligning manner, the periphery of the groove can be covered with a minimum size.

  Next, after an insulating film 12c made of silicon oxide is formed, a polycrystalline silicon film is deposited on the insulating film 12c, p-type impurities are introduced into the polycrystalline silicon film, and the rectangular shape of the field insulating film 3 is obtained. On the portion, patterning is performed concentrically around the polycrystalline silicon film 9a of the gate electrode 9. The insulating film 12c functions as an etching stopper for preventing the trench gate 4 and the gate wiring 6 from being patterned during the patterning. Thereafter, the n + type semiconductor region 12a is formed by ion implantation, for example, and the protection diode 12 in which the n + type semiconductor regions 12a and the p type semiconductor regions 12b are alternately formed in a concentric ring shape is formed. This state is shown in FIG.

Next, ion implantation of a p-type impurity (for example, boron) is performed on the entire surface of the epitaxial layer 2, and diffusion treatment (first heat treatment) is performed for about 100 minutes in a nitrogen gas atmosphere containing 1% O ₂ at about 1100 ° C. ) To form a p-type second semiconductor layer 2b to be a channel formation region. Subsequently, an n-type impurity (for example, arsenic) is selectively ion-implanted, and an annealing process (second heat treatment) is performed for about 30 minutes in a nitrogen gas atmosphere containing 1% O ₂ at about 950 ° C. Then, the third semiconductor layer 2c to be the source region is formed.

  In order to function as an FET, it is important that the second semiconductor layer 2b and the third semiconductor layer 2c go under the eaves of the trench gate 4 and contact the gate insulating film 5 provided in the trench. According to the present invention, in order to control the channel, the first heat treatment and the second heat treatment are performed independently as described above.

  Then, the deep part of the epitaxial layer 2 where these impurities are not introduced, specifically, the epitaxial layer 2 located between the second semiconductor layer 2b and the semiconductor substrate 1 functions as the drain region. It becomes. Note that the number of steps may be reduced by performing the n + type semiconductor region 12a by the same ion implantation process as that of the first semiconductor layer 2a. This state is shown in FIGS.

  Thus, with the upper surface of the trench gate 4 positioned above the main surface of the semiconductor substrate, the second semiconductor layer 2b serving as the channel formation region and the third semiconductor layer 2c serving as the source region are formed by ion implantation. Since the depth profile and the depth of the second semiconductor layer 2b and the third semiconductor layer 2c can be accurately controlled in the semiconductor substrate 2, the second semiconductor layer 2b and the third semiconductor layer 2c are formed. Shallow thinning can be promoted. That is, since the depth of the second semiconductor layer 2b can be accurately controlled, the channel length can be accurately controlled.

Next, for example, a BPSG film is deposited to a thickness of about 500 nm on the entire surface of the main surface of the semiconductor substrate to form an interlayer insulating film 7.
Next, an anisotropic dry etching process using CHF ₃ gas is performed to connect the interlayer insulating film 7 to the third semiconductor layer 2c serving as the source region, the gate wiring 6, the source guard ring semiconductor region 13a, and the protection diode 12. An opening CH (Contact Hole) that exposes the region is provided, a conductive film (metal film) made of aluminum containing silicon, for example, is formed on the entire main surface of the semiconductor substrate including the inside of the opening, and the metal film is patterned. The gate guard ring 8, the gate electrode 9, the source wiring 10, and the source guard ring 13 are formed. This state is shown in FIG.

  Regarding the contact layer 11, conventionally, the contact layer 11 reaching the second semiconductor layer 2 b from the surface of the main surface of the semiconductor substrate is formed, and the source wiring 10 is connected to the contact layer 11 and the third semiconductor layer 2 c surrounding the contact layer 11. . On the other hand, in the present embodiment, first, an opening CH reaching the second semiconductor layer 2b is formed by etching as shown in FIG. 22, and the second semiconductor layer 2b exposed through this opening CH as shown in FIG. A p-type impurity such as boron is directly introduced into the substrate. With this configuration, since the p-type contact layer 11 is formed deep, the avalanche resistance is improved. Since a mask for covering the contact layer 11 is not required when forming the source, the photoresist process is reduced. On the other hand, when the contact layer 11 is unnecessary in the contact portion in another opening CH due to the IC, an opening CH in which the source wiring 10 is easily electrically connected can be obtained by using another mask that covers the contact. Thus, a device having the contact layer 11 only can be formed.

  Further, as shown in FIG. 24, after the impurity introduction from the opening CH, etching for selectively removing the silicon oxide of the interlayer insulating film 7 from the silicon on the main surface of the semiconductor substrate is performed in the present embodiment. The surface of the third semiconductor layer 2c is exposed in a self-aligned manner with respect to the opening CH. As shown in FIG. 25, the contact area between the third semiconductor layer 2c and the source wiring 10 is increased by this configuration, so that the connection resistance can be reduced.

  Next, for example, polyimide is applied and laminated on a silicon oxide film formed by plasma CVD using tetraethoxysilane (TEOS) gas as the main source gas, and a protective insulating film 15 is formed to cover the entire main surface of the semiconductor substrate. An opening that exposes the connection region of the gate electrode 9 and the source wiring 10 is formed in the insulating film 15, and the back surface of the n + type semiconductor substrate 1 is ground, and nickel, titanium, nickel, silver is deposited on the back surface, for example, by vapor deposition. Sequentially stacked drain electrodes 14 are formed, resulting in the state shown in FIG.

  In the present embodiment, the p-type well 14 is provided in a rectangular ring shape as the electric field relaxation portion. However, as the electric field relaxation portion, for example, an opening is provided in the field insulating film 3 and impurities are introduced from this opening to A configuration in which the p-type wells 14 are annularly scattered under the insulating film may be employed. In this configuration, the electric field relaxation portion can be formed after the gate wiring 6 is formed.

(Embodiment 2)
FIG. 26 shows another embodiment of the present invention.
In the present embodiment, unlike the previous embodiment, the insulating film 17 is also formed by the process of forming the field insulating film 3.
Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIG.

  First, an n− type epitaxial layer 2 having a concentration lower than that of the semiconductor substrate 1 is formed to about 5 μm by epitaxial growth on an n + type semiconductor substrate 1 made of, for example, single crystal silicon into which arsenic (As) is introduced. Next, a silicon oxide film having a thickness of about 600 nm is formed on the main surface of the semiconductor substrate by, for example, a thermal oxidation method.

Next, a mask is formed on the silicon oxide film by photolithography, and the field insulating film 3 having a rectangular shape along the outer periphery of the semiconductor substrate and a rectangular portion inside the corner is formed by etching using the mask. To do. At the same time, a resist mask having a trench gate pattern having a mesh gate structure in which the gates are arranged in a grid pattern on the insulating film in the cell formation region surrounded by the field insulating film 3 is formed by photolithography. By this etching using the resist mask, an insulating film 17 having an opening exposing the main surface of the semiconductor substrate having the pattern is formed.
Subsequent steps are substantially the same as those of the embodiment shown in FIGS.

  According to the present embodiment, the number of processes can be reduced by forming the field insulating film 3 and the insulating film 17 in the same process. In this embodiment, the p-type well serving as the electric field relaxation portion is omitted. However, if necessary, for example, an opening is provided in the field insulating film 3 and impurities are introduced from this opening to be under the field insulating film. An electric field relaxation portion can be formed as a configuration in which the p-type wells 14 are scattered in a ring shape.

Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
For example, the present invention can be applied not only to a power MISFET but also to an IGBT (Integrated Gate Bipolar Transistor) or the like.

It is a top view which shows the semiconductor device which is one embodiment of this invention. 1 is an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention. It is a top view which shows the principal part of the semiconductor device which is one embodiment of this invention. It is a fragmentary longitudinal cross-sectional view along the aa line in FIG. It is a fragmentary longitudinal cross-section which shows the protection diode of the semiconductor device which is one embodiment of this invention. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the trench gate of the semiconductor device which is one embodiment of this invention for every manufacturing process. It is a longitudinal cross-sectional view which shows the principal part of the semiconductor device which is other embodiment of this invention for every manufacturing process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Epitaxial layer, 2a ... 1st semiconductor layer (drain region), 2b ... 2nd semiconductor layer (channel formation region), 2c ... 3rd semiconductor layer (source region), 3 ... Field insulating film, DESCRIPTION OF SYMBOLS 4 ... Trench gate, 5 ... Gate insulating film, 6 ... Gate wiring, 7 ... Interlayer insulating film, 8 ... Gate guard ring, 9 ... Gate electrode, 10 ... Source wiring, 11 ... Contact layer, 12 ... Protection diode, 13 ... Source guard ring, 14 ... well, 15 ... protective insulating film, 16 ... drain electrode, 17 ... insulating film, 18 ... resist mask.

Claims (12)

A semiconductor device having a MISFET formed in a first region on a semiconductor substrate and a gate wiring formed in a second region on the semiconductor substrate,
the semiconductor substrate having an n-type conductivity type;
An n-type first semiconductor layer formed on the semiconductor substrate and serving as a drain region of the MISFET;
A p-type second semiconductor layer formed on the first semiconductor layer and serving as a channel formation region of the MISFET;
An n-type third semiconductor layer formed on the second semiconductor layer and serving as a source region of the MISFET;
A first trench reaching from the upper surface of the third semiconductor layer to the first semiconductor layer in the first region;
A gate insulating film of the MISFET formed in the first trench;
A second trench formed in the second region;
A gate wiring formed inside the second trench and outside the second trench in the second region;
The gate electrode and the gate wiring are electrically connected,
An upper portion of the gate insulating layer is located on the third semiconductor layer,
The upper part of the gate electrode is located on the upper part of the gate insulating film,
An insulating film is formed in the second region;
A gate wiring formed outside the second trench is located on the insulating film. 2. The semiconductor device according to claim 1, further comprising:
An interlayer insulating film formed on the gate electrode and the gate wiring;
Having first and second conductive films formed on the interlayer insulating film;
The first conductive film is electrically connected to the second and third semiconductor layers;
The semiconductor device, wherein the second conductive film is electrically connected to the gate wiring.   3. The semiconductor device according to claim 2, wherein the insulating film is not formed in the first region.   3. The semiconductor device according to claim 2, wherein the insulating film is formed by thermal oxidation, and the interlayer insulating film is formed by CVD.   3. The semiconductor device according to claim 2, wherein the gate electrode and the gate wiring are made of the same material.   3. The semiconductor device according to claim 2, wherein the drain electrode is formed on the back surface of the semiconductor substrate.   3. The semiconductor device according to claim 2, wherein a field insulating film is formed in the second region, and a part of the gate wiring is located on the field insulating film.   3. The semiconductor device according to claim 2, wherein the semiconductor substrate includes an epitaxial layer, and the first, second, and third semiconductor layers are formed in the epitaxial layer.   9. The semiconductor device according to claim 8, wherein the upper portion of the gate insulating film is located on the upper surface of the epitaxial layer, and the upper portion of the gate electrode is located on the upper portion of the gate insulating film.   10. The semiconductor device according to claim 9, wherein the insulating film is formed on an upper surface of the epitaxial layer in the second region. A semiconductor device having a MISFET formed in a first region on a semiconductor substrate and a gate wiring formed in a second region on the semiconductor substrate,
The semiconductor substrate having a first conductivity type;
A first semiconductor layer having the first conductivity type formed on the semiconductor substrate;
A second semiconductor layer formed on the first semiconductor layer and having a second conductivity type opposite to the first conductivity type;
A third semiconductor layer having the first conductivity type formed on the second semiconductor layer;
A first trench reaching from the upper surface of the third semiconductor layer to the first semiconductor layer in the first region;
A gate insulating film of the MISFET formed in the first trench;
A gate electrode of the MISFET formed on the gate insulating film;
A second trench formed in the second region;
A gate wiring formed inside the second trench and outside the second trench in the second region;
The gate electrode and the gate wiring are electrically connected,
An upper portion of the gate insulating layer is located on an upper surface of the third semiconductor layer;
The upper part of the gate electrode is located on the upper part of the gate insulating film,
An insulating film is formed in the second region;
A gate wiring formed outside the second trench is located on the insulating film. 12. The semiconductor device according to claim 11, further comprising:
An interlayer insulating film formed on the gate electrode and the gate wiring;
Having first and second conductive films formed on the interlayer insulating film;
The first conductive film is electrically connected to the second and third semiconductor layers;
The semiconductor device, wherein the second conductive film is electrically connected to the gate wiring.

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