JP2006080594A - Timer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timer circuit capable of producing a signal for a long time in spite of a small circuit configuration. <P>SOLUTION: The timer circuit 1 used for a semiconductor integrated circuit is characterized in to include: a timer unit 2 provided with a capacitor 21 connected between an input terminal A and an output terminal B and an output side transistor 11 of a current mirror circuit 4 whose collector is connected to the capacitor 21 and the output terminal B; and a time adjustment unit 3 provided with an input side transistor 12 of the current mirror circuit and a bias circuit purpose current mirror circuit 5 acting like a time adjustment purpose constant current source connected to the collector of the input side transistor 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a timer circuit that generates a waveform that serves as a reference for time measurement in a semiconductor integrated circuit or the like.

  A semiconductor integrated circuit is often equipped with a timer circuit for generating a signal for a predetermined time. A conventional timer circuit will be described with reference to FIGS.

  As shown in FIG. 4, the conventional timer circuit 20 includes an RC circuit including a capacitor 21 and a resistor 22. When an input signal as shown in FIG. 5A is given from the input terminal A, the capacitor 21 is charged and discharged to the ground through the resistor 22. An output signal at the output terminal B is shown in FIG. When the output signal of the timer circuit 20 is input to the buffer 23 connected to the output terminal B, the buffer 23 shapes the signal with 50% of the power supply voltage as a threshold value, so that a signal with the time width T is output from the buffer 23. The The output signal of the buffer 23 is shown in FIG.

  For example, when the output signal of the buffer 23 is a pulse having a width of 100 μs using the conventional timer circuit 20 shown in FIG. 4, the capacitor 21 is set to 140 pF and the resistor 22 is set to 1 MΩ. In this way, the timer circuit 20 generates a signal for a predetermined time.

A timer circuit used in a semiconductor integrated circuit and employing a current mirror circuit is disclosed in Patent Document 1. In the timer circuit of Patent Document 1, current generating means and resistance voltage dividing means are connected to the input and output of the current mirror circuit, respectively, a capacitor is connected to the input of the current mirror circuit, and the output of each resistance voltage dividing means. It is described that it is possible to operate with a low power supply voltage by using a configuration in which each current generating means is connected.
JP-A-5-335916

  When the conventional timer circuit 20 is mounted on a semiconductor integrated circuit, for example, if the resistor 22 is 1 MΩ, an area corresponding to several tens of transistors is required.

  Since a semiconductor integrated circuit has a limited area for forming a circuit on a semiconductor, it is desirable to have a small circuit configuration even for a timer circuit that generates a signal for a long time.

  Since the timer device described in Patent Document 1 is intended for low voltage operation, the timer circuit described in Patent Document 1 cannot be adopted as a timer circuit that generates a signal for a long time.

  Accordingly, an object of the present invention is to provide a timer circuit capable of generating a signal for a long time with a small circuit configuration.

  According to the present invention, in a timer circuit used in a semiconductor integrated circuit, a capacitor connected between an input end and an output end, and an output side transistor of a current mirror circuit in which a collector is connected to the capacitor and the output end are provided. And a time adjusting unit provided with an input side transistor of the current mirror circuit and a time adjusting constant current source connected to a collector of the input side transistor.

  The timer circuit of the present invention is used in a semiconductor integrated circuit, and includes a capacitor connected between an input end and an output end, and an output side transistor of a current mirror circuit in which a collector is connected between the capacitor and the output end. By including a timer unit, a time adjustment unit having an input side transistor of the current mirror circuit, and a constant current source for time adjustment connected to the collector of the input side transistor, the time constant of the conventional timer circuit is obtained. Since the resistor to be determined can be replaced with the output side transistor of the current mirror circuit, when the output waveform of the timer circuit needs to be a waveform with a long time width, the area occupied by the semiconductor circuit of the timer circuit is reduced. can do.

  According to a first invention of the present application, in a timer circuit used in a semiconductor integrated circuit, a capacitor connected between an input end and an output end, and an output side transistor of a current mirror circuit having a capacitor and a collector connected to the output end are provided. A time adjustment unit provided with a timer unit provided and a constant current source for time adjustment connected to the input side transistor of the current mirror circuit and the collector of the input side transistor, The output side transistor of the current mirror circuit is used instead of the resistor of the conventional timer circuit. This makes it possible to easily set the time by controlling the amount of current to the input side transistor of the current mirror circuit in the case of a timer circuit that generates a signal for a long time. Since the resistor for determining the time constant can be replaced with the output side transistor of the current mirror circuit, the configuration of the timer circuit can be reduced.

  The second invention of the present application is characterized in that a new timer unit is connected so as to connect the output side transistors of the current mirror circuit in parallel, and is connected in parallel to the output side transistors of the current mirror circuit. By connecting a new timer unit as described above, the time adjustment unit can be used in common, so that even when a plurality of timer circuits are provided, the circuit configuration can be reduced.

  The third invention of the present application is characterized in that a switching element is connected between the output terminal and a ground or a power supply, and by connecting a switching element connected to the ground or the power supply to the output terminal, When the output-side transistor of the current mirror circuit is in an inoperative state, by turning on the switching element, the potential at the output end is determined to be L level or H level regardless of the signal input from the input end. Can do.

  According to a fourth aspect of the present invention, the switching element outputs when the constant current source is in an operating state, the connection between the output terminal and the ground or the power supply is turned off, and the constant current source is in an inactive state. A switching unit for turning on the connection between the end and the ground or the power source is provided, and switching elements can be easily switched.

  The fifth invention of the present application is characterized in that the constant current source is connected in common with other current mirror circuits, and the constant current source is connected in common with other current mirror circuits. Thus, the circuit configuration of the entire semiconductor integrated circuit can be made small.

  The configuration of the timer circuit according to the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a diagram for explaining the configuration of a timer circuit according to an embodiment of the present invention.

  In the present embodiment, an example in which the timer circuit 1 outputs a signal serving as a reference of 100 μs will be described.

  A timer circuit 1 according to an embodiment of the present invention is formed as a part of a semiconductor integrated circuit, and includes a timer unit 2 and a time adjustment unit 3.

  In the timer unit 2, the capacitor 21 connected between the input terminal A and the output terminal B, and the collector of the output side transistor 11 of the current mirror circuit 4 are connected to the capacitor 21 and the output terminal B.

  A waveform shaping buffer 23 is connected to the output terminal B of the timer circuit 1.

  The buffer 23 has a function of shaping and outputting a signal input from the output terminal B with a signal waveform shaped using 50% of the power supply voltage as a threshold value. The power supply voltage of the buffer 23 is 5.0V.

  The capacitor 21 is provided to have a capacity of 10 pF.

  In the time adjustment unit 3, a bias circuit current mirror circuit 5, which is a constant current source for time adjustment, is connected to the collector of the input side transistor 12 of the current mirror circuit 4.

  The current mirror circuit 4 has a function of flowing a current comparable to the current flowing from the collector of the input side transistor 12 to the emitter from the collector of the output side transistor 11 to the emitter.

  The bias circuit current mirror circuit 5 supplies a bias current of the current mirror circuit 4 and other circuit blocks, and the transistor 15 of the bias circuit current mirror circuit 5 functions to flow the base current of the current mirror circuit 4. The current is supplied to the input side transistor 12 via the collector of the transistor 15. Many semiconductor integrated circuits are equipped with a circuit that constitutes a current mirror circuit or the like, and therefore this bias circuit current mirror circuit 5 is mounted. Therefore, the circuit configuration can be reduced by providing the timer circuit 1 of the present embodiment in addition to the bias circuit current mirror circuit 5 used for these.

  Since a current of about 0.25 μA is supplied from the current mirror circuit 5 for the bias circuit to the input side transistor 12 of the current mirror circuit 4, only the same level of current flows through the collector of the output side transistor 12. That is, by limiting the current flowing from the capacitor 21 to the output-side transistor 12, an equivalent circuit in which the output-side transistor 12 has a high resistance can be obtained. The time setting of the timer circuit 1 can be determined by the amount of current supplied from the bias circuit current mirror circuit 4 to the input side transistor 12 of the current mirror circuit 3.

  Further, a MOS transistor 13 as a switching element is connected between the output terminal B and the ground. In this embodiment, the MOS transistor 13 is connected between the output terminal B and the ground. However, since it is sufficient that the potential of the output terminal B can be determined, a switching element is connected between the output terminal and the power source. May be.

  By controlling the gate of the MOS transistor 13, the potential of the output terminal B can be determined. This is because current supply from the bias circuit current mirror circuit 4 to the input side transistor 12 of the current mirror circuit 3 is stopped when the entire semiconductor integrated circuit is set to the power saving mode, and the output side transistor 11 is OFF. This is to prevent the potential at the output terminal B from becoming unstable due to the state.

  More specifically, in the state in which the timer unit 2 is operated, if the gate voltage is such that the MOS transistor 13 is turned off, no current flows from the drain connected to the output terminal B to the source, and the output terminal B There is no impact on Accordingly, a current flows from the capacitor 21 to the output side transistor 11, and the waveform is shaped by the buffer 23. On the other hand, when the entire semiconductor integrated circuit is in the power saving mode and the output side transistor 11 is in an OFF state, a current flows from the drain to the source by applying a gate voltage for turning on the MOS transistor 13. The potential of the output terminal B can be determined by the potential of the voltage drop of the MOS transistor 13.

  In order to determine the potential of the output terminal B, the switching unit 6 that controls the switching operation of the MOS transistor 13 is connected to the gate of the MOS transistor 13.

  The switching unit 6 turns off the connection between the output terminal B and the ground when the MOS transistor 13 is in the operating state, and the bias circuit current mirror circuit 5 is in the non-operating state. In this case, the connection between the output terminal B and the ground is turned on.

  The switching unit 6 is connected to the constant current source 16 connected to the base of the transistor 15, the switch 17 for switching the connection between the constant current source 16 and the transistor 15, and connected to the switch 17 so that the ground and the pull are connected. A switch 18 for connecting to the up resistor 19 is provided. The gate of the MOS transistor 13 is connected between the switch 18 and the pull-up resistor 19. The switches 17 and 18 can be composed of MOS transistors or the like.

  The switching operation between the switch 17 and the switch 18 is controlled by inputting a signal from an enable terminal E provided as an external terminal of the semiconductor integrated circuit. When the L signal is input from the enable terminal E, the switches 17 and 18 are turned ON (connected state), and when the H signal is input, the switches 17 and 18 are turned OFF (not connected state).

  The operation of the timer circuit according to the embodiment of the invention configured as described above will be described with reference to FIGS. FIG. 2 is a waveform diagram for explaining the operation of the timer circuit according to the embodiment of the present invention. (A) is a diagram showing an input waveform, (b) is a diagram showing an output waveform, and (c) is a buffer. It is a figure which shows the waveform output via.

  First, the gate voltage at which the MOS transistor 13 is turned off is set, and the current mirror circuit 4 for bias circuit is set so that the current supplied to the input side transistor 12 of the current mirror circuit 3 is about 0.25 μA.

  Then, the L signal is input from the enable terminal E. The switches 17 and 18 are connected, the bias circuit current mirror circuit 5 is in an operating state, and the gate of the MOS transistor 13 is short-circuited to the ground by the switch 18, so that the MOS transistor 13 is turned off. Therefore, there is no influence on the output terminal B by the MOS transistor 13.

  A signal having a waveform as shown in FIG.

  The signal input from the input terminal A is charged to the capacitor 21 and the potential of the output terminal B rises. At the same time, the collector current of the output side transistor 11 of the current mirror circuit 3 starts to flow.

  The current mirror circuit 3 has a function of causing a current approximately equal to the current flowing through the collector of the input side transistor 12 to flow through the collector of the output side transistor 11. Since the current supplied from the current mirror circuit 4 for the bias circuit is set to be about 0.25 μA, the current flowing through the collector of the output side transistor 11 is also about 0.25 μA. That is, it is almost equivalent to connecting a 10 MΩ resistor between the collector and emitter of the output side transistor 11.

  The waveform of the signal at the output terminal B at this time is shown in FIG. Thus, the output waveform at the output terminal B is a waveform indicating a transient phenomenon.

  Since the current flowing through the output-side transistor 11 is limited by the bias circuit current mirror circuit 4, the voltage at the output terminal B decreases linearly. Since the buffer 23 outputs a waveform with a threshold value of 50% of the power supply voltage, the output waveform of the buffer 23 is a pulse having a width of 100 μs, which is a time T shown in FIG.

  Therefore, since the timer circuit 1 shown in FIG. 1 is equivalent to the timer circuit 20 shown in FIG. 4, the output waveforms shown in FIG. 2B and FIG. Also, the output waveform of the conventional timer circuit 20 shown in FIG.

  Next, an H signal is input from the enable terminal E. The switches 17 and 18 are disconnected from each other, the bias circuit current mirror circuit 5 is deactivated, and the gate of the MOS transistor 13 is set to the power supply voltage by the pull-up resistor 19. As a result, the MOS transistor 13 is turned on. Therefore, since the output terminal B is connected to the ground by the MOS transistor 13, the potential of the output terminal B is almost the ground potential.

  In the present embodiment, the output of the timer circuit 1 is set to 100 μs, but this time is appropriately determined by the capacity of the capacitor 21 and the current value supplied from the current mirror circuit 4 for the bias circuit that is a constant current source. Can do.

  Next, a timer circuit according to another embodiment of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing a timer circuit according to another embodiment of the present invention. In FIG. 3, the same components as those in FIG.

  As shown in FIG. 3, the timer circuit 7 is connected to a new timer unit 8 so that the output side transistors 11 of the current mirror circuit 4 are connected in parallel.

  The timer unit 8 can have the same configuration as the timer unit 2, and it is also possible to output waveforms at different times by changing the capacitance of the capacitor 14 of the timer unit 8 with the capacitance of the capacitor 21. .

  In FIG. 3, the newly added timer circuit 8 is one circuit, but two or more circuits may be used. Therefore, by providing one circuit for the time adjusting unit 3, a plurality of timer units can be easily provided.

  In the present invention, when the output waveform needs to be a long time, the area of the timer integrated circuit can be reduced, so that the timer circuit for generating a waveform for a predetermined time in the semiconductor integrated circuit or the like It is suitable for.

The figure which shows the timer circuit which concerns on embodiment of this invention It is a wave form diagram explaining operation | movement of the timer circuit which concerns on embodiment of this invention, (a) is a figure which shows an input waveform, (b) is a figure which shows an output waveform, (c) is output via a buffer. Diagram showing the waveform The figure which shows the timer circuit which concerns on other embodiment of this invention. The figure which shows the conventional timer circuit It is a wave form diagram explaining operation | movement of the conventional timer circuit, (a) is a figure which shows an input waveform, (b) is a figure which shows an output waveform, (c) is a figure which shows the waveform output through the buffer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,7 Timer circuit 2,8 Timer part 3 Time adjustment part 4 Current mirror circuit 5 Current mirror circuit 5 for bias circuits 6 Switching part 11 Output side transistor 12 Input side transistor 13 MOS transistor 14, 21 Capacitor 15 Transistor 16 Constant current source 17 , 18 Switch 19 Pull-up resistor 23 Buffer

Claims (5)

In a timer circuit used in a semiconductor integrated circuit,
A timer unit provided with a capacitor connected between an input terminal and an output terminal, and an output side transistor of a current mirror circuit having a collector connected to the capacitor and the output terminal;
A timer circuit comprising: a time adjustment unit provided with an input side transistor of the current mirror circuit and a constant current source for time adjustment connected to a collector of the input side transistor. 2. The timer circuit according to claim 1, wherein a new timer unit is connected so as to connect the output side transistors of the current mirror circuit in parallel. The timer circuit according to claim 1, wherein a switching element is connected between the output terminal and a ground or a power source. The switching element turns off the connection between the output terminal and the ground or the power supply when the constant current source is in an operating state, and turns off the output terminal and the power supply when the constant current source is in a non-operating state. 4. The timer circuit according to claim 3, further comprising a switching unit for turning on the connection with the ground or the power source. 5. The timer circuit according to claim 1, wherein the constant current source is connected in common with another current mirror circuit. 6.

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