JP2006065916A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which realizes development of product variety of memory products to be simplified and the cost therefor to be reduced. <P>SOLUTION: A regulator 10 and a memory chip 11 are combined and packaged, for example, into one package, and the regulator 10 is provided with a function in which a power supply voltage value specified among a plurality of power supply voltage values beforehand is outputted to the memory chip 11 even though any power supply voltage values are inputted among the plurality of power supply voltage values that can be taken when the memory chip 11 is subjected to development of product variety. Thus, development of product variety including a plurality of power supply voltage specifications can be satisfied by developing and manufacturing only the chip memory 11 which operates by one specified power supply voltage value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly, to a technology effective when applied to a semiconductor device including a memory product in which a plurality of product types are developed.

  According to a study by the present inventor, the followings can be considered as a technology for developing the types of memory products.

  For example, when developing a variety of memory products, a memory chip (referred to as a developed product) in which the bit configuration or power supply voltage specification is changed based on a certain memory chip (referred to as a base product) is usually developed. As a result, in one memory product, for example, there are three bit configurations (4 bits / 8 bits / 16 bits, etc.) and three power supply voltage specifications (2.5 V / 1.8 V / 1. There are as many memory chips as a combination of 5V and the like.

  The type development of the bit configuration is normally realized by switching the wiring layer pattern on the upper layer of the memory chip, and the type development of the power supply voltage specification is realized, for example, by changing parameters of a circuit or a process. Such a variety development is an indispensable technology for meeting various demands and applications in the market.

  By the way, as a result of the study of the present inventor on the technology for developing the types of memory products as described above, the following has been clarified.

  For example, when developing a variety of memory products, there are many development products as described above, and therefore it is necessary to individually develop and manufacture memory chips corresponding to each development product. If it does so, the cost required for the design development and process development of each deployment product, and various manufacturing costs will increase. The manufacturing cost includes, for example, a cost required for manufacturing a photomask, a time cost (manufacturing time for changing manufacturing conditions, a waiting time in a process, etc.), and a loss due to overproduction.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can simplify the development of memory product types and reduce costs.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention has a power supply terminal and operates at a predetermined power supply voltage value, and any power supply voltage value among a plurality of power supply voltage values that can be taken when the memory chip is developed. The power supply voltage conversion means for outputting the specific power supply voltage value to the power supply terminal of the memory chip even when the power is input.

  That is, by using a combination of means for converting an external power supply voltage into a single power supply voltage and a memory chip that operates with this single power supply voltage, only a memory chip that operates with a single power supply voltage can be used. By developing and manufacturing, it is possible to easily develop the power supply voltage specifications. And it becomes possible to reduce the development cost associated with the development of varieties and the production cost associated with the production of various varieties.

  Here, the specific power supply voltage value is preferably the lowest value among a plurality of power supply voltage values that can be taken when the product is developed. That is, as the power supply voltage conversion means, for example, when a series regulator or a DC-DC converter that steps down the input voltage and outputs it is used, the power supply voltage value of the memory chip is the lowest among the power supply voltage values accompanying the product development. Must be set to a value.

  In addition, the memory chip and the power supply voltage conversion unit can be independent chips. As a result, the memory chip and the power supply voltage conversion means can be combined flexibly, and there is no need to increase the area of the memory chip itself.

  Further, in the semiconductor device according to the present invention, the memory chip is supplied with the specific power supply voltage value by the first power supply terminal, and inputs / outputs signals to / from the outside, and the second power supply terminal And a memory unit that includes a memory element and a drive circuit for the memory element, and that inputs and outputs signals to and from the interface unit, wherein the power supply voltage conversion means includes a first power supply voltage conversion unit, The first power supply voltage converting means for outputting to the second power supply terminal and the second power supply voltage converting means for outputting to the second power supply terminal are provided.

  As a result, the current load on each power supply voltage conversion means can be reduced, and noise generated in each of the interface unit and the memory unit can be separated, so that the quality and stability of the power supply voltage can be improved.

  In the semiconductor device according to the present invention, the memory chip and the power supply voltage conversion unit are mounted in one package. As a result, it is possible to provide a product including a plurality of power supply voltage specifications as a packaged memory product.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By combining the means for converting an external power supply voltage into a single power supply voltage and a memory chip that operates with this single power supply voltage, it is possible to simplify the development of memory product types and reduce costs. it can.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a conceptual diagram showing an example of the configuration of a semiconductor device according to an embodiment of the present invention. The semiconductor device shown in FIG. 1 includes a regulator 10 and a memory chip 11. The regulator 10 is, for example, a DC-DC converter or the like, and the plurality of power supply voltages in advance, regardless of which power supply voltage value is input among a plurality of power supply voltage values that can be taken when the memory chip 11 is developed. A function of outputting one power supply voltage value specified from the values to the memory chip 11 is provided.

  The memory chip 11 operates with this specified one power supply voltage value, and can adopt a plurality of bit configurations as the product is developed, but the power supply voltage value has a single specification. In other words, when developing the product type, the memory chip 11 with the bit configuration developed is developed using the memory chip 11 that operates with the specified one power supply voltage value as the base product, but the memory chip 11 with the developed power supply voltage specification is developed. Do not develop. As the memory chip 11, for example, a RAM such as a DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), a flash memory, an EEPROM (Electrically Erasable Programmable ROM), or the like. There are various things.

  In FIG. 1, for example, a memory chip 11 having a power supply voltage specification of 1.5 V with a 16-bit bit configuration has been developed, and further a 4-bit configuration and 8-bit configuration memory chip 11 in which the bit configuration is expanded. Develop. Then, by using the regulator 10 as a developed product of the power supply voltage specification, for example, three specifications of 1.5V / 1.8V / 2.5V are provided.

  Thus, in the prior art, it was necessary to develop nine types of memory chips with three types of bit configurations and three types of power supply voltage specifications. However, three types of bit configurations differing by using the configuration of FIG. Only the memory chip needs to be developed. Therefore, it is possible to simplify the product development and reduce the cost of design development and process development for each product. Further, since the number of varieties to be manufactured is reduced, the manufacturing cost can be reduced by improving the manufacturing efficiency.

  FIG. 2 is a conceptual diagram showing an example of a configuration different from FIG. 1 in the semiconductor device according to the embodiment of the present invention. In FIG. 2, for example, the memory chip 21 includes a memory unit 21a that operates with an external power supply VDD and an input / output unit 21b that operates with an external power supply VDDQ. The external power supply of the memory unit 21a and the input / output unit 21b Regulators (1) 20a and (2) 20b are provided for each of the external power supplies.

  The memory unit 21a includes a large number of memory elements that store information and their drive circuits. The input / output unit 21b is a so-called input / output interface, receives an external signal and inputs it to the memory unit 21a, and receives a signal from the memory unit 21a and outputs it to the outside.

  The functions of the regulators (1) 20a and (2) 20b are the same as those described above with reference to FIG. As an example, as shown in FIG. 2, the regulator (1) 20a receives a power supply voltage of 2.5 V from the outside, supplies a power supply voltage of 1.5 V to the memory unit 21a, and the regulator (2) 20b also Similarly, a power supply voltage of 2.5V is input from the outside, and a power supply voltage of 1.5V is supplied to the input / output unit 21b.

  Thus, by providing a regulator for each of the memory unit 21a and the input / output unit 21b, it is possible to disperse the current load of each regulator and to reduce the occurrence of noise due to voltage drop or the like. . In addition, since noise generated in the memory unit 21a and noise generated in the input / output unit 21b can be separated, it is possible to suppress the occurrence of malfunction due to power supply noise.

  By the way, for example, a regulator as shown in FIG. 3 can be used as the regulator described above. 3A and 3B are schematic configuration diagrams showing an example of the configuration of the regulator in the semiconductor device according to the embodiment of the present invention. FIG. 3A is a configuration example of a series regulator, and FIG. 3B is a configuration example of a switching regulator. .

  The regulator shown in FIG. 3A is generally called a series regulator, and includes, for example, a reference voltage generation circuit 30a, an error amplification circuit 31, a control transistor 32, and resistance elements R30a and R30b. The reference voltage generation circuit 30a generates a constant reference voltage Vref (1) regardless of the input voltage by using, for example, a band gap of a bipolar transistor or a threshold voltage of a MOS transistor. The error amplification circuit 31 compares the feedback voltage Vfb (1) obtained by dividing the output voltage Vout by the two resistance elements R30a and R30b with the reference voltage Vref (1), and generates an output corresponding to the difference voltage between them. Then, the control transistor 32 is driven. The control transistor 32 generates an output voltage Vout from the input voltage Vin in accordance with the output of the error amplifier circuit 31.

  On the other hand, the regulator shown in FIG. 3B is generally called a switching regulator or a DC-DC converter. For example, a reference voltage generating circuit 30b, an error amplifying circuit 33, and a PWM (Pulse Width Modulation) controller 34 are used. And a switching transistor 35, a smoothing circuit 36, resistance elements R31a and R31b, and the like. The reference voltage generation circuit 30b and the error amplification circuit 33 have the same functions as described above. The PWM controller 34 includes, for example, a triangular wave generation circuit and a comparator, generates a switching signal whose pulse width is changed according to the output of the error amplification circuit 33, and drives the switching transistor 35 with this switching signal. The switching transistor 35 supplies the input voltage Vin to the smoothing circuit 36 according to the switching signal. The smoothing circuit 36 smoothes the voltage supplied by the switching transistor 35 by the choke coil L1, the capacitor C1, and the flywheel diode D1, and generates the output voltage Vout from the accumulated voltage of the capacitor C1.

  Each of these regulators can be reduced in size and has a function of generating a constant output voltage Vout by the ratio of two resistance elements (R30a and R30b or R31a and R31b) that divide the output voltage Vout. In other words, by defining these two resistance ratios, it is possible to cope with a plurality of power supply voltage specifications associated with the above-described product development.

  Therefore, the resistance values of the resistance elements R30a, R30b, R31a, and R31b may be variably adjusted using, for example, a fuse. As a result, it is possible to cope with the development of power supply voltage types with a single type of regulator. Moreover, as a regulator, the thing of the system which falls an input voltage and produces | generates an output voltage like FIG. 3 (a), (b) is desirable. Therefore, the memory chip developed as the base product should have the lowest power supply voltage specification.

  By the way, when the series regulator as described above is used, the output voltage Vout can be stabilized. However, when the difference between the input voltage Vin and the output voltage Vout or the output current increases, the power loss increases. On the other hand, when the switching regulator is used, the quality of the output voltage Vout is inferior to that of the series regulator, but the power loss can be reduced. Therefore, although the outer shape becomes slightly larger, it is possible to improve the stability of the output voltage and the power loss by using a configuration in which a series regulator is connected after the switching regulator as described above.

  In addition to those described here, regulators of various configurations are known, and there are applications suitable for each. Therefore, depending on the specifications (electrical characteristics, area, etc.) of the memory chip, Choose the best one.

  Next, a mounting form of the memory chip and the regulator as described in FIGS. 1 to 3 will be described.

  FIG. 4 is a perspective view showing an example of a package form in a semiconductor device according to an embodiment of the present invention, and FIGS. 4A and 4B show cases where regulators are mounted differently. is there. 4A and 4B exemplify a case of a package such as BGA (Ball Grid Array) and CSP (Chip Size Package).

  In FIG. 4A, a memory chip 41a and a regulator 40a are mounted in separate areas on a substrate 42a provided with solder balls 43a at the bottom. The signal electrode pads on the memory chip 41a are connected to the substrate 42a by bonding wires 44a, and are connected to the solder balls 43a via wiring in the substrate 42a. An external power supply voltage is input to the regulator 40a from the solder ball 43a via the wiring in the substrate 42a and the bonding wire 47a, and the output voltage of the regulator 40a is applied to the power supply electrode pad (power supply terminal) on the memory chip 41a. Is supplied via the bonding wire 46a. The memory chip 41a, the regulator 40a, the bonding wires 44a, 46a, 47a and the like are protected by being covered with the resin 45a.

  On the other hand, in FIG. 4B, a memory chip 41b is mounted on a substrate 42b having solder balls 43b in the lower part. The signal electrode pads on the memory chip 41b are connected to the substrate 42b by bonding wires 44b, and are connected to the solder balls 43b via wiring in the substrate 42b. A regulator 40b is mounted on the memory chip 41b. An external power supply voltage is input to the regulator 40b from the solder ball 43b through the wiring in the substrate 42b and the bonding wire 47b. The output voltage of the regulator 40b is applied to the power supply electrode pad on the memory chip 41b. Is supplied through. The memory chip 41b, the regulator 40b, the bonding wires 44b, 46b, 47b and the like are protected by being covered with the resin 45b.

  As described above, when there is a margin on the board or when the board space can be expanded, mounting as shown in FIG. 4A is performed. Implementation as shown in FIG. Here, the electrode pads on the memory chip and the regulator are connected to the substrate by bonding wires. However, after the bump electrodes are formed on the memory chip and the regulator, they are connected to the substrate by flip-chip connection. It is also possible to supply the output voltage to the memory chip by wiring on the substrate.

  FIG. 5 is a perspective view showing an example of a package form different from that in FIG. 4 in the semiconductor device according to the embodiment of the present invention, and FIGS. Is shown. 5A and 5B exemplify the case of TSOP (Thin Small Outline Package).

  In FIG. 5A, a memory chip 51a and a regulator 50a are mounted in separate areas on the tab 52a, respectively. Signal electrode pads on the memory chip 51a are connected to leads 53a by bonding wires 54a. An external power supply voltage is input to the regulator 50a from the lead 53a via the bonding wire 57a, and the output voltage of the regulator 50a is supplied to the electrode pad for power supply on the memory chip 51a via the bonding wire 56a. The memory chip 51a, the regulator 50a, the bonding wires 54a, 56a, 57a and the like are protected by being covered with the resin 55a.

  On the other hand, in FIG. 5B, the memory chip 51b is mounted on the tab 52b. The signal electrode pads on the memory chip 51b are connected to the leads 53b by bonding wires 54b. A regulator 50b is mounted on the memory chip 51b. An external power supply voltage is input to the regulator 50b from the lead 53b via the bonding wire 57b, and the output voltage of the regulator 50b is supplied to the electrode pad for power supply on the memory chip 51b via the bonding wire 56b. The memory chip 51b, the regulator 50b, the bonding wires 54b, 56b, 57b and the like are protected by being covered with the resin 55b.

  As described above, when the space on the tab has a margin or when the tab space can be expanded, the mounting as shown in FIG. 5A is performed. Implementation as shown in FIG. Note that a similar mounting form is used in the case of SOJ (Small Outline J-leaded) or the like.

  FIG. 6 is a plan view showing an example of the mounting form of the semiconductor device according to the embodiment of the present invention. The semiconductor device shown in FIG. 6 is, for example, a memory module. A plurality of memory chips 61 and a regulator 60 are mounted on the module substrate 62. The external power supply voltage supplied to the module substrate 62 is input to the regulator 60, and the output voltage of the regulator 60 is distributed by wiring on the module substrate 62 and input to the power supply terminals of the plurality of memory chips 61.

  As described above, the power supply voltage specifications outside the product (outside of the memory product and outside of the memory module product) can be obtained even when the memory chip has a single power supply voltage specification by using the mounting form described in FIGS. It is possible to provide a plurality of types. That is, product development is facilitated, and cost reduction as described above can be realized. Further, for example, even when there is a sudden demand for a power supply voltage specification from a customer, it becomes possible to easily and quickly respond by combining a memory chip and a regulator.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the description so far, the memory chip and the regulator are treated as separate chips, but it is also possible to incorporate a regulator for the above-described purpose as a partial circuit in the memory chip.

  The semiconductor device of the present invention is particularly useful when applied to a single memory product in which product development is performed. Furthermore, the present invention is not limited to this, and the memory device in general includes a memory module product including a plurality of memory chips. Widely applicable to.

1 is a conceptual diagram showing an example of the configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a conceptual diagram showing an example of a configuration different from FIG. 1 in the semiconductor device according to the embodiment of the present invention. In the semiconductor device by one embodiment of this invention, it is the structure schematic which shows an example of a structure of a regulator, (a) is a structural example of a series regulator, (b) is a structural example of a switching regulator. In the semiconductor device by one embodiment of this invention, it is a perspective view which shows an example of the package form, (a), (b) shows the case where the mounting form of a regulator differs, respectively. FIG. 5 is a perspective view showing an example of a package form different from that in FIG. 4 in the semiconductor device according to the embodiment of the present invention, and FIGS. is there. In the semiconductor device by one embodiment of this invention, it is a top view which shows an example of the mounting form.

Explanation of symbols

10, 20a, 20b, 40a, 40b, 50a, 50b, 60 Regulator 11, 21, 41a, 41b, 51a, 51b, 61 Memory chip 21a Memory unit 21b Input / output unit 30a, 30b Reference voltage generation circuit 31, 33 Error amplification Circuit 32 Control transistor 34 PWM controller 35 Switching transistor 36 Smoothing circuit 42a, 42b Substrate 43a, 43b Solder ball 44a, 44b, 46a, 46b, 47a, 47b, 54a, 54b, 56a, 56b, 57a, 57b Bonding wire 45a, 45b , 55a, 55b Resin 52a, 52b Tab 53a, 53b Lead 62 Module board R30a, R30b, R31a, R31b Resistance element L1 Choke coil D1 Flywheel diode C1 Conde Support

Claims (5)

A memory chip that includes a power supply terminal and operates at a predetermined power supply voltage value;
A power supply that outputs the specific power supply voltage value to the power supply terminal of the memory chip, regardless of which power supply voltage value is input among a plurality of power supply voltage values that can be taken when the memory chip is developed. A semiconductor device comprising voltage conversion means. The semiconductor device according to claim 1,
The specific power supply voltage value is the lowest value among a plurality of power supply voltage values that can be taken when the product is developed. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the memory chip and the power supply voltage converting means are independent chips. The semiconductor device according to claim 3.
The memory chip is
An interface unit that is supplied with the specific power supply voltage value by a first power supply terminal and inputs / outputs a signal to / from the outside;
The specific power supply voltage value is supplied by a second power supply terminal, includes a memory element and a drive circuit for the memory element, and includes a memory unit that inputs and outputs signals to and from the interface unit
The power supply voltage conversion means is
First power supply voltage conversion means for outputting to the first power supply terminal;
A semiconductor device comprising: a second power supply voltage conversion means for outputting to the second power supply terminal. The semiconductor device according to claim 3.
The semiconductor device, wherein the memory chip and the power supply voltage conversion means are mounted in one package.

Images