JP2005327972A - Thin-film multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film multilayer wiring board high in electric signal transmission speed and in mechanical strength with a pattern thereon processable with high precision. <P>SOLUTION: For the formation of the thin-film multilayer wiring board, at least two wiring layers are formed on either or both sides of a first insulating layer-made inner board with second insulating layers sandwiched between. The first insulating layer 11 is formed of an insulating material having a Young's modulus of ≥5,000 MPa and a breaking strength of ≥400 MPa. The second insulating layers 51a are formed of insulating materials each having a Young's modulus of ≤2,500 MPa, a dielectric constant of ≤2.9 at 1 GHz, a dielectric dissipation factor of ≤0.01, and a water absorption coefficient of ≤0.3%. Each of second insulating layers 51a has a surface roughness Ra of ≥0.01 μm but ≤0.2 μm. Side faces of the first insulating layer 11 on the periphery of the thin-film multilayer wiring board is coated with resin 51 comprising the second insulating layers 51a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer printed wiring board, and more particularly to a thin film multilayer wiring board formed with a wiring layer having a layer thickness of 12 μm or less capable of high-density mounting.

The performance of portable electronic devices such as mobile devices has been remarkably improved, and various devices have been applied to the substrates used therefor in order to meet the demands for speeding up, thinning, high integration, and weight reduction. As such a thin film multilayer wiring board,
(A) Build-up type high-density wiring board (b) Film laminated high-density wiring board (c) Build-up type high-density wiring board on a metal plate.

  In the build-up type high density wiring board (a), as shown in FIG. 8, on the core substrate 110 in which the wiring layer 102 and the through hole 101 are formed on both surfaces of the insulating base material 111 in which a glass cloth is impregnated with an epoxy resin. In general, a thin-film multilayer wiring board by a build-up method in which an insulating layer 112 and an insulating layer 113 are stacked on each other, and wiring layers and vias are formed and sequentially stacked. A method is known in which the core substrate 110 and the insulating layers 112 and 113 are made as thin as possible to satisfy a reduction in thickness and weight, and further, an insulating material is made of a low dielectric constant material to achieve high speed. (For example, refer to Patent Document 1).

  Moreover, in the film lamination type high density wiring board of (b), as shown in FIG. 9, after forming a wiring pattern on both surfaces of a thinner resin with a double-sided copper foil, for example, a polyimide substrate 311 with a double-sided copper foil, A polyimide 312 with a single-sided copper foil is laminated via an adhesive layer 321 such as a prepreg. Thereafter, there is a method of forming a thin film multilayer wiring board by forming a wiring pattern 332 and a solder resist pattern 351 and forming a flip chip pad 341 and a BGA pad 342 (see, for example, Patent Document 2).

  Furthermore, in the build-up type high density wiring board on the metal plate of (c), as shown in FIG. 10A, after the electrode pad 421 is formed on the metal plate 410, the insulating layer 411, the via 422, By sequentially repeating the formation of the wiring layer 423 and finally removing the metal plate 410 by etching, the BGA pad 421 is formed on one surface of the insulating layer (insulating base material) 411 as shown in FIG. There is known a method of manufacturing a thin film multilayer wiring board in which a via 422, a wiring layer 423, a via 424, a wiring layer 425, a solder resist pattern 441 and a flip chip pad 431 are formed.

  However, since the build-up type high-density wiring board (a) includes a core substrate in which a glass cloth is impregnated with an epoxy resin, the entire substrate cannot be reduced in dielectric constant, and the thickness of the substrate can be reduced. However, it cannot be made thinner, and the wiring length becomes longer, resulting in higher conductor loss. This is not preferable for high-speed transmission of electrical signals. Further, the surfaces of the insulating layer 111, the insulating layer 112, and the insulating layer 113 have a surface roughness on the order of several μm in order to ensure the adhesion of the wiring layer by the anchoring effect. In the case of pattern processing by etching, there is a problem that the wiring processing accuracy (particularly linearity) is affected, and at the same time, the transmission characteristics of electric signals in a high frequency region are deteriorated.

  In the film-laminated high-density wiring board of (b), polyimide having a dielectric constant lower than that of epoxy can be used, but since it has an adhesive layer, the water absorption rate of the resin itself with this part and the double-sided copper foil itself is high, resulting in environmental fluctuations. As a result, there is a problem that the electrical characteristics of the insulating material fluctuate and the reliability is lowered. In addition, after forming the second insulating layer 312, when the shape inspection of the wiring layer of the inner substrate is performed with a CCD camera, Since the light transmittance of the polyimide insulating layer is low, a good contrast of the wiring layer of the inner substrate cannot be obtained, and the predetermined inspection accuracy of the shape inspection of the wiring layer of the inner substrate using a CCD camera cannot be obtained. is there.

In the build-up type high density wiring board on the metal plate of (c), an insulating material having a low water absorption and a low dielectric constant, for example, benzocyclobutene (BCB) can be used. In order to obtain adhesion, the surface of the insulating layer is roughened, and there is a problem that the wiring processing accuracy deteriorates. Moreover, since such a material has remarkably inferior mechanical strength as compared with polyimide, there is a problem that the substrate is likely to crack.
Japanese Patent No. 3050807 JP 2002-319762 A

  The present invention has been devised in view of the above problems, and an object of the present invention is to provide a thin-film multilayer wiring board having high-speed transmission characteristics of electric signals and mechanical strength of a substrate and having excellent pattern processing accuracy.

  To achieve the above object, according to the first aspect of the present invention, in claim 1, at least two or more wiring layers are formed on one side or both sides of the inner layer substrate made of the first insulating layer via the second insulating layer. In the multilayer wiring board, the first insulating layer is made of an insulating material having a Young's modulus of 5000 MPa or more and a breaking strength of 400 MPa or more.

  In the present invention, the second insulating layer has a Young's modulus of 2500 MPa or less, a dielectric constant at 1 GHz of 2.9 or less, a dielectric loss tangent of 0.01 or less, and a water absorption of 0.3%. The thin film multilayer wiring board is characterized by being composed of the following insulating material.

  The thin film multilayer wiring board according to claim 1 or 2, wherein the surface roughness Ra of the second insulating layer is 0.01 µm or more and 0.2 µm or less. is there.

  According to a fourth aspect of the present invention, the thin film multilayer wiring board according to any one of the first to third aspects is characterized in that the second insulating layer is a thermosetting resin.

  The thin film multilayer wiring board according to any one of claims 1 to 4, wherein the second insulating layer has a light transmittance of not less than 85% at 400 nm to 700 nm. It is a thing.

  Furthermore, in claim 6, the side surface of the first insulating layer at the periphery of the thin film multilayer wiring board according to any one of claims 1 to 5 is covered with a resin made of the second insulating layer. The thin film multilayer wiring board is characterized by the above.

  According to the present invention, an insulating material having a Young's modulus of 5000 MPa or more and a breaking strength of 400 MPa or more is used as the first insulating layer 11, and the first insulating layer (inner layer substrate) has a low dielectric constant, a low dielectric loss tangent, and a low water absorption. High-reliability thin-film multilayer can secure the mechanical strength of the thin-film multilayer substrate and reduce the fluctuation of electrical characteristics due to environmental fluctuations. A substrate can be obtained.

  Further, by smoothing the second insulating layer, the pattern processing accuracy is improved and the high-speed transmission characteristic of the electric signal is improved.

  Furthermore, by setting the light transmittance at 400 nm to 700 nm of the second insulating layer to 85% or more, the shape of the wiring layer of the inner substrate can be inspected through the second insulating layer using a CCD camera. Inspection accuracy is improved.

  Hereinafter, embodiments of the present invention will be described.

  One embodiment of the thin film multilayer wiring board of the present invention is shown in FIG. The thin film multilayer wiring board 100 of the present invention has a wiring layer 24 and a wiring layer 21a, a second insulating layer 51a, a wiring layer 26a and a wiring layer 26b, a solder resist 61, a flip chip on both surfaces of the inner layer substrate made of the first insulating layer 11. Pads 28 and BGA pads 29 are sequentially formed. The wiring layer 24 and the wiring layer 21a are filled via 23, the wiring layer 24 and the wiring layer 26a are filled via 27, and the wiring layer 21a and the wiring layer 26b are The via 27 is electrically connected, and the side surface of the thin film multilayer wiring board is covered with the resin 51 of the second insulating layer 51a.

  In the invention according to claim 1, an insulating material having a Young's modulus of 5000 MPa or more and a breaking strength of 400 MPa or more is used as the inner layer substrate, that is, the first insulating layer 11. By using such a tough material, a thin film is obtained. The mechanical strength of the multilayer substrate can be secured.

  In the invention according to claim 2, as the second insulating layer 51a, an insulating material having a Young's modulus of 2500 MPa or more, a dielectric constant of 2.9 or less at 1 GHz, a dielectric loss tangent of 0.01 or less, and a water absorption of 0.3% or less. It has a configuration using. Here, the water absorptivity is a water absorptivity according to JISK 7209-2000, and the measurement conditions are measured after drying at 100 ° C. for 24 hours, cooling to room temperature. Furthermore, the test piece is taken out after being immersed in distilled water at 23 ° C. for 24 hours, and the test is performed by the A method in which moisture is wiped off and measured.

  By using an insulating material having a low dielectric constant and a low dielectric loss tangent on the outer side of the inner layer substrate, that is, the first insulating layer 11, the high-speed transmission characteristic of the electric signal is improved. Furthermore, by using an insulating material having a low water absorption rate, moisture absorbed in the first insulating layer can be suppressed, fluctuations in electrical characteristics due to environmental fluctuations can be suppressed, and a highly reliable multilayer substrate can be obtained. It is a thing.

  In the invention according to claim 3, the surface roughness Ra of the second insulating layer is 0.01 μm or more and 0.2 μm or less, more preferably 0.03 μm or more and 0.1 μm or less, whereby the wiring layer is etched. In addition to improving accuracy, the high-speed transmission characteristics of electrical signals are improved. Here, the surface roughness Ra is an arithmetic average roughness according to JIS standard B0601-1994, and specifically, measured with an AFM (atomic force microscope) NV-3000 (manufactured by Olympus). The measurement conditions are a scanning range of 120 mm square, 256 scanning lines, and a scanning speed of 2 seconds / line.

  Adhesion between the second insulating layer and the wiring layer is ensured to be 600 gf / cm, which is practically necessary, by introducing a compound having metal coordination ability into the surface of the insulating layer. On the other hand, if Ra is 0.2 μm or more, the etching accuracy (linearity) of the wiring layer and the high-speed transmission characteristics of electric signals are not preferable.

  In the invention which concerns on Claim 4, since the thermosetting resin is used as a 2nd insulating layer, it can laminate | stack directly on a 1st insulating layer, and it has a water absorption rate between the layers of a 1st insulating layer and a 2nd insulating layer. It is not necessary to use a highly adhesive layer, and a highly reliable thin film multilayer wiring board can be obtained.

  In the invention according to claim 5, by making the light transmittance at 400 nm to 700 nm of the second insulating layer 85% or more, it becomes possible to inspect the shape of the wiring layer through the second insulating layer using a CCD camera. The accuracy of pass / fail judgment of the inspection machine is improved.

  In the invention according to claim 6, moisture absorption from the side surface of the first insulating layer 11 of the thin film multilayer wiring board is achieved by coating the side surface portion of the first insulating layer at the periphery of the thin film multilayer wiring board with the resin made of the second insulating layer. Therefore, it is possible to reduce fluctuations in electrical characteristics due to environmental fluctuations, and to obtain a highly reliable thin film multilayer substrate.

  The coating of the second insulating layer on the peripheral side surface portion of the thin film multilayer wiring board is performed by laminating a predetermined number of cut thin film multilayer wiring boards and dipping, roller coating, vacuum laminating, etc. the resin solution of the second insulating layer The covering layer can be formed with the resin of the second insulating layer.

  FIGS. 5A to 5E show an example in which a coating layer of the second insulating layer is formed on the peripheral side surface portion of the thin film multilayer wiring board when the thin film multilayer wiring board is manufactured by the multi-sided attachment method. First, a wiring layer, a via, and the like are formed on the inner substrate composed of the first insulating layer 11 with three surfaces (see FIG. 5A), and then an opening groove is formed in the peripheral portion outside the pattern region of the imposition unit substrate. 33 is formed (see FIG. 5B).

  Next, the second insulating layer 51a is formed on the substrate by a coating method, a transfer method, a vacuum laminating method, the second insulating resin is embedded in the opening groove 33, and a wiring layer, a via, and the like are formed. An imposition thin film multilayer wiring board is produced (see FIGS. 5C and 5D). Finally, the three-sided thin film multilayer wiring board is cut to obtain a thin film multilayer wiring board in which the side surface of the first insulating layer 11 at the periphery of the thin film multilayer wiring board is covered with the resin 51 of the second insulating layer. .

  The manufacturing method of the thin film multilayer wiring board of this invention is demonstrated.

  2 (a) to (e), FIGS. 3 (f) to (j), and FIGS. 4 (k) to (m), schematic constituent parts showing an example of the method of manufacturing the thin film multilayer wiring board according to the present invention in the order of steps. A cross-sectional view is shown.

  First, a double-sided copper-clad laminate 10 in which a copper foil 21 is laminated on both sides of a first insulating layer (insulating base material) 11 made of an insulating material having a Young's modulus of 5000 MPa or more and a breaking strength of 400 MPa or more is prepared ( (See FIG. 2 (a)).

  Next, via holes 31 are formed by laser processing at a predetermined position on one side of the double-sided copper-clad laminate 10, desmear of the via holes 31, application of catalyst nuclei, and electroless copper plating are performed. In particular, it is formed (see FIG. 2B).

  Next, electrolytic copper plating is performed to form a filled via 23 and a conductor layer 22 having a predetermined thickness (see FIG. 2C).

  Next, a photosensitive layer is formed by a method such as laminating a dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 41 (see FIG. 2D).

  Next, using the resist pattern 41 as a mask, the conductor layer 22 and the copper foil 21 are etched to produce the circuit board 20 on which the wiring layer 24 and the wiring layer 21a are formed (see FIG. 2E).

  Next, an insulating material having a Young's modulus of 2500 MPa or less, a dielectric constant at 1 GHz of 2.9 or less, a dielectric loss tangent of 0.01 or less, and a water absorption of 0.3% or less on both surfaces of the circuit board 20 is used. The insulating film sheet to be formed is vacuum-laminated to form a second insulating layer 51a having a predetermined thickness (see FIG. 3 (f)).

  Next, via holes 32 are formed at predetermined positions of the second insulating layer 51a by laser processing (see FIG. 3G), desmear, catalyst nucleus application, and electroless copper plating are performed, and the plating base conductor layer 25 is formed. (See FIG. 3H).

  Next, electrolytic copper plating is performed to form the filled via 27 and the conductor layer 26 (see FIG. 3I).

  Next, a photosensitive layer is formed by a method such as laminating a dry film, and a series of patterning processes such as pattern exposure and development are performed to form a resist pattern 42 (see FIG. 3J).

  Next, using the resist pattern 42 as a mask, the conductor layer 26 and the plating base conductor layer 25 are etched to form the wiring layer 26a and the wiring layer 26b (see FIG. 4K).

  Next, a solder resist photosensitive solution is applied by screen printing or the like, a solder resist photosensitive layer is formed, a series of patterning processes such as pattern exposure and development are performed, and a solder resist pattern 61 is formed to form the flip chip pad 28 and A BGA pad 29 is formed to obtain a thin film multilayer wiring board (see FIG. 4L).

  Finally, in the case of multi-sided attachment, after cutting individually, a predetermined number of thin film multilayer wiring boards are laminated, and a coating layer 51 made of a resin of the second insulating layer is formed on the side surface of the thin film multilayer wiring board. The wiring layers 24 and 21a, the second insulating layer 51a, the wiring layers 26a and 26b, the solder resist 61, the flip chip pad 28, and the BGA pad 29 are formed on both surfaces of the inner layer substrate made of the first insulating layer 11, and the wiring layer 24 is formed. And the wiring layer 21a are electrically connected by a filled via 23, the wiring layer 24 and the wiring layer 26a are electrically connected by a filled via 27, and the wiring layer 21a and the wiring layer 26b are electrically connected by a via 27. The thin-film multilayer wiring board 100 according to the present invention whose side surfaces are covered with the resin of the second insulating layer 51a is obtained (see FIG. 4 (m)).

  Here, after cutting, the peripheral side surface of the thin film multilayer wiring board is coated with the resin of the second insulating layer, but as described above, the periphery of the first insulating layer (inner layer substrate) is formed before the second insulating layer is formed. If the second insulating layer is formed by forming an opening groove in the thin film, the thin film multilayer wiring board 100 of the present invention can be obtained at the time of the last cutting.

  Hereinafter, the present invention will be described in detail by way of examples.

  First, a 9 μm-thick copper foil 21 is formed on both surfaces of a 50 μm-thick first insulating layer (insulating base material) 11 made of a polyimide film (Iupicel N BE1420: trade name manufactured by Ube Industries) having a Young's modulus = 9121 Pa and a breaking strength = 520 MPa. A double-sided copper-clad laminate 10 having a size of 100 mm × 100 mm was prepared (see FIG. 2A).

  Next, a via hole 31 having a diameter of 40 μm was formed at a predetermined position of the double-sided copper-clad laminate 10 using ultraviolet rays composed of the third harmonic of the YAG laser (see FIG. 2B). Next, the substrate was immersed in an aqueous solution at 70 ° C. adjusted to have a permanganate concentration of 70 g / l and a sodium hydroxide concentration of 30 g / l for 20 minutes, and after washing the substrate with water, the hydroxylamine sulfate concentration was 20 g / l, sulfuric acid. It was immersed in an aqueous solution at 45 ° C. adjusted to 50 g / l for 5 minutes and subjected to neutralization reduction treatment.

  Next, the substrate was immersed in a pre-dip solution prepared so that Pre-dip Neogant B (trade name, manufactured by Atotech Co., Ltd.) was 20 ml / l and sulfuric acid concentration was 1 ml / l at 25 ° C. for 1 minute, and then the activator neo-gant 834 concrete (trade name, manufactured by Atotech Co., Ltd.) 30 ml / l, boric acid concentration 5 g / l, and immersed in a Pd catalyst solution at 40 ° C. adjusted to PH = 11.0 with sodium hydroxide for 5 minutes.

  Next, after washing the substrate with water, the plating catalyst was reduced by immersing in a solution adjusted to reducer neogant WA (Atotech Co., Ltd.) 5 ml / l and boric acid concentration 25 g / l at 30 ° C. for 5 minutes. .

  The substrate thus obtained has a metal copper concentration of 2.3 g / l, EDTA (ethylenediaminetetraacetic acid) of 20 g / l, and a formalin concentration of 1.0 g / l as the basic composition. The pH is adjusted to 12.0 with sodium hydroxide. An electroless copper plating solution made of the adjusted electroless copper plating solution KC-500 (trade name, manufactured by Japan Energy Co., Ltd.) is immersed in air at 60 ° C. for 15 minutes while being stirred in air, and is subjected to electroless copper plating treatment and a plating base. A conductor layer (particularly not shown) was formed.

Next, the substrate was copper sulfate pentahydrate concentration 200 g / l, sulfuric acid concentration 100 g / l, chlorine concentration 50 mg / l, cupronal VF-A (trade name of Meltex Co., Ltd.) 1.5 ml / l as an additive, Cupronal VF-B (trade name of Meltex company) 75 while supplying electricity to a current density of 1 A / dm ² at a temperature of 23 ° C. while stirring the electrolytic copper plating adjusted to 20 ml / l with air. The electroplating process was performed for a minute, and the 12-micrometer-thick conductor layer 22 and the filled via | veer 23 were formed (refer FIG.2 (c)).

  Next, after washing and drying the substrate, a dry film resist RY3215 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is bonded by thermocompression bonding to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed. As a result, a resist pattern 41 was formed (see FIG. 2D).

Next, using the resist pattern 41 as a mask, a ferric chloride solution having a specific gravity of 1.3 g / cm ³ and a free hydrochloric acid concentration of 0.3%, temperature = 40 ° C., pressure = 1.5 kg / cm ² Spray etching was performed under the above conditions to obtain the circuit board 20 on which the wiring layer 24 and the wiring layer 21a were formed (see FIG. 2E). Next, an opening groove 33 was formed in the outer peripheral portion outside the pattern region of the circuit board 20 by laser processing (see FIG. 5B).

On the other hand, as the curable composition, 8-ethyl-tetracyclo [4.4.0.1 ^2,5 . ^17,10 ] a hydrogenated polymer obtained by hydrogenating a ring-opened polymer of ^dodec -3-ene and further modifying with maleic anhydride (Mn = 33,200, Mw = 68,300, Tg = 170). ° C, maleic acid residue content = 25 mol%): 100 parts, bisphenol A bis (propylene glycol glycidyl ether) ether: 40 parts, 2- [2-hydroxy-3,5-bis (α, α-dimethylbenzyl) ) Phenyl] benzotriazole: 5 parts and 1-benzyl-2-phenylimidazole: 0.1 part were dissolved in a mixed solvent consisting of 215 parts of xylene and 54 parts of cyclopentanone to obtain a varnish.

  Next, the varnish is coated on a carrier film 12 made of a polyethylene naphthalate film having a thickness of 300 mm square and a thickness of 40 μm using a die coater, and then dried in a nitrogen oven, for example, at 120 ° C. for 10 minutes. An insulating layer film 30 with a carrier on which a second insulating resin layer 51 having a thickness of 40 μm was formed was obtained. Next, the circuit board 20 was superposed on both surfaces so that the second insulating resin layer surface of the insulating layer film with a carrier was inside (see FIG. 2E).

  Next, using a vacuum laminator provided with heat-resistant rubber press plates at the top and bottom, the pressure is reduced to 200 Pa, and thermocompression bonding is performed at a temperature of 125 ° C. and a pressure of 0.5 MPa for 60 seconds to form a curable composition on the circuit board 20. After forming the film, the carrier film 20 was peeled off, and then the aqueous solution adjusted so that 1- (2-aminoethyl) -2-methylimidazole (AMZ) was 0.3% at 25 ° C. for 10 minutes. After immersing, the treatment of immersing in another water bath for 1 minute is repeated 3 times to wash with water, and then the excess solution is removed with an air knife, and then left in a nitrogen oven at 170 ° C. for 60 minutes, A second insulating layer 51a having a thickness of 30 μm was formed on both surfaces of the circuit board 20 (see FIG. 3F).

  Here, the opening 51 was also filled with the resin 51 made of the second insulating layer 51a. The Young's modulus of the second insulating layer 51a was 2100 MPa, the breaking strength was 70 MPa, and the water absorption after being immersed in distilled water for 24 hours was 0.07%.

  Next, a via hole having a diameter of 40 μmφ was formed at a predetermined position of the second insulating layer 51a using ultraviolet light composed of YAG laser third harmonic (THG) (see FIG. 3G). Subsequently, it was immersed for 5 minutes in the 80 degreeC aqueous solution adjusted so that it might become a permanganic acid density | concentration of 80 g / liter and sodium hydroxide density | concentration of 40 g / liter. At this time, the surface roughness Ra of the insulating layer 2 was 0.1 μm. Next, the treatment of immersing the substrate in a water bath for 1 minute is repeated twice, and further, the substrate is washed with water by irradiating ultrasonic waves in another water bath at 25 ° C. for 2 minutes, and then the hydroxylamine sulfate concentration is 20 g / liter, sulfuric acid. The substrate was immersed in an aqueous solution at 45 ° C. adjusted to 50 g / liter for 5 minutes, neutralized and reduced, and then washed with hot water at 60 ° C. for 10 minutes. Next, after immersing the multilayer substrate after hot water washing at 25 ° C. for 1 minute in a pre-dip solution prepared so that Pre-dip Neogant B (trade name, manufactured by Atotech Co., Ltd.) is 20 ml / liter and sulfuric acid concentration is 1 ml / liter. Activator Neogant 834 Conch (trade name, manufactured by Atotech Co., Ltd.) 30 ml / liter, boric acid concentration 5 g / liter, 50 ° C. Pd salt-containing plating catalyst adjusted to pH = 11.0 with sodium hydroxide concentration Immerse in the solution for 5 minutes.

  Next, after washing the substrate with the same method as described above, reducer Neogant WA (trade name, manufactured by Atotech Co., Ltd.) 5 ml / liter, adjusted to a boric acid concentration of 25 g / liter at 30 ° C. for 5 minutes, Immersion was performed to reduce the plating catalyst. Furthermore, an electroless copper plating solution KC-500 having a basic composition of 2.3 g / liter of metal Cu, 20 g / liter of EDTA, 1.0 g / liter of formalin, and adjusted to pH 12.5 with sodium hydroxide ( The plating base conductor layer 25 was formed by performing electroless plating by dipping for 15 minutes at a temperature of 60 ° C. while blowing air into an electroless plating solution made of Japan Energy Co., Ltd. (trade name) (FIG. 3 (h)). reference).

Subsequently, it was washed with water in the same manner as described above, and then the substrate was copper sulfate pentahydrate concentration 200 g / l, sulfuric acid concentration 100 g / l, chlorine concentration 50 mg / l, and cupronal VF-A (Meltex Co., Ltd.) as an additive. (Trade name) 1.5 ml / l, cupronal VF-B (Meltex company trade name) adjusted to 20 ml / l, electrolytic copper plating adjusted to a current density of 1 A / dm ² at a temperature of 23 ° C. with air stirring. Thus, the electroplating process was performed for 75 minutes while energizing electricity, and the 12-micrometer-thick conductor layer 26 and the filled via | veer 27 were formed (refer FIG.3 (i)).

  Next, after washing and drying, a dry film resist RY3215 (trade name, manufactured by Hitachi Chemical Co., Ltd.) is bonded by thermocompression bonding to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed. A resist pattern 42 was formed (see FIG. 3J).

Next, using the resist pattern 42 as a mask, the conductor layer 26 is made of a ferric chloride solution having a specific gravity = 1.3 g / cm ³ and a free hydrochloric acid concentration = 0.3%, temperature = 40 ° C., pressure = 1. Wiring layers 26a and 26b having an etching line and space (L / S) of 20 μm were formed under the condition of 0.5 kg / cm ² (see FIG. 4 (k)).

  Next, the OPC Defencer (trade name, manufactured by Okuno Pharmaceutical Co., Ltd.) was immersed in a rust prevention solution adjusted to 8 ml / liter at 25 ° C. for 1 minute, washed with water, dried, subjected to rust prevention treatment, and 170 ° C. Heat treatment was performed in an oven for 30 minutes. Furthermore, a solder resist ink (PSR-4000 (trade name): manufactured by Taiyo Ink) is applied by screen printing and dried to form a solder resist layer, and patterning treatment such as pattern exposure and development is performed. A thin film multilayer wiring of the present invention in which a flip chip pad 28 and a BGA pad 29 are formed by forming a pattern 61 and the side surface of the first insulating layer in the peripheral portion of the thin film multilayer wiring board is covered with the resin 51 of the second insulating layer 51a. A plate 100 was obtained (see FIG. 4 (m)).

  The breaking strength of the thin film multilayer wiring board 100 was as high as 500 MPa, and no change was observed in the dielectric constant and dielectric loss tangent of the first insulating layer before and after being immersed in distilled water for 24 hours. Further, the error occurrence rate of the wiring layer shape inspection by taking in the image through the second insulating layer of the CCD camera was very good at 5% or less.

  First, a 9 μm-thick copper foil 21 is formed on both sides of a 50 μm-thick first insulating layer (insulating base material) 11 made of a polyimide film (Iupicel N BE1420: trade name manufactured by Ube Industries) having a Young's modulus = 9121 Pa and a breaking strength = 520 MPa. A double-sided copper-clad laminate 10 having a size of 100 mm × 100 mm was prepared (see FIG. 2A).

  Next, a second insulating layer 51a having a thickness of 32 μm is formed on both sides of the double-sided copper-clad laminate 10 with a prescription using the same material as in Example 1, and via hole formation, conductor layer formation, and patterning are performed. The thin film multilayer wiring board of Example 2 having a microstrip line structure having a wiring layer with a signal line width of 77 μm and a signal line length of 50 mm was obtained.

  The electrical property evaluation results of the obtained thin film multilayer substrate are shown in FIGS. Thus, the thin-film multilayer wiring board of the present invention has a small S21 parameter of −8 db at 40 GHz in the S21 parameter indicating the attenuation rate of the signal transmitted through the signal line. In addition, TDT which evaluated the rise characteristic of a signal when a signal having a rise time (tr) of 35 psec was input to the above-described line showed an early rise time of 60 psec.

  In the same manner as in Example 1, first, a first insulating layer (insulating base material) 11 having a thickness of 50 μm made of a polyimide film having a Young's modulus = 9121 Pa and a breaking strength = 520 MPa (Iupicel N BE1420: trade name manufactured by Ube Industries, Ltd.) A thermosetting epoxy resin having a Young's modulus = 2900 MPa on both sides of the circuit board 20 on which the wiring layer 21a, the wiring layer 24 and the filled via 23 are formed, and a water absorption rate of 1.2% after being immersed in distilled water for 24 hours. ABF-SH9K (manufactured by Ajinomoto Finetech) was depressurized to 200 Pa using a vacuum laminator equipped with heat-resistant rubber press plates at the top and bottom, temperature 100 ° C., pressure 0.7 MPa for 30 seconds, temperature = 100 ° C., pressure = A second insulating layer made of a thermosetting resin layer was formed by two-step thermocompression bonding at 5.5 MPa for 60 seconds. Subsequently, it was immersed for 20 minutes in the 70 degreeC aqueous solution adjusted so that it might become a permanganic acid density | concentration of 80 g / liter and sodium hydroxide density | concentration of 40 g / liter. At this time, the surface roughness Ra of the insulating layer was 1.5 μm.

  Next, via-hole formation, conductor layer formation, and conductor layer patterning treatment were performed with the same formulation as in Example 1 to obtain a thin film multilayer wiring board of Example 3. The breaking strength of the thin film multilayer wiring board of Example 3 was very high at 500 MPa, but the second insulating layer cracked in the JIS 71132 single tensile test piece from above 100 MPa, and the mechanical properties of the thin film multilayer substrate The strength was below the practical level. Further, the dielectric constant and dielectric loss tangent of the first insulating layer fluctuated by 10% before and after the treatment immersed in distilled water for 24 hours.

  Thus, in Example 3, as a result of using a material having a Young's modulus and breaking strength lower than those of the second insulating layer of the present invention as the second insulating layer, cracks were generated from about 100 MPa in the above-described tensile test, and environmental fluctuations were further observed. Accordingly, since the dielectric constant and dielectric loss tangent of the first insulating layer fluctuate by 10%, the high-speed transmission characteristic of an electric signal is adversely affected when the characteristic impedance matching is important. This proves that the second insulating layer is preferably a material having a low Young's modulus and a low water absorption.

  First, a 9 μm-thick copper foil 21 is formed on both sides of a 50 μm-thick first insulating layer (insulating base material) 11 made of a polyimide film (Iupicel N BE1420: trade name manufactured by Ube Industries) having a Young's modulus = 9121 Pa and a breaking strength = 520 MPa. A second insulating layer having a thickness of 32 μm is formed on both surfaces of a 100 mm × 100 mm double-sided copper-clad laminate 10 having a thickness similar to that in Example 3 to form via holes, conductor layers, Patterning was performed to obtain a thin film multilayer wiring board of Example 4 having a microstrip line structure having a wiring layer with a signal line width of 71 μm and a signal line length of 50 mm.

  The electrical property evaluation results of the thin film multilayer wiring board obtained in Example 4 are shown in FIGS. Thus, the thin-film multilayer wiring board of Example 4 was as large as −16 db at 40 GHz in the S21 parameter representing the attenuation rate of the signal transmitted through the signal line. This is because the surface roughness of the surface of the second insulating layer is rough and the dielectric constant and dielectric loss tangent of the second insulating layer are high. In addition, TDT which evaluated the rise characteristic of a signal when a signal having a rise time (tr) of 35 psec is input to the above-mentioned line has a slow rise time of 140 psec.

  That is, since the dielectric loss tangent is high, the rise is slow, and the surface of the second insulating layer is rough, and the rise characteristic of the signal is also deteriorated due to the skin effect. From these results, it was confirmed that the surface roughness Ra is 0.2 μm or less and that the dielectric constant and dielectric loss tangent of the second insulating layer are preferably low.

1 is a schematic partial sectional view showing an embodiment of a thin film multilayer wiring board according to the present invention. (A)-(e) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the thin film multilayer wiring board of this invention. (F)-(j) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the thin film multilayer wiring board of this invention. (K)-(m) is a fragmentary sectional view which shows typically a part of manufacturing process in the manufacturing method of the thin film multilayer wiring board of this invention. (A)-(e) is explanatory drawing which shows an example of the method of coat | covering the resin of a 2nd insulating layer on the peripheral part side surface of the thin film multilayer wiring board of this invention. (A) is the model top view which formed the wiring layer etc. in the 1st insulating layer 11 of 3 surfaces. FIG. 4B is a schematic plan view in which an opening groove is formed in the peripheral portion outside the pattern region of the first insulating layer 11. (C) is the schematic top view which formed the 2nd insulating layer 51a. (D) is the schematic cross section which cut | disconnected (c) by the A-A 'line | wire. (E) is a schematic cross-sectional view of a cut thin film multilayer wiring board. It is explanatory drawing which shows the S21 parameter characteristic of the thin film multilayer wiring board obtained by the Example of this invention. It is explanatory drawing which shows the starting characteristic of the signal of the thin film multilayer wiring board obtained by the Example of this invention. It is a typical structure fragmentary sectional view which shows an example of the conventional multilayer wiring board. It is a typical structure fragmentary sectional view which shows an example of the conventional multilayer wiring board. (A) is process schematic structure partial sectional drawing which shows an example of the manufacturing method of the conventional multilayer wiring board. (B) is a schematic structure fragmentary sectional view which shows an example of the conventional multilayer wiring board.

Explanation of symbols

10 …… Double-sided copper-clad laminate 11 …… First insulation layer (insulation substrate)
DESCRIPTION OF SYMBOLS 12 ... Carrier film 20 ... Circuit board 21 ... Copper foil 21a, 24, 26a, 26b, 102, 112, 122, 332, 423, 425 ... Wiring layers 22, 26 ... Conductive layers 23, 27, 111 , 121, 331, 422, 424 ... filled via 25 ... plating conductor layers 28, 131, 341, 431 ... flip chip pads 29, 132, 342, 421 ... BGA pad 30 ... insulating layer film 31 with carrier 32 ... via hole 33 ... opening groove 41, 42 ... resist pattern 51 ... second insulating resin layer 51a ... second insulating layer 61, 141, 351, 441 ... solder resist pattern 111 ... insulation Base material 101 ... Through hole 110 ... Core substrate 112, 113, 411, 412 ... Insulating layer 311 ... Poly with double-sided copper foil Bromide substrate 312 ...... single-sided copper foil polyimide 321 ...... adhesive layer 410 ...... metal plate 421 ...... electrode pads

Claims (6)

  In a multilayer wiring board in which at least two wiring layers are formed on one or both surfaces of an inner substrate composed of a first insulating layer via a second insulating layer, the first insulating layer has a Young's modulus of 5000 MPa or more. And a thin film multilayer wiring board comprising an insulating material having a breaking strength of 400 MPa or more.   The second insulating layer is made of an insulating material having a Young's modulus of 2500 MPa or less, a dielectric constant at 1 GHz of 2.9 or less, a dielectric loss tangent of 0.01 or less, and a water absorption of 0.3% or less. A thin film multilayer wiring board, characterized in that   The thin film multilayer wiring board according to claim 1 or 2, wherein the surface roughness Ra of the second insulating layer is 0.01 µm or more and 0.2 µm or less.   The thin film multilayer wiring board according to any one of claims 1 to 3, wherein the second insulating layer is a thermosetting resin.   5. The thin film multilayer wiring board according to claim 1, wherein the second insulating layer has a light transmittance of not less than 85% at 400 nm to 700 nm.   6. The thin film multilayer wiring board according to claim 1, wherein a side surface of the first insulating layer in the periphery of the thin film multilayer wiring board according to claim 1 is covered with a resin of the second insulating layer.

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