JP2005309649A - Shared memory transfer control circuit and system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an efficient power management and a proper band width scheduling. <P>SOLUTION: The shared memory transfer control circuit 2 comprises a transfer request congestion number detection circuit 6 for detecting a transfer request congestion number RML showing the duplicate degree of a transfer request from transfer request signals REQ1-REQn; a transfer request level signal maximum value detection circuit 7 for detecting from transfer request level signals LV1-LVn a transfer request level signal maximum value LVMAX that is the maximum value thereof; a transfer clock control part 7 for controlling the frequency of transfer clock TCLK on the basis of the transfer request congestion number RML and the transfer request level signal maximum value LVMAX, and an access right adjusting circuit 5 for adjusting the access right to a shared memory 1 of a plurality of master devices 31, 32 to 3n. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to transfer control when a plurality of master devices access a shared memory, and more particularly to a technique for realizing efficient power management and appropriate bandwidth scheduling.

In a conventional shared memory transfer control circuit, for example, when receiving transfer information from a plurality of master devices, when a transfer request received from a master device that is highly necessary to perform real-time processing conflicts with a request from another master device. A dedicated timer value provided for each master device is used to calculate the “maximum time that can be waited” for a master device that requires real-time processing and the “scheduled time to occupy shared memory” calculated from registration information of a master device other than the master device. Compared with each other, bus arbitration in shared memory access was performed (see, for example, Patent Document 1).
JP 2000-148668 A

  However, in the conventional shared memory transfer control circuit, since the transfer clock frequency corresponding to the wide bandwidth at the peak time is fixedly used, the high transfer clock corresponding to the peak time can be obtained even in the time zone where the wide bandwidth is not required. Since the frequency remains set, there is a situation in which power consumption is wasted due to an excessive transfer clock frequency with respect to the data transfer amount.

  On the other hand, it is possible to reduce power consumption with the clock gating method that supplies the clock only at the necessary timing, but in that case, the frequency at the time of operation remains constant in the conventional method. There was a circumstance that was not connected.

  It is an object of the present invention to provide a shared memory transfer control circuit that realizes efficient power management and appropriate bandwidth scheduling.

  The shared memory transfer control circuit of the present invention receives a priority level signal indicating the urgent level of transfer from a plurality of master devices that make a transfer request to the shared memory, performs bus arbitration between each master device based on the information, When there are few congested requests from the master device and the urgency of each request is small, the transfer clock frequency including the shared memory transfer control circuit itself and the shared memory is lowered, and the drive capability to the shared memory It is characterized in that dynamic control is performed to suppress the frequency to a sufficient level for the selected frequency.

  According to the present invention, the necessary bandwidth is secured at the maximum load by arbitrating access to the shared memory by a plurality of master devices and selecting the optimum transfer clock frequency and the optimum drive capacity to the shared memory. It is possible to save power without impairing the power consumption and suppress unnecessary rush current.

  One aspect of the shared memory transfer control circuit of the present invention is a shared memory transfer that arbitrates an access right to a shared memory based on a transfer request signal supplied from a plurality of master devices and a transfer request level signal indicating the urgency of the transfer request. A transfer request congestion number detection circuit for detecting a transfer request congestion number indicating a degree of duplication of transfer requests from the transfer request signal; and a transfer request for detecting a transfer request level signal maximum value from the transfer request level signal. A level signal maximum value detection circuit, a transfer clock control unit that controls the frequency of a transfer clock based on the number of transfer request congestions and the transfer request level signal maximum value, and access to the shared memory of the plurality of master devices by the transfer clock And an access right arbitration circuit for mediating rights.

  According to the above configuration, efficient power management and appropriate bandwidth scheduling are achieved by arbitrating access to the shared memory by a plurality of master devices and selecting an optimal transfer clock frequency and an optimal drive capacity to the shared memory. Can be realized.

  In the shared memory transfer control circuit of the present invention, the transfer clock control unit increases the transfer clock frequency when the sum of the transfer request congestion number and the transfer request level signal maximum value is a predetermined value or more, When the sum is smaller than a predetermined value, the transfer clock frequency is lowered.

  According to the above configuration, since the transfer clock is always controlled in conjunction with the sum of the transfer request congestion number and the maximum request level, the transfer clock frequency can be reduced and saved without losing the required transfer bandwidth. It can be powered.

  In the shared memory transfer control circuit of the present invention, the transfer clock control unit stops the transfer clock when there is no transfer request from the plurality of master devices.

  In addition, the shared memory transfer control circuit of the present invention includes an I / O port that varies the drive capability for the shared memory in accordance with the frequency of the transfer clock.

  According to the above configuration, since the drive capability of the I / O port is adjusted in accordance with the transfer clock frequency for the shared memory, the shared memory transfer control circuit and the shared memory can be further reduced in power consumption.

  Also, the shared memory transfer control circuit of the present invention performs shared memory transfer control for arbitrating access rights to the shared memory based on a transfer request signal supplied from a plurality of master devices and a transfer request level signal indicating the urgency of the transfer request. A transfer request congestion number detection circuit for detecting a transfer request congestion number indicating a degree of duplication of transfer requests from the transfer request signal, and a transfer request level for detecting a transfer request level signal maximum value from the transfer request level signal. A signal maximum value detection circuit, and a frequency of a first transfer clock supplied to the plurality of master devices and a second transfer clock supplied to the shared memory based on the transfer request congestion number and the transfer request level signal maximum value And a plurality of master devices by the first and second transfer clocks. And an access arbiter for arbitrating access to the shared memory of the scan.

  According to the above configuration, it is possible to save power without increasing the internal logic frequency, increase only the clock frequency supplied to the shared memory, and expand the total bandwidth.

  In the shared memory transfer control circuit of the present invention, the frequencies of the first and second transfer clocks have a linearity magnification relationship.

  According to the present invention, it is necessary to arbitrate access to the shared memory by a plurality of master devices, and at the same time, by selecting an optimal transfer clock frequency and a drive capacity to the shared memory that are not excessive or insufficient at that time, a necessary band at the maximum load is obtained. It is possible to save power without deteriorating the width. Further, unnecessary rush current can be suppressed by reducing the frequency.

  FIG. 1 is a diagram showing a schematic configuration of a shared memory transfer control system for explaining a first embodiment of the present invention. In the shared memory transfer control system of the present embodiment, the shared memory transfer control circuit 2 arbitrates accesses of a plurality of master devices 31, 32,..., 3n having a function of controlling data transfer to the shared memory 1.

  The shared memory transfer control circuit 2 determines transfer request signals REQ1 to REQn supplied from the transfer circuits 41, 42,..., 4n of the plurality of master devices 31, 32,. The access right for the shared memory 1 is arbitrated based on the transfer request level signals LV1 to LVn shown.

  The shared memory transfer control circuit 2 includes, from the transfer request signals REQ1 to REQn, the transfer request congestion number detection circuit 6 that detects the transfer request congestion number RML indicating the degree of duplication of transfer requests, and the transfer request level signals LV1 to LVn. Transfer request level signal maximum value detection circuit 7 that detects the maximum transfer request level signal value LVMAX that is the maximum value, transfer that controls the frequency of the transfer clock TCLK based on the transfer request congestion number RML and the transfer request level signal maximum value LVMAX The clock control unit 8 and the access right arbitration circuit 5 that arbitrates the access right to the shared memory 1 of the plurality of master devices 31, 32,..., 3n by the transfer clock TCLK.

Further, the transfer clock control unit 8 divides the reference clock supplied from the clock generation source 11 that generates the reference clock having the frequency f0 to generate the divided clocks having the frequencies f0 / 2,..., F0 / ^2n. A transfer clock generation circuit 9 to be generated and a transfer clock frequency selection circuit 10 for selecting a predetermined transfer clock TCLK from the divided clock are included.

  Transfer request signals REQ1 to REQn and transfer request level signals LV1 to LVn are output from the transfer circuits 41, 42,..., 4n of the master device group 3 to the shared memory transfer control circuit 2, respectively. Transfer enable signals ACK1 to ACKn are input from the circuit 2 to the transfer circuits 41, 42,..., 4n.

  The data input / output buses DATA1, DATA2,..., DATAn are connected between the shared memory transfer control circuit 2 and the transfer circuits 41, 42,. The transfer request signals REQ 1 to REQn are input to the transfer request congestion number detection circuit 6 together with the access right arbitration circuit 5 in the shared memory transfer control circuit 2. The transfer request level signals LV1 to LVn are input to the request level maximum value detection circuit 7 together with the access right arbitration circuit 5.

  Each of the master devices 31, 32,..., 3n activates the transfer request signals REQ1 to REQn corresponding to the master device when a transfer request to the shared memory 1 occurs, and uses the transfer request level signals LV1 to LVn. Then, the urgency of the transfer request of the master device is transmitted to the shared memory transfer control circuit 2 as a status signal.

  The shared memory transfer control circuit 2 issues an access right permission in the access right arbitration circuit 5 based on the information of the transfer request signals REQ1 to REQn and the transfer request level signals LV1 to LVn. If the transfer request is congested, the access right is determined in descending order of the request level, and the transfer permission signals ACK1 to ACKn are used to notify only the one master device that the access right has been acquired.

  The transfer request congestion number detection circuit 6 monitors the transfer request signals REQ1 to REQn from the respective master devices 31, 32,..., 3n, detects the transfer request congestion number RML, and transmits it to the transfer clock frequency selection circuit 10. . Further, the request level maximum value detection circuit 7 monitors the transfer request level signals LV1 to LVn from the respective master devices 31, 32,..., 3n, and similarly supplies the maximum request level value LVMAX to the transfer clock frequency selection circuit 10. introduce. The larger the value of the transfer request level signal maximum value LVMAX, the higher the urgency of the transfer request.

The transfer clock frequency selection circuit 10 has a plurality of clock frequencies CLK0 to CLKn (f0, f0 / 2,..., F0) generated by the transfer clock generation circuit 9 based on the transfer request congestion number RML and the request level maximum value LVMAX. / 2 ⁿ ), the minimum clock frequency that can ensure the necessary bandwidth is selected, and transfer (synchronization) of the transfer circuits 41, 42,..., 4n, the shared memory transfer control circuit 2, and the shared memory 1 is performed. Supply as clock TCLK.

  FIG. 2 is an example showing under what conditions the shared memory transfer control circuit 2 controls the transfer clock frequency selection circuit 10 in the shared memory transfer control system according to the first embodiment of the present invention. It is a flowchart. The transfer request level signal maximum value LVMAX is an output of the request level maximum value detection circuit 7 and indicates the maximum request level value. The transfer request congestion number RML is an output from the transfer request congestion number detection circuit 6 and indicates the congestion degree of the transfer request.

  The sum of the transfer request congestion number RML and the transfer request level signal maximum value LVMAX is set as a J value (step S1), and the frequency of the transfer clock TCLK is selected based on this J value. If J is 3 or more at a certain time (step S2), the frequency of the transfer clock TCLK becomes the reference frequency fo (step S3).

  If J is 2 at a certain time (step S4), the frequency of the transfer clock TCLK is set to fo / 2 which is a half of the reference frequency (step S5), and if J is 1 (step S6). The frequency of the transfer clock TCLK is set to fo / 4 which is a quarter of the reference frequency (step S7). In other cases, that is, when J is 0, it means that a transfer request is not generated at this point, and the transfer clock TCLK is STOP, that is, stopped (step S8).

  FIG. 3 is a time chart for explaining under what conditions the shared memory transfer control circuit 2 controls the transfer clock frequency selection circuit 10 in the first embodiment of the present invention. The vertical axis represents the transfer request congestion number RML, the transfer request level signal maximum value LVMAX, and the transfer clock TCLK, and the horizontal axis represents time.

  As shown in FIG. 3, since J = RML + LVMAX = 0 from the time point A to the time point B, the transfer clock TCLK is stopped. When the time point B is exceeded, J = RML + LVMAX = 4 and J ≧ 3, and therefore the frequency of the transfer clock TCLK becomes the maximum value f0. Since the situation of J ≧ 3 does not change at the points C and D, the frequency of the transfer clock TCLK is maintained at f0.

  At time E, J = RML + LVMAX = 0 again, and the transfer clock TCLK is stopped. At time F, J = RML + LVMAX = 2, and the frequency of the transfer clock TCLK is f0 / 2, which is half of the maximum time. Further, at time G, J = RML + LMAX = 1, and control is performed so as to decrease to f0 / 4 which is a quarter of the maximum.

  As described above, since the transfer clock TCLK is always controlled in conjunction with the sum of the transfer request congestion number RML and the request level maximum value LVMAX, the frequency of the transfer clock TCLK without losing the required transfer bandwidth. Can be reduced to save power.

FIG. 4 is a diagram showing a schematic configuration of the shared memory transfer control circuit 2 for explaining the second embodiment of the present invention. In the shared memory transfer control circuit 2 of this embodiment, the transfer clock frequency selection circuit 10 of the transfer clock control unit 8 has a plurality of clock frequencies CLK0 to CLKn (f0, f0 / 2,. .., F0 / 2 ⁿ ) is different from the first embodiment in that two transfer clocks TCLK and TSDCLK are individually selected.

  The master devices 31, 32,..., 3 n access the shared memory 1 through the arbitration of the shared memory transfer control circuit 2. Transfer request signals REQ1 to REQn and transfer request level signals LV1 to LVn are output from the transfer circuits 41, 42,..., 4n of the master device group 3 to the shared memory transfer control circuit 2, respectively. Transfer enable signals ACK1 to ACKn are input from the circuit 2 to the transfer circuits 41, 42,..., 4n. A data input / output bus is connected between the shared memory transfer control circuit 2 and the transfer circuits 41, 42,..., 4n.

  The transfer request signals REQ 1 to REQn are input to the transfer request congestion number detection circuit 6 together with the access right arbitration circuit 5 in the shared memory transfer control circuit 2. The transfer request level signals LV 1 to LVn are input to the request level maximum value detection circuit 7 together with the access right arbitration circuit 5.

  The transfer clock control unit 8 includes a transfer clock generation circuit 9 and a transfer clock frequency selection circuit 10. The transfer clock generation circuit 9 divides and multiplies the clock generation source 11 to generate clocks CLK0 to CLKn having a plurality of frequencies.

  Each of the master devices 31, 32,..., 3n activates the transfer request signals REQ1 to REQn corresponding to the master device when a transfer request to the shared memory 1 occurs, and uses the transfer request level signals LV1 to LVn. Then, the urgency of the transfer request of the master device is transmitted to the shared memory transfer control circuit 2 as a status signal.

  In the shared memory transfer control circuit 2, the access right arbitration circuit 5 issues an access right permission based on the information of the transfer request signals REQ1 to REQn and the transfer request level signals LV1 to LVn. If the transfer request is congested, the access right is determined in descending order of the request level, and the transfer permission signals ACK1 to ACKn are used to notify only the one master device that the access right has been acquired.

  The transfer request congestion number detection circuit 6 monitors the transfer request signals REQ1 to REQn from the respective master devices 31, 32,..., 3n, detects the transfer request congestion number RML, and transmits it to the transfer clock frequency selection circuit 10. To do. The request level maximum value detection circuit 7 monitors transfer request level signals LV1 to LVn from the respective master devices 31, 32,..., 3n, and transmits the maximum request level value LVMAX to the transfer clock frequency selection circuit 10 as well. To do. The larger the value of the transfer request level signal maximum value LVMAX, the higher the urgency of the transfer request.

  The transfer clock frequency selection circuit 10 is the minimum of the plurality of clock frequencies CLK0 to CLKn generated by the transfer clock generation circuit 9 that can secure the necessary bandwidth, based on the transfer request congestion number RML and the request level maximum value LVMAX. The clock frequency is selected, the transfer (synchronous) clock TCLK12 is supplied to the transfer circuits 41, 42,..., 4n and the shared memory transfer control circuit 2, and the transfer (synchronous) clock TSDCLK13 is supplied to the shared memory 1. Supply each separately.

  At that time, the synchronous clock TCLK12 for the transfer circuits 41, 42,..., 4n and the shared memory transfer control circuit 2 is controlled in the same manner as in the first embodiment, but the synchronous clock TSDCLK13 for the shared memory 1 is It is always controlled independently of the synchronous clock TCLK12. In this case, the synchronous clock TSDCLK13 is controlled in such a manner that the synchronous clock TCLK12 and the clock frequency always maintain a proportional relationship.

  According to the present embodiment, power saving can be performed without increasing the internal logic frequency TCLK12, and only the clock frequency TSDCLK13 supplied to the shared memory 1 can be increased to expand the total bandwidth.

  FIG. 5 is a diagram showing a schematic configuration of the shared memory transfer control circuit 2 for explaining the third embodiment of the present invention. In the shared memory transfer control circuit 2 of the present embodiment, a drive capability switching control signal 15 corresponding to the transfer clock selected by the transfer clock frequency selection circuit 10 is supplied to the I / O port 14 for accessing the shared memory 1. This is different from the first embodiment.

  The master devices 31, 32,..., 3 n access the shared memory 1 through the arbitration of the shared memory transfer control circuit 2. Transfer request signals REQ1 to REQn and transfer request level signals LV1 to LVn are output from the transfer circuits 41, 42,..., 4n of the master device group 3 to the shared memory transfer control circuit 2, respectively. Transfer enable signals ACK1 to ACKn are input from the circuit 2 to the transfer circuits 41, 42,..., 4n. The data input / output bus is connected between the shared memory transfer control circuit 2 and the transfer circuits 41, 42,.

  The transfer request signals REQ 1 to REQn are input to the transfer request congestion number detection circuit 6 together with the access right arbitration circuit 5 in the shared memory transfer control circuit 2. The transfer request level signals LV 1 to LVn are input to the request level maximum value detection circuit 7 together with the access right arbitration circuit 5.

  The transfer clock control unit 8 includes a transfer clock generation circuit 9 and a transfer clock frequency selection circuit 10. The transfer clock generation circuit 9 divides and multiplies the clock generation source 11 to generate clocks CLK0 to CLKn having a plurality of frequencies.

  Each of the master devices 31, 32,..., 3n activates the transfer request signals REQ1 to REQn corresponding to the master device when a transfer request to the shared memory 1 is generated, and uses the transfer request level signals LV1 to LVn. Then, the urgency of the transfer request of the master device is transmitted to the shared memory transfer control circuit 2 as a status signal.

  The shared memory transfer control circuit 2 issues an access right permission in the access right arbitration circuit 5 based on the information of the transfer request signals REQ1 to REQn and the transfer request level signals LV1 to LVn. If the transfer request is congested, the access right is determined in descending order of the request level, and only the one master device is notified using the transfer permission signals ACK1 to ACKn that the access right has been acquired.

  The transfer request congestion number detection circuit 6 monitors the transfer request signals REQ1 to REQn from the respective master devices 31, 32,..., 3n, detects the transfer request congestion number RML, and transmits it to the transfer clock frequency selection circuit 10. To do. The request level maximum value detection circuit 7 monitors the transfer request level signals LV1 to LVn from the respective master devices 31, 32,..., 3n, and transmits the maximum request level value LVMAX to the transfer clock frequency selection circuit 10 as well. . The larger the value of the transfer request level signal maximum value LVMAX, the higher the urgency of the transfer request.

  The transfer clock frequency selection circuit 10 is a minimum that can secure a necessary bandwidth among the plurality of clock frequencies CLK0 to CLKn generated by the transfer clock generation circuit 9 based on the transfer request congestion number RML and the request level maximum value LVMAX. , 4n, the shared memory transfer control circuit 2, and the shared memory 1 are supplied with the synchronous clock TCLK12.

  The I / O port 14 is a port for accessing the shared memory 1, and a control signal 15 for switching its output drive capability is supplied from the transfer clock frequency selection circuit 10. The control signal 15 is linked with the frequency of the transfer clock TCLK12, and controls the drive capability of the I / O port 14 in the suppression direction when the transfer clock frequency is switched to f0 / 2 or lower, for example.

  According to the present embodiment, the drive capability of the I / O port 14 of the shared memory transfer control circuit 2 can be adjusted in accordance with the transfer clock frequency for the shared memory 1, so that the shared memory transfer control circuit 2 and the shared memory can be adjusted. 1 can further save power.

  The shared memory control circuit of the present invention arbitrates access to the shared memory by a plurality of master devices, and at the same time selects an optimal transfer clock frequency and a drive capacity to the shared memory that are not excessive or insufficient at the time, so that the maximum load is achieved. Therefore, it is possible to save power without impairing the required bandwidth. It also has the effect of suppressing unnecessary rush currents by reducing the frequency, and realizes transfer control when multiple master devices access the shared memory, especially efficient power management and appropriate bandwidth scheduling. It is useful as a technique to do so.

The figure which shows schematic structure for demonstrating the shared memory transfer control system concerning the 1st Embodiment of this invention. Flowchart for explaining the operation of the shared memory transfer control circuit in the first embodiment of the present invention Time chart for explaining a control method of the shared memory transfer control circuit in the first embodiment of the present invention The figure which shows schematic structure for demonstrating the shared memory transfer control circuit concerning the 2nd Embodiment of this invention 1 is a diagram showing a schematic configuration for explaining a shared memory transfer control circuit according to a first embodiment of the present invention;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Shared memory 2 Shared memory transfer control circuit 3 Master device group 5 Access right arbitration circuit 6 Transfer request congestion number detection ground circuit 7 Request level maximum value detection circuit 8 Transfer clock control part 9 Transfer clock generation circuit 10 Transfer clock frequency selection circuit 11 Clock Source 12 Transfer (synchronization) clock 13 Synchronous clock for shared memory 14 I / O port 15 I / O port drive switching control signal 31, 32,..., 3n Master device 41, 42,.

Claims (6)

A shared memory transfer control circuit for arbitrating access rights to the shared memory based on a transfer request signal supplied from a plurality of master devices and a transfer request level signal indicating the urgency of the transfer request;
A transfer request congestion number detection circuit for detecting a transfer request congestion number indicating the degree of duplication of transfer requests from the transfer request signal;
A transfer request level signal maximum value detection circuit for detecting a transfer request level signal maximum value from the transfer request level signal;
A transfer clock controller that controls the frequency of a transfer clock based on the transfer request congestion number and the transfer request level signal maximum value;
An access right arbitration circuit that arbitrates access rights to the shared memory of the plurality of master devices by the transfer clock;
A shared memory transfer control circuit. The shared memory transfer control circuit according to claim 1, wherein the transfer clock control unit includes:
When the sum of the transfer request congestion number and the transfer request level signal maximum value is a predetermined value or more, increase the transfer clock frequency,
A shared memory transfer control circuit for lowering the transfer clock frequency when the sum is smaller than a predetermined value. The shared memory transfer control circuit according to claim 1, wherein the transfer clock control unit includes:
A shared memory transfer control circuit for stopping the transfer clock when there is no transfer request from the plurality of master devices; The shared memory transfer control circuit according to claim 1,
A shared memory transfer control circuit comprising an I / O port that varies the drive capability for the shared memory in accordance with the frequency of the transfer clock. A shared memory transfer control circuit for arbitrating access rights to the shared memory based on a transfer request signal supplied from a plurality of master devices and a transfer request level signal indicating the urgency of the transfer request;
A transfer request congestion number detection circuit for detecting a transfer request congestion number indicating the degree of duplication of transfer requests from the transfer request signal;
A transfer request level signal maximum value detection circuit for detecting a transfer request level signal maximum value from the transfer request level signal;
A transfer clock controller for controlling the frequency of a first transfer clock supplied to the plurality of master devices and a second transfer clock supplied to the shared memory based on the transfer request congestion number and the transfer request level signal maximum value;
An access right arbitration circuit that arbitrates an access right to the shared memory of the plurality of master devices by the first and second transfer clocks;
A shared memory transfer control circuit. The shared memory transfer control circuit according to claim 5,
The shared memory transfer control circuit, wherein the frequencies of the first and second transfer clocks have a linearity relationship.

Images