JP2005347328A - Memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory device which is not sensitive to the thickness of a charge barrier layer and never induces defects in an insulation film of the charge barrier layer and can write/read at a low voltage and never requires an expensive material and can remarkably reduce the manufacturing cost of a future large-capacity memory. <P>SOLUTION: The memory device has a structure of a field effect transistor wherein a semiconductor layer 1, first charge barrier layer 2, charge accumulation layer 3, second charge barrier layer 4, and gate electrode 4 are stacked in this order. By using specified materials for the semiconductor layer 1, the first charge barrier layer 2, and the charge accumulation layer 3; electric conduction is induced between the semiconductor layer 1 and the charge accumulation layer 3 by Schottky discharge. The memory device accumulates charge in the charge accumulation layer 3, and stores information by a change in threshold value of the field effect transistor due to the accumulated charge. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a field effect transistor type semiconductor memory element such as a metal-oxide-semiconductor (MOS) type or a metal-insulator-semiconductor (MIS) type.

  First, a charge storage memory element having a structure similar to that of the memory element of the present invention will be described. The charge storage memory element has the film configuration shown in FIG. 11, and includes at least a semiconductor layer 100, a first charge barrier layer 101, a charge storage layer 102 (also called a floating gate electrode), a second charge barrier layer 103, It has a gate electrode 104 (also called a control gate electrode), a source 105, and a drain 106.

Currently, a floating gate type charge storage type memory element using polysilicon for the charge storage layer 102 is mainly used, and the first and second charge barrier layers 101 and 103 are made of SiO ₂ films. is there. The charge storage layer 102 is made of polysilicon and has a floating gate. A voltage is applied between the semiconductor layer 100 and the gate electrode 104, a charge is injected from the semiconductor layer 100 to the gate electrode 104 through the first charge barrier layer 101, and the charge is stored in the charge storage layer 102, thereby obtaining a MOS. Information is stored by changing the transistor threshold.

  This floating gate type charge storage type storage element holds the charge stored in the charge storage layer 102 for 10 years or more in order to store information for 10 years or more. For this reason, the first and second charge barrier layers 101 and 103 must be excellent in electrical insulation and should not be conductive to a weak electric field. Injecting or extracting charges (that is, writing or erasing information) to the charge storage layer 102 increases the voltage applied between the semiconductor layer 100 and the gate electrode 104 and flows through the first charge barrier layer 101 by a strong electric field. This is done by Fowler-Nordheim type (FN type) tunneling current and other conduction mechanisms appearing under strong electric fields. Since the FN tunnel current flows when the kinetic energy acquired from the electric field in the range of the spread of the wave function becomes larger than the triangular potential barrier formed by the electric field in the insulating film, the FN tunnel current flows. Flows when applied to the insulating film.

The first charge barrier layer 101 is made of a material that hardly leaks in a low electric field, has a large barrier height between the semiconductor layer 100 and the charge barrier layer 101, and has MOS interface characteristics. Therefore, it is necessary to use a thermally oxidized SiO ₂ film exclusively. The barrier height ΔEc (energy difference at the bottom of the conduction band) of the SiO ₂ film with respect to electrons in the conduction band of (100) plane orientation Si is about 3.5 eV (see, for example, Non-Patent Document 1). The second charge barrier layer 103 is thicker than the first charge barrier layer 101 in order to prevent current from flowing.

Reading of information is performed depending on whether or not a current flows when a voltage is applied to the gate electrode 105 of the MOS transistor whose threshold value has changed due to charge accumulation and a voltage is applied between the source 105 and the drain 106. This read operation is almost the same as the operation of a normal MOS transistor. However, since the second charge barrier layer 103 and the charge storage layer 102 are thick, it is necessary to apply a high gate voltage. In addition, the floating gate type accumulates charges in conductive polysilicon, and the charge retention depends on the insulating performance of the first charge barrier layer 101. For this reason, the floating gate type charge storage type storage element has difficulty in reducing the thickness of the first charge barrier layer 101 ( _{7 to 8} nm by the SiO ₂ film). 10-20V) has also reached its limit. Therefore, an example using polyacetylene (for example, see Patent Document 1) or the like has been proposed in order to store a large amount of charge in the charge storage layer 3 that functions as a floating gate.

In addition to the above floating gate type, the charge storage type storage element includes an insulating film trap type that traps charges at localized levels where defects are generated. In an insulating film trap type charge storage type memory element, a SiN film or an A1 ₂ O ₃ film is used for the charge storage layer 102, and these include a MONOS (metal oxide nitde oxide silicon) type or an NROM (multi-bit type). There are types such as a mold or a SONOS (silicon oxide nitride oxide silicon) mold (for example, see Non-Patent Document 2). Research and development of an insulating film trap type charge storage type storage element has been energetically conducted for future increase in capacity. In addition, since the charge trap memory storage element of the insulating film trapping traps charges at a localized level created by a defect in the insulating film, the first charge barrier layer 101 is locally turned on by a defect or the like. However, the charge trapped in the localized level in the vicinity of the defect only escapes, and not all the charges in the charge storage layer 102 escape, but the insulation requirement of the first charge barrier layer 101 is required. The conditions are more relaxed than the floating gate type charge storage type storage element. Therefore, in the insulating film trap type charge storage type storage element, the first charge barrier layer 101 can be thinned so that carriers can tunnel, and the voltage for writing, reading, and erasing information can be lowered.

  However, there is a limit to the insulating film trap type charge storage type storage element. In other words, since the insulating film trap type charge storage type memory element needs to trap charges in the deep localized level of the insulating film and suppress conduction between the traps, the spatial density of the trap cannot be increased. The distance between traps is considered to be 5 nm or more. Therefore, in order to trap the amount of charge necessary to change the threshold value of the transistor, a relatively large volume is required for the insulating film. Therefore, there is a limit to miniaturization of elements, and there is a limit to lowering the voltage.

  Next, a direct tunnel memory similar in operation to the memory element of the present invention will be described. In the direct tunnel memory, first, the first charge barrier layer 101 of the floating gate type charge storage type storage element shown in FIG. 11 is formed to be extremely thin so that a direct tunnel current can flow. It has been devised as a storage element that accumulates and performs a storage operation. When the first charge barrier layer 101 is thinned to about 2 nm, a direct tunnel current flows through the first charge barrier layer 101 as shown in an example of the band diagram of FIG. Can be made.

  However, in the direct tunnel memory having the structure of FIG. 11, the charge in the charge storage layer 102 easily escapes to the source 105 or the drain 106 by the direct tunnel phenomenon through the overlap between the charge storage layer 102 and the source 105 and drain 106. There was a drawback of end.

  Therefore, a direct tunnel memory having the structure shown in FIG. 13 has been proposed (see, for example, Non-Patent Document 3). In FIG. 13, 114 and 114 ′ are gate electrodes, which are provided on the left and right sides of the charge storage layer 112. In the structure of FIG. 13, since the charge storage layer 112 does not overlap the source 115 and the drain 116, the charge in the charge storage layer is difficult to escape. This type of memory is capable of high-speed writing / erasing with a low voltage, but since the charge moves through the first charge barrier layer 101 by a direct tunnel, it cannot hold the charge for a long time, and the flash It has an intermediate charge retention time between memory and DRAM (dynamic random access memory). As is well known, since the direct tunnel current is very sensitive to the thickness of the insulating film of the first charge barrier 101, it is difficult to control the film thickness of the extremely thin charge barrier layer and to ensure uniformity. There is a drawback.

  Next, the DRAM will be described. The DRAM is generally a 1T1C type in which one transistor and one capacitor are used as one cell. Information is written by storing charge in the capacitor through the channel of the transistor. A transistor serves as a switch, and information is stored by storing electric charge in a capacitor. Since the charge stored in the capacitor leaks mainly through the semiconductor layer of the transistor (the pn junction between the source / drain and the substrate), it disappears in a relatively short time. Therefore, information is detected and rewritten frequently (on the order of 100 msec) to maintain information storage. In recent miniaturized cells, a 5-10 μm deep trench (deep trench) is dug in a Si substrate, an oxide film is grown on the surface of the trench, the trench is then filled with polysilicon, and the Si substrate and polysilicon Is used as a capacitor.

  Recently, in order to promote further miniaturization, a cylindrical protrusion or fin is formed on the wiring to increase the area, and an insulating film and an electrode are formed on the surface to form a capacitor. In future predictions (for example, see Non-Patent Document 4), an insulating film having a high dielectric constant is used, and an MIM (metal insulator metal) capacitor is formed on the wiring to secure the capacitance of the fine element. It can be said that the capacity of the DRAM is determined by how much the capacitor can be miniaturized. According to Non-Patent Document 4, the dielectric constant of the insulating film of the MIM capacitor in the DRAM is required to exceed 100 even in the near future, and in the future, a value exceeding 1000 is required. As a material for realizing such a high dielectric constant, a material having a perovskite crystal structure is considered. Further, expensive metals such as Pt, Ru, and Ir that promote crystallization of perovskite crystals are required for the lower and upper electrodes. The electrode has a multilayer film structure that shares functions with expensive materials, and the number of manufacturing steps is remarkably increased, so that an increase in cost is inevitable.

JP-A-5-152576 J. Robertson, J. Vac. Sci. Technl. B18, 1785 (2000). Nikkei Microdevice, June 2003, pages 85-90. Futaki, Usuki, Horiguchi, FED Journal, Vol. 11, No. 4, pp. 67-75, 2000. International Technology Roadmap for semiconductors, URL: http://www.itrs.net/.

  As described above, the floating gate type charge storage type storage element has a limit to lowering the voltage, the insulating trap type charge storage type storage element has a limit to miniaturization, and the direct memory has a direct tunnel. The current is sensitive to the thickness of the insulating film of the barrier layer, and it is difficult to ensure the control and uniformity of the film thickness. Further, the DRAM has a 1T1C type, and a capacitor is essential, resulting in a high cost.

  An object of the present invention is to propose a memory element in which charges are moved by a Schottky current based on an operating principle different from that of the memory element described above, and the drawbacks of the memory element are eliminated.

  The memory element of the invention according to claim 1 is a semiconductor layer, a first charge barrier layer on the semiconductor layer, a charge storage layer on the first charge barrier layer, and a second charge barrier on the charge storage layer. In a field effect transistor type semiconductor memory device having at least a gate electrode on the second charge barrier layer, a predetermined material is used for the semiconductor layer, the first charge barrier layer, and the charge storage layer. This causes electrical conduction by Schottky emission between the semiconductor layer and the charge storage layer, stores charge in the charge storage layer, and stores information by changing the threshold value of the field effect transistor due to the charge. Let it be fine.

According to a second aspect of the present invention, in the memory element according to the first aspect, the semiconductor layer has a semiconductor with the following material having an energy gap of about 1 eV: single crystal silicon, polysilicon, amorphous silicon, Ge, SiGe, A material selected from GaAs, a compound semiconductor based on GaAs, a compound semiconductor based on InP, InP, and InN, β-FeSi ₂ , and the first charge barrier layer is the semiconductor layer The first barrier against the electric charge is 2 eV or less (excluding 0 eV), and the second barrier against the electric charge in the charge storage layer is 2 eV or less (excluding 0 eV). It is characterized by that.

The invention according to claim 3 is the memory element according to claim 1 or 2, wherein the charge is a negative charge due to electrons, and the first charge barrier layer is based on SiC, GaAs, or GaAs. Semiconductors, compound semiconductors based on InP, InP, GaN, AlN, ZnO, ZnS, CuO, CdS, CdSe, oxides of metal elements (Ti, Y, Zr, Hf, Ta, La series elements) and oxynitrides Among the aluminates and their nitrides, titanate compounds (MTiO ₃ , M is a divalent and transition metal element), and zirconate compounds (MZrO ₃ , M is a divalent and transition metal element) The charge storage layer is a compound semiconductor based on Si, Al, Ta, Ge, SiGe, GaAs, GaAs, GaP, GaSb. InP, compound semiconductors and InP as a matrix, HfSi, that the _{ZrSi 2, TaSi 2, VSi 2} , TiSi 2, CrSi 2, WSi 2, MoSi 2, TiN, one selected from among TaN material Features.

The invention according to claim 4 is the memory element according to claim 1, wherein the semiconductor layer is made of one selected from SiC, diamond, GaN, and ZnO, and the first charge barrier layer is , SiO ₂ , SiN, SiON, A1 ₂ O ₃ , AlN, AlON, SiAlO, and SiAlON.

  The invention according to claim 5 is the memory element according to claim 2 or 3, wherein the second barrier is made larger than the first barrier.

  A memory element according to a sixth aspect of the invention includes a semiconductor layer, a third charge barrier layer on the semiconductor layer, a charge storage layer on the third charge barrier layer, and a fourth charge barrier on the charge storage layer. In a field effect transistor type semiconductor memory device having at least a layer and a gate electrode on the fourth charge barrier layer, a predetermined material is used for the charge storage layer, the fourth charge barrier layer, and the gate electrode To cause electrical conduction by Schottky emission between the gate electrode and the charge storage layer, store the charge in the charge storage layer, and store information by changing the threshold value of the field effect transistor due to the charge. And

According to a seventh aspect of the present invention, in the memory element according to the sixth aspect, the semiconductor layer has a semiconductor with the following material having an energy gap of about 1 eV: single crystal silicon, polysilicon, amorphous silicon, Ge, SiGe, One selected from GaAs, a compound semiconductor based on GaAs, a compound semiconductor based on InP, InP, and InN, β-FeSi ₂ is a material, and the gate electrode is a material having conductivity. And the fourth charge barrier layer has a fourth barrier against the charge of the gate electrode of 2 eV or less (however, does not include 0 eV), and the third barrier against the charge of the charge storage layer is It is a material that is 2 eV or less (however, 0 eV is not included).

The invention according to claim 8 is the memory element according to claim 6 or 7, wherein the charge is a negative charge due to electrons, and the gate electrode is formed of polysilicon, Ge, transition metal silicide, Ti, TiN, Ta, 4. The fourth charge barrier layer according to claim 3, wherein the fourth charge barrier layer is made of one selected from TaN, W, Al, Cu, Pt, Au, Ru, RuO ₂ , Ir, and IrO _2. One of the materials mentioned as the material of the barrier layer is a material, and the charge storage layer is one of materials mentioned as a material of the charge storage layer in claim 3.

  According to a ninth aspect of the present invention, in the memory element of the sixth aspect, the fourth charge barrier layer is made of a covalent semiconductor, and the gate electrode is made of one of Al, divalent metal, and transition metal. The charge storage layer is made of one of Al, divalent metal, and transition metal.

According to a tenth aspect of the present invention, in the memory element of the sixth aspect, the semiconductor layer is made of one selected from SiC, diamond, GaN, and ZnO, and the fourth charge barrier layer is made of SiO. ₂ , SiN, SiON, A1 ₂ O ₃ , AlN, AlON, SiAlO, SiAlON are used as a material.

  The invention according to claim 11 is the memory element according to claim 7 or 8, wherein the third barrier is made larger than the fourth barrier.

  The memory element of the present invention is a memory element that operates on a principle different from that of a conventional memory element, in which electrons flow over the lower end of the conduction band of the charge barrier layer, or the upper end of the valence band has holes. The charge is transferred by a Schottky current that flows over the heat, so it is not sensitive to the thickness of the charge barrier layer, and does not induce defects in the insulating film of the charge barrier layer. Can do. Furthermore, it is not necessary to use expensive materials, and the manufacturing cost of the future large-capacity memory can be greatly reduced.

  Further, while the existing DRAM is configured by 1T1C, the memory element of the present invention can obtain the function of the DRAM only by 1T. Reading data from the 1T1C type DRAM is destructive reading, and rewriting is performed immediately after reading. However, the memory element of the present invention can read data nondestructively, and this point is also superior to the 1T1C type DRAM. ing. In addition, since the EOT of the gate insulating film can be reduced, the cell area can be reduced, and future scaling can be supported for a long time.

  Examples of the present invention will be described below.

  FIG. 1 is a diagram showing a schematic cross-section of the basic configuration of Embodiment 1 of the memory element of the present invention. A first charge barrier layer 2, a charge storage layer (also called floating gate electrode) 3, a second charge barrier layer 4, and a gate electrode (also called control gate electrode) 5 are sequentially stacked on the semiconductor layer 1, at both ends. A source 6 and a drain 7 are arranged. The charge storage layer 3 functions as a floating gate electrode, and the gate electrode 5 functions as a control gate electrode.

FIG. 2 is a band diagram of the memory element of FIG. 1, and the same parts as those in FIG. Although the case where the semiconductor layer 1 is p-type will be described, even if it is n-type, if the p-type inversion layer is read as an n-type accumulation layer, the operation is almost the same. FIG. 2 shows a case where no voltage is applied to the gate electrode 5 and the energy levels of the Fermi level 8 of the semiconductor layer 1 and the Fermi level 9 of the gate electrode 5 are equal. 10 is the upper end (Ev) of the valence band of the semiconductor layer 1, and 11 is the lower end (Ec) of the conduction band. The case where the same material as the semiconductor layer 1 is used for the charge storage layer 3 is shown. If the semiconductor layer 1 is silicon, the charge storage layer 3 is polysilicon. In this case, the first barrier phi _Be1 and the second phi _Be2 are close values for electrons (approximately the same value).

An operation when electrons are stored in the charge storage layer 3 will be described. As shown in FIG. 3, a positive voltage is applied to the gate electrode 5 with respect to the semiconductor layer 1, and the portion in contact with the charge barrier layer 2 at the lower end 11 of the conduction band of the semiconductor layer 1 is below the Fermi level 8. As a result, an inversion layer appears on the charge barrier layer 2 side of the semiconductor layer 1, and electrons that are minority carriers appear in the vicinity of the charge barrier layer 2. Here, when the thermal energy acquired by the electrons in the inversion layer is larger than the barrier φ _{Be 1} , the electrons in the inversion layer move over the barrier φ _{Be 1} and are trapped in the charge storage layer 3.

  Such a current is a current due to Schottky emission of electrons. The present invention utilizes current due to Schottky emission. When the voltage of the gate electrode 5 is returned to the original level 12 of 0V, electrons are stored in the charge storage layer 3 for a while. In that state, the threshold voltage of the transistor, that is, the gate voltage at which the inversion layer is formed in the semiconductor layer 1 requires a larger positive voltage than the state in which electrons are not accumulated in the charge accumulation layer 3. This can be easily understood by considering the fact that the electron-electron coulomb repulsion acts.

  That is, while the electrons are trapped in the charge storage layer 3, the threshold value of the transistor is shifted to the positive side. This state can be a state in which information “0” is written. This “0” information can be detected by detecting that the transistor does not turn on when a gate voltage that turns on the transistor is applied in a state where no charge is accumulated in the charge accumulation layer 3.

When the charge storage layer 3 is polysilicon, electrons in the charge storage layer 3 can exceed the barrier φ _Be2 , and if left untreated, electrons in the charge storage layer 3 escape to the semiconductor layer 1. Therefore, the threshold value of the transistor is detected before all the electrons accumulated in the charge accumulation layer 3 escape, and it is determined whether or not electrons are accumulated in the charge accumulation layer 3. Can maintain the written information by rewriting. That is, periodic refreshing may be performed.

Next, an operation when information “1” is written will be described. FIG. 4 shows a case where a negative voltage is applied to the gate electrode 5 with respect to the semiconductor layer 1. The electrons stored in the charge storage layer 3 move over the barrier φ _Be2 and move to the semiconductor layer 1, and the charge storage layer 3 has no charge. At this time, if holes in the valence band of the semiconductor layer 1 get over the barrier φ _Bh1 , the holes are accumulated in the charge accumulation layer 3. Not related to memory operation. That is, even if there is no charge in the charge storage layer 3 or a positive charge exists, the threshold value of the transistor is lower than when the negative charge is stored. Because it can be regarded.

As a method for a longer period of time holds the electrons stored in the charge storage layer 3, a method of the height of the second barrier phi _Be2 larger than the first barrier phi _Be1 is valid. By doing so, it becomes difficult for the charge to escape toward the semiconductor layer 1 in a memory retention state where no voltage is applied to the gate electrode 5.

The height of the barrier that a part of the electrons excited by the heat at room temperature or the operating temperature of the device (room temperature to 90 ° C.) is about 2 eV or less (however, 0 eV is not included). The current due to Schottky emission is noticeable when the barrier height is 1 eV or less (however, 0 eV is not included). The current (J) flowing by Schottky emission is given by equation (1) (SMSze, semiconductor device physics (2), Yanai, Odagawa, Ikoma, Translated by Corona, 3rd edition, 1975, 118).
J = A ^* T ² exp {−q (φ _B − (qE / (4πε _i ))) / kT} (1)
Where A ^* is the effective Richardson constant, T is the absolute temperature, q is the elementary charge, φ _B is the height of the barrier, E is the magnitude of the electric field, and ε _i is the insulating film (first charge barrier layer 2) And k is a Boltzmann constant.

In the equation (1), the numerator of the exponential function is the activation energy for the movement of electrons, but decreases as the electric field E increases. The reduction rate depends on the dielectric constant ε _i of the insulating film. Since the electrons accelerated by the electric field are usually faster than the movement of the ionized elements in the insulator, this dielectric constant ε _i is different from the dielectric constant measured at frequencies below the frequency of infrared radiation. The dielectric constant is measured by stopping the movement of the element (in the adiabatic state). In addition, since it is affected by the image force, it should be noted that the value varies depending on whether the insulating film is in contact with a low-resistance metal or a semiconductor. In the case of contact with a semiconductor (including a semiconductor doped with a high concentration of impurities), the carrier density is not so high, and the influence of the image force is negligible. Further, when the insulating film is extremely thin, due to the effect of the image force, the height phi _B own barriers it is necessary to note that reduced. Such a phenomenon is observed in, for example, an Al / HfO ₂ / Si layered system (K. Saito, Y. Jin, and M. Shimada, “MOS Diode Characteristic with HfO ₂ Gate Insulator Deposited by ERC. Spattring ”Journal of the Electrochemical Society, Vol. 151, 2004, pp. G327). Therefore, by selecting a material for the height of the moderate barrier phi _B as the charge blocking layer 2, it is possible to feed the electrons by Schottky released into the charge accumulation layer 3.

When the semiconductor layer 1 is silicon, a material suitable as the first charge barrier layer 2 is such that the energy at the lower end of the conductor is higher than the energy at the lower end 11 of the silicon conductor, and the difference ΔEc between them. (Barrier φ _Be1 ) is considered to be an insulator or a semiconductor having 2 eV or less (but not including 0 eV). This is because it must be small enough to allow current flow due to Schottky emission. As reported in the above-mentioned document, the present invention confirms the Schottky emission current with a structure in which ΔEc is considered to be 1.2 to 2.1 eV. Examples of such materials are SiC, III-V compound semiconductors (GaAs, InP, GaN, AlN, etc.), II-VI group compound semiconductors (ZnO, ZnS, CuO, CdS, CdSe, etc.), transition metals, for example. Among oxides of elements, those having a small ΔEc (TiO ₂ , YO ₂ , ZrO ₂ , HfO ₂ , Ta ₂ O ₅ , oxides of La series elements) and their nitrides, silicates of Hf and Zr (HfSiO ₄ and ZrSiO ₄ ), aluminates (Al-containing oxides) and nitrides thereof, titanic acid compounds ((MTiO ₃ , M is divalent (Be, Mg, Ca, Sr, Ba) and transition metal elements), Zirconic acid compounds (MZrO ₃ , M is a divalent and transition metal element) and the like.

Incidentally, ΔEc of SiO ₂ , Si ₃ N ₄ , and A1 ₂ O ₃ and Si have reported values of 3.5, 2.4, and 2.8 eV, respectively (J. Robertson, J .Vac.Sci.Technol.B18, 1785 (2000).) In fact, there are many reports that these FN tunnel-type currents flow in these insulating films, which is not suitable for the first charge barrier layer 2. .

ΔEc of the laminated structure of HfO ₂ / Si is reported in the range of 1.1 to 2.0 eV in theoretical calculation values and experimental values. The theoretical calculation value of ΔEc and the reported value of the experimental value vary due to accuracy problems. In the current measurement by the inventors of the present application, as reported in the above-mentioned document, Schottky emission current is observed in n-type silicon and HfO ₂ .

The barrier φ _B (that is, ΔEc) obtained from the measured temperature dependence of the current was 1.2 eV in the case of the HfO ₂ film having a thickness of 5 nm. In other reports, there is a report example of current due to Frenke1-Poole (FP) type emission, in which current flows through a defect in the film. It is considered that it depends on the film quality of the insulating film as the charge barrier layer 2. When the defect density of the insulating film is low, the FP type emission is not dominant, and the Schottky type or the FN tunnel type is dominant.

In the first embodiment, the current by the Schottky conduction mechanism is used as described above. The reason is that in the Schottky type conduction mechanism, a current flows even when an extremely weak electric field is applied to the first charge barrier layer 2, and the Schottky type conduction mechanism is insulated as the first charge barrier layer 2. This is because it is considered that no defect is generated in the film, and there is a high possibility that the repeated operation with respect to 10 ¹⁵ times of writing and reading, which is the basic performance of DRAM, can be compensated.

  Incidentally, it is considered that the FN tunnel type current also does not cause a defect in the barrier itself, but in order to pass the FN tunnel type current, a strong electric field is formed in the first charge barrier layer 2 and the carrier The kinetic energy of must be increased. Therefore, it is considered that the FN tunnel current easily induces a defect in the insulating film as the first charge barrier layer 2, and the FN tunnel current stress is applied to the MOS capacitor or the MOS transistor using the thermal oxide film. In an experiment evaluating interface properties, phenomena that increase interface states and traps have been reported (T. Hosoi, M. Akizawa, and S. Matsumoto, J. Appl. Phys. 57, 2072 (1985). S. Horiguchi, T. Kobayasbi, and K. Saito, J. Appl. Phys. 58, 387 (1985)). Therefore, there is anxiety about long-term reliability.

The charge storage layer 3 is not limited to polysilicon, but is a material that does not create a large amount of defects at the interface with the first charge barrier layer 2, and the height of the barrier φ _Be2 with the first charge barrier layer 2 is 2 eV. Any material that can emit electrons by Schottky emission at the operating temperature of the device may be used. Since the energy Ec from the vacuum level of silicon to the lower end 11 of the conductor is 4.05 eV, any material can be used as long as the Ec of the charge storage layer 3 or the work function of the metal is close to 4 eV.

Examples of such a material include Al (4.2 eV), Ta (4.2 eV), Ge (4.0 eV), GaAs (4.07 eV), GaP (4.3 eV), and GaSb (4.06 eV). And InP (4.4 eV) are suitable. A compound semiconductor based on GaAs or a compound semiconductor based on InP is also considered suitable. Among silicide, suitable relatively small work function, as a silicide having a work function of _{4.3~4.5eV, HfSi, ZrSi 2, TaSi} 2, VSi 2, TiSi 2, CrSi 2, WSi 2, And MoSi ₂ . It is known that a metal nitride has a relatively small work function of TiN or TaN.

In the first embodiment, the second charge barrier layer 4 serves to prevent charge transfer between the charge storage layer 3 and the gate electrode 5, and is the barrier higher than the first charge barrier layer 2? The film is thick, or the film satisfies both of them. In consideration of the low-voltage operation of the transistor, it is better to form a material with a high dielectric constant slightly thicker. An HfO ₂ film, an oxide of a La series element, or the like that can be expected to have a relatively large barrier height is preferable. A method of forming a thin A1 ₂ O ₃ film having a large barrier height and a relative dielectric constant of 8 to 10 is also effective.

The carriers stored in the charge storage layer 3 in FIG. 1 may be holes, and FIG. 5 shows a band diagram when an n-type semiconductor is used as the semiconductor layer 1. In FIG. 5, when a negative voltage is applied to the semiconductor layer 1 to the gate electrode 5 so that the upper end 10 of the valence band of the semiconductor layer 1 is above the Fermi level 8, an inversion layer is formed. Holes are induced near the charge barrier layer 2. When the energy of holes obtained from heat becomes larger than the first barrier φ _Bh1 , the holes are accumulated in the charge storage layer 3 beyond the barrier φ _Bh1 .

  Even when the voltage applied to the gate electrode 5 is returned to 0 V, the threshold value of the transistor is low while holes are accumulated in the charge accumulation layer 3, and the state where information “0” is written is maintained. . A voltage for turning on the transistor is applied to the gate electrode 5 in a state where holes are not accumulated in the charge storage layer 3, and the sense circuit detects that the transistor is not turned on, and reads the written information “0”. be able to. Since holes in the charge storage layer 3 escape to the semiconductor layer 1 due to thermal excitation, refreshing is performed while a change in the threshold value of the transistor can be detected. When a positive voltage is applied to the gate electrode 5, holes stored in the charge storage layer 3 can be returned to the semiconductor layer 1.

  Even when a negative voltage is applied to the gate electrode using a p-type semiconductor as the semiconductor layer 1, due to Schottky emission of holes from the charge storage layer 3 formed on the charge barrier layer 2 side of the semiconductor layer 1. The charge accumulation operation is the same as that of the inversion layer using an n-type semiconductor.

As a method for a longer period of time holds the holes stored in the charge storage layer 3, a method of the magnitude of the second barrier phi _BH2 larger than the first barrier phi _Bh1 is valid. By doing so, it becomes difficult for the charge to escape toward the semiconductor layer 1 in a memory retention state where no voltage is applied to the gate electrode 5.

  When silicon is used for the semiconductor layer 1, the insulator or semiconductor having a hole barrier height of 2 eV or less (excluding 0 eV) has a band gap of 4 eV or less (excluding 0 eV). Those are preferred. Since most of the energy at the upper end of the valence band of the oxide of the transition metal element is deep, a material having a small band gap such as a III-V group or II-VI group compound semiconductor is preferable.

FIG. 6 is a diagram showing a schematic cross section of Example 3 of the memory element of the present invention. This memory element is different from the memory element of Example 1 in the thicknesses of the first and second charge barrier layers 13 and 14, and the charge injection into the charge storage layer 3 is performed from the gate electrode 5, so that the first The second charge barrier layer (fourth charge barrier layer in claims) 14 is thin, and the first charge barrier layer (third charge barrier layer in claims) 13 is thick. The first charge barrier layer 13 may use a film having a large band gap such as a SiO ₂ film or an A1 ₂ O ₃ film in order to increase the barrier with the semiconductor layer 1. In view of this, it is better to use a high dielectric constant (High-k) gate insulating film, a film having a small equivalent oxide thickness (EOT) and a small leakage current. EOT is defined as follows.
EOT = {(dielectric constant of SiO ₂ film) ÷ (dielectric constant of high-k film)} × (film thickness of high-k film)
Recently, A1 ₂ O ₃ , AlON, HfO ₂ , RfON films, and the like have attracted attention as high-k films with low EOT and leakage current.

In the third embodiment, the relationship between the work function or Ec of the gate electrode 5, the Ec of the second charge barrier layer 14, and the work function or Ec of the charge storage layer 3 is important. The height of the barrier φ _Be3 between the charge barrier layers 14 and the height of the barrier φ _Be4 between the charge storage layer 3 and the gate electrode 5 must be small enough to allow current to flow due to Schottky emission. FIG. 7 shows a band diagram when the semiconductor layer 1 is an n-type semiconductor and the gate electrode 5 is applied with a negative voltage.

The heights of the third and fourth barriers φ _Be3 and φ _Be4 must be 2 eV or less (excluding 0 eV). In the case where a metal such as Al having a low resistivity is used for the gate electrode 5 and the second charge barrier layer 14 is extremely thin, the barrier φ _Be4 is remarkably compared with the case where it is thick due to the influence of the image force. It is also possible to obtain a small barrier φ _Be4 using the lowering.

The present inventors have found that the measured temperature dependence of the MOS diode leakage current, the gate electrode 5 as a second charge blocking layer 14, HfO ₂ film having a thickness of 2.2 nm (thickness estimated from the deposition rate) An experimental value of the height of the barrier φ _Be4 of 0.3 to 0.4 eV is obtained for the Al / HfO ₂ laminated structure. This value is significantly lower than the estimated height (1.4 to 2.2 eV) of the barrier φ _Be4 in the thick film. When the tunnel current is mixed, the height of the barrier _φBe4 becomes low, so the tunnel current is also mixed. However, since the leakage current has a clear measurement temperature dependence, it is considered that the current is due to Schottky emission.

When metal is used for the gate electrode 5 and the charge storage layer 3 and a covalent semiconductor such as silicon or germanium is used for the second charge barrier layer 14, the barrier φ _Be3 , φ having a height approximately half the energy gap of the semiconductor. You get _Be4 . In contrast to this phenomenon, due to the shielding effect of the wave function of the free electrons that ooze out from the metal, the semiconductor energy gap of about 1/2 atomic layer in contact with the metal is closed and metallized, and the Fermi level of the semiconductor in that part is free of metal. There is a theoretical study to be pinned to the Fermi level of electrons. The inventors of the present application believe that the influence of shielding of metal free electrons is also exerted on the reduction of the barrier height in Al / HfO ₂ .

As materials suitable for the gate electrode 5, various materials having conductivity can be considered. In the silicon process, polysilicon, Ge, transition metal silicide, Ti, TiN, Ta, TaN, W, Al, Cu, Pt, Au, Ru, RuO ₂ , Ir, IrO _{2 and the} like have been studied. Any combination of the charge barrier layer 14 and the charge storage layer 3 can be used. However, since the work function of the material of the gate electrode 5 becomes an important factor for determining the threshold value of the transistor, the material is determined in consideration thereof. There will also be new material developments to adjust the threshold.

  As a material of the second charge barrier layer 14, in consideration of the fact that the work function of the metal and the Ec and Ev of the semiconductor are approximately similar values without the influence of the shielding of the metal free electrons described above, It is considered that the semiconductor or the insulator having a relatively small band gap mentioned as the material suitable for the first charge barrier layer 2 can be applied as it is. The same applies to the charge storage layer 3.

  When electrons are injected from the gate electrode 5 into the charge storage layer 3 and stored, the threshold value of the transistor changes toward a higher gate voltage. When the change becomes large, the transistor is turned on without applying a voltage to the gate electrode 5. This state can be made to correspond to storage of information “1”, and a state in which a reverse polarity voltage is applied to the gate electrode 5 to extract electrons accumulated in the charge storage layer 3 can correspond to information “0”. Depending on the characteristics of the transistor, the change in the threshold value may be small, but “1” and “0” of the stored information can be detected by applying an appropriate bias voltage to the gate electrode 5 when reading the stored information. it can.

As a method for holding the electrons stored in the charge storage layer 3 for a longer period, a method in which the height of the third barrier φ _Be3 is larger than that of the fourth barrier φ _Be4 is effective. This makes it difficult for the charge to escape toward the gate electrode 5 in a memory retention state where no voltage is applied to the gate electrode 5.

  In the memory element of FIG. 6, a covalent semiconductor such as Si, Ge, SiGe, SiC, GaAs, InP is used for the second charge barrier layer 14, and Al, divalent metal, and the like are used for the gate electrode 5 and the charge storage layer 3. When a low resistance metal (several tens of μΩcm or less) such as a transition metal is used, holes can be injected from the gate electrode 5 into the charge storage layer 3. In such a configuration, the shielding of the metal free electrons that have exuded to the semiconductor side due to the quantum effect has the function of closing (metalizing) the semiconductor band gap, so that the closed semiconductor band is pinned to the Fermi energy of the metal. Is done. Since the center of the semiconductor band gap is at the same position as the work function of the metal, a small hole barrier of about 0.3 to 0.5 eV can be obtained without effort.

FIG. 8 shows a band diagram when a p-type semiconductor is used as the semiconductor layer 1 and a positive voltage is applied to the gate electrode 5. The holes of the gate electrode 5 get over the small fourth barrier φ _Bh4 of the second charge barrier layer 14 by Schottky emission, and are accumulated in the charge storage layer 3. This state changes the transistor threshold in a lower direction. If this change is large, the transistor can be turned on even when no voltage is applied to the gate electrode 5. This state is a state in which information “1” is written, and a state in which a negative voltage is applied to the gate electrode 5 to extract holes from the charge storage layer 3 (the transistor is turned off when no gate voltage is applied). It can be in a state where 0 ″ is written. Depending on the characteristics of the transistor, the change in the threshold value may be small, but “1” and “0” of the stored information can be detected by applying an appropriate bias voltage to the gate electrode 5 when reading the stored information. it can.

As a method for retaining the holes accumulated in the charge storage layer 3 for a longer period of time, the material of the gate electrode 5 and the charge storage layer 3 is appropriately selected, and the height of the third barrier φ _Bh3 is set from the fourth barrier φ _Bh4 . It is effective to increase the size. This makes it difficult for the charge to escape toward the gate electrode 5 in a memory retention state where no voltage is applied to the gate electrode 5.

  The above configuration is also effective for storing electrons in the charge storage layer 3. Although a positive voltage is applied to the gate electrode 5 in FIG. 8, when a negative voltage is applied, the electrons emitted from the gate electrode 5 pass over a small electron barrier of about 0.3 to 0.5 eV and charge storage layer. 3 can be stored.

In the description of Examples 1 to 4 above, the case where single crystal silicon is mainly used for the semiconductor layer 1 has been described. However, even if another semiconductor having a band gap of about 1 eV is used for the semiconductor layer 1, The memory element of the invention can be formed. Examples of semiconductors having a band gap of about 1 eV include compound semiconductors based on polysilicon, amorphous silicon, Ge, SiGe, GaAs, and GaAs, compound semiconductors based on InP and InP, and InN and β-FeSi _2. It is done.

  In the present invention, a memory element that operates in a high-temperature environment can be formed using a wide-gap semiconductor such as SiC, diamond, GaN, or ZnO that has recently attracted attention. Wide gap semiconductors have been applied to power devices by taking advantage of their high breakdown voltage characteristics. However, the carrier concentration is not easily affected by heat, so there is an advantage that transistors that can withstand use at high temperatures can be manufactured. is there. That is, it can be used for electronic equipment used in a high-temperature furnace. Alternatively, it is possible to provide a semiconductor device capable of high-temperature operation that is used for exploring planets with high surface temperatures.

As can be seen from the above equation (1), the Schottky emission of carriers from the semiconductor is a function of temperature. When the temperature increases, the current increases almost exponentially. Therefore, when the temperature increases, current can flow even when the barrier height φ _B increases. For example, in an environment of 200 to 300 ° C., a large Schottky current can flow even when the barrier height φ _B is about 2 to 3 eV. Therefore, when using the wide gap semiconductor as described above and operating the memory element of the present invention in a high temperature operating environment, ΔEc (φ _Be1 to φ _Be4 , φ _Bh1 to φ described above) between the charge barrier layer and the semiconductor layer is used. _Bh4 ) may be 2 eV or more. In that case, a material such as SiO ₂ , SiN, SiON, A 1 ₂ O ₃ , AlN, AlON, SiAlO, or SiAlON having a large band gap may be used for the charge barrier layer. it can.

  Next, an example of a cell configuration in the case where the memory element of the present invention is used as a memory and its driving circuit will be described. The memory element of the present invention stores information by utilizing a change in the threshold value of one transistor, and can be configured as a one-transistor memory cell 21 as shown in FIG. 22 is a word line control circuit, 23 is a bit line control circuit, and 24 is a sense circuit. For data writing, a write voltage is applied between the bit lines BL1 and BL2 and the word line WL.

  For example, in a memory element having a p-type semiconductor inversion layer as a channel like the memory element of the first embodiment, the write voltage of the word line WL is positive with respect to the bit lines BL1 and BL2 (FIG. 3). 0V is applied to the bit lines BL1 and BL2, and + 2V is applied to the word line WL.

  By this writing, negative charges are accumulated in the charge accumulation layer 3, and the threshold value of the transistor moves in the positive direction as shown in FIG. 10, so that a higher gate voltage is required to turn on the transistor. This state is a state in which information “0” is written. To read data, a read voltage is applied to the word line WL, and the on / off state of the transistor is determined by the sense circuit 24 connected to the bit lines BL1 and BL2. Although it is necessary to apply an appropriate voltage in consideration of the threshold offset voltage to the gate electrode 5, if the offset voltage is adjusted to 0 V, it is not necessary to apply the gate voltage. In this case, the data is read nondestructively. When data “1” is written, the voltages of the bit lines BL1 and BL2 are increased with respect to the word line WL. For example, 0V is applied to the word line WL, and + 2V is applied to the bit lines BL1 and BL2. The threshold of the transistor moves in the opposite direction, and turns on at a low gate voltage.

  Unlike the flash memory, this memory element does not need to erase information at a high voltage all at once, and can be stored by random access. However, the threshold value of the transistor depends on the charge held in the charge storage layer 3, and the charge holding time depends on the height and thickness of the charge barrier layer 2. In order to operate the memory at a high speed with a low voltage while securing a data retention time of several hundred milliseconds to several seconds, the barrier is lowered and the EOT is thinned. For this reason, the memory element needs to be periodically refreshed. The refresh is performed by reading the data within the data holding time, reading it, and writing the same data as in the case of the 1T1C type DRAM using the existing capacitor.

It is a figure which shows schematic sectional structure of the memory element of Example 1 of this invention which made the semiconductor layer p-type. FIG. 3 is a diagram showing a band diagram when no voltage is applied to the gate electrode of the memory element of Example 1. 3 is a diagram showing a band diagram when a positive voltage is applied to the gate electrode of the memory element of Example 1 with respect to the semiconductor layer. FIG. FIG. 3 is a diagram showing a band diagram when a negative voltage is applied to the gate electrode of the memory element of Example 1 with respect to the semiconductor layer. FIG. 6 is an explanatory diagram of a memory element according to Example 2 of the present invention in which the semiconductor layer is n-type in the structure of FIG. It is a figure which shows the general | schematic cross-section of the memory | storage element of Example 3 of this invention which made the semiconductor layer n-type, made the 1st charge barrier layer thick, and made the 2nd charge barrier layer thin. It is a figure which shows a band diagram when a negative voltage is applied with respect to a semiconductor layer to the gate electrode of the memory element of Example 3. FIG. 7 is an explanatory diagram of Example 4 of the present invention in which the semiconductor layer is p-type in the structure of FIG. 6, and is a diagram illustrating a band diagram when a negative voltage is applied to the gate electrode with respect to the semiconductor layer. It is a figure which shows the basic circuit of the charge storage type memory of Example 5 of this invention. FIG. 10 is a diagram for explaining an operation of a transistor of the memory element in FIG. 9. It is a schematic sectional drawing which shows the conventional charge storage memory element (flash memory). It is a figure which shows the band diagram for demonstrating the operating principle of the conventional direct tunnel memory. It is a figure which shows the outline of the cross-section of the conventional improved direct tunnel memory.

Explanation of symbols

1: Semiconductor layer 2: First charge barrier layer 3: Charge storage layer (also known as floating gate electrode)
4: Second charge barrier layer 5: Gate electrode (also known as control gate electrode)
6: source 7: drain 8: Fermi level of semiconductor layer 9: Fermi level of gate electrode 10: upper end of valence band of semiconductor layer 11: lower end of conduction band of semiconductor layer 12: level of 0V 13: first (first) 3) of the charge barrier layer 14: second (electron barrier layer of the 4) e ^-: electronic h ^+: a hole _{φ Be1, φ Be2, φ Be3} , φ Be4,: barrier phi _Bh1 for electrons, φ _Bh2, φ _Bh3 , φ _Bh4 : Barrier against holes

Claims (11)

A semiconductor layer; a first charge barrier layer on the semiconductor layer; a charge storage layer on the first charge barrier layer; a second charge barrier layer on the charge storage layer; and the second charge barrier layer In a field effect transistor type semiconductor memory device having at least an upper gate electrode,
By using a predetermined material for the semiconductor layer, the first charge barrier layer, and the charge storage layer, electrical conduction is caused by Schottky emission between the semiconductor layer and the charge storage layer, and a charge is generated in the charge storage layer. And storing information by changing a threshold value of the field-effect transistor due to the electric charge. The memory element according to claim 1, wherein
The semiconductor layer is a semiconductor of the following material having an energy gap of about 1 eV: a compound semiconductor based on single crystal silicon, polysilicon, amorphous silicon, Ge, SiGe, GaAs, GaAs, or a compound based on InP, InP. One selected from semiconductor, InN, β-FeSi ₂ is used as a material,
In the first charge barrier layer, the first barrier against the charge of the semiconductor layer is 2 eV or less (excluding 0 eV), and the second barrier against the charge of the charge storage layer is 2 eV or less ( However, the memory element is a material that does not include 0 eV. The memory element according to claim 1 or 2,
The charge is a negative charge due to electrons,
The first charge barrier layer includes a compound semiconductor based on SiC, GaAs, GaAs, a compound semiconductor based on InP, InP, GaN, AlN, ZnO, ZnS, CuO, CdS, CdSe, a metal element (Ti, Y, Zr, Hf, Ta, La series elements) oxides and oxynitrides, aluminates and their nitrides of the metal elements, titanate compounds (MTiO ₃ , M is a divalent and transition metal element), and , One selected from zirconate compounds (MZrO ₃ , M is a divalent and transition metal element),
The charge storage layer, Si, Al, Ta, Ge , SiGe, GaAs, compound semiconductors of GaAs as a matrix, GaP, GaSb, InP, compound semiconductors and InP as a _{matrix, HfSi, ZrSi 2, TaSi 2} , VSi 2 , TiSi ₂ , CrSi ₂ , WSi ₂ , MoSi ₂ , TiN, TaN. The memory element according to claim 1, wherein
The semiconductor layer is made of one selected from SiC, diamond, GaN, and ZnO,
The memory element, wherein the first charge barrier layer is made of one selected from SiO ₂ , SiN, SiON, A 1 ₂ O ₃ , AlN, AlON, SiAlO, and SiAlON. The memory element according to claim 2 or 3,
A memory element, wherein the second barrier is made larger than the first barrier. A semiconductor layer; a third charge barrier layer on the semiconductor layer; a charge storage layer on the third charge barrier layer; a fourth charge barrier layer on the charge storage layer; and the fourth charge barrier layer In a field effect transistor type semiconductor memory device having at least an upper gate electrode,
By using a predetermined material for the charge storage layer, the fourth charge barrier layer, and the gate electrode, electrical conduction is caused by Schottky emission between the gate electrode and the charge storage layer, and a charge is generated in the charge storage layer. And storing information according to a change in the threshold value of the field effect transistor due to the electric charge. The storage element according to claim 6.
The semiconductor layer is a semiconductor of the following material having an energy gap of about 1 eV: a compound semiconductor based on single crystal silicon, polysilicon, amorphous silicon, Ge, SiGe, GaAs, GaAs, or a compound based on InP, InP. One selected from semiconductor, InN, β-FeSi ₂ is a material,
The gate electrode is a conductive material,
In the fourth charge barrier layer, the fourth barrier against the charge of the gate electrode is 2 eV or less (excluding 0 eV), and the third barrier against the charge of the charge storage layer is 2 eV or less. A memory element characterized by being a material that does not include 0 eV. The storage element of claim 6 or 7,
The charge is a negative charge due to electrons,
The gate electrode is one selected from polysilicon, Ge, transition metal silicide, Ti, TiN, Ta, TaN, W, Al, Cu, Pt, Au, Ru, RuO ₂ , Ir, and IrO _2. As a material,
The fourth charge barrier layer is made of one of the materials mentioned as the material of the first charge barrier layer in claim 3,
4. The memory element according to claim 3, wherein the charge storage layer is made of one of the materials mentioned as the charge storage layer in claim 3. The storage element of claim 6.
The fourth charge barrier layer is made of a covalent semiconductor,
The gate electrode is made of one of Al, divalent metal, and transition metal,
The memory element, wherein the charge storage layer is made of one of Al, divalent metal, and transition metal. The storage element of claim 6.
The semiconductor layer is made of one selected from SiC, diamond, GaN, and ZnO,
The memory element, wherein the fourth charge barrier layer is made of one selected from SiO ₂ , SiN, SiON, Al ₂ O ₃ , AlN, AlON, SiAlO, and SiAlON. The memory element according to claim 7, wherein the third barrier is larger than the fourth barrier.

Images