JP2005235844A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having an ESD protection element capable of decreasing the operating resistance by making the avalanche voltage of a pn diode lower than that of an element to be protected (MOSFET). <P>SOLUTION: Avalanche voltage of a pn diode is made lower than that of an MOSFET 21 by forming a 3n well region 15 in contact with a 2n well region 12 on the outer circumference of the 2n well region 12, and making the diffusion depth L3 of the 3n well region deeper than the diffusion depth L1 of a 1n well region and the diffusion depth L2 of the 2n well region. Furthermore, operating resistance of a pnp transistor is decreased by making shallow the diffusion depth L2 of the 2n well region. Consequently, an ESD protection element 20 having an avalanche voltage lower than that of the MOSFET 21 and a small operating resistance can be formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which an ESD protection element for preventing electrostatic discharge (ESD) breakdown and the like is formed.

The electrostatic discharge is generated from other circuit portions or insulators of the device in which the semiconductor device is arranged, or a human body handling the semiconductor device, and causes destruction or damage of the semiconductor device. ESD (hereinafter referred to as an ESD surge) is an important factor that affects the reliability of a semiconductor device, and it is desirable to sufficiently increase the breakdown resistance against the ESD surge in order to ensure more stable operation. In particular, in the automobile field and the like, there are many occasions where charged people and objects come into contact with each other, and there is a demand for a power IC having a large ESD breakdown resistance.
The example which discloses the ESD protection element which protects an element from this ESD surge is demonstrated.
In the first example, a Zener diode having a withstand voltage lower than that between the drain and the substrate is provided between the source and drain of the lateral high-frequency power MISFET, and this Zener diode is used as an ESD protection element to improve the breakdown strength against ESD surge current. (Patent Document 1).

In the second example, in the up-drain MOSFET, a p base region extends adjacent to the deep n ⁺ region (drain region) in the surface layer portion of the n well layer, and the p base region is identical to the deep n ⁺ region. The p ⁺ region (p base region) is connected to the source electrode. Thus, it is described that a surge bypass diode (ESD protection element) is formed between the source and the drain to protect the MOSFET from the ESD surge (Patent Document 2).
Next, a conventional ESD protection element having a structure different from the above example will be described.
FIG. 5 is a cross-sectional view of a main part of a semiconductor device having a conventional ESD protection element. The ESD protection element 70 is a base-emitter short pnp transistor 68 and the protected element is a lateral MOSFET 21.

A p epitaxial layer 52 (concentration is about 1 × 10 ¹⁵ cm ⁻³ ) having a concentration lower than that of the p substrate 51 is formed on the high concentration p substrate 51, and an impurity concentration of 1 × 10 6 is formed on the surface layer of the p epitaxial layer 52. A first n-well region 53 having a thickness of about ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ and a thickness of about 2 to 5 μm is formed. A p-well region 54 having an impurity concentration of about 5 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ and a thickness of about 1 μm to 2 μm is formed on the surface layer of the first n-well region 53. An n source region 55 and an n drain region 56 are formed on the surface layer of the p well region 54, and a gate having a thickness of several tens of nm is formed on the p well region 54 sandwiched between the n source region 55 and the n drain region 56. A gate electrode 58 is formed of polysilicon through an oxide film 57. On the surface layers of the n source region 55 and the n drain region 56, a high concentration n layer (not shown) for ohmic contact is formed. A LOCOS oxide film 59 for increasing the breakdown voltage is formed on the drain side.

On the other hand, a second n well region 62 having an impurity concentration higher than that of the first n well region 53 and a deep diffusion depth is formed on the surface layer of the p epitaxial layer 52 apart from the first n well region 53. A p emitter region 63 and an n short region 64 that short-circuits the p emitter region 63 are formed in the surface layer of the well region 62. An emitter electrode 66 is formed on the p emitter region 63 and the n short region 64, and a back electrode 67 is formed on the back surface of the p substrate 51. The p-substrate 51, the p-epitaxial layer 52, the second n-well region 62, the p-emitter region 63, and the n-short region 64 form a base-emitter short-type pnp transistor 68. The pnp transistor 68 serves as an ESD protection element 70.
FIG. 6 is a diagram showing the relationship between the diffusion depth of the second n-well region and the avalanche voltage. The avalanche voltage decreases as the diffusion depth L5 of the second n-well region 62 increases. As described above, by increasing the diffusion depth L5 of the second n-well region 62 from the diffusion depth L4 of the first n-well region 53, the avalanche voltage of the pnp transistor 68 is made lower than the avalanche voltage of the MOSFET 21, and the ESD surge. Is applied, the ESD surge current is passed through the ESD protection element 70 to extract the charge, thereby preventing the MOSFET 21 from being damaged by ESD.

In the pnp transistor 68, when the base is open (when the n-short region 64 is not formed), the avalanche operation significantly reduces the avalanche voltage as compared with the case where the base-emitter is short-circuited. A large current may flow to the ESD protection element. In addition, the temperature dependence of the avalanche voltage is increased.
Therefore, the base-emitter is short-circuited to suppress the injection efficiency from the p emitter region 63 to the n base region (second n-well region 62), thereby preventing the avalanche voltage from being excessively lowered and the temperature dependence of the avalanche voltage. A base-emitter short type pnp transistor with reduced characteristics is used as the ESD protection element 70.
FIG. 7 is a cross-sectional view of a main part of a semiconductor device having another conventional ESD protection element. The difference from FIG. 5 is that the ESD protection element 70 is formed by forming the first n well region 53 and the second n well region 62 with the same impurity concentration and diffusion depth in order to reduce the manufacturing cost. When the first and second n-well regions 53 and 62 are formed at the same time, in order to increase the avalanche voltage of the MOSFET 21 and increase the current amplification factor hFE of the pnp transistor 68 to decrease the operating resistance, When the impurity concentrations of the second n-well regions 53 and 62 are lowered by the same value, both the avalanche voltages of the pnp transistor 68 and the MOSFET 21 are increased as shown in FIG. FIG. 8B shows the dependency of the operating resistance of the pnp transistor 68 on the impurity concentration of the second n-well region 62.

Here, when the current corresponding to the peak value of the ESD surge current (for example, 60 A) is IP, the voltage value VP at the current value (IP), and the avalanche voltage VAV, the operating resistance is [(VP − VAV) ÷ IP].
Japanese Patent Laid-Open No. 10-290008 FIG. JP 2001-127294 A FIG.

However, in FIG. 5, when the diffusion depth L5 of the second n-well region 62 is increased, the width of the second n-well region 62, which is the n-base region of the pnp transistor 68, increases, and the hole transport efficiency decreases, The current amplification factor hFE of the pnp transistor 68 is reduced, and the operating resistance is increased.
When the operating resistance increases and the ESD surge current flowing through the ESD protection element 70 by applying an ESD surge increases, the product of the operating resistance and the ESD surge current increases, and the voltage between the collector and the emitter in the large current region becomes the MOSFET 21. Therefore, the MOSFET 21 cannot be protected from the ESD breakdown.
On the other hand, if the diffusion depth L5 of the second n-well region 62 is decreased and the current amplification factor hFE of the pnp transistor 68 is increased in order to reduce this operating resistance, the diffusion depth L5 is reduced as shown in FIG. If it is too shallow, the avalanche voltage of the pnp transistor 68 becomes higher than the avalanche voltage of the MOSFET 21, and the ESD protection element 70 cannot protect the MOSFET 21 from the ESD surge.

In FIG. 7, if the impurity concentration of the first and second n well regions 53 and 62 is too low in order to reduce the operating resistance of the pnp transistor 68, as shown in FIG. The avalanche voltage of the transistor 68 becomes higher than the avalanche voltage of the MOSFET 21, and the MOSFET 21 cannot be protected by the ESD protection element 70.
An object of the present invention is to solve the above-described problems and provide a semiconductor device having an ESD protection element that can be made lower than the avalanche voltage of a MOSFET that is a protected element to reduce the operating resistance.

In order to achieve the above object, a lateral MISFET and a base-emitter short vertical bipolar transistor in which a lateral MISFET is connected in parallel to the lateral MISFET and shorted between a base region and an emitter region on the same semiconductor substrate, In a semiconductor device having
The bipolar transistor and the bipolar diode are arranged in parallel with the semiconductor substrate, the cathode region of the diode is connected to the base region of the bipolar transistor, and the avalanche voltage of the diode is the avalanche voltage of the bipolar transistor and The avalanche voltage is lower than that of the MISFET.
The diffusion depth of the cathode region of the diode may be deeper than the diffusion depth of the base region of the bipolar transistor.
The impurity concentration of the cathode region of the diode may be higher than the impurity concentration of the bipolar transistor.

  Also, a first conductive type second semiconductor layer having a lower concentration than the first semiconductor layer is formed on the first conductive type first semiconductor layer, and the second conductive layer is formed separately from the surface layer of the second semiconductor layer. A first well region and a second well region of two conductivity types; a third well region of a first conductivity type formed in a surface layer of the first well region; and a surface layer of the third well region. A source region and a drain region of the second conductivity type; a gate electrode formed on the third well region sandwiched between the source region and the drain region via a gate insulating film; and the source region and the drain region A source electrode and a drain electrode, a first conductivity type emitter region in the surface layer of the second well region, and a second conductivity type formed through the emitter region and reaching the second well region. In contact with the short region and the second well region A fourth well region of a second conductivity type formed in the surface layer of the second semiconductor layer with a diffusion depth deeper than that of the second well region; and an emitter electrode formed on the emitter region and the short region And a back electrode formed on the back surface of the first semiconductor layer.

The impurity concentration of the fourth well region may be higher than the impurity concentration of the second well region.
The second well region is a base region of a bipolar transistor, and the fourth well region is a cathode region of a diode.

According to the present invention, an ESD protection element is formed by arranging a base-emitter short type pnp transistor and a pn diode in parallel, and the pnp transistor is operated by the avalanche current of the pn diode, whereby the avalanche voltage is determined by the pn diode. The operating resistance can be determined by a pnp transistor. As a result, an ESD protection element that can reduce the operating resistance while being lower than the avalanche voltage of the MOSFET that is the protected element can be formed, and the protected element can be reliably protected from the ESD surge.
Further, the ESD breakdown resistance can be easily increased by increasing the area of the ESD protection element.

  In the best mode for carrying out the invention, the ESD protection element is composed of a base-emitter short pnp transistor and a pn diode, the avalanche voltage of the ESD protection element is determined by the pn diode, and the operating resistance of the ESD protection element is mainly used. This is to be able to determine with a base-emitter short type pnp transistor. With such a configuration, the avalanche voltage and the operating voltage of the ESD protection element can be determined almost independently. Hereinafter, detailed description will be given in Examples.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. This figure is a cross-sectional view of the ESD protection element 20 and the MOSFET 21. The difference from the conventional ESD protection element 70 is that the third n well region 15 is formed on the outer periphery of the second n well region 12 so as to be in contact with the second n well region 12. MOSFET 21 formed on p epitaxial layer 2 has the same structure as FIG. The thickness of the LOCOS oxide film 9 is about 1 μm.
A p epitaxial layer 2 (concentration is about 1 × 10 ¹⁵ cm ⁻³ ) having a lower concentration than that of the p substrate 1 is formed on the high concentration p substrate 1, and an impurity concentration of 1 is formed on the surface layer of the p epitaxial layer 2. A first n-well region 3 having a diffusion depth of about 2 to 5 μm is formed at about × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ . A p-well region 4 having an impurity concentration of about 5 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ and a diffusion depth of about 1 μm to 2 μm is formed on the surface layer of the first n-well region 3. An n source region 5 and an n drain region 6 are formed on the surface layer of the p well region 4, and a gate having a thickness of several tens of nm is formed on the p well region 4 sandwiched between the n source region 5 and the n drain region 6. A gate electrode 8 is formed of polysilicon through an oxide film 7. An n layer (not shown) for ohmic contact is formed on the surface layers of the n source region 5 and the n drain region 6. A LOCOS oxide film 9 for increasing the breakdown voltage is formed on the drain side.

On the other hand, in the surface layer of the p epitaxial layer 2, the impurity concentration is about 0.8 times lower than the first n well region 3, for example (or the same level), and the diffusion depth is separated from the first n well region 3. The second n-well region 12 is formed by making L2 about 0.8 times shallower than the diffusion depth L1 of the first n-well region 3 (which may be the same). A third n well region in which the outer periphery of the second n well region 12 is in contact with the second n well region 12 and has a higher impurity concentration than the second n well region 12 and a diffusion depth L3 deeper than the diffusion depth L2 of the second n well region 12 15 is formed, and a p emitter region 13 and an n short region 14 for short-circuiting the p emitter region 13 are formed on the surface layer of the second n well region 12.
The impurity concentration of the third well region 15 is, for example, 1.5 to 10 times higher than the impurity concentration of the second n-well region 12 (the higher the magnification, the lower the operation resistance), and the diffusion depth L3. Is deepened from the diffusion depth L2 of the second n-well region 12 to about 1 μm to a depth in contact with the p substrate 1 (the deeper the avalanche voltage is lowered).

Emitter electrode 16 is formed on p emitter region 13 and n short region 14, and back electrode 17 is formed on the back surface of p substrate 1. A base-emitter short pnp transistor 18 is formed by the p substrate 1, the p epitaxial layer 2, the second n well region 12, the p emitter region 13 and the n short region 14, and the p substrate 1, the p epitaxial layer 2 and the third n well are formed. A pn diode 19 is formed in the region 15, and an ESD protection element 20 is formed by both of them. The effect of the ESD protection element 20 will be described with reference to FIGS.
1, S is a source terminal connected to the n source electrode 10, D is a drain terminal connected to the n drain electrode 11, E is an emitter terminal connected to the p emitter electrode 16, and R is connected to the back electrode 17. The back terminal R is a collector terminal of the pnp transistor and an anode terminal of the pn diode. Further, D and E are connected, and although not shown, S and R are also connected.

1 may be formed of an insulating film such as a nitride film, in which case the MOSFET (Metal Oxide FET) is a MISFET (Metal Insulator FET).
FIG. 2 is an equivalent circuit diagram of the ESD protection element, and FIG. 3 is a diagram showing a current / voltage curve of the ESD protection element.
When an ESD surge voltage is applied between the emitter terminal E and the back terminal R, first, the pn diode 19 performs an avalanche operation so that the p substrate 1-p epitaxial layer 2, the third n well region 15 and the second n well region shown in FIG. The avalanche current (ID) of the pn diode 19 flows through the path of the 12-n short region 14. This avalanche current (ID) becomes the base current of the base-emitter short type pnp transistor 18, holes are injected from the p emitter region 13 into the second n well region 12, the pnp transistor 18 operates, and the pnp transistor A collector current (IC) flows, and an ESD surge current flows through both the pn diode 19 and the pnp transistor 18. Since the diffusion depth L2 of the second n-well region 12 is shallower than the diffusion depth L5 of the conventional second n-well region 62, the current amplification factor hFE of the pnp transistor 18 is increased.

Therefore, the operating resistance is smaller than that of the conventional pnp transistor 68, and the voltage between the emitter and the collector when the ESD surge current flows (the voltage shown on the horizontal axis in FIG. 3) is the breakage of the MOSFET 21 even in the large current avalanche region. The MOSFET can be protected from the ESD surge by being kept lower than the down voltage. Here, the operating resistance described in FIG. 8 will be described again in detail.
FIG. 3 is a diagram illustrating the operating resistance. A voltage corresponding to an ESD surge voltage (about 10 kV to 15 kV) is applied to the ESD protection element 20. Then, current begins to flow at the avalanche voltage VAV1 of the pn diode 19, and the current increases in the ESD protection element 20 along the curve indicated by the dotted line, and a current corresponding to the ESD surge current flows. The voltage VP at the peak current value IP (for example, 60 A) of the current is measured. Using these values, the value of [(VP−VAV1) ÷ IP] is obtained and used as the operating resistance.

If the impurity concentration and diffusion depth of the second n-well region 12 are the same as those of the first n-well region 3, the manufacturing cost can be reduced.
The formation location of the third n-well region 15 is not necessarily the outer periphery of the second n-well region 12 and may be formed in a part of the second n-well region 12.

  FIG. 4 is a cross-sectional view of the main part of the semiconductor device according to the second embodiment of the present invention. This is a case where three ESD protection elements 20 of FIG. 1 are connected in parallel to increase the area, and the ESD breakdown resistance can be easily increased by increasing the number of parallel connection.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. 1 is an equivalent circuit diagram of the ESD protection element of FIG. The figure which shows the electric current and voltage curve of the ESD protection element of FIG. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention Sectional drawing of the principal part of the semiconductor device which has the conventional ESD protection element The figure which shows the relationship between the diffusion depth of a 2nd n well area | region, and an avalanche voltage Sectional drawing of the principal part of the semiconductor device which has another conventional ESD protection element In the conventional ESD protection element, FIG. 6A is a diagram showing the relationship between the impurity concentration of the n-well region and the avalanche voltage, and FIG.

Explanation of symbols

1 p substrate 2 p epitaxial layer 3 first n well region 4 p well region 5 n source region 6 n drain region 7 gate oxide film 8 gate electrode 9 LOCOS oxide film 10 source electrode 11 drain electrode 12 second n well region 13 p emitter region 14 n short region 15 3rd n well region 16 emitter electrode 17 back electrode 18 pnp transistor 19 pn diode 20 ESD protection element 21 MOSFET
S source terminal D drain terminal E emitter terminal R back terminal

Claims (6)

In a semiconductor device having a lateral MISFET on the same semiconductor substrate, and a base-emitter short vertical bipolar transistor that is arranged in parallel with the lateral MISFET and has a shorted base region and emitter region.
The bipolar transistor and the bipolar diode are arranged in parallel with the semiconductor substrate, the cathode region of the diode is connected to the base region of the bipolar transistor, and the avalanche voltage of the diode is the avalanche voltage of the bipolar transistor and A semiconductor device characterized by being lower than both avalanche voltages of the MISFET. The semiconductor device according to claim 1, wherein a diffusion depth of a cathode region of the diode is deeper than a diffusion depth of a base region of the bipolar transistor. 3. The semiconductor device according to claim 1, wherein an impurity concentration of a cathode region of the diode is higher than an impurity concentration of the bipolar transistor. A first conductive type second semiconductor layer having a concentration lower than that of the first semiconductor layer is formed on the first conductive type first semiconductor layer, and a second conductive layer formed separately from the surface layer of the second semiconductor layer. First well region and second well region of the mold, a third well region of the first conductivity type formed in the surface layer of the first well region, and a second formed in the surface layer of the third well region Conductive source and drain regions, a gate electrode formed on the third well region sandwiched between the source and drain regions via a gate insulating film, and formed on the source and drain regions Source electrode and drain electrode, a first conductivity type emitter region in the surface layer of the second well region, and a second conductivity type short region formed through the emitter region and reaching the second well region And in contact with the second well region A second conductivity type fourth well region formed on the surface layer of the two semiconductor layers with a diffusion depth deeper than the second well region; an emitter electrode formed on the emitter region and the short region; A semiconductor device comprising a back electrode formed on the back surface of the first semiconductor layer. The semiconductor device according to claim 4, wherein an impurity concentration of the fourth well region is higher than an impurity concentration of the second well region. 6. The semiconductor device according to claim 4, wherein the second well region is a base region of a bipolar transistor, and the fourth well region is a cathode region of a diode.

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