JP2005210074A - Multilayer board and power amplifier module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer board that is small and hardly affected by surrounding devices, and a power amplifier module. <P>SOLUTION: A conductor pattern formed on the surface of an eighth dielectric layer includes an electrode region C1a and a lead electrode region for electrically connecting the electrode region C1a and a via 5. The lead electrode region which is a signal line led out from the via 5 for connecting semiconductor elements S1 and S2 and an outer connection terminal Vcc, electrically connects the electrode region C1a, semiconductor elements S1 and S2, and an outer connection terminal Vcc. In this way, a bypass capacitor having a high self-resonance frequency is formed in an inner layer of a dielectric board. As a result, a power amplifier module that is small and hardly affected by the impedance of the outer connection terminal Vcc, in other words, hardly affected by surrounding devices can be provided. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a multilayer substrate and a power amplifier module.

  In recent years, communication terminal devices, particularly mobile phones, have been rapidly reduced in size, and as a natural consequence, power amplifier modules, which are parts of mobile phones, are strongly required to be downsized. The power amplifier module is one component as a communication terminal device, and the power amplifier module and other devices are connected to the motherboard. For this reason, the impedance of the external connection terminal is deviated, which causes deterioration of characteristics including oscillation. Therefore, a power amplifier module that can satisfy the original characteristics without being affected by surrounding devices is required.

In order to solve the above problem, a multilayer substrate with a bypass capacitor (see, for example, Patent Documents 2 and 3) was applied to a conventional power amplifier module (for example, see Patent Document 1), and the characteristics were examined.
JP-A-2002-141757 (page 4-6, FIG. 3-11). JP-A-8-204341 (page 2-3, FIG. 1-3). Japanese Patent Laid-Open No. 2002-208776 (page 5-7, FIG. 1-2).

  FIG. 3 is a circuit diagram showing a specific configuration of a power amplifier module to which a multilayer substrate with a bypass capacitor is applied. As illustrated in FIG. 3, the power amplifier module 200 includes an input matching circuit unit 101, a semiconductor circuit unit 102, an interstage matching circuit unit 103, a bias circuit unit 104, and an output matching circuit unit 105. ing.

  The input matching circuit unit 101 matches the impedance (50 [Ω]) at the Pin terminal with the input impedance of the semiconductor circuit unit 102, and the signal input from the Pin terminal is input to the semiconductor circuit unit 102 without loss due to impedance mismatching. Transmit to.

  The semiconductor circuit unit 102 includes two-stage semiconductor elements S1 and S2, and amplifies and outputs a signal input from the input matching circuit unit 101.

  The interstage matching circuit unit 103 matches the output impedance of the semiconductor element S1 with the input impedance of the semiconductor element S2, and transmits the signal output from the semiconductor element S1 to the input of the semiconductor element S2 without loss due to impedance mismatching.

  The bias circuit unit 104 includes three inductance elements L1 to L3 and a grounded capacitance element C1, and operates the semiconductor elements S1 and S2 of the semiconductor circuit 102 as amplification elements. The inductance elements L <b> 1 to L <b> 3 are required to have an ideal infinite impedance so that signals amplified at each stage of the semiconductor circuit unit 102 are not leaked to power supply terminals such as Vcc and Vreg. The grounded capacitance element C1 attenuates the high-frequency signal, and at the same time, the grounded capacitance element C1 can be isolated between the output part A of the semiconductor element S1 and the output part B of the semiconductor element S2.

  The output matching circuit unit 105 shown in FIG. 3 matches the output impedance of the semiconductor element S2 with the impedance (50 [Ω]) seen at the Pout terminal, and the signal output from the semiconductor element S2 is lost without impedance mismatching. Transmit to the Pout terminal.

  FIG. 23 is a front view of the power amplifier module shown in FIG. The power amplifier module 200 includes a dielectric substrate 1, an MMIC (Microwave Monolithic IC) 2, and a chip capacitor 6. Further, a thermal via 3, a long hole through hole 4 and a via hole 5 are formed in the surface of the dielectric substrate 1, and the power amplifier module 100 includes a via 7 inside the via hole 5.

  When viewed from above, the dielectric substrate 1 includes a first dielectric layer 21, a second dielectric layer 22, a third dielectric layer 23, a fourth dielectric layer 24, and a fifth dielectric layer. The dielectric layer 25, the sixth dielectric layer 26, and the seventh dielectric layer 27 are stacked. Specifically, the dielectric substrate 1 uses the fourth dielectric layer 24 as a core substrate, and the third dielectric layer 23, the second dielectric layer 22, and the first dielectric layer 21 thereon. The fifth dielectric layer 25, the sixth dielectric layer 26, and the seventh dielectric layer 27 are sequentially laminated, and the fifth dielectric layer 25, the sixth dielectric layer 26, and the seventh dielectric layer 27 are sequentially laminated. The first to seventh dielectric layers 21 to 27 are made of an epoxy resin or the like.

  The fourth dielectric layer 24 that is the core substrate is made of a dielectric having a relative dielectric constant of εr = 9.5 and a thickness of 155 [μm], and the first to third dielectric layers 21. ˜23 and the fifth to seventh dielectric layers 25 to 27 are made of a dielectric having a relative dielectric constant of εr = 10.5 and a thickness of 40 [μm].

  In the first to seventh dielectric layers 21 to 27, chip components excluding the first and second semiconductor elements S1 and S2 included in the MMIC 2 among the circuit components included in the circuit diagram shown in FIG. These chip components are connected so as to have a desired circuit configuration. Although there is no limitation in particular about arrangement | positioning of a circuit component, an example which can be employ | adopted is demonstrated with reference to FIGS. 5-11 and FIG. In addition, only a portion related to the present invention is shown in FIG. 5 to FIG. 11 and FIG.

  FIG. 5 is a plan view of the first dielectric layer 21 as viewed from the surface side, FIG. 6 is a plan view of the second dielectric layer 22 as viewed from the surface side, and FIG. 7 is a diagram of the third dielectric layer 23 as the surface. FIG. 8 is a plan view of the fourth dielectric layer 24 viewed from the surface side, FIG. 9 is a plan view of the fifth dielectric layer 25 viewed from the surface side, and FIG. FIG. 11 is a plan view of the seventh dielectric layer 27 viewed from the front surface side, and FIG. 13 is a plan view of the seventh dielectric layer 27 viewed from the rear surface side. FIG.

  Conductor patterns are formed on the surfaces of the third to seventh dielectric layers 23 to 27 shown in FIGS. The conductor patterns formed on the surfaces of the third to sixth dielectric layers 23 to 26 shown in FIGS. 7 to 10 constitute a part of the inductance elements L1 and L2, and the seventh pattern shown in FIG. The conductor pattern formed on the surface of the dielectric layer 27 constitutes a part of the inductance element L2. The inductance elements L1 and L2 are acquired by these conductor patterns.

  The dielectric substrate 1 shown in FIG. 23 is provided with a signal input terminal Pin, a signal output terminal Pout, a ground terminal GND, an external connection terminal Vcc, and the like in the form of side electrodes or back electrodes.

  The MMIC 2 mounts the circuit components of the semiconductor circuit unit 102 composed of the first and second semiconductor elements S1 and S2 among the circuit components included in the circuit diagram shown in FIG. It is connected to a conductor pattern formed on the dielectric substrate 1 by wire bonding, flip chip mounting or the like. The MMIC 2 is mounted in a sealed state with a sealing resin in order to ensure its reliability.

  In the mounting area of the MMIC 2, a plurality of thermal vias 3 are provided at appropriate intervals so as to continuously pass through the first to seventh dielectric layers 21 to 27. The thermal via 3 is filled with a filler made of a conductive paste such as an Ag paste.

  The long hole through hole 4 is provided in the vicinity of the side surface of the dielectric substrate 1 so as to continuously pass through the layers of the first to seventh dielectric layers 21 to 27.

  The via hole 5 is provided so as to continuously penetrate between the first to seventh dielectric layers 21 to 27.

  The chip capacitor 6 is mounted on the surface of the dielectric substrate 1 and constitutes a grounded capacitance element C1 among the circuit components included in the circuit diagram shown in FIG. The chip capacitor 6 functions as a bypass capacitor that alleviates fluctuations in the power supply voltage and suppresses power supply noise.

  Via 7 electrically connects chip capacitor 6 mounted on the surface of first dielectric layer 21 and external power supply terminal Vcc applied to the back surface of seventh dielectric layer 27 through via hole 5. Connected.

  FIG. 24 is a part of the bias circuit unit 104. FIG. 25 shows an isolation characteristic between Ports 1-2 and an ideal capacitance of 100 [pF] when a chip capacitor 6 having a 0603 size and an electric capacity of 100 [pF] is used as the grounded capacitance element C1 shown in FIG. It is a graph which shows the isolation characteristic at the time of using a capacitor | condenser.

  As shown in FIG. 25, the isolation characteristic when the chip capacitor 6 is used is far from the isolation characteristic when the ideal capacitor is used, that is, the original characteristic of the capacitor. This is because the self-resonant frequency of the chip capacitor 6 is low.

  Further, because of the minute inductance L6 that the chip capacitor 6 has, the routing of the ground electrode GND, the inductance L4 that the long hole through hole 4 has, and the like, between the Ports 1-2 of the actual bias circuit unit 104, as shown in FIG. A series resonant circuit is formed. For this reason, the impedance of the ground electrode on the surface of the dielectric substrate 1 becomes high.

  Due to the circumstances as described above, the grounded capacitance element C1 cannot exhibit the original characteristics of the capacitor, and it is difficult to form a bypass capacitor having a wide band in the power amplifier module 200.

  SUMMARY An advantage of some aspects of the invention is that it provides a multi-layer board, a power amplifier module, and a communication terminal device that are small in size and hardly affected by surrounding devices.

  In order to achieve the above object, a multilayer substrate according to a first aspect of the present invention is a multilayer substrate formed by laminating a plurality of dielectric layers having electrodes on the surface, and is formed on one main surface of the multilayer substrate. A via that electrically connects the mounted semiconductor element and a power supply terminal provided on the other main surface through a via hole, and the first and second electrodes sandwiching the dielectric layer, The first electrode is electrically connected to the semiconductor element and the power supply terminal by a signal line drawn from the via, and the second electrode is grounded, thereby forming a bypass capacitor in the inner layer of the multilayer substrate. It is characterized by that.

In the multilayer substrate, it is preferable that the bypass capacitor is formed using a lower dielectric layer near the ground among the plurality of dielectric layers. In some cases, the capacitor electrode on the signal side drawn out from the via can be sandwiched from the upper and lower layers with a grounded ground electrode, and the capacitance value can be increased by forming a capacitor. It also leads to an isolation effect between the electrode and another pattern. As another example, as shown in FIG. 27, by forming a bypass capacitor symmetrically inside the multilayer substrate, it is possible to provide a high-quality substrate free from warpage or the like.
1. The capacitor may be formed with any number of layers.
2. By sandwiching the capacitor electrode on the signal side between the upper and lower ground electrodes, the bypass capacitor and various circuit patterns formed on other layers in the multilayer substrate can be electromagnetically shielded, so that an isolation effect from other electrodes can also be expected. I can do it.
3. By forming bypass capacitors symmetrically inside the substrate, a high-quality substrate can be provided.

  In the multilayer substrate, it is desirable that the dielectric layer constituting the bypass capacitor has a relative dielectric constant higher than that of other layers and is 40 or more.

  Further, in the multilayer substrate, it is desirable that the dielectric layer constituting the bypass capacitor is thinner than other layers used and is 10 [μm] or less.

  A power amplifier module according to a second aspect of the present invention is a power amplifier module used in a transmission unit of a communication terminal device, and includes an amplifier configured to amplify an input signal and output the amplified signal. A circuit unit, and a bias circuit unit including the bypass capacitor and operating the semiconductor element as an amplifying element, and at least some of the circuit elements constituting the bias circuit unit include: It is formed in the inner layer of the multilayer board | substrate of any one of claim | item 1 thru | or 4.

  According to the present invention, it is possible to provide a multilayer substrate and a power amplifier module which are small in size and hardly affected by surrounding devices.

  Hereinafter, a communication terminal apparatus according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a communication terminal apparatus according to an embodiment of the present invention. The communication terminal device is a mobile phone, for example, and includes an RF (Radio Frequency) unit 10 and a baseband unit 20 as shown in FIG. 1, and the RF unit 10 includes an antenna 11, a switch 12, and the like. The transmission unit 13, the distributor 14, the reception unit 15, and an IF (Intermediate Frequency) unit 16.

  The transmission unit 13 includes a mixer 131 and a power amplification unit 132. The mixer 131 mixes a signal supplied from a modulator (not shown) and a signal supplied from the distributor 14, and supplies a signal obtained by mixing to the power amplification unit 132. The power amplifier 132 amplifies the signal supplied from the mixer 131 and transmits the amplified signal to the antenna 11 via the switch 12.

  In the present embodiment, the frequency band used in the power amplifying unit 132 is 880 to 915 [MHz] or 1710 to 1785 [MHz], and the output required for the power amplifying unit 132 is 35 [dBm] ] Or 32 [dBm].

  The receiving unit 15 includes an amplifier 151 and a mixer 152. The amplifier 151 amplifies a signal input from the antenna 11 via the switch 12, and extracts a signal having a predetermined frequency component from which the noise component is removed from the amplified signal. The mixer 152 mixes the reception signal output from the amplifier 151 and the signal supplied from the distributor 14, and supplies the signal obtained by mixing to the IF unit 16.

  FIG. 2 is a block diagram showing an internal configuration of the power amplification unit 132. As shown in FIG. 2, the power amplification unit 132 includes a power amplifier module 100, a band pass filter 110, a power detection unit 120, a low pass filter 130, and a power control unit 140. The power control unit 140 controls the power of the transmission signal output from the power amplifier 100 based on the power detection signal supplied from the power detection unit 120.

  In the present embodiment, a circuit configuration having a one-system power amplification unit is shown, but a power amplification unit corresponding to a GSM / DCS dual band is also known. The invention is applicable.

  FIG. 3 is a circuit diagram showing a specific configuration of power amplifier module 100 shown in FIG. As shown in FIG. 3, the power amplifier module 100 includes an input matching circuit unit 101, a semiconductor circuit unit 102, an interstage matching circuit unit 103, a bias circuit unit 104, and an output matching circuit unit 105. ing.

  The input matching circuit unit 101 has a function of matching the impedance (50 [Ω]) at the Pin terminal with the input impedance of the semiconductor circuit unit 102, and the semiconductor circuit without loss due to impedance mismatching of the signal input from the Pin terminal To the input of the unit 102.

  The semiconductor circuit unit 102 includes two-stage semiconductor elements S1 and S2, and amplifies and outputs a signal input from the input matching circuit unit 101.

  The Vref terminal is a terminal provided for output control, and the output of the power amplifier module 100 is controlled by the voltage level applied to the Vref terminal. The voltage applied to the Vref terminal is obtained by feeding back the signal obtained by the power detection unit 120 shown in FIG. 2 to the power control unit 140. By the Vref signal that is an output from the power control unit 140, It operates so that the output of the power amplifier module 100 is always constant.

  The interstage matching circuit unit 103 matches the output impedance of the semiconductor element S1 with the input impedance of the semiconductor element S2, and transmits the signal output from the semiconductor element S1 to the input of the semiconductor element S2 without loss due to impedance mismatching.

  The bias circuit unit 104 includes three inductance elements L1 to L3 and a grounded capacitance element C1, and operates the semiconductor elements S1 and S2 of the semiconductor circuit 102 as amplification elements. The inductance elements L <b> 1 to L <b> 3 are required to have an ideal infinite impedance so that signals amplified at each stage of the semiconductor circuit unit 102 are not leaked to power supply terminals such as Vcc and Vreg. For this reason, normally, the inductance elements L1 to L3 constituting the bias circuit 104 have an impedance corresponding to a (λ / 4) long pattern or a (λ / 4) long pattern. The grounded capacitance element C1 attenuates the high-frequency signal, and at the same time, the grounded capacitance element C1 can be isolated between the output part A of the semiconductor element S1 and the output part B of the semiconductor element S2.

  The output matching circuit unit 105 matches the output impedance of the semiconductor element S2 with the impedance (50 [Ω]) seen at the Pout terminal, and transmits the signal output from the semiconductor element S2 to the Pout terminal without loss due to impedance mismatching. To do.

  4 is a front view of the power amplifier module 100 shown in FIG. The power amplifier module 100 includes a dielectric substrate 1 and an MMIC (Microwave Monolithic IC) 2. A thermal via 3, a long hole through hole 4, and a via hole 5 are formed in the surface of the dielectric substrate 1, and the power amplifier module 100 includes a via 7 inside the via hole 5.

  When viewed from above, the dielectric substrate 1 includes a first dielectric layer 21, a second dielectric layer 22, a third dielectric layer 23, a fourth dielectric layer 24, and a fifth dielectric layer. The dielectric layer 25, the sixth dielectric layer 26, the seventh dielectric layer 27, and the eighth dielectric layer 28 are stacked. Specifically, the dielectric substrate 1 uses the fourth dielectric layer 24 as a core substrate, and the third dielectric layer 23, the second dielectric layer 22, and the first dielectric layer 21 thereon. The fifth dielectric layer 25, the sixth dielectric layer 26, the seventh dielectric layer 27, and the eighth dielectric layer 28 are sequentially laminated below the fifth dielectric layer 25, the sixth dielectric layer 26, the seventh dielectric layer 27, and the eighth dielectric layer 28. In addition, the dielectric substrate 1 comprises the first to eighth dielectric layers 21 to 28 by sequentially laminating the first to eighth dielectric layers 21 to 28 which are independent from each other, and pressurizing and heating. A dielectric layer and a necessary conductor pattern may be formed.

The dielectric substrate 1 includes at least one of the first to eighth dielectric layers 21 to 28, in particular, the sixth dielectric layer 26, the seventh dielectric layer 27, and the eighth dielectric layer 28. And a hybrid layer containing a polyvinyl benzyl ether compound and a ceramic dielectric powder such as barium titanate. In the present embodiment, the first to eighth dielectric layers 21 to 28 are all composed of a hybrid layer containing a polyvinyl benzyl ether compound and a ceramic dielectric powder such as barium titanate. An inorganic filler can be added as appropriate. For example, in order to increase the capacity of the capacitor, BaO—TiO ₂ —Nd ₂ O ₃ system, BaO—TiO ₂ —SnO ₂ system, BaO—TiO ₂ —Sm ₂ O ₃ system, PbO—BaO—Nd ₂ O ₃ —TiO ₂ system BaTiO ₃ system, PbTiO ₃ system, SrTiO ₃ system, CaTiO ₃ system, (Ba, Sr) TiO ₃ system, Ba (Ti, Zr) O ₃ system, BaTiO ₃ -SiO ₂ system, SrZrO ₃ system, BiTiO ₄ system , (Bi ₂ O ₃ , PbO) —BaO—TiO ₂ system, La ₂ Ti ₂ O ₇ system, Nd ₂ TiO ₇ system, (Li, Sm) TiO ₃ system, MgTiO ₃ system, Mg ₂ O ₄ system, Al ₂ O ₃ system, TiO ₂ system, BaO-SiO ₂ system, PbO-CaO based, BaWO ₄ system, CaWO _{4 based, Ba (Mg, Nb) O} 3 _{based, Ba (Mg, Ta) O} 3 based, BA Co, Mg, Nb) _{O 3} based, Ba (Co, Mg, Ta ) O 3 _{based, Sr (Mg, Nb) O} 3 _{based, Ba (Zn, Ta) O} 3 _{based, Ba (Zn, Nb) O} 3 System, Sr (Zn, Nb) O ₃ system, Ba (Mg, W) O ₄ system, Ba (Ga, Ta) O ₃ system, ZnTiO ₃ system, ZrTiO ₄ system, (Zr, Sn) TiO ₄ system, etc. Add dielectric material. These may be added alone or in admixture of two or more, and can be appropriately selected depending on the properties desired to be obtained from these materials. Although composed of a polyvinyl benzyl ether compound, other than this, for example, epoxy resins, phenol resins, unsaturated polyester resins, vinyl ester resins, polyimide resins, cyanate resins and polybutadiene resins can be used. The first to eighth dielectric layers 21 to 28 are preferably composed of a hybrid layer containing a resin and a ceramic dielectric powder, but are composed of an organic material such as an epoxy resin alone. May be.

  In the present embodiment, the fourth dielectric layer 24 that is a core substrate is made of a dielectric having a relative dielectric constant of εr = 9.5 and a thickness of 155 [μm]. The third dielectric layers 21 to 23 and the fifth to seventh dielectric layers 25 to 27 are made of a dielectric having a relative dielectric constant of εr = 10.5 and a thickness of 40 [μm]. The eighth dielectric layer 28 has a relative dielectric constant higher than that of the other dielectric layers 21 to 27 and a thickness smaller than that of the other dielectric layers 21 to 27, specifically, a relative dielectric. It is composed of a dielectric having a rate of εr = 40 and a thickness of 10 μm.

  The first to seventh dielectric layers 21 to 27 may be made of a dielectric having a thickness of about 10 [μm], similar to the eighth dielectric layer 28. However, if a thin dielectric is used, Therefore, the difficulty in the lamination process increases. Therefore, as in the present embodiment, it is preferable to use a thin dielectric only for the necessary layers, that is, the eighth dielectric layer 28. In addition, a dielectric having a relative dielectric constant of about εr = 40 may be used for the first to seventh dielectric layers 21 to 27 as in the case of the eighth dielectric layer 28. Is limited, and the degree of design freedom is reduced. For this reason, as in the present embodiment, it is preferable to use a dielectric having a high relative dielectric constant only for a necessary layer, that is, the eighth dielectric layer 28.

  The surface of the seventh dielectric layer 27 and the back surface of the eighth dielectric layer 28 are connected to the ground terminal GND.

  In the first to eighth dielectric layers 21 to 28, chip components excluding the first and second semiconductor elements S1 and S2 included in the MMIC 2 among the circuit components included in the circuit diagram shown in FIG. These chip components are connected so as to have a desired circuit configuration. Although there is no limitation in particular about arrangement | positioning of a circuit component, an example which can be employ | adopted is demonstrated with reference to FIGS. In addition, only a portion related to the present invention is shown in FIG. 5 to FIG. 11 and FIG.

  FIG. 5 is a plan view of the first dielectric layer 21 as viewed from the surface side, FIG. 6 is a plan view of the second dielectric layer 22 as viewed from the surface side, and FIG. 7 is a diagram of the third dielectric layer 23 as the surface. FIG. 8 is a plan view of the fourth dielectric layer 24 viewed from the surface side, FIG. 9 is a plan view of the fifth dielectric layer 25 viewed from the surface side, and FIG. FIG. 11 is a plan view of the seventh dielectric layer 27 viewed from the front side, and FIG. 12 is a plan view of the eighth dielectric layer 28 viewed from the front side. FIG. 13 and FIG. 13 are plan views of the eighth dielectric layer 28 as seen from the back side.

  Conductor patterns are respectively formed on the front surfaces of the third to eighth dielectric layers 22 to 28 shown in FIGS. 7 to 12 and the back surface of the eighth dielectric layer 28 shown in FIG. 13.

  The conductor patterns formed on the surfaces of the third to sixth dielectric layers 22 to 26 shown in FIGS. 7 to 10 constitute part of the inductance elements L1 and L2, and the seventh pattern shown in FIG. The conductor pattern formed on the surface of the dielectric layer 27 constitutes a part of the inductance element L2. The inductance elements L1 and L2 are acquired by these conductor patterns.

  Further, the conductor pattern formed on the surface of the eighth dielectric layer 28 shown in FIG. 12 constitutes the electrode region C1a of the ground capacitance element C1. Opposing the electrode region C1a and the surface region of the seventh dielectric layer 27 connected to the ground terminal GND, and opposing the electrode region C1a and the back surface region of the eighth dielectric layer 28 connected to the ground terminal GND. Thus, the grounded capacitance element C1 that functions as a bypass capacitor is obtained.

  Thus, by forming the grounded capacitance element C1 functioning as a bypass capacitor in the inner layer of the dielectric substrate 1, the power amplifier module 100 is a power amplifier in which the chip capacitor 6 is mounted on the surface of the dielectric substrate 1 as a bypass capacitor. Compared to the module 200, the size can be reduced.

  In addition, since the eighth dielectric layer 28 is made of a dielectric material having a high relative dielectric constant and a small thickness, the power amplifier module includes the electrode region C1a and the surface region of the seventh dielectric layer 27. And the capacitance of the grounded capacitance element C1 obtained by facing the electrode region C1a and the back surface region of the eighth dielectric layer 28 can be increased. In this embodiment, the capacitor is formed by using two dielectric layers, but the capacitor may be formed by two or more layers. Further, if a capacitance value more than necessary can be taken, the capacitance may be formed by one layer. Moreover, it is preferable to use a hybrid material containing ceramic particles having a high relative dielectric constant for the layer forming the bypass capacitor.

  The dielectric substrate 1 shown in FIG. 4 is provided with a signal input terminal Pin, a signal output terminal Pout, a ground terminal GND, an external connection terminal Vcc, and the like in the form of side electrodes or back electrodes. In the present embodiment, the external connection terminal Vcc is attached to the back electrode.

  The MMIC 2 mounts the circuit components of the semiconductor circuit unit 102 composed of the first and second semiconductor elements S1 and S2 among the circuit components included in the circuit diagram shown in FIG. It is connected to a conductor pattern formed on the dielectric substrate 1 by wire bonding, flip chip mounting or the like. The MMIC 2 is mounted in a sealed state with a sealing resin in order to ensure its reliability.

  In the mounting area of the MMIC 2, a plurality of thermal vias 3 are provided at appropriate intervals so as to continuously pass through the first to seventh dielectric layers 21 to 27. The thermal via 3 is filled with a filler made of a conductive paste such as an Ag paste. The filler filled in the thermal via 3 may be a non-conductive material as long as it has excellent thermal conductivity.

  The long hole through hole 4 is provided in the vicinity of the side surface of the dielectric substrate 1 so as to continuously pass through the layers of the first to eighth dielectric layers 21 to 28. The thermal via 3 and the through hole 4 can improve the heat dissipation of the power amplifier module 100.

  The via hole 5 is provided so as to continuously penetrate between the first to eighth dielectric layers 21 to 28.

  The via 7 connects the semiconductor elements S1 and S2 mounted on the surface of the first dielectric layer 21 and the external connection terminal Vcc applied to the back surface of the eighth dielectric layer 28 via the via hole 5. Are electrically connected.

  FIG. 14 is a diagram illustrating a connection configuration of the grounded capacitance element C1, the semiconductor elements S1 and S2, and the external connection terminal Vcc. As shown in FIG. 14, the conductor pattern formed on the surface of the eighth dielectric layer 28 includes an electrode region C1a and an extraction electrode region that electrically connects the electrode region C1a and the via 5. Yes. The ground capacitance element C1 is electrically connected to the semiconductor elements S1 and S2 and the external connection terminal Vcc through a signal line composed of the lead electrode region and the via 5. The width W of the extraction electrode region is formed larger than the minimum diameter of the via 7.

  Thus, the signal region (leading electrode region) drawn from the signal line (via 5) connecting the semiconductor elements S1 and S2 and the external connection terminal Vcc is used to make the electrode region C1a the semiconductor elements S1 and S2 and the external connection terminal Vcc. Therefore, the power amplifier module 100 reduces the routing of the ground electrode including the long hole through hole 4 and the routing of the electrode such as a through hole having an inductance component in series with the ground capacitance element C1. be able to. As a result, the power amplifier module 100 can increase the self-resonance frequency of the capacitance element C1 that functions as a bypass capacitor.

  In the present embodiment, the capacitance element C1 functioning as a bypass capacitor is formed near the eighth dielectric layer, which is the lowermost layer of the dielectric substrate 1, in other words, near the ground plane. This is to prevent a decrease in the self-resonance frequency of the grounded capacitance element C1 when the impedance of the capacitor increases.

  Next, the bias circuit unit 104 of the power amplifier module 100 (FIG. 4) having the bypass capacitor formed in the inner layer as described above and the power amplifier module 200 (FIG. 23) having the chip capacitor 6 mounted on the surface as the bypass capacitor. The isolation characteristics between the output part A and the output part B were compared. In this comparison, the electric capacity of the bypass capacitor formed in the inner layer of the power amplifier module 100 and the chip capacitor 6 mounted as a bypass capacitor on the surface of the power amplifier module 200 are both about 120 [pF]. .

  FIG. 15 is a graph showing isolation characteristics between the output unit A and the output unit B in the bias circuit unit 104 of the power amplifier module 100 and the power amplifier module 200. The power amplifier module 100 can obtain isolation in a wider band than the power amplifier module 200 as shown in FIG. 15 by increasing the self-resonant frequency of the capacitance element C1 functioning as a bypass capacitor.

  Subsequently, as shown in FIG. 16, an output portion when the impedance of the external connection terminal Vcc is changed by connecting the 0603 size chip capacitor Cs to the bias circuit 104 and changing the electric capacity of the chip capacitor Cs. Find the isolation characteristics between A and output B. FIG. 17 is a graph showing the isolation characteristics in the power amplifier module 200 in this case, and FIG. 18 is a graph showing the isolation characteristics in the power amplifier module 100.

  In the 900 [MHz] band, which is the fundamental wave of the power amplifier modules 100 and 200, the power amplifier module 200 in which the chip capacitor 6 is mounted as a bypass capacitor is isolated by being affected by external impedance as shown in FIG. Has changed significantly. On the other hand, in the power amplifier module 100 in which the bypass capacitor is provided as an inner layer, as shown in FIG.

  In this way, by forming a bypass capacitor having a high self-resonance frequency in the inner layer, the power amplifier module 100 can obtain isolation in a wide band. In other words, the influence of the impedance of the external connection terminal Vcc, in other words, the surroundings Less affected by the device.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above embodiment, the conductor pattern formed on the surface of the eighth dielectric layer 28 includes the electrode region C1a and the extraction electrode region that electrically connects the electrode region C1a and the via 5. The ground capacitance element C1 is electrically connected to the semiconductor elements S1 and S2 and the external connection terminal Vcc through a signal line constituted by the lead electrode region and the via 5. However, the present invention is not limited to this, and any method may be used as long as the capacitance element C1 formed at the position pulled out from the via 5 is connected to the semiconductor elements S1 and S2 and the external connection terminal Vcc.

  For example, as shown in FIGS. 19 and 20, even if the capacitance element C1 is connected to the semiconductor elements S1 and S2 and the external connection terminal Vcc by forming an extraction electrode area as a part of the electrode area C1a in the conductor pattern. Good.

  Further, as shown in FIG. 21, the capacitance element C1 is connected to the semiconductor elements S1, S2 and the external connection terminal Vcc by including the electrode region C1a in the signal line connecting the semiconductor elements S1 and S2 and the external connection terminal Vcc. May be.

  Furthermore, in the said embodiment, although the external connection terminal Vcc was provided to the back surface electrode, this invention is not limited to this, You may provide to a side electrode. As shown in FIG. 22, the signal lines in this case connect the semiconductor elements S1 and S2 mounted on the surface of the first dielectric layer 21 and the electrode region C1a on the surface of the eighth dielectric layer 28. By forming the vias 5, the electrode regions C 1 a, and the vias 5 connecting the external connection terminals Vcc applied in the form of side electrodes and the electrode regions C 1 a, the vias 5 on the surface layer side with respect to the stacking direction The inductance component of the ground using can be reduced. Furthermore, the via 5 on the side connected to the external connection terminal can be used as a side terminal in the shape of a half-through hole. For this reason, also by this modification aspect, there can exist an effect similar to the said embodiment.

It is a block diagram which shows the structure of the communication terminal device in this Embodiment. It is a block diagram which shows the structure of the power amplification part shown in FIG. FIG. 3 is a circuit diagram showing a configuration of a power amplifier module shown in FIG. 2. FIG. 3 is a front view of the power amplifier module shown in FIG. 2. It is the top view which looked at the 1st dielectric material layer shown in FIG. 4 from the surface side. It is the top view which looked at the 2nd dielectric material layer shown in FIG. 4 from the surface side. It is the top view which looked at the 3rd dielectric material layer shown in FIG. 4 from the surface side. It is the top view which looked at the 4th dielectric material layer shown in Drawing 4 from the surface side. It is the top view which looked at the 5th dielectric material layer shown in FIG. 4 from the surface side. It is the top view which looked at the 6th dielectric material layer shown in Drawing 4 from the surface side. It is the top view which looked at the 7th dielectric material layer shown in Drawing 4 from the surface side. It is the top view which looked at the 8th dielectric material layer shown in FIG. 4 from the surface side. It is the top view which looked at the 8th dielectric material layer shown in FIG. 4 from the back surface side. It is a figure which shows the connection structure of a ground capacitance element, a semiconductor element, and an external connection terminal. It is a graph which shows the isolation characteristic between the output parts of a bias circuit part. It is a circuit diagram which shows the structure of a bias circuit part provided with a chip capacitor. It is a graph which shows the isolation characteristic between the output parts of a bias circuit part provided with a chip capacitor. It is a graph which shows the isolation characteristic between the output parts of a bias circuit part provided with a chip capacitor. It is a figure which shows the deformation | transformation aspect of the connection structure shown in FIG. It is a figure which shows the deformation | transformation aspect of the connection structure shown in FIG. It is a figure which shows the deformation | transformation aspect of the connection structure shown in FIG. It is a figure which shows the deformation | transformation aspect of the connection structure shown in FIG. It is a front view of the power amplifier module which mounts a chip capacitor. It is a circuit diagram which shows a part of structure of a bias circuit part. It is a graph which shows the isolation characteristic of an ideal capacitor and a chip capacitor. It is an equivalent circuit diagram which shows the actual circuit structure of a bias circuit part. It is a figure which shows the deformation | transformation aspect of the power amplifier module shown in FIG.

Explanation of symbols

1 Dielectric substrate 2 MMIC
DESCRIPTION OF SYMBOLS 3 Thermal via 4 Long hole through hole 5 Via hole 6 Chip capacitor 7 Via 21 1st dielectric layer 22 2nd dielectric layer 23 3rd dielectric layer 24 4th dielectric layer 25 5th dielectric layer 26 sixth dielectric layer 27 seventh dielectric layer 28 eighth dielectric layer 100 power amplifier module 101 input matching circuit unit 102 semiconductor circuit unit 103 interstage matching circuit unit 104 bias circuit unit 105 output matching circuit unit C1 Ground capacitance element C1a electrode region S1 Semiconductor element S2 Semiconductor element Vcc external connection terminal

Claims (8)

A multilayer substrate formed by laminating a plurality of dielectric layers having electrodes on the surface,
A via that electrically connects a semiconductor element mounted on one main surface of the multilayer substrate and a power supply terminal provided on the other main surface through a via hole;
Of the first and second electrodes sandwiching the dielectric layer, the first electrode is electrically connected to the semiconductor element and the power supply terminal by a signal line drawn from the via, and a second By grounding the electrode, a bypass capacitor was formed in the inner layer of the multilayer substrate.
A multilayer substrate characterized by that. The first electrode forming the bypass capacitor is formed inside the multilayer substrate, and is connected to the semiconductor element through the via hole,
The second electrode forming the bypass capacitor is a ground electrode formed on the multilayer substrate and having a larger area than the first electrode.
The multilayer substrate according to claim 1. The first electrode forming the bypass capacitor is formed inside the multilayer substrate, and is connected to the semiconductor element through the via hole,
The second electrode forming the bypass capacitor is a ground electrode formed on the multilayer substrate and having a larger area than the first electrode,
The third electrode forming the bypass capacitor is a ground electrode formed in a layer opposite to the second electrode so as to sandwich the first electrode.
The multilayer substrate according to claim 1 or 2, characterized in that The ground electrode formed on the IC mounting side with respect to the first electrode forming the bypass capacitor is a part of the capacitance electrode of the bypass capacitor, and is electrically insulated from the ground electrode, and The first electrode and the semiconductor element were electrically connected through the via hole formed so as to pass through directly.
The multilayer substrate according to claim 1, 2 or 3. The bypass capacitor is formed using a lower dielectric layer near the ground among the plurality of dielectric layers.
The multilayer board according to claim 1, wherein the multilayer board is provided. The dielectric layer constituting the bypass capacitor is higher in dielectric constant than other dielectric layers,
The multilayer substrate according to any one of claims 1 to 5, wherein: The dielectric layer constituting the bypass capacitor is thinner than other dielectric layers,
The multilayer substrate according to claim 1, wherein the multilayer substrate is a multilayer substrate. A power amplifier module used in a transmission unit of a communication terminal device,
An amplification circuit unit configured by the semiconductor element and amplifying and outputting an input signal;
A bias circuit section including the bypass capacitor and operating the semiconductor element as an amplifying element;
With
At least a part of the plurality of circuit elements constituting the bias circuit unit is formed in an inner layer of the multilayer substrate according to any one of claims 1 to 7.
A power amplifier module characterized by that.

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