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JP2005203664A - Mounting method for semiconductor device - Google Patents

Mounting method for semiconductor device Download PDF

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Publication number
JP2005203664A
JP2005203664A JP2004010208A JP2004010208A JP2005203664A JP 2005203664 A JP2005203664 A JP 2005203664A JP 2004010208 A JP2004010208 A JP 2004010208A JP 2004010208 A JP2004010208 A JP 2004010208A JP 2005203664 A JP2005203664 A JP 2005203664A
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Japan
Prior art keywords
circuit board
semiconductor device
mounting
jig
positioning
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JP2004010208A
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Japanese (ja)
Inventor
Takeshi Toyoda
剛士 豊田
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Citizen Watch Co Ltd
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Citizen Watch Co Ltd
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Priority to JP2004010208A priority Critical patent/JP2005203664A/en
Publication of JP2005203664A publication Critical patent/JP2005203664A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a mounting method for a semiconductor using a flip-chip method which enables mounting of the semiconductor on a thin resin circuit board less than 0.3 mm in thickness without causing a deformation of the circuit board, such as a warp, during a heating process in a heater, such as a reflow furnace for melting soldering bumps, thus offering a reliable mounter. <P>SOLUTION: The mounting method includes a circuit board placing process of placing the resin circuit board which has positioning holes on a transfer jig having positioning pins, electrode wiring, and mounting pads; a holding jig placing process of placing a board holding jig which has positioning holes on the transfer jig, and a through-hole having a size that allows the through-hole to position the outline of the semiconductor device; a positioning process of inserting the semiconductor device with the soldering bumps directed to the circuit board into the through-hole, and bringing the soldering bumps in contact with the mounting pads to position the semiconductor device on the circuit board; and a heating process of melting the soldering bumps to bond and fix them electrically to the mounting pads. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置を回路基板上へ実装する実装方法に関するもので、さらに詳しくは、半田バンプを有する半導体装置を回路基板上にフリップチップ実装する方法に関するものである。   The present invention relates to a mounting method for mounting a semiconductor device on a circuit board, and more particularly to a method for flip-chip mounting a semiconductor device having solder bumps on a circuit board.

近年、半導体実装は高密度化方向にあり、実装面積の低減および電極数の増加に対して、フリップチップ実装が有効とされている。このフリップチップ実装は、半導体装置の各パッド電極上に導電性のバンプを設け、このバンプを回路基板上の各実装パッドと電気的に接続するようにして実装するものである。   In recent years, semiconductor mounting is in the direction of higher density, and flip-chip mounting is effective for reducing the mounting area and increasing the number of electrodes. In the flip chip mounting, a conductive bump is provided on each pad electrode of a semiconductor device, and the bump is mounted so as to be electrically connected to each mounting pad on a circuit board.

また、同一回路基板上に複数個の半導体チップをフリップチップ実装するには、リフロー炉等の加熱装置で一括実装が可能な半田バンプによるフリップチップ実装が有効である。この様に、半田バンプを有する半導体装置を回路基板に実装する方法が既に提案されている（例えば特許文献１参照。）。   Further, in order to flip-chip mount a plurality of semiconductor chips on the same circuit board, flip-chip mounting by solder bumps that can be collectively mounted by a heating device such as a reflow furnace is effective. Thus, a method for mounting a semiconductor device having solder bumps on a circuit board has been proposed (see, for example, Patent Document 1).

〔従来の半導体装置の実装方法の説明：図５〜図７〕
その従来の実装方法について、図５〜図７を用いて説明する。図５〜図７は、従来の半導体装置の半田バンプによるフリップチップ型の実装方法を示す工程断面図である。 [Description of Conventional Semiconductor Device Mounting Method: FIGS. 5 to 7]
The conventional mounting method will be described with reference to FIGS. 5 to 7 are process sectional views showing a flip chip type mounting method using solder bumps of a conventional semiconductor device.

初めに図５に示すように、例えば、ポリイミド等の材料からなる回路基板５を搬送治具１１上に載置する。この時、回路基板５の位置決め穴９が搬送治具１１上の位置決めピン１５を貫通するようにして載置し、これにより、回路基板５の位置決めが成される。また、回路基板５に形成された実装パッド７上に、半田の濡れ性を良好にするためのフラックスを予め供給しておく。   First, as shown in FIG. 5, for example, the circuit board 5 made of a material such as polyimide is placed on the transport jig 11. At this time, the positioning hole 9 of the circuit board 5 is placed so as to penetrate the positioning pin 15 on the conveying jig 11, and thereby the positioning of the circuit board 5 is achieved. Further, a flux for improving the wettability of the solder is supplied in advance on the mounting pad 7 formed on the circuit board 5.

ここで回路基板５には、半導体装置１上の半田バンプ３と合致する位置に実装パッド７が設けられていて、この実装パッド７の表面には半導体装置１の半田バンプ３との濡れ性を良好にするために、ニッケル−金メッキまたは半田メッキを施すことが好ましい。   Here, the circuit board 5 is provided with a mounting pad 7 at a position matching the solder bump 3 on the semiconductor device 1, and the surface of the mounting pad 7 has wettability with the solder bump 3 of the semiconductor device 1. In order to make it favorable, it is preferable to perform nickel-gold plating or solder plating.

次に図６に示すように、回路基板５の実装パッド７と半導体装置１上の半田バンプ３の位置合わせを行い、直径約０．１ｍｍの半田バンプ３が複数個設けられた半導体装置１を位置決めされた回路基板５上に搭載する。その後、半導体装置１を回路基板５上に設置した状態でリフロー等の加熱装置を用いて半田の融点より高い温度で加熱して半田バンプ３を溶融させた後、常温に戻して回路基板５上に半導体装置１を固着する。これで、半導体装置１と回路基板５とが、電気的に接続される。   Next, as shown in FIG. 6, the mounting pads 7 of the circuit board 5 and the solder bumps 3 on the semiconductor device 1 are aligned, and the semiconductor device 1 provided with a plurality of solder bumps 3 having a diameter of about 0.1 mm is obtained. Mounted on the positioned circuit board 5. After that, the semiconductor device 1 is placed on the circuit board 5 and heated at a temperature higher than the melting point of the solder using a heating device such as reflow to melt the solder bumps 3, and then returned to room temperature and placed on the circuit board 5. The semiconductor device 1 is fixed to the substrate. Thus, the semiconductor device 1 and the circuit board 5 are electrically connected.

最後に図７に示すように、半田バンプ３周りに付着しているフラックス残渣を洗浄して、半導体装置１と回路基板５の間に封止樹脂２１を注入し、この封止樹脂２１を加熱硬化させることで実装体が完成する。そして、この実装体を搬送治具から外すことで、目的の回路基板５に半導体装置１が実装された実装体を得ることができる。   Finally, as shown in FIG. 7, the flux residue adhering around the solder bumps 3 is washed, the sealing resin 21 is injected between the semiconductor device 1 and the circuit board 5, and the sealing resin 21 is heated. The mounting body is completed by curing. And the mounting body by which the semiconductor device 1 was mounted in the target circuit board 5 can be obtained by removing this mounting body from a conveyance jig.

特公平８−２８８２９１号公報（第３−４頁、第９図−１１図）。Japanese Patent Publication No. 8-288291 (page 3-4, FIGS. 9-11).

しかしながら上記した方法により、金属基板、ガラス基板等の回路基板、または厚さが
０．３ｍｍ以上の樹脂基板製の回路基板には、半導体装置をフリップチップ実装した実装体を得ることができるが、０．３ｍｍ未満の薄い厚さの樹脂製の回路基板に対して以下に示す問題点があった。 However, according to the above-described method, a circuit board such as a metal substrate or a glass substrate, or a circuit board made of a resin substrate having a thickness of 0.3 mm or more can obtain a mounting body in which a semiconductor device is flip-chip mounted. There are the following problems with respect to resin-made circuit boards having a thin thickness of less than 0.3 mm.

従来の半導体装置の実装方法を、０．３ｍｍ未満の薄い厚さの樹脂製の回路基板へのフリップチップ実装にそのまま適用すると、半田バンプ３を溶融するために、リフロー炉などの加熱装置で加熱の際に、回路基板５に反りなどの変形が生じる。すると位置合わせを行なって実装パッド７上に搭載した半導体装置１にズレが生じる。このズレを生じたまま半導体装置１を加熱装置で加熱し、半田バンプ３を溶融すると、半田バンプ３と実装パッド７との接続が不完全となる。この結果、半導体装置１と回路基板５との電気的接続が不十分となり、電気的に信頼性を損なうという場合があった。   When the conventional semiconductor device mounting method is applied as it is to flip chip mounting on a resin circuit board having a thin thickness of less than 0.3 mm, the solder bumps 3 are heated by a heating device such as a reflow furnace. At this time, the circuit board 5 is deformed such as warpage. Then, the semiconductor device 1 mounted on the mounting pad 7 is aligned and misaligned. If the semiconductor device 1 is heated with a heating device while this deviation occurs, and the solder bump 3 is melted, the connection between the solder bump 3 and the mounting pad 7 becomes incomplete. As a result, the electrical connection between the semiconductor device 1 and the circuit board 5 becomes insufficient, and there are cases where electrical reliability is impaired.

〔発明の目的〕
そこで本発明の目的は、上記課題を解決して、半田バンプを有する半導体装置を０．３ｍｍ未満の薄い厚さの樹脂製の回路基板に実装するフリップチップ実装方法において、半田バンプ溶融するために、リフロー炉などの加熱装置で加熱の際に、回路基板に反りなどの変形を生じることなく実装ができ、信頼性の高い実装体を得るためのフリップチップによる半導体装置の実装方法を提供することである。 (Object of invention)
SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and to melt a solder bump in a flip chip mounting method in which a semiconductor device having a solder bump is mounted on a resin circuit board having a thin thickness of less than 0.3 mm. To provide a method of mounting a semiconductor device using a flip chip to obtain a highly reliable mounting body that can be mounted without causing deformation such as warping in a circuit board when heated by a heating device such as a reflow furnace. It is.

上記目的を達成するために、本発明の半導体装置の実装方法は、下記記載の方法を採用する。   In order to achieve the above object, the method described below is adopted as a method for mounting a semiconductor device of the present invention.

本発明の半導体装置の実装方法は、半田バンプを有する半導体装置を回路基板上にフリップチップ実装する方法において、位置決めピンを有する搬送治具上に、位置決め穴を有し、電極配線および実装パッドが形成された樹脂製の回路基板を載置する回路基板載置工程と、搬送治具上に位置決め穴を有し、かつ半導体装置の外形サイズを位置決めできるだけの貫通孔を有する基板押え治具を載置する押え治具載置工程と、半田バンプが回路基板と向き合う方向に、貫通孔内に半導体装置を挿入し、半田バンプと実装パッドを当接させて、回路基板上に位置決めして搭載する位置決め工程と、半田バンプを溶融させて、半田バンプと実装パッドを電気的に接合して固着させる加熱工程と、半導体装置と回路基板の間に封止樹脂を流し込み、この封止樹脂を加熱硬化させる封止工程とを備えることを特徴とする。   The semiconductor device mounting method of the present invention is a method of flip-chip mounting a semiconductor device having solder bumps on a circuit board. The method includes mounting holes on a transfer jig having positioning pins, and electrode wiring and mounting pads are provided. A circuit board mounting step for mounting the formed resin circuit board, and a substrate holding jig having a positioning hole on the transfer jig and having a through hole capable of positioning the outer size of the semiconductor device are mounted. Place the holding jig and place the semiconductor device in the through hole in the direction where the solder bump faces the circuit board, place the solder bump and the mounting pad in contact, and position and mount on the circuit board. A positioning step, a heating step in which the solder bump is melted, and the solder bump and the mounting pad are electrically bonded and fixed, and a sealing resin is poured between the semiconductor device and the circuit board. Characterized in that it comprises a sealing step of heating and curing the sealing resin.

本発明において、半田バンプを有する半導体装置を、例えば０．３ｍｍ未満の薄い厚さの樹脂製の回路基板にフリップチップ実装する半導体装置の実装方法において、回路基板は搬送治具上に供給され、この時、回路基板の位置決め穴と搬送治具上の位置決めピンによって位置決めされる。また回路基板上には基板押え治具が供給され、搬送治具上の位置決めピンと基板押え治具の位置決め穴によって位置決めされる。   In the present invention, in a semiconductor device mounting method in which a semiconductor device having solder bumps is flip-chip mounted on a resin circuit board having a thin thickness of less than 0.3 mm, for example, the circuit board is supplied onto a conveying jig, At this time, the positioning is performed by positioning holes on the circuit board and positioning pins on the conveying jig. Further, a substrate pressing jig is supplied onto the circuit board and is positioned by positioning pins on the conveying jig and positioning holes of the substrate pressing jig.

回路基板は、半導体装置を搭載する周辺が、搬送治具と基板押え治具で挟まれた状態で、回路基板上に半導体装置を搭載後、加熱装置で加熱される。このため、基板押え治具の重量によって、回路基板には反りなどの変形が生じることはないために、半導体装置のズレが生じない。以上の工程によって、電気的に信頼性の高い実装体を得るための半導体装置の実装方法が提供される。   The circuit board is heated by a heating device after the semiconductor device is mounted on the circuit board in a state where the periphery on which the semiconductor device is mounted is sandwiched between the transport jig and the substrate pressing jig. For this reason, the circuit board is not deformed such as warping due to the weight of the substrate pressing jig, and thus the semiconductor device is not displaced. Through the above steps, a semiconductor device mounting method for obtaining an electrically reliable mounting body is provided.

以下、図面を用いて本発明の半導体装置の実装方法について説明する。図1〜図４は、本発明の実装方法を示す断面工程図である。図において、従来技術と同一形状の部材は同
一符号で示す。 The semiconductor device mounting method of the present invention will be described below with reference to the drawings. 1 to 4 are sectional process diagrams showing the mounting method of the present invention. In the figure, members having the same shape as in the prior art are denoted by the same reference numerals.

〔本発明の半導体装置の実装方法の説明：図１〜図４〕
はじめに図１に示すように、回路基板５を搬送治具１１に載置する。この時、回路基板５の位置決め穴９が搬送治具１１上の位置決めピン１３を貫通するように配置する。これで、回路基板５が搬送治具１１上に固定される。また、回路基板５の実装パッド７上には、半田の濡れ性を良好にするために、予めフラックスを供給しておくことが好ましい。 [Description of Mounting Method of Semiconductor Device of the Present Invention: FIGS. 1 to 4]
First, as shown in FIG. 1, the circuit board 5 is placed on the conveying jig 11. At this time, the positioning holes 9 of the circuit board 5 are arranged so as to penetrate the positioning pins 13 on the conveying jig 11. Thus, the circuit board 5 is fixed on the transport jig 11. Further, it is preferable to supply a flux on the mounting pads 7 of the circuit board 5 in advance in order to improve the wettability of the solder.

また、回路基板５には位置決め穴９が複数個設けられ、搬送治具１１には位置決めピン１３がこの位置決め穴９と同数個設けられている。位置決め穴９と位置決めピン１３は、合致するように、回路基板５と搬送治具１１が配置されている。
さらに、回路基板５には、半導体装置１上の半田バンプ３と合致する位置に実装パッド７が設けられていて、この実装パッド７の表面には、半導体装置１の半田バンプ３との濡れ性を良好にするために、ニッケル−金メッキまたは半田メッキが施されている。 The circuit board 5 has a plurality of positioning holes 9, and the conveying jig 11 has the same number of positioning pins 13 as the positioning holes 9. The circuit board 5 and the conveying jig 11 are arranged so that the positioning hole 9 and the positioning pin 13 coincide with each other.
Further, the circuit board 5 is provided with a mounting pad 7 at a position matching the solder bump 3 on the semiconductor device 1, and the surface of the mounting pad 7 is wettable with the solder bump 3 of the semiconductor device 1. In order to improve the resistance, nickel-gold plating or solder plating is applied.

次に図２に示すように、回路基板５の上に、例えば金属材料であり、次工程で載置する半導体装置のサイズよりも若干大きな貫通孔を有する穴が設けられている基板押え治具１７を載置する。この時、基板押え治具１７の位置決め穴１９が搬送治具１１上の位置決めピン１３を貫通するように配置する。これで、基板押え治具１７は、回路基板５と同様に、搬送治具１１上に固定される。   Next, as shown in FIG. 2, a substrate pressing jig in which a hole having a through hole which is made of, for example, a metal material and is slightly larger than the size of the semiconductor device to be mounted in the next process is provided on the circuit substrate 5. 17 is placed. At this time, the positioning holes 19 of the substrate pressing jig 17 are arranged so as to penetrate the positioning pins 13 on the conveying jig 11. Thus, the substrate holding jig 17 is fixed on the conveying jig 11 in the same manner as the circuit board 5.

なお、この基板押え治具１７は、前述した金属材料に限定されるものではなく、後段で説明をする半導体装置に設けた半田バンプと実装パッド７との電気的接合と、固着のための加熱工程で、熱変形が起こり難い材料であれば、他の材料の部材を用いても構わない。また、基板押え治具１７の位置決め穴１９は、搬送治具１１の位置決めピン１３と合致する位置に位置決めピン１３と同数個設けられている。   The substrate pressing jig 17 is not limited to the above-described metal material, and electrical bonding between solder bumps and mounting pads 7 provided in a semiconductor device described later and heating for fixing. Other materials may be used as long as the material hardly causes thermal deformation in the process. Further, the same number of positioning holes 19 of the substrate pressing jig 17 as the positioning pins 13 are provided at positions matching the positioning pins 13 of the transport jig 11.

次に図３に示すように、半導体装置１に形成された半田バンプ３と回路基板５上に形成された実装パッド７とが合致するように、半導体装置１の位置合わせを行ない、その後、半導体装置１を回路基板５上に搭載する。   Next, as shown in FIG. 3, the semiconductor device 1 is aligned so that the solder bumps 3 formed on the semiconductor device 1 and the mounting pads 7 formed on the circuit board 5 coincide with each other. The device 1 is mounted on the circuit board 5.

ここで半導体装置１の大きさは、厚さ０．４ｍｍから０．７ｍｍで、外形１ｍｍ角から１０ｍｍ角である。半導体装置１に形成された半田バンプ３は、半導体装置１の外周に直径約０．１ｍｍの大きさで、０．１５ｍｍから０．３ｍｍピッチで配置されるように複数個設けられている。またこの半田バンプ３は、マスク蒸着法や電解メッキ法を用いて形成される。   Here, the semiconductor device 1 has a thickness of 0.4 mm to 0.7 mm and an outer shape of 1 mm square to 10 mm square. A plurality of solder bumps 3 formed on the semiconductor device 1 are provided on the outer periphery of the semiconductor device 1 so as to have a diameter of about 0.1 mm and be arranged at a pitch of 0.15 mm to 0.3 mm. The solder bumps 3 are formed using a mask vapor deposition method or an electrolytic plating method.

次に、半導体装置１を回路基板５上に設置した状態でリフロー等の加熱装置を用いて半田の融点より高い温度で加熱して半田バンプ３を溶融し、その後、常温に戻してこの半田バンプ３を硬化させることで、半田バンプ３と実装パッド７との電気的な接続と、回路基板５上に半導体装置１を固着する。これで半導体装置１と回路基板５とが電気的に接続される。その後、基板押え治具１７を回路基板５上より取り外す。   Next, with the semiconductor device 1 placed on the circuit board 5, the solder bump 3 is melted by heating at a temperature higher than the melting point of the solder using a heating device such as reflow, and then returned to room temperature. 3 is hardened, and the electrical connection between the solder bump 3 and the mounting pad 7 and the semiconductor device 1 are fixed onto the circuit board 5. Thus, the semiconductor device 1 and the circuit board 5 are electrically connected. Thereafter, the board holding jig 17 is removed from the circuit board 5.

最後に図４に示すように、半田バンプ３周りに付着しているフラックス残渣を洗浄して、半導体装置１と回路基板５の間に封止樹脂２１を注入し、加熱硬化させる。そして、この搬送治具１１を取り外すことで実装体が完成する。   Finally, as shown in FIG. 4, the flux residue adhering around the solder bumps 3 is washed, the sealing resin 21 is injected between the semiconductor device 1 and the circuit board 5, and is cured by heating. Then, the mounting body is completed by removing the transport jig 11.

以上の説明で明らかなように、半田バンプを有する半導体装置１を０．３ｍｍ未満の薄い厚みの樹脂製の回路基板に実装するフリップチップ実装方法において、回路基板５は搬送治具１１上に載置し、この時、回路基板５の位置決め穴９と、搬送治具１１上の位置決
めピン１３によって位置決めされる。 As is apparent from the above description, in the flip chip mounting method in which the semiconductor device 1 having solder bumps is mounted on a resin circuit board having a thin thickness of less than 0.3 mm, the circuit board 5 is mounted on the conveying jig 11. At this time, the positioning hole 9 of the circuit board 5 and the positioning pin 13 on the conveying jig 11 are positioned.

また回路基板５上には、基板押え治具１７が載置され、搬送治具１１上の位置決めピン１３と、基板押え治具１７の位置決め穴１９によって、この基板押え治具１７も回路基板５と同様に位置決めされる。   A substrate holding jig 17 is placed on the circuit board 5, and the board holding jig 17 is also arranged on the circuit board 5 by positioning pins 13 on the conveying jig 11 and positioning holes 19 in the board holding jig 17. Positioned in the same way as

回路基板５は、半導体装置１を搭載する周辺が、搬送治具１１と基板押え治具１７で挟まれた状態で、回路基板５上に半導体装置１を搭載後、加熱装置で加熱される。このため、基板押え治具１７の重量によって、回路基板５には反りなどの変形は生じることはないために、半導体装置１のズレが生じない。以上の工程によって、電気的に信頼性の高い実装体を得るためのフリップチップによる半導体装置の実装方法が提供される。   The circuit board 5 is heated by a heating device after the semiconductor device 1 is mounted on the circuit board 5 in a state where the periphery on which the semiconductor device 1 is mounted is sandwiched between the transport jig 11 and the substrate pressing jig 17. For this reason, the circuit board 5 is not deformed such as warp due to the weight of the substrate pressing jig 17, so that the semiconductor device 1 is not displaced. Through the above steps, a flip chip mounting method for a semiconductor device for obtaining an electrically reliable mounting body is provided.

本発明の実施の形態における半導体装置の実装方法を示す工程断面図である。It is process sectional drawing which shows the mounting method of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の実装方法を示す工程断面図である。It is process sectional drawing which shows the mounting method of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の実装方法を示す工程断面図である。It is process sectional drawing which shows the mounting method of the semiconductor device in embodiment of this invention. 本発明の実施の形態における半導体装置の実装方法を示す工程断面図である。It is process sectional drawing which shows the mounting method of the semiconductor device in embodiment of this invention. 従来の半導体装置の実装方法を示す工程断面図である。It is process sectional drawing which shows the mounting method of the conventional semiconductor device. 従来の半導体装置の実装方法を示す工程断面図である。It is process sectional drawing which shows the mounting method of the conventional semiconductor device. 従来の半導体装置の実装方法を示す工程断面図である。It is process sectional drawing which shows the mounting method of the conventional semiconductor device.

符号の説明Explanation of symbols

１ 半導体装置
３ 半田バンプ
５ 回路基板
９ 位置決め穴
１３ 位置決めピン
１７ 基板押え治具
１９ 位置決め穴 DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Solder bump 5 Circuit board 9 Positioning hole 13 Positioning pin 17 Substrate pressing jig 19 Positioning hole

Claims (1)

半田バンプを有する半導体装置を回路基板上にフリップチップ実装する半導体装置の実装方法において、
位置決めピンを有する搬送治具上に、位置決め穴を有し、電極配線および実装パッドが形成された樹脂製の回路基板を載置する回路基板載置工程と、
前記搬送治具上に位置決め穴を有し、かつ前記半導体装置の外形サイズを位置決めできるだけの貫通孔を有する基板押え治具を載置する押え治具載置工程と、
前記半田バンプが前記回路基板と向き合う方向に、前記貫通孔内に前記半導体装置を挿入し、前記半田バンプと前記実装パッドを当接させて、前記回路基板上に位置決めして搭載する位置決め工程と、
前記半田バンプを溶融させて、前記半田バンプと前記実装パッドを電気的に接合して固着させる加熱工程と、
前記半導体装置と前記回路基板の間に封止樹脂を流し込み、この封止樹脂を加熱硬化させる封止工程と、
を備えることを特徴とする半導体装置の実装方法。 In a semiconductor device mounting method in which a semiconductor device having a solder bump is flip-chip mounted on a circuit board,
A circuit board mounting step for mounting a resin circuit board having positioning holes on the conveying jig having positioning pins and having electrode wiring and mounting pads formed thereon;
A holding jig mounting step of mounting a substrate pressing jig having a positioning hole on the transport jig and having a through hole capable of positioning the outer size of the semiconductor device;
A positioning step in which the semiconductor device is inserted into the through hole in a direction in which the solder bump faces the circuit board, the solder bump and the mounting pad are brought into contact, and positioned on the circuit board to be mounted; ,
A heating step of melting the solder bump and electrically bonding and fixing the solder bump and the mounting pad;
A sealing step of pouring a sealing resin between the semiconductor device and the circuit board, and heating and curing the sealing resin;
A method for mounting a semiconductor device, comprising:
JP2004010208A 2004-01-19 2004-01-19 Mounting method for semiconductor device Pending JP2005203664A (en)

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Publications (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011030753A1 (en) * 2009-09-09 2011-03-17 東京エレクトロン株式会社 Method for manufacturing a semiconductor device
US8067835B2 (en) 2007-11-27 2011-11-29 Renesas Electronics Corporation Method and apparatus for manufacturing semiconductor module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8067835B2 (en) 2007-11-27 2011-11-29 Renesas Electronics Corporation Method and apparatus for manufacturing semiconductor module
WO2011030753A1 (en) * 2009-09-09 2011-03-17 東京エレクトロン株式会社 Method for manufacturing a semiconductor device
JP2011060941A (en) * 2009-09-09 2011-03-24 Tokyo Electron Ltd Method of manufacturing semiconductor device
US8664106B2 (en) 2009-09-09 2014-03-04 Tokyo Electron Limited Method of manufacturing semiconductor device

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