JP2005252126A - Method of working wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer working method by which decomposed layers are formed along scheduled dividing lines of a wafer, and folding resistances of chips divided along the scheduled dividing lines formed with the decomposed layers can be improved. <P>SOLUTION: A wafer working method for dividing a wafer by which functional elements are disposed in areas divided by lattice-shaped scheduled dividing lines on a front surface includes a decomposed layer forming step for forming a decomposed layer along the scheduled dividing lines inside the wafer by irradiating the wafer with a pulse laser beam that is permeable along the scheduled dividing lines; a dividing step for dividing the wafer into chips along the scheduled dividing lines by applying an external force along the scheduled dividing lines formed with the decomposed layers; a chip supporting step for disposing the divided chips on a supporting member while turning their rear surfaces upside with a space between each other; and a decomposed area removing step for removing the decomposed layers residual on side faces of the chips disposed on the supporting member with a space between each other. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wafer dividing method for dividing a wafer in which functional elements are arranged in regions partitioned by scheduled dividing lines formed in a lattice shape on the surface along the scheduled dividing lines.

  In the semiconductor device manufacturing process, a plurality of regions are partitioned by dividing lines called streets arranged in a lattice pattern on the surface of a substantially disc-shaped semiconductor wafer, and circuits such as ICs, LSIs, etc. are partitioned in these partitioned regions. (Functional element) is formed. Then, by cutting the semiconductor wafer along the planned dividing line, the region where the circuit is formed is divided to manufacture individual semiconductor chips. In addition, an optical device wafer in which a light receiving element (functional element) such as a photodiode or a light emitting element (functional element) such as a laser diode is laminated on the surface of a sapphire substrate is cut along individual lines by dividing each photo. Divided into optical devices such as diodes and laser diodes, they are widely used in electrical equipment.

  The cutting along the division lines such as the above-described semiconductor wafer and optical device wafer is usually performed by a cutting device called a dicer. This cutting apparatus includes a chuck table for holding a workpiece such as a semiconductor wafer or an optical device wafer, a cutting means for cutting the workpiece held on the chuck table, and a chuck table and the cutting means. And a cutting feed means for moving it. The cutting means includes a spindle unit having a rotary spindle, a cutting blade mounted on the spindle, and a drive mechanism for driving the rotary spindle to rotate. The cutting blade is composed of a disk-shaped base and an annular cutting edge mounted on the outer periphery of the side surface of the base. The cutting edge is fixed to the base by electroforming, for example, diamond abrasive grains having a particle size of about 3 μm. It is formed to a thickness of about 20 μm.

  However, since the cutting blade has a thickness of about 20 μm, the dividing line that divides the chip needs to have a width of about 50 μm, and the area ratio of the dividing line to the area of the wafer is large, resulting in poor productivity. There is. Moreover, since the sapphire substrate, the silicon carbide substrate, and the like have high Mohs hardness, cutting with the cutting blade is not always easy.

On the other hand, in recent years, as a method for dividing a plate-like workpiece such as a semiconductor wafer, a pulse laser beam that uses a pulsed laser beam that is transparent to the workpiece and aligns the condensing point inside the region to be divided is used. A laser processing method for irradiating the film has also been attempted. The dividing method using this laser processing method irradiates a pulsed laser beam in an infrared region having transparency to the work piece by aligning a condensing point from one side of the work piece to the inside. The workpiece is divided by continuously forming a deteriorated layer along the planned division line inside the workpiece and applying external force along the planned division line whose strength has been reduced by the formation of this modified layer. To do. (For example, refer to Patent Document 1.)
Japanese Patent No. 3408805

  Thus, an altered layer is formed along the planned division line of the wafer, and the altered layer remains on the side surface of the chip divided by applying an external force along the planned division line on which the altered layer is formed. In addition, there is a problem that this deteriorated layer reduces the bending strength of the chip. In addition, since the back surface of the wafer is ground to a predetermined thickness by a grinding device before being divided into individual chips, microcracks generated by grinding remain on the back surface of the wafer. In combination with the above-mentioned residual deteriorated layer, the bending strength of the chip is further reduced.

  The present invention has been made in view of the above-mentioned facts, and the main technical problem thereof is to form a deteriorated layer by irradiating a pulsed laser beam along a planned division line of the wafer, and to form the divided layer in which the deteriorated layer is formed. It is an object of the present invention to provide a wafer processing method capable of improving the bending strength of chips divided along a predetermined line.

In order to solve the above-described main technical problem, according to the present invention, a wafer in which functional elements are arranged in a region partitioned by a predetermined division line formed in a lattice shape on the surface is divided along the predetermined division line. Wafer processing method,
A deteriorated layer forming step of irradiating the wafer with a pulsed laser beam having transparency to the dividing line and forming a deteriorated layer along the dividing line inside the wafer;
A dividing step of applying an external force along the planned division line on which the altered layer is formed, and dividing the wafer into individual chips along the planned division line;
A chip support step in which the individually divided chips are arranged on the support member with the back side up and spaced apart from each other;
An altered region removing step of removing the altered layer remaining on the side surface of the chip disposed at a distance from the support member,
A method for processing a wafer is provided.

Further, according to the present invention, there is provided a wafer processing method for dividing a wafer in which functional elements are arranged in a region partitioned by a predetermined division line formed in a lattice shape on a surface along the predetermined division line. ,
A deteriorated layer forming step of irradiating the wafer with a pulsed laser beam having transparency to the dividing line and forming a deteriorated layer along the dividing line inside the wafer;
A tape adhering step for adhering the surface of the wafer to the holding tape before or after performing the deteriorated layer forming step;
A dividing step of applying an external force along the planned dividing line on which the altered layer of the wafer mounted on the holding tape is formed, and dividing the wafer into individual chips along the planned dividing line;
A tape expansion step of expanding a holding tape to which a wafer divided into individual chips is attached to form a gap between the chips;
An altered layer removing step of removing the altered layer remaining on the side surface of the chip in a state where the holding tape is expanded and a gap is formed between the chips,
A method for processing a wafer is provided.

  The deteriorated layer removing step is preferably performed by etching, particularly plasma etching. Furthermore, it is preferable that the dividing step is performed by expanding the holding tape in the tape expanding step.

  Since the wafer processing method in the present invention comprises the above steps, the altered layer is formed by irradiating a pulse laser beam along the planned division lines formed on the surface in a lattice pattern, and the altered layer is formed. Since the deteriorated layer remaining on the side surfaces of the chips divided along the division lines is removed, the bending strength of the divided chips can be improved.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of a wafer processing method according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a perspective view of a semiconductor wafer as a wafer to be processed according to the present invention. A semiconductor wafer 2 shown in FIG. 1 is made of a silicon wafer, and a plurality of division lines 21 are formed in a lattice shape on the surface 2a, and in a plurality of regions partitioned by the plurality of division lines 21. A circuit 22 as a functional element is formed.

  The semiconductor wafer 2 configured in this manner performs a tape adhering step of adhering the surface 2a to a holding tape attached to an annular frame. In the tape attaching step, the surface 2a of the semiconductor wafer 2 is attached to the surface of the extendable holding tape 30 attached to the annular frame 3 as shown in FIG. 2 (therefore, the back surface 2b of the semiconductor wafer 2 is attached). On the top). In the illustrated embodiment, the holding tape 30 has an acrylic resin-based paste applied to the surface of a stretchable sheet base material made of polyvinyl chloride (PVC) having a thickness of 100 μm to a thickness of about 5 μm. Yes. This paste has a property that the adhesive strength is reduced by an external stimulus such as ultraviolet rays.

  If the surface 2a of the semiconductor wafer 2 is attached to the holding tape 30 attached to the annular frame 3 by performing the tape attaching process, the back surface 2b of the semiconductor wafer 2 is ground to a predetermined thickness. A grinding process is performed. This grinding process is performed by the grinding apparatus 4 shown in FIG. That is, in the grinding process, first, the holding tape 30 side of the semiconductor wafer 2 is placed on the chuck table 41 of the grinding device 4 (therefore, the back surface 2b of the semiconductor wafer 2 is on the upper side) as shown in FIG. The semiconductor wafer 2 is sucked and held on the chuck table 41 by the suction means that does not. In FIG. 3, the annular frame 3 to which the holding tape 30 is attached is omitted, but the annular frame 3 is held by an appropriate clamp mechanism provided on the chuck table 41. If the semiconductor wafer 2 is held on the chuck table 41 in this way, the back surface of the semiconductor wafer 2 is rotated by rotating the grinding tool 43 provided with the grinding wheel 42 at, for example, 6000 rpm while rotating the chuck table 41 at, for example, 300 rpm. By contacting 2b, the back surface 2b of the semiconductor wafer 2 is ground to form the semiconductor wafer 2 to a predetermined thickness.

  Next, a pulsed laser beam having transparency to the wafer is irradiated along the planned dividing line from the back surface 2b side of the semiconductor wafer 2 ground to a predetermined thickness, and along the planned dividing line inside the wafer. A deteriorated layer forming step of forming a deteriorated layer is performed. This deteriorated layer forming step is performed using a laser processing apparatus 5 shown in FIGS. A laser processing apparatus 5 shown in FIGS. 4 to 6 includes a chuck table 51 that holds a workpiece, laser beam irradiation means 52 that irradiates the workpiece held on the chuck table 51 with a laser beam, and a chuck table 51. An image pickup means 53 for picking up an image of the workpiece held thereon is provided. The chuck table 51 is configured to suck and hold a workpiece, and can be moved in a machining feed direction indicated by an arrow X and an index feed direction indicated by an arrow Y in FIG. Yes.

  The laser beam irradiation means 52 includes a cylindrical casing 521 disposed substantially horizontally. In the casing 521, as shown in FIG. 5, a pulse laser beam oscillation means 522 and a transmission optical system 523 are arranged. The pulse laser beam oscillation means 522 is composed of a pulse laser beam oscillator 522a composed of a YAG laser oscillator or a YVO4 laser oscillator, and a repetition frequency setting means 522b attached thereto. The transmission optical system 523 includes an appropriate optical element such as a beam splitter. A condenser 524 containing a condenser lens (not shown) composed of a combination lens that may be in a known form is attached to the tip of the casing 521. The laser beam oscillated from the pulse laser beam oscillating means 522 reaches the condenser 524 through the transmission optical system 523, and a predetermined focused spot diameter is applied to the workpiece held on the chuck table 51 from the condenser 524. Irradiated with D. As shown in FIG. 6, the focused spot diameter D is D (μm) = 4 × λ × f / (π when a pulse laser beam having a Gaussian distribution is irradiated through the objective condenser lens 524 a of the condenser 524. × W), where λ is defined by the wavelength (μm) of the pulsed laser beam, W is the diameter (mm) of the pulsed laser beam incident on the objective lens 524a, and f is the focal length (mm) of the objective lens 524a.

  In the illustrated embodiment, the image pickup means 53 mounted on the tip of the casing 521 constituting the laser beam irradiation means 52 emits infrared rays to the workpiece in addition to a normal image pickup device (CCD) that picks up an image with visible light. Infrared illumination means for irradiating, an optical system for capturing infrared light emitted by the infrared illumination means, an image pickup device (infrared CCD) for outputting an electrical signal corresponding to the infrared light captured by the optical system, and the like Then, the captured image signal is sent to the control means described later.

The deteriorated layer forming step performed using the laser processing apparatus 5 described above will be described with reference to FIGS. 4, 7, and 8.
In this deteriorated layer forming step, the dicing tape 30 side of the semiconductor wafer 2 is first placed on the chuck table 51 of the laser processing apparatus 5 shown in FIG. 4 (therefore, the back surface 2b of the semiconductor wafer 2 is on the upper side). The semiconductor wafer 2 is sucked and held on the chuck table 51 by suction means (not shown). 4, 7, and 8, the annular frame 3 to which the holding tape 30 is attached is omitted, but the annular frame 3 is attached to an appropriate clamping mechanism disposed on the chuck table 51. Is retained. The chuck table 51 that sucks and holds the semiconductor wafer 2 in this way is positioned directly below the imaging means 53 by a moving mechanism (not shown).

  When the chuck table 51 is positioned immediately below the image pickup means 53, an alignment operation for detecting a processing region to be laser processed of the semiconductor wafer 2 is executed by the image pickup means 53 and a control means (not shown). That is, the image pickup means 53 and the control means (not shown) include the division line 21 formed in a predetermined direction of the semiconductor wafer 2, and the condenser 524 of the laser beam irradiation means 52 that irradiates the laser beam along the division line 21. Image processing such as pattern matching is performed to align the laser beam, and alignment of the laser beam irradiation position is performed. In addition, alignment of the laser beam irradiation position is similarly performed on the division line 21 formed on the semiconductor wafer 2 and extending at right angles to the predetermined direction. At this time, the surface 2a on which the division line 21 of the semiconductor wafer 2 is formed is located on the lower side, but the imaging unit 53 corresponds to the infrared illumination unit, the optical system for capturing infrared rays and the infrared ray as described above. Since the image pickup device is provided with an image pickup device (infrared CCD) or the like that outputs an electric signal, the division planned line 21 can be picked up through the back surface 2b.

  If the division planned line 21 formed on the semiconductor wafer 2 held on the chuck table 51 is detected as described above and the laser beam irradiation position is aligned, it is shown in FIG. In this way, the chuck table 51 is moved to the laser beam irradiation region where the condenser 524 of the laser beam irradiation means 52 for irradiating the laser beam is located, and one end (the left end in FIG. 7A) of the predetermined division line 21 is irradiated with the laser beam. Positioned just below the light collector 524 of the means 52. The chuck table 51, that is, the semiconductor wafer 2, is moved at a predetermined feed speed in the direction indicated by the arrow X1 in FIG. Then, as shown in FIG. 7B, when the irradiation position of the condenser 524 of the laser beam irradiation means 52 reaches the position of the other end of the division planned line 21, the irradiation of the pulse laser beam is stopped and the chuck table 51, The movement of the semiconductor wafer 2 is stopped. In this deteriorated layer forming step, the condensing point P of the pulse laser beam is matched with the vicinity of the surface 2a (lower surface) of the semiconductor wafer 2, so that the deteriorated layer 210 is exposed to the surface 2a (lower surface) and from the surface 2a toward the inside. Is formed. This altered layer 210 is formed as a melt-resolidified layer. By forming the altered layer 210 so as to be exposed on the surface 2 a of the semiconductor wafer 2, division by applying an external force along the altered layer 210 is facilitated.

Note that the processing conditions in the deteriorated layer forming step are set as follows, for example.
Light source: LD excitation Q switch Nd: YVO4 laser wavelength: 1064 nm pulse laser Pulse output: 10 μJ
Condensing spot diameter: φ1μm
Pulse width: 100 nsec
Peak power density at condensing point; 3.2 × 10 ¹⁰ W / cm ²
Repetition frequency: 400 kHz
Processing feed rate: 400mm / sec

  When the thickness of the semiconductor wafer 2 is thick, the plurality of deteriorated layers 210 are formed by changing the condensing point P stepwise as shown in FIG. Form. Note that, since the thickness of the deteriorated layer formed at one time is about 50 μm under the above-described processing conditions, in the illustrated embodiment, six deteriorated layers are formed on the wafer 2 having a thickness of 300 μm. . As a result, the altered layer 210 formed inside the semiconductor wafer 2 is formed from the front surface 2a to the back surface 2b along the planned dividing line 21. In this way, by performing the deteriorated layer forming process along all the planned division lines 21 formed on the semiconductor wafer 2, the semiconductor wafer 2 includes all the planned division lines 21 as shown in FIG. 9. Thus, the altered layer 210 is formed.

  If the deteriorated layer 210 is formed along the planned division line 21 inside the semiconductor wafer 2 by the above-described deteriorated layer forming step, a division process for dividing the semiconductor wafer 2 along the planned division line 21 is performed. In the illustrated embodiment, this dividing step is performed using a dividing device 6 shown in FIG. 10 includes a frame holding means 61 for holding the annular frame 3 and a tape expanding means 62 for expanding the holding tape 30 attached to the annular frame 3 held by the frame holding means 61. It has. The frame holding means 61 includes an annular frame holding member 611 and a plurality of clamp mechanisms 612 as fixing means disposed on the outer periphery of the frame holding member 611. An upper surface of the frame holding member 611 forms a mounting surface 611a on which the annular frame 3 is placed, and the annular frame 3 is placed on the mounting surface 611a. The annular frame 3 placed on the placement surface 611a is fixed to the frame holding member 611 by the clamp mechanism 612. The frame holding means 61 configured in this manner is supported by the tape expanding means 62 so as to be able to advance and retract in the vertical direction.

  The tape expansion means 62 includes an expansion drum 621 disposed inside the annular frame holding member 611. The expansion drum 621 has an inner diameter and an outer diameter that are smaller than the inner diameter of the annular frame 3 and larger than the outer diameter of the semiconductor wafer 2 attached to the holding tape 30 attached to the annular frame 3. Further, the expansion drum 621 includes a support flange 622 at the lower end. The tape expansion means 62 in the illustrated embodiment includes support means 63 that can advance and retract the annular frame holding member 611 in the vertical direction. The support means 63 includes a plurality of air cylinders 631 disposed on the support flange 622, and the piston rod 632 is coupled to the lower surface of the annular frame holding member 611. As described above, the support means 63 including the plurality of air cylinders 631 has the annular frame holding member 611 with a predetermined amount from the reference position where the mounting surface 611a is substantially at the same height as the upper end of the expansion drum 621, and the upper end of the expansion drum 621. Move up and down between the lower extended positions. Therefore, the support means 63 composed of a plurality of air cylinders 631 functions as expansion movement means for relatively moving the expansion drum 621 and the frame holding member 611 in the vertical direction.

  A dividing process performed using the dividing apparatus 6 configured as described above will be described with reference to FIG. That is, as shown in FIG. 9, the annular frame 3 that supports the semiconductor wafer 2 (the altered layer 210 is formed along the division line 21) via the holding tape 30 is shown in FIG. As shown, it is placed on the placement surface 611 a of the frame holding member 611 constituting the frame holding means 61, and is fixed to the frame holding member 611 by the clamp mechanism 612. At this time, the frame holding member 611 is positioned at the reference position shown in FIG. Next, the plurality of air cylinders 631 as the support means 63 constituting the tape expansion means 62 are operated to lower the annular frame holding member 611 to the expansion position shown in FIG. 11B (tape expansion process). . Accordingly, since the holding frame 30 fixed on the mounting surface 611a of the frame holding member 611 is also lowered, the holding tape 30 attached to the annular frame 3 is expanded drum 621 as shown in FIG. It is expanded by abutting against the upper edge of the. As a result, the tensile force acts radially on the semiconductor wafer 2 adhered to the holding tape 30. When a tensile force is applied to the semiconductor wafer 2 in a radial manner in this manner, the strength of the altered layer 210 formed along each scheduled division line 21 is reduced, so that the semiconductor wafer 2 breaks along the altered layer 210. And divided into individual semiconductor chips 220. The expansion amount, that is, the elongation amount of the holding tape 30 in the expansion step can be adjusted by the downward movement amount of the frame holding member 611. According to the experiments by the present inventors, the holding tape 30 is stretched by about 20 mm. Sometimes the semiconductor wafer 2 could be broken along the altered layer 210.

In addition to the dividing method described above, the following dividing method can be used for the dividing step.
That is, by placing the semiconductor wafer 2 (the altered layer 210 is formed along the planned dividing line 21) attached to the holding tape 30 on a flexible rubber sheet and pressing the upper surface thereof with a roller. A method of cleaving the semiconductor wafer 2 along the planned dividing line 21 in which the deteriorated layer 210 is formed and the strength is reduced can be used. Further, for example, a method in which an ultrasonic wave composed of a longitudinal wave (dense wave) having a frequency of about 28 kHz is applied along the planned division line 21 where the deteriorated layer 210 is formed and the strength is reduced, or the strength is reduced when the deteriorated layer 210 is formed. A method of applying a pressing member along the planned division line 21 or a method of applying a heat shock by irradiating a laser beam along the planned division line 21 where the altered layer 210 is formed and the strength is reduced can be used.

  If the dividing step described above is performed, a chip supporting step is performed in which the individually divided chips are arranged on the support member with the back surface facing upward. In the illustrated embodiment, in the illustrated embodiment, first, the individually divided chips 220 are peeled off from the surface of the holding tape 30 as shown in FIG. At this time, by irradiating the holding tape 30 with ultraviolet rays, the adhesive strength of the acrylic resin-based paste applied to the surface of the holding tape 30 is reduced, so that the chip 220 can be easily peeled off. Next, the chips 220 peeled off from the surface of the holding tape 30 are arranged on the surface of the support member 7 with the back surface 220b facing up, with a space S therebetween, as shown in FIG. The support member 7 is formed of a glass plate having a thickness of about 3 mm, and an acrylic resin paste is applied on the surface thereof to a thickness of about 5 μm. This paste has a property that the adhesive strength is reduced by an external stimulus such as ultraviolet rays. Therefore, the surface 220a of the chip 220 disposed on the surface of the support member 7 is adhered. Note that the deteriorated layer 210 remains on the side surface of the chip 220 divided by breaking the semiconductor wafer 2 along the deteriorated layer 210.

  If the above-described chip supporting process is performed, the deteriorated layer removing process for removing the deteriorated layer 210 remaining on the side surfaces of the chips 220 disposed with a space S between the support members 7 is performed. In the illustrated embodiment, this deteriorated layer removing step is performed by the plasma etching apparatus 8 shown in FIG. The plasma etching apparatus 8 shown in FIG. 13 includes a housing 81 that forms a sealed space 81a. The housing 81 includes a bottom wall 811, an upper wall 812, left and right side walls 813 and 814, and a rear side including a side wall 815 and a front side wall (not shown), and the right side wall 814 has an opening for loading and unloading a workpiece. 814a is provided. A gate 82 for opening and closing the opening 814a is disposed outside the opening 814a so as to be movable in the vertical direction. The gate 82 is actuated by the gate actuating means 83. The gate actuating means 83 includes an air cylinder 831 and a piston rod 832 connected to a piston (not shown) disposed in the air cylinder 831, and the air cylinder 831 is connected to the bottom of the housing 81 via a bracket 833. It is attached to the wall 811 and the tip (upper end in the figure) of the piston rod 832 is connected to the gate 82. When the gate 82 is opened by the gate actuating means 83, the chips 220 arranged on the surface of the support member 7 as a workpiece at a distance from each other can be carried in and out through the opening 814a. An exhaust port 811 a is provided in the bottom wall 811 constituting the housing 81, and this exhaust port 811 a is connected to the gas discharge means 84.

In the sealed space 81a formed by the housing 81, a lower electrode 85 and an upper electrode 86 are disposed to face each other.
The lower electrode 85 is made of a conductive material, and includes a disk-shaped workpiece holding portion 851 and a columnar support portion 852 formed to project from the center of the lower surface of the workpiece holding portion 851. It is made up of. In this way, the lower electrode 85 constituted by the workpiece holding portion 851 and the columnar support portion 852 is disposed by inserting the support portion 852 through the hole 811b formed in the bottom wall 811 of the housing 81, It is supported in a state of being sealed to the bottom wall 811 via an insulator 87. Thus, the lower electrode 85 supported by the bottom wall 811 of the housing 81 is electrically connected to the high frequency power supply 88 through the support portion 852.

  A circular fitting recess 851a having an open top is provided on the workpiece holding portion 851 constituting the lower electrode 85, and a disc-like shape formed of a porous ceramic material in the fitting recess 851a. The suction holding member 853 is fitted. A chamber 851b formed on the lower side of the suction holding member 853 in the fitting recess 851a communicates with the suction means 89 by a communication path 852a formed in the workpiece holding portion 851 and the support portion 852. Therefore, by placing the workpiece on the suction holding member 853 and operating the suction means 89 to connect the communication passage 852a to the negative pressure source, a negative pressure acts on the chamber 851b, and the suction holding member 853 is placed on the suction holding member 853. The placed workpiece is sucked and held. Further, by operating the suction means 89 to open the communication path 852a to the atmosphere, the suction holding of the workpiece sucked and held on the suction holding member 853 is released.

  A cooling passage 851b is formed in the lower part of the workpiece holding portion 851 constituting the lower electrode 85. One end of the cooling passage 851b communicates with a refrigerant introduction passage 852b formed in the support portion 852, and the other end of the cooling passage 851b communicates with a refrigerant discharge passage 852c formed in the support portion 852. The refrigerant introduction passage 852b and the refrigerant discharge passage 852c are communicated with the refrigerant supply means 90. Therefore, when the refrigerant supply means 90 operates, the refrigerant is circulated through the refrigerant introduction passage 852b, the cooling passage 851b, and the refrigerant discharge passage 852c. As a result, heat generated during plasma processing, which will be described later, is transmitted from the lower electrode 85 to the refrigerant, so that an abnormal temperature rise of the lower electrode 85 is prevented.

  The upper electrode 86 is made of a conductive material, and includes a disk-like gas ejection part 861 and a columnar support part 862 formed to project from the center of the upper surface of the gas ejection part 861. Yes. Thus, the upper electrode 86 composed of the gas ejection part 861 and the columnar support part 862 is disposed so that the gas ejection part 861 faces the workpiece holding part 851 constituting the lower electrode 85, and the support part 862. Is inserted through a hole 812a formed in the upper wall 812 of the housing 81, and is supported by a seal member 91 mounted in the hole 812a so as to be movable in the vertical direction. An operating member 863 is attached to the upper end portion of the support portion 862, and this operating member 863 is connected to the lifting drive means 92. The upper electrode 86 is grounded via the support portion 862.

  The disc-shaped gas ejection portion 861 that constitutes the upper electrode 86 is provided with a plurality of ejection ports 861a that are open on the lower surface. The plurality of jet outlets 861 a communicate with the gas supply means 93 through a communication path 861 b formed in the gas ejection section 861 and a communication path 862 a formed in the support section 862. The gas supply means 93 supplies a mixed gas for generating plasma mainly composed of fluorine gas such as SF6, CF4, C2F6 and helium (He).

  The plasma etching apparatus 8 in the illustrated embodiment includes a control means for controlling the gate operating means 83, the gas discharging means 84, the high frequency power supply 88, the suction means 89, the refrigerant supply means 90, the elevating drive means 92, the gas supply means 93, and the like. 94. The control means 94 includes data relating to the pressure in the sealed space 81 a formed by the housing 81 from the gas discharge means 84, data relating to the refrigerant temperature (that is, electrode temperature) from the refrigerant supply means 90, and data relating to the gas flow rate from the gas supply means 93. The control means 94 outputs a control signal to each of the above-mentioned means based on these data.

The plasma etching apparatus 8 in the illustrated embodiment is configured as described above, and the chip support process is performed as described above, and the chips 220 disposed on the support member 7 with a space S therebetween are plasma etched. An example will be described.
First, the gate actuating means 83 is actuated to move the gate 82 downward in FIG. 13 to open the opening 814a provided in the right side wall 814 of the housing 81. Next, the support member 7 supporting the chip 220 as described above by the unillustrated unloading / unloading means is conveyed from the opening 814a to the sealed space 81a formed by the housing 81, and the workpiece holding portion 851 constituting the lower electrode 85. The support member 7 side is placed on the suction holding member 853. At this time, the raising / lowering drive means 92 is operated and the upper electrode 86 is raised. Then, by operating the suction means 89 to apply a negative pressure to the chamber 851b as described above, the support member 7 placed on the suction holding member 853 is sucked and held (see FIG. 14).

  When the support member 7 having the chip 220 disposed on the surface is sucked and held on the suction holding member 853, the gate actuating means 83 is actuated to move the gate 82 upward in FIG. The opening 814a provided in 814 is closed. Then, the raising / lowering driving means 92 is operated to lower the upper electrode 86, and the lower electrode 85 constituting the upper electrode 86 and the workpiece holding part 851 constituting the lower electrode 85 are held as shown in FIG. The distance between the upper surface of the chip 220 supported by the supported support member 7 is positioned at a predetermined inter-electrode distance (D) suitable for the plasma etching process. This inter-electrode distance (D) is set to 10 mm in the illustrated embodiment.

  Next, the gas discharge means 84 is operated to evacuate the sealed space 81 a formed by the housing 81. When the sealed space 81a is evacuated, the gas supply means 93 is operated to supply a mixed gas of fluorine-based gas and helium to the upper electrode 86 as a plasma generating gas. The mixed gas supplied from the gas supply means 93 passes through the communication passage 862a formed in the support portion 862 and the communication passage 861b formed in the gas ejection portion 861 from the plurality of jet openings 861a onto the adsorption holding member 853 of the lower electrode 85. Are ejected toward the chip 220 disposed on the surface of the support member 7 held by the substrate. Then, the inside of the sealed space 81a is maintained at a predetermined gas pressure. In this way, a high frequency voltage is applied between the lower electrode 85 and the upper electrode 86 from the high frequency power supply 88 in a state where the mixed gas for generating plasma is supplied. As a result, plasma is generated in the space between the lower electrode 85 and the upper electrode 86, and the active material generated by this plasma acts on the back and side surfaces of the chip 220, so that the back and side surfaces of the chip 220 are etched. As a result, microcracks generated on the back surface of the chip 220 by the polishing process described above are removed, and the deteriorated layer 210 formed in the deteriorated layer forming step and remaining on the side surface of the chip 220 is also removed.

After a silicon wafer having a diameter of 6 inches and a thickness of 500 μm is ground to a thickness of 300 μm, the above-described deteriorated layer forming step and dividing step are performed to obtain a length (a) of 2 mm, a width (b) of 2 mm, and a thickness (h ) A 300 μm chip was manufactured, and plasma etching was performed for 3 minutes by using the above-described plasma etching apparatus using an etching gas mainly containing SF 6 + He. In this plasma etching, the spacing S between the chips was divided into groups of 35 μm, 200 μm, 500 μm, and 1000 μm, and 100 each was performed. Then, as shown in FIG. 15, the chip 220 is placed on a pair of fulcrum rolls A and A arranged at a constant distance (L), and the pressing roll B is placed at a central point between the fulcrum rolls of the chip 220. Then, a three-point bending test in which a load P was applied to the pressing roll B was performed to examine the bending strength.
The internal stress (σ) generated inside the chip is called bending strength and is expressed by the following equation.
σ = 3PL / 2bh ²
Here, P is the breaking load, b, h, and L are in mm, P is in Newton (N), and σ is in megapascal (MPa).
A three-point bending test was performed on 100 chips of each group described above, and the bending strength was calculated using the above formula based on the breaking load P at the time when the semiconductor chip broke, and the average value was obtained. As a result, as shown in FIG. 16, the bending strength (average value) is 680 megapascals (MPa) for the plasma-etched chips with an inter-chip spacing S of 35 μm, and the inter-chip spacing S is 200 μm. Chips were 900 megapascals (MPa), 1020 megapascals (MPa) were plasma etched with an inter-chip spacing S of 500 μm, and 1190 megapascals (MPa) were plasma etched with an inter-chip spacing S of 1000 μm. )Met.
In the comparative example shown in FIG. 16, the above-described three-point bending test is performed on 100 chips before the above-described plasma etching is performed, and the above formula is used based on the breaking load P when the chip is broken. The bending strength is calculated and the average value is obtained. As a result, the bending strength (average value) was 300 megapascals (MPa) as shown in FIG.

  As described above, it can be seen that the bending strength of the chip is improved by performing the above-described plasma etching. Then, by performing the plasma etching with the space S between the chips being increased, the active substance generated by the plasma discharge can sufficiently act on the side surface of the chip, and the altered region formed on the side surface of the chip can be reduced. It can be seen that it can be removed.

  Next, another embodiment in which plasma etching is performed with a space between chips will be described. In this embodiment, as shown in FIG. 17, the dividing device 6 is combined with the lower electrode 85 of the plasma etching device 8. That is, the dividing device 6 is disposed on the bottom wall 811 of the plasma etching device 8 so as to surround the lower electrode 85. Then, as shown in FIG. 9 described above, the annular frame 3 that supports the semiconductor wafer 2 (having the altered layer 210 formed along the planned dividing line 21) via the holding tape 30 is shown in FIG. ) Is placed on the placement surface 611a of the frame holding member 611 constituting the frame holding means 61, and is fixed to the frame holding member 611 by the clamp mechanism 612. At this time, the frame holding member 611 is positioned at the reference position shown in FIG. Next, a plurality of air cylinders 631 as the support means 63 constituting the tape expansion means 62 are operated to lower the annular frame holding member 611 to the expansion position shown in FIG. Accordingly, since the holding frame 30 fixed on the mounting surface 611a of the frame holding member 611 is also lowered, the holding tape 30 attached to the annular frame 3 is expanded drum 721 as shown in FIG. It is expanded by contacting the upper edge of the tape (tape expansion process). As a result, the tensile force acts radially on the semiconductor wafer 2 adhered to the holding tape 30. When a tensile force is applied to the semiconductor wafer 2 in a radial manner in this manner, the strength of the altered layer 210 formed along each scheduled division line 21 is reduced, so that the semiconductor wafer 2 breaks along the altered layer 210. And divided into individual semiconductor chips 220. A gap S is formed between the semiconductor chips 220. As described above, in the embodiment shown in FIGS. 17 and 18, by performing the tape expansion process, the dividing process of dividing the wafer into individual chips along the planned dividing line is performed, and a gap is provided between the chips. S is formed. In addition, you may implement the division | segmentation process mentioned above before implementing a tape expansion process.

  If the tape expansion process described above is performed, the holding tape in which the suction means 89 shown in FIG. 13 is actuated and the semiconductor chips 220 spaced from each other as described above are adhered onto the suction holding member 853. 30 is sucked and held. And the deteriorated layer removal process by the plasma etching process mentioned above is implemented.

  Although the present invention has been described based on the illustrated embodiment, the present invention is not limited to the embodiment, and various modifications are possible within the scope of the gist of the present invention. For example, although the above-described deteriorated layer removing step shows an example of plasma etching (dry etching), wet layer etching or chemical mechanical polishing (CMP) may be used as the deteriorated layer removing step.

The perspective view of the semiconductor wafer divided | segmented by the processing method of the wafer by this invention. The perspective view which shows the state which affixed the surface of the semiconductor wafer shown in FIG. 1 on the holding tape with which the cyclic | annular flame | frame was mounted | worn. Explanatory drawing which shows the grinding | polishing process of the back surface of the wafer by this invention. The principal part perspective view of the laser processing apparatus which implements the deteriorated layer formation process in the processing method of the wafer by this invention. The block diagram which shows simply the structure of the laser beam irradiation means with which the laser processing apparatus shown in FIG. 4 is equipped. The simplification figure for demonstrating the condensing spot diameter of a pulse laser beam. Explanatory drawing of the deteriorated layer formation process in the processing method of the wafer by this invention. Explanatory drawing which shows the state formed by laminating | stacking a deteriorated layer inside a wafer in the deteriorated layer formation process shown in FIG. The perspective view of the wafer in which the process of forming a deteriorated layer in the wafer processing method according to the present invention was performed. The perspective view which shows one Embodiment of the division | segmentation apparatus which implements the division | segmentation process in the processing method of the wafer by this invention. Explanatory drawing of the division | segmentation process in the processing method of the wafer by this invention. The perspective view which shows the state which the chip | tip support process in the processing method of the wafer by this invention was implemented, and the each divided | segmented chip | tip was arrange | positioned in the support member spaced apart mutually. Sectional drawing of the plasma etching apparatus for implementing the deteriorated layer removal process in the processing method of the wafer by this invention. Sectional drawing which shows the state which mounted the supporting member by which the chip | tip was arrange | positioned on the workpiece holding part which comprises the lower electrode of the plasma etching apparatus shown in FIG. Explanatory drawing of a three-point bending test. The figure which shows the bending strength of the chip | tip divided | segmented by the processing method of the wafer by this invention. The principal part sectional view of the plasma etching apparatus which performs plasma etching in the state where the space was provided between the chips. FIG. 18 is an explanatory diagram showing a state in which a tape expansion process is performed in the wafer processing method according to the present invention in the plasma etching apparatus shown in FIG. 17.

Explanation of symbols

2: Semiconductor wafer 21: Planned division line 22: Circuit 210: Alteration layer 220: Semiconductor chip 3: Annular frame 30: Dicing tape 4: Polishing device 41: Chuck table of polishing device 43: Polishing tool 5: Laser processing device 51 : Laser processing apparatus chuck table 51: Laser beam irradiation means 53: Imaging means 6: Dividing apparatus 61: Frame holding means 62: Tape expansion means 63: Support means 7: Support member 8: Plasma etching apparatus 81: Housing 82: Gate 83 : Gate operation means 84: Discharge means 85: Lower electrode 86: Upper electrode 88: High frequency power supply 89: Suction means 90: Refrigerant supply means 92: Lifting drive means 93: Gas supply means 94: Control means

Claims (7)

A wafer processing method for dividing a wafer in which a functional element is disposed in a region partitioned by a planned division line formed in a lattice shape on a surface, along the planned division line,
A deteriorated layer forming step of irradiating the wafer with a pulsed laser beam having transparency to the dividing line and forming a deteriorated layer along the dividing line inside the wafer;
A dividing step of applying an external force along the planned division line on which the altered layer is formed, and dividing the wafer into individual chips along the planned division line;
A chip support step in which the individually divided chips are arranged on the support member with the back side up and spaced apart from each other;
An altered region removing step of removing the altered layer remaining on the side surface of the chip disposed at a distance from the support member,
A method for processing a wafer.   2. The wafer dividing method according to claim 1, wherein the deteriorated layer removing step is performed by etching.   3. The wafer dividing method according to claim 2, wherein the etching in the deteriorated layer removing step is performed by plasma etching. A wafer processing method for dividing a wafer in which a functional element is disposed in a region partitioned by a planned division line formed in a lattice shape on a surface, along the planned division line,
A deteriorated layer forming step of irradiating the wafer with a pulsed laser beam having transparency to the dividing line and forming a deteriorated layer along the dividing line inside the wafer;
A tape adhering step for adhering the surface of the wafer to the holding tape before or after performing the deteriorated layer forming step;
A dividing step of applying an external force along the planned dividing line on which the altered layer of the wafer mounted on the holding tape is formed, and dividing the wafer into individual chips along the planned dividing line;
A tape expansion step of expanding a holding tape to which a wafer divided into individual chips is attached to form a gap between the chips;
An altered layer removing step of removing the altered layer remaining on the side surface of the chip in a state where the holding tape is expanded and a gap is formed between the chips,
A method for processing a wafer.   The wafer dividing method according to claim 4, wherein the deteriorated layer removing step is performed by etching.   6. The wafer dividing method according to claim 5, wherein the etching in the deteriorated layer removing step is performed by plasma etching.   The wafer dividing method according to claim 4, wherein the dividing step is performed by expanding a holding tape in the expanding step.

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