JP2005252192A - Method for manufacturing complementary semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a complementary semiconductor device which does not cause the depletion of a gate electrode and the deterioration of a gate insulating film. <P>SOLUTION: Polysilicon gate electrodes 17 composed of polysilicon containing phosphor or arsenic are formed on gate insulating films 14 of a p-type well 12 and n-type well 13 of a silicon substrate 10, respectively. After side walls 20 are formed on side walls of the gate electrode 17, source/drain regions 21, 22 are formed by impurity implantation and heat treatment with the side wall 20 and gate electrode 17 as masks. A Ni film 23 is formed on the whole surface of the substrate 10, and NiSi layers 24, 25 are formed on the source/drain regions 21, 22 by carrying out heat treatment and the whole polysilicon gate electrode is transformed into silicified NiSi gate electrodes 26, 27. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a complementary semiconductor device, and more particularly to a method for manufacturing a complementary field effect transistor having a salicide structure.

In a conventional semiconductor device, a gate insulating film made of a silicon oxide film (SiO ₂ film) and a gate electrode made of a polysilicon film (hereinafter referred to as “polysilicon gate electrode”) have been used.
In order to improve the performance of a semiconductor device such as a MOS transistor, the SiO ₂ film, which is a gate insulating film, is thinned, or a high dielectric constant film (also referred to as “High-k film”) is used as the gate insulating film. It is necessary to use it.
However, when a polysilicon gate electrode is used, there is a problem of depletion of the gate electrode, and this problem becomes more serious when the gate insulating film is thinned. In particular, this depletion problem is serious in PMOS transistors. This is because the polysilicon gate electrode of the PMOS transistor is doped with boron, but the doped boron is not sufficiently activated.

As a countermeasure against the depletion, a metal gate structure has been proposed. However, during RTA (Rapid Thermal Annealing) for forming source / drain regions, there is a problem that mutual diffusion occurs between the metal of the gate electrode and the gate insulating film, and the gate insulating film is deteriorated.
Therefore, a method of siliciding polysilicon after RTA has been proposed (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 11-284179 (page 5-6, FIG. 1-5)

  However, when the above method is applied to the manufacture of a complementary semiconductor device such as a complementary MOS transistor (CMOS transistor), there is a problem that the entire gate electrode cannot be silicided in both NMOS and PMOS transistors. This is because the entire gate electrode of the PMOS cannot be silicided.

  Further, in order to silicide the entire gate electrode, the thickness of the gate electrode has to be reduced, and there is a problem that a desired gate electrode shape cannot be obtained.

  The present invention has been made to solve the above-described conventional problems, and an object of the present invention is to provide a method for manufacturing a complementary semiconductor device that does not cause depletion of a gate electrode and deterioration of a gate insulating film.

A method for manufacturing a complementary semiconductor device according to the present invention includes a step of forming a p-type well and an n-type well in an upper layer of a semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode made of polysilicon containing an n-type impurity on each of the gate insulating films on the p-type well and the n-type well;
Forming a sidewall on the sidewall of the gate electrode;
Using the gate electrode and the sidewall as a mask, an n-type impurity is implanted into the p-type well, a p-type impurity is implanted into the n-type well, and then heat treatment is performed to form an n-type source / drain in the p-type well. Forming a region and forming a p-type source / drain region in the n-type well;
Forming a metal film on the entire surface of the semiconductor substrate after forming the n-type and p-type source / drain regions, and performing a heat treatment to silicidize the entire gate electrode. It is.

A method for manufacturing a complementary semiconductor device according to the present invention includes a step of forming a p-type well and an n-type well in an upper layer of a semiconductor substrate;
Forming a gate insulating film on the entire surface of the semiconductor substrate;
Forming gate electrodes made of polysilicon germanium containing an n-type impurity and having a Ge composition of 30% or less on the gate insulating film on the p-type well and the n-type well,
Forming a sidewall on the sidewall of the gate electrode;
Using the gate electrode and the sidewall as a mask, an n-type impurity is implanted into the p-type well, a p-type impurity is implanted into the n-type well, and then heat treatment is performed to form an n-type source / drain in the p-type well. Forming a region and forming a p-type source / drain region in the n-type well;
Forming a metal film on the entire surface of the semiconductor substrate after forming the n-type and p-type source / drain regions, and performing a heat treatment to silicidize the entire gate electrode. It is.

  In the complementary semiconductor device manufacturing method according to the present invention, it is preferable that the metal film is formed with a film thickness equal to or greater than ½ of the gate length of the gate electrode.

In the method for manufacturing a complementary semiconductor device according to the present invention, the step of forming the sidewall includes:
Forming an insulating film on the entire surface of the semiconductor substrate;
It is preferable to include a step of etching back the insulating film so that an upper portion of the side wall of the gate electrode is exposed by a length smaller than the thickness of the metal film.

  As described above, the present invention can provide a method for manufacturing a complementary semiconductor device that does not cause depletion of a gate electrode and deterioration of a gate insulating film.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof may be simplified or omitted.

1 to 3 are process cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
First, as shown in FIG. 1A, an element isolation 11 made of a silicon oxide film is formed in a silicon substrate 10 using an STI (Shallow Trench Isolation) method. The element isolation 11 defines an NMOS region (A) where an n-type channel MOS transistor is formed and a PMOS region (B) where a p-type channel MOS transistor is formed. Subsequently, a p-type well 12 as a p-type semiconductor region is formed in the NMOS region (A), and an n-type well 13 as an n-type semiconductor region is formed in the PMOS region (B). Thereafter, although not shown, impurities for adjusting the threshold voltage of the MOS transistor are implanted into the p-type well 12 and the n-type well 13, respectively.

Next, as shown in FIG. 1B, a gate insulating film 14 is formed on the entire surface of the substrate 10. As the gate insulating film 14, an SiO ₂ film formed by a thermal oxidation method or an SiON film formed by a thermal oxynitriding method (hereinafter referred to as “SiO ₂ film”) can be applied.
Further, a high dielectric constant film (high-k film) can be used as the gate insulating film 14 instead of the SiO ₂ film or the like. As the high dielectric constant film, a metal oxide film such as an HfO ₂ film or a ZrO ₂ film formed by MOCVD (Metal Organic Chemical Vapor Deposition) method using a material containing Hf (hafnium) or Zr (zirconium), Alternatively, a metal silicate film such as an HfSiO film or a ZrSiO film formed by MOCVD using a material in which Si is further added to the above material can be used. As other high dielectric constant films, a metal nitride film, a metal oxynitride film, or a metal aluminate film can be applied.
Further, a laminated film of a SiO ₂ film or the like and a high dielectric constant film can be applied as the gate insulating film 14. For example, the gate insulating film 14 can be a stacked film in which a SiO ₂ film having a thickness of 2 nm or less is formed in the lower layer and an HfO ₂ film, ZrO ₂ film, HfSiO film, or ZrSiO film is formed in the upper layer.

Next, a polysilicon film 15 as a gate electrode film is formed on the gate insulating film 14 by a low pressure chemical vapor deposition (LPCVD) method using SiH ₄ or SiD ₄ as a raw material, for example, with a film thickness of 50 nm to 200 nm. . Then, P (phosphorus) or As (arsenic) 16 which is an n-type impurity is contained in the polysilicon film 15 in the NMOS region (A) and the PMOS region (B) by an ion implantation method. Thereby, a gate electrode film containing an n-type impurity (P or As) is formed on the gate insulating film 14 in the NMOS region (A) and the PMOS region (B). Note that by adding PH ₃ or AsH ₃ to the raw material when forming the polysilicon film 15, an n-type impurity implantation step into the polysilicon film 15 becomes unnecessary, and the manufacturing process can be simplified.
Note that as the gate electrode film, a polysilicon germanium film can be used instead of the polysilicon film. In order to prevent deterioration of the depletion rate in the MOS transistor, the Ge (germanium) composition in the polysilicon germanium film is set to 30% or less. As a raw material for the polysilicon germanium film, SiH ₄ or SiD ₄ to which GeH ₄ is added may be used.

  Next, a resist pattern is formed on the polysilicon film containing n-type impurities, and the polysilicon film is anisotropically etched using the resist pattern as a mask. Thereby, as shown in FIG. 1C, a polysilicon gate electrode 17 containing an n-type impurity is formed in the NMOS region (A) and the PMOS region (B).

  Next, as shown in FIG. 2A, n-type impurities are implanted into the NMOS region (A) at a low concentration by ion implantation using the polysilicon gate electrode 17 as a mask, and the polysilicon gate is implanted into the PMOS region (B). A p-type impurity is implanted at a low concentration by ion implantation using the electrode 17 as a mask. As a result, an n-type extension region 18 is formed with the polysilicon gate electrode 17 in the NMOS region (A) interposed therebetween, and a p-type extension region 19 is formed with the polysilicon gate electrode 17 in the PMOS region (B) interposed therebetween.

Next, a silicon nitride film is formed on the entire surface of the substrate 10 so as to cover the polysilicon gate electrode 17, and the silicon nitride film is etched back until the upper portion of the polysilicon gate electrode 17 is exposed. Thereby, as shown in FIG. 2B, a sidewall 20 covering the side surface of the polysilicon gate electrode 17 is formed in a self-aligning manner. Here, the length 17a of the exposed side wall of the polysilicon gate electrode 17, that is, the length from the upper end of the side wall 20 to the upper surface of the polysilicon gate electrode 17, is a film thickness 23a of a metal film 23 described later (see FIG. 3A). ).
The patterning of the gate insulating film 14 can be performed by etching back for forming the sidewalls 20 and can be performed by anisotropic etching using the sidewalls 20 as a mask after the sidewalls 20 are formed.

  Next, as shown in FIG. 2C, n-type impurities are implanted into the NMOS region (A) at a high concentration by ion implantation using the gate electrode 17 and the sidewall 20 as a mask, and the gate is formed in the PMOS region (B). A p-type impurity is implanted at a high concentration by ion implantation using the electrode 17 and the sidewall 20 as a mask. Thereafter, the implanted impurities are activated by RTA (Rapid Thermal Annealing) at a temperature of about 1000 ° C. As a result, an n-type source / drain region 21 connected to the n-type extension region 18 in the NMOS region (A) is formed, and a p-type source / drain region 22 connected to the p-type extension region 19 in the PMOS region (B) is formed. It is formed.

Next, as shown in FIG. 3A, a Ni (nickel) film as a metal film 23 is deposited on the entire surface of the substrate 10 by sputtering. Here, the Ni film 23 is formed so that the film thickness 23a of the Ni film 23 becomes 1/2 or more of the gate length 17b of the gate electrode 17 and is thicker than the length 17a of the exposed polysilicon gate electrode 17 side wall. To do. For example, the film thickness 23a of the Ni film 23 is 5 nm to 30 nm. As a result, an amount of Ni film required for silicidation described later can be deposited with good coverage. As the metal film 23, a Co (cobalt) film, a TiN (titanium nitride) film / Ni film laminated film, or a TiN film / Co film laminated film can be used instead of the Ni film.
Then, annealing is performed in a nitrogen atmosphere at a temperature of 400 to 550 ° C. for several seconds to several tens of minutes. As a result, the Ni film 23 reacts with the silicon of the substrate 10 to form NiSi (nickel silicide) layers 24 and 25 on the source / drain regions 21 and 22. At the same time, the Ni film 23 deposited not only on the gate electrode 17 but also on the sidewall 20 reacts with the polysilicon of the gate electrode 17 to form NiSi gate electrodes 26 and 27 made of NiSi (nickel silicide). Here, the polysilicon gate electrode 17 that reacts with the Ni film 23 in the NMOS region (A) and the PMOS region (B) contains an n-type impurity (P or As), and the n-type impurity is a movable atom of Ni. As a big effect. That is, Ni (23) can be diffused throughout the polysilicon of the gate electrode 17 by the action of the n-type impurity, and the entire polysilicon gate electrode 17 can be silicided. As described above, when a polysilicon germanium electrode is formed instead of the polysilicon gate electrode, a NiSi _x Ge _(1-x) gate electrode is formed by silicidation.
Thereafter, the unreacted Ni film is removed with sulfuric acid / hydrogen peroxide (liquid obtained by adding hydrogen peroxide to sulfuric acid) or the like. As a result, as shown in FIG. 3B, a complementary MOS transistor having a salicide structure is formed.

  Next, as shown in FIG. 3C, a silicon oxide film as an interlayer insulating film 28 is formed on the entire surface of the substrate 10 so as to cover the gate electrodes 26 and 27. Then, tungsten plugs 29 and 30 connected to the NiSi layers 24 and 25 above the source / drain regions 21 and 22 are formed in the interlayer insulating film 28, and tungsten plugs (not shown) connected to the gate electrodes 26 and 27 are formed. ). Further, wirings 31 and 32 are formed on the tungsten plugs 29 and 30.

As described above, in the present embodiment, the polysilicon gate electrode 17 containing n-type impurities is formed in the NMOS region and the PMOS region, and the entire polysilicon gate electrode 17 is silicided. Since the n-type impurity in the gate electrode 17 acts as a movable atom of Ni, the entire polysilicon gate electrode 17 in the NMOS region and the PMOS region can be silicided. Therefore, occurrence of depletion of the gate electrode can be prevented.
Further, in this embodiment mode, silicidation is performed at a low temperature after the source / drain regions are formed, so that an interface reaction between the metal and the gate insulating film does not occur, and deterioration of the gate insulating film can be prevented.
Therefore, it is possible to provide a method for manufacturing a complementary semiconductor device that does not cause depletion of the gate electrode and deterioration of the gate insulating film.

  Further, in this embodiment, since the entire gate electrode can be silicided without reducing the thickness of the gate electrode, a complementary semiconductor device having a desired gate electrode shape can be manufactured.

It is process sectional drawing for demonstrating the manufacturing method of the complementary semiconductor device by embodiment of this invention (the 1). It is process sectional drawing for demonstrating the manufacturing method of the complementary semiconductor device by embodiment of this invention (the 2). It is process sectional drawing for demonstrating the manufacturing method of the complementary semiconductor device by embodiment of this invention (the 3).

Explanation of symbols

10 Substrate (silicon substrate)
11 element isolation 12 p-type well 13 n-type well 14 gate insulating film 15 polysilicon film 16 n-type impurity (P, As)
17 Polysilicon gate electrode 18 n-type extension region 19 p-type extension region 20 sidewall 21 n-type source / drain region 22 p-type source / drain region 23 Metal film (Ni film)
24, 25 NiSi layer 26 NiSi gate electrode 27 NiSi gate electrode 28 Interlayer insulating film 29, 30 Tungsten plug 31, 32 Wiring

Claims (4)

Forming a p-type well and an n-type well in an upper layer of the semiconductor substrate;
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode made of polysilicon containing an n-type impurity on each of the gate insulating films on the p-type well and the n-type well;
Forming a sidewall on the sidewall of the gate electrode;
Using the gate electrode and the sidewall as a mask, an n-type impurity is implanted into the p-type well, a p-type impurity is implanted into the n-type well, and then heat treatment is performed to form an n-type source / drain in the p-type well. Forming a region and forming a p-type source / drain region in the n-type well;
Forming a metal film on the entire surface of the semiconductor substrate after forming the n-type and p-type source / drain regions, and performing a heat treatment to silicidize the entire gate electrode. Type semiconductor device manufacturing method. Forming a p-type well and an n-type well in an upper layer of the semiconductor substrate;
Forming a gate insulating film on the entire surface of the semiconductor substrate;
Forming gate electrodes made of polysilicon germanium containing an n-type impurity and having a Ge composition of 30% or less on the gate insulating film on the p-type well and the n-type well,
Forming a sidewall on the sidewall of the gate electrode;
Using the gate electrode and the sidewall as a mask, an n-type impurity is implanted into the p-type well, a p-type impurity is implanted into the n-type well, and then heat treatment is performed to form an n-type source / drain in the p-type well. Forming a region and forming a p-type source / drain region in the n-type well;
Forming a metal film on the entire surface of the semiconductor substrate after forming the n-type and p-type source / drain regions, and performing a heat treatment to silicidize the entire gate electrode. Type semiconductor device manufacturing method. The method of manufacturing a complementary semiconductor device according to claim 1 or 2,
A method of manufacturing a complementary semiconductor device, wherein the metal film is formed with a film thickness of ½ or more of a gate length of the gate electrode. In the manufacturing method of the complementary semiconductor device according to any one of claims 1 to 3,
The step of forming the sidewall includes
Forming an insulating film on the entire surface of the semiconductor substrate;
And a step of etching back the insulating film so that an upper portion of the side wall of the gate electrode is exposed by a length smaller than the thickness of the metal film.

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