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JP2005244093A - Method and subatrate for packaging electronic component - Google Patents

Method and subatrate for packaging electronic component Download PDF

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Publication number
JP2005244093A
JP2005244093A JP2004054674A JP2004054674A JP2005244093A JP 2005244093 A JP2005244093 A JP 2005244093A JP 2004054674 A JP2004054674 A JP 2004054674A JP 2004054674 A JP2004054674 A JP 2004054674A JP 2005244093 A JP2005244093 A JP 2005244093A
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Japan
Prior art keywords
electronic component
circuit board
bonding material
reinforcing resin
electrode
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2004054674A
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Japanese (ja)
Inventor
Hiroaki Onishi
浩昭 大西
Masahito Mori
将人 森
Masato Hirano
正人 平野
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2004054674A priority Critical patent/JP2005244093A/en
Priority to US10/597,949 priority patent/US20070164079A1/en
Priority to PCT/JP2005/003043 priority patent/WO2005081602A1/en
Publication of JP2005244093A publication Critical patent/JP2005244093A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for packaging an electronic component capable of packaging a highly reliable bonding without decreasing a productivity and a packaging quality even for a micro and narrow pitch of the electronic component. <P>SOLUTION: The method for packaging the elctronic component comprises the steps of printing cream solders 4, 5 on a circuit board 1 with the use of a mask having the predetermined opening part, suppressing a mobility of the cream solder so as to keep the printed shape of the printing cream solders 4, 5, applying a reinforcing thermosetting resin 10 on the circuit board 1 including cream solders 14, 15 with their mobility suppressed, mounting the electronic components 6, 7 to the predetermined position of the circuit board 1, soldering electrode lands 2, 3 and the electrodes 6a, 7a of the electronic components 6, 7 on the circuit board 1 and hardening the reinforcing resin 10 by heating. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、回路基板に形成された電極ランドと電子部品の電極とを半田等の接合材料にて接合する電子部品実装方法及び電子部品実装基板に関するものである。   The present invention relates to an electronic component mounting method and an electronic component mounting substrate in which an electrode land formed on a circuit board and an electrode of an electronic component are bonded with a bonding material such as solder.

従来、電子部品実装基板の製造において、部品の両端に電極を有するチップ部品や、半田等のボールが格子状に配列された電極を有するCSP(Chip Size Package)等のパッケージ部品等に代表される電子部品を、クリーム半田を用いて回路基板上に半田付けする実装方法が汎用されており、その実装工程は、クリーム半田印刷工程、電子部品装着工程、リフロー工程に大別される。   2. Description of the Related Art Conventionally, in the manufacture of an electronic component mounting substrate, a chip component having electrodes at both ends of the component, a package component such as a CSP (Chip Size Package) having electrodes in which balls such as solder are arranged in a lattice shape, and the like are represented. A mounting method for soldering an electronic component onto a circuit board using cream solder is widely used. The mounting process is roughly divided into a cream solder printing process, an electronic component mounting process, and a reflow process.

この実装工程を図2を参照して説明する。図2(a)において、21は回路基板、22はチップ部品26の電極が接合される電極ランド、23はCSP27の電極が接合される電極ランドである。以下では、チップ部品26とCSP27を電子部品26、27と総称することがある。   This mounting process will be described with reference to FIG. In FIG. 2A, 21 is a circuit board, 22 is an electrode land to which the electrode of the chip component 26 is bonded, and 23 is an electrode land to which the electrode of the CSP 27 is bonded. Hereinafter, the chip component 26 and the CSP 27 may be collectively referred to as electronic components 26 and 27.

まず、クリーム半田印刷工程では、回路基板21を所望のパターン開口部が形成された金属製のマスク(図示せず)に位置決めして重ね合わせ、印刷用のスキージ(図示せず)をマスク上に適正な印圧で接触させた状態で印刷方向に沿って直線移動させ、クリーム半田をマスクの開口部に充填させた後、回路基板21をマスクから版離れさせることにより、図2(b)に示すように、マスクを介して回路基板21の電極ランド22、23上にクリーム半田24、25を印刷、塗布する。   First, in the cream solder printing process, the circuit board 21 is positioned and superimposed on a metal mask (not shown) in which a desired pattern opening is formed, and a printing squeegee (not shown) is placed on the mask. FIG. 2B shows the circuit board 21 separated from the mask by linearly moving along the printing direction in a state where it is in contact with an appropriate printing pressure, filling cream opening into the opening of the mask, and then separating the circuit board 21 from the mask. As shown, cream solders 24 and 25 are printed and applied onto the electrode lands 22 and 23 of the circuit board 21 through a mask.

次に、電子部品実装工程では、電子部品装着用ノズル(図示せず)により電子部品26、27を吸着して位置決めした後、図2(c)に示すように、電子部品26、27を回路基板21上に装着、搭載する。この際、チップ部品26の電極26aや、CSP27の電極27aは、電極ランド22、23に印刷されたクリーム半田24、25の上に載せられ、これらのクリーム半田24、25の粘着力により電子部品26、27が保持されて次の工程に進む。   Next, in the electronic component mounting process, after the electronic components 26 and 27 are attracted and positioned by an electronic component mounting nozzle (not shown), the electronic components 26 and 27 are arranged as shown in FIG. Attached and mounted on the substrate 21. At this time, the electrode 26 a of the chip component 26 and the electrode 27 a of the CSP 27 are placed on the cream solders 24 and 25 printed on the electrode lands 22 and 23, and an electronic component is obtained by the adhesive force of these cream solders 24 and 25. 26 and 27 are held and the process proceeds to the next step.

最後のリフロー工程では、熱風や赤外線ヒータ等の熱源(図示せず)により加熱して、印刷されたクリーム半田24、25を溶融し、図2(d)に示すように、回路基板21上に電子部品26、27を溶融して凝固した半田接合部28、29にて接合する。   In the final reflow process, heat is applied by a heat source (not shown) such as hot air or an infrared heater to melt the printed cream solders 24 and 25, and as shown in FIG. The electronic parts 26 and 27 are joined by solder joints 28 and 29 which are melted and solidified.

以上の工程で、回路基板21の電極ランド22、23と電子部品26、27の電極26a、27aとの半田付けが完了するが、近年はCSP等のパッケージ部品の小型・多ピン化によって電極の狭ピッチ化や微細化が進み、半田接合部28、29の接合強度が不足する等の接合信頼性が低下するという問題がある。そこで、CSP27と回路基板21の隙間にアンダーフィルと呼ばれる補強用の樹脂を充填・硬化する工程が別工程で追加される。このアンダーフィル充填工程では、図2(e)に示すように、半田接合部29にて接合されているCSP27と回路基板21との隙間に塗布装置(図示せず)等によりアンダーフィル30を塗布することにより毛細管現象で隙間に充填させる。   In the above process, the soldering of the electrode lands 22 and 23 of the circuit board 21 and the electrodes 26a and 27a of the electronic components 26 and 27 is completed. There is a problem that bonding reliability such as a decrease in the bonding strength of the solder joint portions 28 and 29 is lowered due to the progress of narrowing and miniaturization. Therefore, a process of filling and curing a reinforcing resin called underfill in the gap between the CSP 27 and the circuit board 21 is added as a separate process. In this underfill filling step, as shown in FIG. 2E, the underfill 30 is applied to the gap between the CSP 27 and the circuit board 21 joined by the solder joint portion 29 by a coating device (not shown) or the like. By doing so, the gap is filled by capillary action.

最後に、アンダーフィル硬化工程では、図2(f)に示すように、熱風や赤外線ヒータ等の熱源(図示せず)により加熱して、充填したアンダーフィル30を硬化させ、硬化したアンダーフィル31にてCSP27と回路基板21を接着する。以上の工程により電子部品実装基板が製造されていた。   Finally, in the underfill curing step, as shown in FIG. 2F, the filled underfill 30 is cured by heating with a heat source (not shown) such as hot air or an infrared heater, and the cured underfill 31 is cured. The CSP 27 and the circuit board 21 are bonded together. The electronic component mounting substrate has been manufactured through the above steps.

しかしながら、以上の電子部品実装方法では、回路基板の電極ランドと電子部品の電極との半田付け工程が完了した後に、別工程にてアンダーフィルの充填及び硬化が必要であり、製造工程が複雑になって製造コストが高くなることや生産性が低下するなどの問題がある。   However, in the above electronic component mounting method, after the soldering process of the electrode land of the circuit board and the electrode of the electronic component is completed, underfill filling and curing are required in a separate process, which complicates the manufacturing process. Thus, there are problems such as an increase in manufacturing cost and a decrease in productivity.

また、近年の電子機器の小型・高機能化に伴い、電子部品実装基板の小型・高密度化の要求から、CSP等のパッケージ部品の小型・多ピン化による電極の狭ピッチ化や微細化が益々進んでおり、最近では電極(ボール)ピッチが0.4mmのCSPが量産され始め、今後も狭ピッチ化が急速に進むと予測されている。しかるに、電極ピッチ0.5mmのCSPと、1.0×0.5mmや0.6×0.3mmのチップ部品などの従来サイズの電子部品の実装においては、回路基板上へのクリーム半田印刷は、通常0.10mm以上(0.10〜0.15mm程度)の均一厚の金属製マスクを用いており、すべての電子部品に対して印刷厚は一定であったが、電極ピッチが0.4mm以下のCSPになると、マスクの開口部の寸法が小さくなり、従来の0.10mm以上のマスク厚では、クリーム半田がマスクの開口部に詰まってしまい、印刷欠け等の印刷不良が発生する。これを回避するために、マスク厚を薄くすることが考えられるが、逆に従来サイズの電子部品のクリーム半田量が少なくなって実装後の半田接合強度が弱くなり、接合信頼性が低下する結果となってしまう。このように、CSPの電極の狭ピッチ化により、従来サイズの電子部品と狭ピッチの電子部品を同一の回路基板に一括で実装することができないという問題がある。   In addition, along with the recent downsizing and higher functionality of electronic devices, the demand for smaller and higher density electronic component mounting boards has led to the reduction in pitch and miniaturization of electrodes due to the downsizing and multi-pins of package components such as CSP. Recently, CSPs having an electrode (ball) pitch of 0.4 mm have begun to be mass-produced, and it is predicted that narrowing of the pitch will continue to proceed rapidly in the future. However, when mounting CSP with an electrode pitch of 0.5 mm and conventional size electronic components such as 1.0 × 0.5 mm or 0.6 × 0.3 mm chip components, cream solder printing on a circuit board is not possible. Usually, a metal mask with a uniform thickness of 0.10 mm or more (about 0.10 to 0.15 mm) is used, and the printing thickness is constant for all electronic components, but the electrode pitch is 0.4 mm. When the following CSP is used, the size of the opening of the mask is reduced. With the conventional mask thickness of 0.10 mm or more, cream solder is clogged in the opening of the mask, and printing defects such as printing defects occur. In order to avoid this, it is conceivable to reduce the mask thickness, but conversely, the amount of cream solder of the electronic components of the conventional size is reduced, the solder joint strength after mounting is weakened, and the joint reliability is lowered. End up. Thus, due to the narrow pitch of the CSP electrodes, there is a problem that the electronic components of the conventional size and the electronic components of the narrow pitch cannot be collectively mounted on the same circuit board.

このような問題を解決する手段として、ノーフローアンダーフィル実装方法が提案されている(例えば、特許文献1参照。)。ノーフローアンダーフィルは、フラックス成分を含んでいて半田付け時のフラックス作用を有するとともに、硬化することより上記アンダーフィルと同様の接合信頼性向上の作用を発揮する樹脂である。   As a means for solving such a problem, a no-flow underfill mounting method has been proposed (for example, see Patent Document 1). The no-flow underfill is a resin that contains a flux component, has a flux action during soldering, and exhibits the same effect of improving the joint reliability as the underfill by being cured.

このノーフローアンダーフィル実装方法の各工程について、図3を参照して説明する。図3(a)において、41は回路基板、42はチップ部品46の電極が接合される電極ランド、43はCSP47の電極が接合される電極ランドである。   Each step of the no-flow underfill mounting method will be described with reference to FIG. In FIG. 3A, 41 is a circuit board, 42 is an electrode land to which the electrode of the chip component 46 is bonded, and 43 is an electrode land to which the electrode of the CSP 47 is bonded.

まず、クリーム半田印刷工程では、所望のパターン開口部が形成された0.10mm以上の均一厚の金属製マスクを用いて、クリーム半田44を印刷、塗布する。ここで、狭ピッチCSP47が実装される電極ランド43に対応した部分にマスクの開口部を形成せずに、図3(b)に示すように、クリーム半田を狭ピッチCSP47が実装される電極ランド43には印刷を行わないようにする。これにより、従来の0.10mm以上のマスク厚における狭ピッチCSP部分での印刷欠け等の印刷不良を回避する。   First, in the cream solder printing step, the cream solder 44 is printed and applied using a metal mask having a uniform thickness of 0.10 mm or more in which a desired pattern opening is formed. Here, without forming the opening of the mask in the portion corresponding to the electrode land 43 on which the narrow pitch CSP 47 is mounted, as shown in FIG. 3B, the solder land is applied to the electrode land on which the narrow pitch CSP 47 is mounted. No printing is performed at 43. This avoids printing defects such as missing prints at a narrow pitch CSP portion in a conventional mask thickness of 0.10 mm or more.

次に、ノーフローアンダーフィル塗布工程では、図3(c)に示すように、狭ピッチCSP47用の電極ランド43上に塗布装置(図示せず)等により必要量のノーフローアンダーフィル50を予め塗布する。   Next, in the no-flow underfill coating process, as shown in FIG. 3C, a necessary amount of no-flow underfill 50 is previously applied on the electrode lands 43 for the narrow pitch CSP 47 by a coating device (not shown) or the like. Apply.

次に、電子部品装着工程では、電子部品装着用ノズル(図示せず)により電子部品46、47を順次吸着して位置決めした後、図3(d)に示すように、電子部品46、47を回路基板41上に装着、搭載する。この際、チップ部品46の電極46aや、狭ピッチCSP47の電極47aは、電極ランド42に印刷されたクリーム半田44上、及び電極ランド43に塗布されたノーフローアンダーフィル50上にそれぞれ載せられ、これらの粘着力により電子部品46、47が保持されて次の工程に進む。   Next, in the electronic component mounting step, after the electronic components 46 and 47 are sequentially sucked and positioned by an electronic component mounting nozzle (not shown), the electronic components 46 and 47 are moved as shown in FIG. Attached and mounted on the circuit board 41. At this time, the electrode 46 a of the chip component 46 and the electrode 47 a of the narrow pitch CSP 47 are respectively placed on the cream solder 44 printed on the electrode land 42 and on the no-flow underfill 50 applied to the electrode land 43. The electronic components 46 and 47 are held by these adhesive forces, and the process proceeds to the next step.

最後のリフロー工程では、図3(e)に示すように、熱風や赤外線ヒータ等の熱源(図示せず)により加熱して、回路基板41上に電子部品46、47を半田付けする。この際、チップ部品46の電極46aと電極ランド42は、クリーム半田44が溶融して半田48にて半田付けされ、狭ピッチCSP47の電極47aと電極ランド43は、半田ボールにて形成された電極47a自体が溶融した半田電極49にて半田付けされる。また、このリフロー工程においてノーフローアンダーフィル50も合わせて硬化し、硬化したノーフローアンダーフィル51にて狭ピッチCSP47と回路基板41が接着固定される。
特許第2589239号明細書
In the final reflow process, as shown in FIG. 3E, the electronic components 46 and 47 are soldered onto the circuit board 41 by heating with a heat source (not shown) such as hot air or an infrared heater. At this time, the electrodes 46a and the electrode lands 42 of the chip component 46 are melted and soldered by the solder solder 48, and the electrodes 47a and the electrode lands 43 of the narrow pitch CSP 47 are formed by solder balls. 47a itself is soldered by the molten solder electrode 49. In this reflow process, the no-flow underfill 50 is also cured and the narrow pitch CSP 47 and the circuit board 41 are bonded and fixed by the cured no-flow underfill 51.
Japanese Patent No. 2589239

しかしながら、上記ノーフローアンダーフィル実装方法では、以下のような問題を有していた。まず、ノーフローアンダーフィル実装方法では、狭ピッチCSP47が実装される電極ランド43にクリーム半田の印刷を行わないが、通常、CSPの電極(ボール)は高さばらつきを有しており、図3(d)に示すように、電極高さの低い電極Xの場合、狭ピッチCSP47を装着した後、電極Xに比べて電極高さの高い電極47aは電極ランド43と接触するが、電極Xは電極ランド43に届かず接触しない。このような状態でリフローを行うと、この電極高さばらつきを吸収することができずに、図3(e)にYで示すように、電極47aと電極ランド43が接合されず、未接合等の実装不良が発生するという問題がある。   However, the above no-flow underfill mounting method has the following problems. First, in the no-flow underfill mounting method, the solder lands are not printed on the electrode lands 43 on which the narrow pitch CSP 47 is mounted. Usually, however, the CSP electrodes (balls) have variations in height. As shown in (d), in the case of the electrode X having a low electrode height, the electrode 47a having a higher electrode height than the electrode X is in contact with the electrode land 43 after the narrow pitch CSP 47 is mounted. It does not reach the electrode land 43 and does not contact. If reflow is performed in such a state, this electrode height variation cannot be absorbed, and the electrode 47a and the electrode land 43 are not joined as shown by Y in FIG. There is a problem that mounting defects occur.

また、ノーフローアンダーフィル実装方法では、CSP47の電極47aと回路基板41の電極ランド43とを半田ボールにて形成された電極47a自体を溶融して半田付けするが、電極47aの半田量は非常に微量であり、半田付け後の接合強度は極めて低く、アンダーフィル51にて補強を行っても接合信頼性が確保できないという問題がある。   In the no-flow underfill mounting method, the electrode 47a of the CSP 47 and the electrode land 43 of the circuit board 41 are melted and soldered by the solder ball. However, the amount of solder of the electrode 47a is very large. The bonding strength after soldering is extremely low, and there is a problem that the bonding reliability cannot be ensured even if reinforcement is performed with the underfill 51.

さらに、CSP47の電極47aはリフロー工程の加熱により溶融する半田ボールで形成する必要があり、リフロー工程の加熱により溶融しない銅ボール、真鍮ボール、高温半田ボールなどにて電極47aが形成されたCSP47は実装することができないという問題がある。   Further, the electrode 47a of the CSP 47 must be formed of a solder ball that is melted by heating in the reflow process. The CSP 47 in which the electrode 47a is formed of a copper ball, a brass ball, a high temperature solder ball, or the like that is not melted by heating in the reflow process is used. There is a problem that it cannot be implemented.

本発明は、上記従来の問題点に鑑み、電子部品の微小・狭ピッチ化に対しても生産性、実装品質を低下させることなく、接合信頼性の高い実装が行える電子部品実装方法及び電子部品実装基板を提供することを目的とする。   In view of the above-described conventional problems, the present invention provides an electronic component mounting method and an electronic component that can be mounted with high bonding reliability without deteriorating productivity and mounting quality even when the electronic components are made minute and narrow in pitch. An object is to provide a mounting substrate.

本発明の電子部品実装方法は、所望の開口部を有するマスクを用いて接合材料を回路基板上に印刷する工程と、印刷された接合材料の印刷形状を保持するように接合材料の流動性を抑制する工程と、接合材料を含む回路基板上に熱硬化可能な補強樹脂を塗布する工程と、回路基板の所定の位置に電子部品を装着する工程と、加熱により回路基板上のランドと電子部品の電極の接合と補強樹脂の硬化を行う工程とを有するものである。   The electronic component mounting method of the present invention includes a step of printing a bonding material on a circuit board using a mask having a desired opening, and the flowability of the bonding material so as to maintain the printed shape of the printed bonding material. A step of applying, a step of applying a thermosetting reinforcing resin on a circuit board including a bonding material, a step of mounting an electronic component on a predetermined position of the circuit board, and a land and an electronic component on the circuit board by heating. The step of joining the electrodes and curing the reinforcing resin.

この構成によると、印刷した接合材料の流動性を抑制し、その接合材料を含む回路基板上に補強樹脂を塗布するので、補強樹脂の塗布時に接合材料の印刷形状が崩れず、その後電子部品を装着した後、加熱して接合を行うとともに補強樹脂を硬化させるので、実装工程が単純で生産性良く実装することができ、かつ電子部品の微小・狭ピッチ化により印刷マスクの厚さを薄くせざる得なくなって接合材料の量が少なくなっても、補強樹脂にて回路基板と電子部品が接着され、また上記のように接合材料の印刷形状が崩れず、また接合材料の厚みによって電極高さにばらつきを吸収することができるため、実装品質を低下させることなく、接合信頼性の高い実装が行うことができる。   According to this configuration, since the fluidity of the printed bonding material is suppressed and the reinforcing resin is applied onto the circuit board including the bonding material, the printed shape of the bonding material does not collapse when the reinforcing resin is applied, and then the electronic component is After mounting, it is heated and bonded, and the reinforcing resin is cured, so the mounting process is simple and can be mounted with good productivity, and the thickness of the printing mask is reduced by making the electronic parts minute and narrow pitch. Even if the amount of the bonding material becomes unavoidable, the circuit board and the electronic component are bonded with the reinforcing resin, and the printed shape of the bonding material does not break as described above, and the electrode height depends on the thickness of the bonding material. Therefore, mounting with high bonding reliability can be performed without deteriorating the mounting quality.

また、接合材料の流動性の抑制工程において、補強樹脂の塗布時には接合材料の印刷形状を保持するが、電子部品を装着する際の装着荷重によって変形するようにその流動性を制御すると、補強樹脂を塗布する際の補強樹脂の流動に伴って接合材料の印刷形状が崩れることがなく、かつ電子部品の装着荷重による接合材料の変形と補強樹脂の粘着力により装着された電子部品を保持でき、欠品等の実装不良の発生を防止できて好適である。   In addition, in the step of suppressing the fluidity of the bonding material, when the reinforcing resin is applied, the printed shape of the bonding material is maintained, but if the fluidity is controlled so as to be deformed by the mounting load when the electronic component is mounted, the reinforcing resin The printed shape of the bonding material does not collapse with the flow of the reinforcing resin when applying the coating, and the mounted electronic component can be held by the deformation of the bonding material due to the mounting load of the electronic component and the adhesive resin's adhesive force, This is preferable because it can prevent the occurrence of mounting defects such as missing parts.

また、接合材料の流動性の抑制工程において、接合材料を乾燥して接合材料中の溶剤などを揮発させるのが簡便で好適である。また、その際、回路基板上のほぼ全ての領域の接合材料、若しくは特定の領域の接合材料を選択的に乾燥することができる。また、乾燥は、熱風、ヒーター、マイクロ波、光による乾燥、若しくは真空乾燥によって行うのが好適である。   In the step of suppressing the fluidity of the bonding material, it is convenient and preferable to dry the bonding material and volatilize the solvent in the bonding material. At that time, it is possible to selectively dry the bonding material in almost all regions on the circuit board or the bonding material in a specific region. In addition, drying is preferably performed by hot air, a heater, microwaves, light drying, or vacuum drying.

また、補強樹脂は、回路基板上のほぼ全ての領域、若しくは特定の領域に選択的に塗布することができ、またフラックス作用を有するものを用い、電子部品と回路基板を接着する作用を有するものを用いるのが好適である。   In addition, the reinforcing resin can be selectively applied to almost all areas or specific areas on the circuit board, and has a function of adhering the electronic component and the circuit board by using one having a flux action. Is preferably used.

また、装着した電子部品は、装着荷重による接合材料の変形と補強樹脂の粘着力により保持するのが好適である。   The mounted electronic component is preferably held by deformation of the bonding material due to the mounting load and the adhesive force of the reinforcing resin.

また、本発明の電子回路基板は、以上の電子部品実装方法にて回路基板上に電子部品が実装されているものであり、上記効果を奏する電子回路基板を提供できる。   Moreover, the electronic circuit board of the present invention is such that an electronic component is mounted on the circuit board by the above-described electronic component mounting method, and an electronic circuit board having the above effects can be provided.

本発明の電子部品実装方法によれば、印刷した接合材料の流動性を抑制し、その接合材料を含む回路基板上に補強樹脂を塗布した後、電子部品を装着し、その後加熱して接合するとともに補強樹脂の硬化させるので、電子部品の微小・狭ピッチ化に対しても生産性、実装品質を低下させることなく、接合信頼性の高い実装が行うことができる。   According to the electronic component mounting method of the present invention, the fluidity of the printed bonding material is suppressed, and after applying the reinforcing resin on the circuit board including the bonding material, the electronic component is mounted, and then heated and bonded. At the same time, since the reinforcing resin is cured, mounting with high bonding reliability can be performed without degrading productivity and mounting quality even when the electronic parts are made minute and narrow in pitch.

以下、本発明の電子部品実装方法の一実施形態について、図1を参照して説明する。   Hereinafter, an embodiment of an electronic component mounting method of the present invention will be described with reference to FIG.

図1は、本実施形態の電子部品実装方法の工程図である。図1(a)において、1は回路基板、2はチップ部品6の電極が接合される電極ランド、3は狭ピッチCSP7の電極が接合される電極ランドである。本実施形態では、チップ部品6として1.0×0.5mmサイズのチップコンデンサを、狭ピッチCSP7として0.4mmピッチCSPの実装を行う。   FIG. 1 is a process diagram of the electronic component mounting method of the present embodiment. In FIG. 1A, 1 is a circuit board, 2 is an electrode land to which the electrodes of the chip component 6 are bonded, and 3 is an electrode land to which electrodes of a narrow pitch CSP 7 are bonded. In this embodiment, a chip capacitor having a size of 1.0 × 0.5 mm is mounted as the chip component 6 and a 0.4 mm pitch CSP is mounted as the narrow pitch CSP 7.

まず、接合材料としてのクリーム半田の印刷工程では、回路基板1を所望のパターン開口部が形成された金属製のマスク(図示せず)に位置決めして重ね合わせ、印刷用のスキージ(図示せず)をマスク上に適正な印圧で接触させた状態で印刷方向に沿って直線移動させ、クリーム半田をマスクの開口部に充填させた後、回路基板1をマスクから版離れさせることにより、図1(b)に示すように、マスクを介して回路基板1の電極ランド2、3上にクリーム半田4、5を印刷、塗布する。   First, in a printing process of cream solder as a bonding material, the circuit board 1 is positioned and overlapped with a metal mask (not shown) in which a desired pattern opening is formed, and a squeegee for printing (not shown). ) Is moved linearly along the printing direction in contact with the mask with an appropriate printing pressure, cream solder is filled in the opening of the mask, and then the circuit board 1 is separated from the mask. As shown in FIG. 1 (b), cream solders 4 and 5 are printed and applied onto the electrode lands 2 and 3 of the circuit board 1 through a mask.

ここで、マスク厚は、従来の0.10mm以上(通常0.10〜0.15mm)よりも薄くして、0.06〜0.08mmの厚みとした。このように狭ピッチCSP7が実装される電極ランド3に印刷可能な厚みの均一厚マスクを用いることで、従来サイズチップ部品6を含めたすべての電子部品が実装される電極ランド2、3に対してクリーム半田4、5の印刷を安定して行うことができる。   Here, the mask thickness was made thinner than the conventional 0.10 mm or more (usually 0.10 to 0.15 mm) to a thickness of 0.06 to 0.08 mm. In this way, by using a uniform thickness mask that can be printed on the electrode lands 3 on which the narrow pitch CSP 7 is mounted, the electrode lands 2 and 3 on which all electronic components including the conventional size chip component 6 are mounted are used. Thus, the cream solders 4 and 5 can be printed stably.

なお、本実施形態においては、マスク厚を0.06〜0.08mmとしたが、これに限定されるものではなく、狭ピッチの電子部品が実装される電極ランドに印刷可能な厚みであれば良い。   In the present embodiment, the mask thickness is set to 0.06 to 0.08 mm. However, the present invention is not limited to this, and any thickness that can be printed on an electrode land on which a narrow pitch electronic component is mounted. good.

次に、クリーム半田乾燥工程では、電極ランド2、3上にクリーム半田4、5が印刷された回路基板1をホットプレート(図示せず)上で加熱し、クリーム半田4、5中の溶剤等を揮発させて乾燥することで、図1(c)に示すように、流動性を抑制したクリー半田14、15の状態にする。乾燥は、120〜180℃の温度で20〜120秒間行う。流動性を抑制したクリーム半田14、15は、後工程の補強樹脂塗布工程及び電子部品装着工程において、補強樹脂を塗布する際の補強樹脂の流動に対してはクリーム半田の印刷形状を保持するが、電子部品を装着する際の装着荷重に対しては変形するようにその流動性が制御される。   Next, in the cream solder drying step, the circuit board 1 on which the cream solders 4 and 5 are printed on the electrode lands 2 and 3 is heated on a hot plate (not shown), and the solvent in the cream solders 4 and 5 and the like. As shown in FIG. 1C, the solder paste 14 and 15 with suppressed fluidity is obtained. Drying is performed at a temperature of 120 to 180 ° C. for 20 to 120 seconds. The cream solders 14 and 15 with suppressed fluidity retain the printed shape of the cream solder against the flow of the reinforcing resin when the reinforcing resin is applied in the reinforcing resin coating process and the electronic component mounting process in the subsequent process. The fluidity is controlled so as to be deformed with respect to the mounting load when mounting the electronic component.

なお、本実施形態では回路基板1の全体を加熱して回路基板1上のほぼ全ての領域のクリーム半田4、5を乾燥したが、これに限定されるものではなく、回路基板1上に装着される電子部品の内、1又は複数の特定の電子部品に対応した領域のクリーム半田4又は5を選択的に乾燥しても良い。   In the present embodiment, the entire circuit board 1 is heated to dry the cream solders 4 and 5 in almost all areas on the circuit board 1. However, the present invention is not limited to this and is mounted on the circuit board 1. Among the electronic components to be processed, the cream solder 4 or 5 in an area corresponding to one or more specific electronic components may be selectively dried.

また、乾燥する手段として本実施形態ではホットプレートを用いたが、これに限定されるものではなく、熱風、ヒーター、マイクロ波、光等による乾燥や、真空乾燥等を用いてクリーム半田4、5を乾燥しても良い。   In this embodiment, the hot plate is used as a means for drying. However, the present invention is not limited to this, and the cream solder 4, 5 is dried using hot air, a heater, microwaves, light, or the like, or vacuum drying. May be dried.

次に、補強樹脂塗布工程では、図1(d)に示すように、流動性を抑制したクリーム半田14、15を含む回路基板1の全面に塗布装置(図示せず)等により必要量の熱硬化可能な補強樹脂10を予め塗布する。補強樹脂10は、通常良く使用されているエポキシ系樹脂が好適に用いられる。流動性を抑制したクリーム半田14、15は補強樹脂10を塗布する際の補強樹脂10の流動によっても印刷形状が崩れることがないので、印刷形状を保持することができる。   Next, in the reinforcing resin coating process, as shown in FIG. 1 (d), a necessary amount of heat is applied to the entire surface of the circuit board 1 including the cream solders 14 and 15 with suppressed fluidity by a coating device (not shown). A curable reinforcing resin 10 is applied in advance. As the reinforcing resin 10, an epoxy resin that is usually used well is preferably used. The cream solders 14 and 15 with suppressed fluidity can maintain the printed shape because the printed shape is not destroyed by the flow of the reinforcing resin 10 when the reinforcing resin 10 is applied.

なお、本実施形態においては、回路基板1上のほぼ全ての領域に熱硬化可能な補強樹脂10を塗布したが、これに限定されるものではなく、乾燥工程と同様に、回路基板1上に装着される電子部品の内、1又は複数の特定の電子部品に対応した領域に選択的に塗布しても良く、その際前工程で選択的に乾燥した領域に合致した領域に塗布するのが好適である。   In the present embodiment, the thermosetting reinforcing resin 10 is applied to almost all regions on the circuit board 1, but the present invention is not limited to this. Of the electronic components to be mounted, it may be selectively applied to a region corresponding to one or a plurality of specific electronic components, and in this case, it is applied to a region that matches the region that has been selectively dried in the previous step. Is preferred.

なお、本実施形態では塗布装置を用いて塗布したが、これに限定されるものではなく、印刷装置やインクジェット装置等を用いても良く、回路基板1上に必要量の熱硬化可能な補強樹脂10を均一に供給できれば良い。   In this embodiment, application is performed using an application apparatus, but the present invention is not limited to this, and a printing apparatus, an inkjet apparatus, or the like may be used. 10 may be supplied uniformly.

次に、電子部品実装工程では、電子部品装着用ノズル(図示せず)によりチップ部品6、狭ピッチCSP7を順次吸着して位置決めした後、図1(e)に示すように、チップ部品6、狭ピッチCSP7を回路基板1上に装着、搭載する。この際、流動性を抑制したクリーム半田14、15は上述のようにこれらチップ部品6、狭ピッチCSP7を装着する際の装着荷重に対しては変形するようにその流動性が制御されており、装着後のチップ部品6の電極6a及び狭ピッチCSP7の電極7aは、流動性を抑制したクリーム半田14、15に突き刺さるような状態になり、流動性を抑制したクリーム半田14、15を介して電極ランド2、3に安定してつながっているので、狭ピッチCSP7の電極7aが電極高さのばらつきを有し、高さの低い電極Xを有していても、その高さばらつきを吸収して未接合等の実装不良の発生を防止することができる。   Next, in the electronic component mounting process, after the chip components 6 and the narrow pitch CSP 7 are sequentially sucked and positioned by an electronic component mounting nozzle (not shown), as shown in FIG. A narrow pitch CSP 7 is mounted and mounted on the circuit board 1. In this case, the fluidity of the cream solders 14 and 15 with suppressed fluidity is controlled so as to be deformed with respect to the mounting load when the chip component 6 and the narrow pitch CSP 7 are mounted as described above. After mounting, the electrode 6a of the chip component 6 and the electrode 7a of the narrow pitch CSP 7 are in a state of piercing the cream solders 14 and 15 with suppressed fluidity, and the electrodes are interposed via the cream solders 14 and 15 with suppressed fluidity. Since the electrodes 7a of the narrow pitch CSP 7 have variations in electrode height because they are stably connected to the lands 2 and 3, even if the electrodes X have a low height, the height variations are absorbed. Occurrence of mounting defects such as non-bonding can be prevented.

さらに、チップ部品6、狭ピッチCSP7を装着する際の装着荷重による流動性を抑制したクリーム半田14、15の変形と、熱硬化可能な補強樹脂10の粘着力により、装着されたチップ部品6、狭ピッチCSP7を保持することで、電極ランド3に印刷可能な厚みの薄いマスクを用いることでチップ部品6用のクリーム半田14の量が少なくなってもチップ部品6、狭ピッチCSP7の保持力が低下することがなく、確実に保持されて次の工程に進むため、欠品等の実装不良を防止することができる。   Further, the chip component 6 mounted due to the deformation of the cream solders 14 and 15 that suppresses the fluidity due to the mounting load when mounting the chip component 6 and the narrow pitch CSP 7 and the adhesive force of the thermosetting reinforcing resin 10. By holding the narrow pitch CSP 7, even if the amount of cream solder 14 for the chip component 6 is reduced by using a thin mask that can be printed on the electrode land 3, the holding force of the chip component 6 and the narrow pitch CSP 7 is maintained. Since it does not decrease and is reliably held and proceeds to the next step, it is possible to prevent mounting defects such as missing parts.

なお、本実施形態では特に装着荷重の制御は行わなかったが、装着荷重を制御して、任意の荷重で装着できるようにしても良く、これにより流動性を制御したクリーム半田14、15の変形量をコントロールし、チップ部品6及び狭ピッチCSP7の保持力の調整や、装着後の半田拡がり量の調整等を行い、欠品やショート等の実装不良を確実に防止することができる。   In this embodiment, the mounting load is not particularly controlled. However, the mounting load may be controlled so that the mounting can be performed with an arbitrary load, whereby the deformation of the cream solders 14 and 15 in which the fluidity is controlled. By controlling the amount and adjusting the holding force of the chip component 6 and the narrow pitch CSP 7 and adjusting the amount of solder spread after mounting, it is possible to reliably prevent mounting defects such as shortage and short circuit.

最後のリフロー工程では、熱風や赤外線ヒータ等の熱源(図示せず)により加熱してクリーム半田14、15を溶融し、図1(f)に示すように、溶融して凝固した半田にて回路基板1上にチップ部品6及び狭ピッチCSP7を半田付けし、半田接合部8、9を形成する。リフロー条件は、鉛フリー半田の標準的なプロファイルである、140〜180℃の温度で90〜120秒間プリヒートを行い、ピーク温度を240〜250℃にし、半田溶融温度の220℃を30秒以上確保するようにする。   In the final reflow process, the cream solders 14 and 15 are melted by heating with a heat source (not shown) such as hot air or an infrared heater, and the circuit is formed by the melted and solidified solder as shown in FIG. The chip components 6 and the narrow pitch CSP 7 are soldered on the substrate 1 to form solder joints 8 and 9. Reflow conditions are the standard profile of lead-free solder, preheating at a temperature of 140 to 180 ° C for 90 to 120 seconds, setting the peak temperature to 240 to 250 ° C, and ensuring the solder melting temperature of 220 ° C for 30 seconds or more. To do.

この際、チップ部品6の電極6aと電極ランド2は、クリーム半田14が溶融して半田付けされ、狭ピッチCSP7の電極7aと電極ランド3は、クリーム半田15及び半田ボールにて形成された電極7a自体が溶融して半田付けされる。また、合わせて補強樹脂10も硬化され、加熱硬化した補強樹脂11により回路基板1とチップ部品6及び狭ピッチCSP7が接着されて半田接合部8、9の補強が行われる。かくして、狭ピッチCSP7は、その電極7aの半田量にクリー半田5の半田量を加えた半田量にて半田付けを行うので、半田付け後の接合強度が向上し、かつ加熱硬化した補強樹脂11による半田接合部9の補強で、高い接合信頼性を確保することができる。   At this time, the electrodes 6a and the electrode lands 2 of the chip component 6 are soldered by melting the cream solder 14, and the electrodes 7a and the electrode lands 3 of the narrow pitch CSP 7 are formed by the cream solder 15 and the solder balls. 7a itself is melted and soldered. In addition, the reinforcing resin 10 is also cured, and the circuit board 1, the chip component 6, and the narrow pitch CSP 7 are bonded by the heat-cured reinforcing resin 11 to reinforce the solder joints 8 and 9. Thus, since the narrow pitch CSP 7 performs soldering with a solder amount obtained by adding the solder amount of the cream solder 5 to the solder amount of the electrode 7a, the bonding strength after soldering is improved and the reinforcing resin 11 is heat-cured. With the reinforcement of the solder joint portion 9, high joint reliability can be ensured.

また、加熱硬化した補強樹脂11により回路基板1とチップ部品6が接着されてその半田接合部8の補強が行われているので、狭ピッチCSP7が実装される電極ランド3に印刷可能な厚みの薄いマスクを用いることでチップ部品6用のクリーム半田量が少なくなっても、高い接合信頼性を確保することができる。   Further, since the circuit board 1 and the chip component 6 are bonded by the heat-cured reinforcing resin 11 and the solder joint portion 8 is reinforced, the printed land has a thickness that can be printed on the electrode land 3 on which the narrow pitch CSP 7 is mounted. Even when the amount of cream solder for the chip component 6 is reduced by using a thin mask, high bonding reliability can be ensured.

なお、本実施形態においては、回路基板1上のほぼすべての領域において加熱硬化した補強樹脂11により回路基板1と電子部品5、6が接着されているが、これに限定されるものではなく、前工程の塗布工程と合致した領域において選択的に加熱硬化した補強樹脂により回路基板1と電子部品5、6を接着しても良い。   In the present embodiment, the circuit board 1 and the electronic components 5 and 6 are bonded to each other by the reinforcing resin 11 that is heat-cured in almost all regions on the circuit board 1, but the present invention is not limited to this. The circuit board 1 and the electronic components 5 and 6 may be bonded to each other by a reinforcing resin that is selectively heat-cured in a region that matches the coating process of the previous process.

また、上記実施形態では狭ピッチCSP7の電極7aが半田ボールにて形成された例を示したが、リフロー工程の加熱により溶融するクリーム半田15にて半田付けを行うので、これに限定されるものではなく、リフロー工程の加熱により溶融しない銅ボールや真鍮ボール、高温半田ボール等で電極7aが形成された電子部品であっても良い。   In the above embodiment, the example in which the electrodes 7a of the narrow pitch CSP 7 are formed by solder balls is shown. However, the soldering is performed by the cream solder 15 that is melted by heating in the reflow process. Instead, it may be an electronic component in which the electrode 7a is formed of a copper ball, a brass ball, a high-temperature solder ball, or the like that is not melted by heating in the reflow process.

また、クリーム半田4、5のフラックスにより半田付けの際の電極や電極ランドの酸化物等の除去を行う例を示したが、これに限定されるものではなく、さらにフラックス作用を向上させるために熱硬化可能な補強樹脂がフラックス作用を有しても良い。   Moreover, although the example which removes the oxide of the electrode at the time of soldering, an electrode land, etc. with the flux of cream solder 4 and 5 was shown, it is not limited to this, In order to improve a flux effect | action further A thermosetting reinforcing resin may have a flux action.

本発明の電子部品実装方法は、印刷した接合材料の流動性を抑制し、その接合材料を含む回路基板上に補強樹脂を塗布した後、電子部品を装着し、その後加熱して接合を行うとともに補強樹脂の硬化させるため、電子部品の微小・狭ピッチ化に対しても生産性、実装品質を低下させることなく、接合信頼性の高い実装が行うことができ、回路基板の電極ランドと電子部品の電極をクリーム半田などの接合材料により接合する電子部品実装などに有用である。   The electronic component mounting method of the present invention suppresses the fluidity of a printed bonding material, and after applying a reinforcing resin on a circuit board including the bonding material, mounts the electronic component, and then heats and bonds the bonding material. Because the reinforced resin is cured, it is possible to perform mounting with high bonding reliability without degrading productivity and mounting quality even when the electronic components are made minute and narrow in pitch. Circuit board electrode lands and electronic components This is useful for electronic component mounting in which the electrodes are bonded by a bonding material such as cream solder.

本発明の一実施形態における電子部品実装方法の工程図である。It is process drawing of the electronic component mounting method in one Embodiment of this invention. 従来例のアンダーフィル実装方法の工程図である。It is process drawing of the underfill mounting method of a prior art example. 他の従来例のノーフローアンダーフィル実装方法の工程図である。It is process drawing of the no-flow underfill mounting method of another prior art example.

符号の説明Explanation of symbols

1 回路基板
2、3 電極ランド
4、5 クリーム半田(接合材料)
6 チップ部品(電子部品)
7 狭ピッチCSP(電子部品)
8、9 半田接合部
10 補強樹脂
11 加熱硬化した補強樹脂
14、15 流動性を抑制したクリーム半田(接合材料)
1 Circuit board 2, 3 Electrode land 4, 5 Cream solder (joining material)
6 Chip parts (electronic parts)
7 Narrow pitch CSP (electronic components)
8, 9 Solder joint 10 Reinforcement resin 11 Heat-cured reinforcement resin 14, 15 Cream solder with suppressed fluidity (joining material)

Claims (10)

所望の開口部を有するマスクを用いて接合材料を回路基板上に印刷する工程と、印刷された接合材料の印刷形状を保持するように接合材料の流動性を抑制する工程と、接合材料を含む回路基板上に熱硬化可能な補強樹脂を塗布する工程と、回路基板の所定の位置に電子部品を装着する工程と、加熱により回路基板上のランドと電子部品の電極の接合と補強樹脂の硬化を行う工程とを有することを特徴とする電子部品実装方法。   Including a step of printing a bonding material on a circuit board using a mask having a desired opening, a step of suppressing fluidity of the bonding material so as to maintain a printed shape of the printed bonding material, and a bonding material The step of applying a thermosetting reinforcing resin on the circuit board, the step of mounting the electronic component at a predetermined position on the circuit board, the bonding of the land and the electrode of the electronic component by heating, and the hardening of the reinforcing resin An electronic component mounting method comprising the steps of: 接合材料の流動性の抑制工程において、補強樹脂の塗布時には接合材料の印刷形状を保持するが、電子部品を装着する際の装着荷重によって変形するようにその流動性を制御することを特徴とする請求項1記載の電子部品実装方法。   In the step of suppressing the fluidity of the bonding material, the printed shape of the bonding material is maintained when the reinforcing resin is applied, but the fluidity is controlled so as to be deformed by the mounting load when mounting the electronic component. The electronic component mounting method according to claim 1. 接合材料の流動性の抑制工程において、接合材料を乾燥して接合材料中の溶剤などを揮発させることを特徴とする請求項1又は2記載の電子部品実装方法。   3. The electronic component mounting method according to claim 1, wherein in the step of suppressing the fluidity of the bonding material, the bonding material is dried to volatilize a solvent or the like in the bonding material. 回路基板上のほぼ全ての領域の接合材料、若しくは特定の領域の接合材料を選択的に乾燥することを特徴とする請求項3記載の電子部品実装方法。   4. The electronic component mounting method according to claim 3, wherein the bonding material in almost all regions on the circuit board or the bonding material in a specific region is selectively dried. 乾燥は、熱風、ヒーター、マイクロ波、光による乾燥、若しくは真空乾燥によって行うことを特徴とする請求項3又は4記載の電子部品実装方法。   5. The electronic component mounting method according to claim 3, wherein the drying is performed by hot air, a heater, microwaves, light drying, or vacuum drying. 補強樹脂を、回路基板上のほぼ全ての領域、若しくは特定の領域に選択的に塗布することを特徴とする請求項1〜5の何れかに記載の電子部品実装方法。   6. The electronic component mounting method according to claim 1, wherein the reinforcing resin is selectively applied to almost all areas or specific areas on the circuit board. フラックス作用を有する補強樹脂を用いることを特徴とする請求項1〜6の何れかに記載の電子部品実装方法。   The electronic component mounting method according to claim 1, wherein a reinforcing resin having a flux action is used. 電子部品と回路基板を接着する作用を有する補強樹脂を用いることを特徴とする請求項1〜7の何れかに記載の電子部品実装方法。   The electronic component mounting method according to claim 1, wherein a reinforcing resin having an action of bonding the electronic component and the circuit board is used. 装着した電子部品は、装着荷重による接合材料の変形と補強樹脂の粘着力により保持することを特徴とする請求項1〜8の何れかに記載の電子部品実装方法。   The electronic component mounting method according to claim 1, wherein the mounted electronic component is held by deformation of a bonding material due to a mounting load and an adhesive force of a reinforcing resin. 請求項1〜9の何れかの電子部品実装方法にて回路基板上に電子部品が実装されていることを特徴とする電子部品実装基板。   An electronic component mounting board, wherein an electronic component is mounted on a circuit board by the electronic component mounting method according to claim 1.
JP2004054674A 2004-02-24 2004-02-27 Method and subatrate for packaging electronic component Pending JP2005244093A (en)

Priority Applications (3)

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JP2004054674A JP2005244093A (en) 2004-02-27 2004-02-27 Method and subatrate for packaging electronic component
US10/597,949 US20070164079A1 (en) 2004-02-24 2005-02-24 Electronic component mounting method, and circuit substrate and circuit substrate unit used in the method
PCT/JP2005/003043 WO2005081602A1 (en) 2004-02-24 2005-02-24 Electronic component mounting method, and circuit board and circuit board unit used therein

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009236804A (en) * 2008-03-28 2009-10-15 Tdk Corp Angular velocity sensor element
CN112804832A (en) * 2020-12-31 2021-05-14 深圳市瑞丰光电子股份有限公司 Method for improving thrust of welding spot of module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009236804A (en) * 2008-03-28 2009-10-15 Tdk Corp Angular velocity sensor element
CN112804832A (en) * 2020-12-31 2021-05-14 深圳市瑞丰光电子股份有限公司 Method for improving thrust of welding spot of module

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