JP2005123861A - High frequency power amplifier circuit and electronic component for high frequency power amplification - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress variation in high frequency power amplification characteristics by automatically correcting shift of a bias point due to short channel effect of an FET or early effect of a bipolar transistor in a high frequency power amplifier circuit imparting a bias to an FET for amplification by current mirror system. <P>SOLUTION: The high frequency power amplifier circuit imparting a bias to an FET for amplification by current mirror system comprises a current simulation transistor (Q7) having a channel length or a base width identical to that of a transistor (Q0) for amplification and being fabricated by the identical process, and a bias generating circuit for comparing a voltage formed based on a current flowing through the transistor with a reference voltage generated by a current/voltage converting element (Q1) for converting the current from a constant current circuit into a voltage and imparting the transistor for amplification and the current simulation transistor with such a bias as suppressing variation in the idle current of the transistor for amplification due to short channel effect or early effect. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technology that is effective when applied to a high-frequency power amplifier circuit and a high-frequency power amplifier electronic component incorporating the high-frequency power amplifier circuit. The present invention relates to a technique for realizing the amplification characteristics.

  A high-frequency power amplifier circuit (generally a multi-stage circuit) using a semiconductor amplifier element such as a MOSFET (insulated gate field effect transistor) or a GaAs-MESFET in a transmission side output unit of a wireless communication device (mobile communication device) such as a cellular phone Built-in).

  This high-frequency power amplifier circuit generally includes a semiconductor chip including an amplifying transistor and its bias circuit, and other semiconductor chips and capacitors on an insulating substrate such as a ceramic substrate with printed wiring on the surface or inside. It is often configured as a single electronic component by being mounted together with discrete components and connected to each other by the printed wiring or bonding wires. This electronic component is called an RF power module.

  Incidentally, semiconductor chips used for RF power modules for mobile phones are being highly integrated in order to improve the performance and size of the modules. In recent years, from the viewpoint of stabilizing the high-frequency power amplification characteristics, as shown in FIG. 12, an amplifying FET Q0 and a biasing FET Q1 having a gate connected in common are provided, and a constant current source CI is used. A bias current Iin is generated by a current mirror circuit composed of FETs Q3 and Q4 for transferring current, and this bias current Iin is supplied to the biasing FET Q1 so as to bias the amplification FET Q0 in a current mirror manner. An invention relating to an RF power module in which a current lout corresponding to a ratio of gate widths is supplied has been proposed (for example, see Patent Document 1).

The RF power module that applies a bias to the amplifying FET Q0 by such a current mirror method does not change the idle current flowing through the amplifying FET Q0 even if the threshold voltage (Vth) of the FET varies, so that correction for element variations is unnecessary. There is an advantage that the yield is also improved. In this specification, a drain current that flows through an amplifying transistor when a bias is applied to the amplifying transistor by a current mirror method in a state where no high-frequency signal is input, that is, no signal is referred to as an idle current in this specification.
JP 2003-017954 A

  In order to improve the high frequency power amplification characteristics of the RF power module and achieve high integration, it is effective to shorten the channel length of the amplification FET. However, it is known that in the region where the channel length is short, the FET has a phenomenon that the threshold voltage Vth and the channel length modulation coefficient λ vary greatly due to slight variations in the channel length, as shown in FIG. Such a phenomenon is called a short channel effect.

  In an RF power module that applies a bias to an amplifying FET by a current mirror method, if the threshold voltage Vth of the FET or the channel length modulation coefficient λ varies, a desired current mirror ratio cannot be obtained, so the drain current of the amplifying FET ( (Idle current) is deviated from a desired value, and a desired high-frequency power amplification characteristic cannot be obtained, for example, a necessary output power is not generated, and power consumption increases. However, in the conventional current mirror type RF power module including the above-mentioned invention of the prior application, no consideration is given to the deviation of the bias point due to the short channel effect of the FET. For this reason, in an RF power module using an amplifying FET with a short channel length, the dispersion of high-frequency power amplification characteristics between the modules becomes too large to ignore unless correction measures are taken, and stable amplification characteristics cannot be obtained. There is a fear.

  It is also conceivable to correct the bias point shift due to the short channel effect of the FET by adjusting an external resistance element. In this case, however, a process for accurately measuring the characteristics of the FET and a process for adjusting the resistance element are required, resulting in an increase in cost. Moreover, in short-channel FETs, the channel modulation coefficient λ cannot be ignored even in the saturation region, and the power supply voltage varies slightly depending on the user system. Therefore, the bias point deviation is corrected by adjusting the external resistance element as described above. However, when the power supply voltage differs depending on the system used, it has become clear that there is a problem that an idle current of a desired magnitude cannot be flowed to the amplification FET due to the influence of λ.

  Further, a high frequency amplifier circuit using a bipolar transistor in place of the FETs Q0 and Q1 in the circuit of FIG. The use of a bipolar transistor can avoid problems due to the short channel effect, but the bipolar transistor does not have a short channel effect in the FET, but the collector-emitter voltage can be maintained even if the base-emitter voltage is kept constant. As the voltage increases, there is an Early effect that the effective base width decreases and the collector current increases.

  Therefore, in a high-frequency amplifier circuit using a bipolar transistor as an amplifying element, if the base thickness of the amplifying transistor is reduced in order to improve high-frequency power amplification characteristics, the element size (base thickness) will be reduced due to manufacturing variations. If it varies every time, the bias point of the base varies from chip to chip due to the Early effect, and the collector current (idle current) changes, which may make it impossible to stabilize the high-frequency power amplification characteristics.

  An object of the present invention is to automatically correct a bias point shift caused by a short channel effect or the like of a FET in a high frequency power amplifier circuit in which a bias is applied to an amplifying FET by a current mirror method. An object of the present invention is to reduce variations in high-frequency power amplification characteristics between chips.

  Another object of the present invention is to automatically correct a bias point shift due to the Early effect of the bipolar transistor in a high-frequency power amplifier circuit in which a bias is applied to the amplifying bipolar transistor by a current mirror method. An object is to reduce variation in amplification characteristics between power amplifier circuit chips.

  Still another object of the present invention is to provide a high-frequency power amplifier circuit with small variations in high-frequency power amplification characteristics and capable of being compact and highly integrated, and an electronic component for high-frequency power amplification (RF power module) incorporating this high-frequency power amplifier circuit Is to provide.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

The following is a brief description of an outline of typical inventions disclosed in the present application.
That is, the present invention relates to a current simulating transistor having the same channel length or base width as that of the amplifying transistor and formed by the same process in a high frequency power amplifying circuit for applying a bias to the amplifying transistor by a current mirror method. And a diode-connected transistor connected in series with the transistor, and a voltage formed based on a current flowing through the diode-connected transistor and a current from the constant current circuit are converted into a voltage. Bias generation that applies a bias to the amplifying transistor and the current simulating transistor so as to suppress a change in idle current of the amplifying transistor due to a short channel effect or an early effect by comparing with a reference voltage generated by the element A circuit is provided.

  More specifically, a current simulating transistor having the same channel length or base width as the amplifying transistor and formed by the same process, a diode-connected transistor connected in series with the transistor, and the transistor A current mirror-connected transistor, a first current-voltage conversion element connected in series with the transistor, a voltage generated by the first current-voltage conversion element, and a constant current from the constant current circuit as a voltage A bias generation circuit including a differential amplifier circuit that compares a reference voltage generated by a second current-voltage conversion element to be converted and outputs a voltage corresponding to a potential difference is provided, and the differential amplifier circuit includes the first The voltage generated by the current-voltage conversion element operates to match the reference voltage, and the output voltage of the differential amplifier circuit is changed to the amplification transistor. Configured to be applied to the control terminal of the motor.

  According to the above-described means, the amplification characteristics of the amplification transistor are automatically desired without measuring the characteristics of the amplification transistor or adjusting the resistance element even if the channel length or base width of the amplification transistor varies. It is possible to generate a bias voltage corrected so as to satisfy the above characteristics and supply it to the control terminal (gate terminal or base terminal) of the amplifying transistor.

  Here, the gate width or emitter size of the current simulating transistor is desirably smaller than the gate width or emitter size of the amplifying transistor. As a result, an increase in power consumption due to the provision of the simulation transistor can be suppressed.

  Preferably, the channel length or base width of the current simulating transistor Tr1 is set to Lg (Tr1) or Lb (Tr1), and the channel length or base width of the diode-connected transistor Tr2 in series with Tr1 is set to Lg (Tr2) or Lb. Further, when the current-voltage conversion element is formed of a diode-connected transistor, if the channel length of the transistor Tr3 is Lg (Tr3), then Lg (Tr3)> Lg (Tr1) or Lb ( Set so that Tr3)> Lb (Tr1). Further, Lg (Tr2) ≧ Lg (Tr3)> Lg (Tr1) or Lb (Tr2) ≧ Lb (Tr3)> Lb (Tr1) is set.

  As a result, a reference voltage that does not depend on variations in the channel length or base width of the amplification transistor can be generated as the reference voltage input to the differential amplifier circuit. A bias that suppresses changes due to the Early effect can be reliably applied to the amplifying transistor.

  Further, preferably, the final stage amplification transistor is connected to the gate terminal or the base terminal so that the same voltage as the voltage applied to the gate terminal or the base terminal is connected, and is proportional to the current flowing through the amplification transistor. A transistor for detecting output power is provided so that a current flows. As a result, by controlling the bias voltage by feeding back the current detected by the output power detection transistor to the bias circuit, it is possible to perform output power control with good linearity.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
In other words, according to the present invention, in the high-frequency power amplifier circuit, the bias point shift due to the short channel effect of the FET and the early effect of the bipolar transistor can be automatically corrected to reduce the variation in the high-frequency power amplification characteristics between chips. it can.

  In addition, according to the present invention, when a high-frequency power amplification circuit is actively used as an amplifying transistor of a high-frequency power amplifier circuit, a FET with a short channel length or a bipolar transistor with a thin base width is positively used to improve the high-frequency power amplification characteristic and reduce the size. In addition, there is an effect that variation in characteristics between modules can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic configuration of a first embodiment of a high-frequency power amplifier circuit according to the present invention. Although not particularly limited, for example, three high-frequency power amplifying circuits having the configuration as in the embodiment of FIG. 1 are connected in cascade and mounted on an insulating substrate such as ceramic together with an external resistor element and capacitor element. An RF power module is configured (see FIGS. 9 and 10). The cascade connection means a state in which the high-frequency output of the previous stage is connected so as to be input to the input terminal of the next stage. The high-frequency power amplifier circuit at each stage has the same configuration as that of FIG. 1, but the size (gate width) of the amplifying FET is different, and the first, second, and third stages are in this order. A large size is used. In the FET of this embodiment, the channel length is equal to the gate length, and the channel width is equal to the gate width.

  The high-frequency power amplifier circuit of this embodiment includes an amplifying FET Q0 connected between an output terminal (pad) P1 and a ground point GND, and a reference bias circuit 11 for generating a reference gate bias of the amplifying FET Q0. The current simulation circuit 12 for simulating the current Iout flowing through the amplification FET Q0, and the bias voltage generated by the reference bias circuit 11 based on the current detected by the current simulation circuit 12 is corrected to correct the amplification FET Q0. And a bias correction circuit 13 for correcting the bias state of the amplifying FET Q0.

  The amplification FET Q0 has a gate length Lg shorter than that of a normal FET (for example, Lg = 0.3 μm) in order to improve the high frequency power amplification characteristics. Since the output power of the RF power module as a whole becomes larger as the amplifier circuit in the subsequent stage, the gate width Wg of the amplifier FET Q0 in the first amplifier circuit is 2 mm, for example, and the gate of the amplifier FET Q0 in the amplifier circuit in the final stage The width Wg is 60 mm, and the gate width Wg of the amplifying FET Q0 of the second stage amplifier circuit is an intermediate value between 2 mm and 60 mm.

  The gate terminal of each amplification FET Q0 is connected to an external terminal (pad) P2 to which a high frequency signal RFin to be amplified is input, and the drain terminal of the amplification FET Q0 is connected to the output terminal P1. The output terminal P1 is connected to the power supply voltage terminal Vdd via an inductor L1 for blocking high frequency components and impedance matching, and connected to a high frequency input terminal (not shown) of the next stage amplifier circuit via a capacitor C1. Is done. Capacitors C1 and C2 connected to the external terminals P1 and P2 are capacitive elements that cut the DC component of the high-frequency signal. The capacitive elements C1 and C2 may be discrete components, but may be composed of a pair of conductive layers formed on the front and back surfaces of the dielectric layer constituting the module substrate. The inductor L1 can also be configured by a microstrip line formed on the module substrate.

  The reference bias circuit 11 includes a so-called diode-connected bias FET Q1 whose gate and drain are coupled, and a P-channel type connected in series with Q1 between the drain terminal of the bias FET Q1 and the power supply voltage terminal Vdd. Standard MOSFET Q4 and a P-channel standard MOSFET Q3 commonly connected to the gate of the MOSFET Q4. The MOSFET Q3 has a diode connection in which its gate and drain are coupled, whereby Q3 and Q4 are connected to each other. A current mirror circuit is configured. The biasing FET Q1 is an FET having the same symbol Q1 in which the gate terminal of the amplifying FET Q0 is connected to the gate terminal of the amplifying FET Q0 via the resistor R2 in the conventional current mirror type bias circuit shown in FIG. FET corresponding to.

  The drain terminal of the MOSFET Q3 is connected to a ground point via a resistance element R1 connected to the external terminal P3. By appropriately setting the resistance value of the resistance element R1, a current flowing through Q3 and Q1 can be set as desired. The value can be set. In this embodiment, a constant current circuit is constituted by the MOSFETs Q3 and Q4 and the resistor element R1. The FET Q1 is diode-connected to convert the current flowing through it into a voltage.

  Further, the FET Q1 is not particularly limited, but in this embodiment, it is formed by the same process as the amplifying FET Q0. As a result, the element size and thus the chip size can be reduced. Specifically, the standard MOSFETs Q3 and Q4 formed by a general CMOS process have a gate length of 2 μm, while the FET Q1 formed by a different process has a short length as shown in FIG. The gate length Lg is set to a value such as 0.5 μm so as not to cause a channel effect.

The current simulation circuit 12 includes a simulation FET Q7 formed by the same process as the amplification FET Q0 and having a gate length Lg of the same value as 0.3 μm, such as 0.3 μm, and a standard connected in series with the FET Q7. MOSFET Q6. In the FET Q7, the same voltage as that applied to the gate of the amplifying FET Q0 is applied to the gate so that the drain current of the amplifying FET Q0 can be simulated. However, since the current that flows through the amplifying FET Q0 is large, if the same current flows through the amplifying FET Q0 and the simulation FET Q7, the power consumption of the entire circuit increases, so the gate width Wg is Q7. Is set to be 1/10 to 1/100 of Q0. Specifically, for the amplification FET Q0 having a gate width of 2 mm to 60 mm, the gate width Wg of the simulation FET Q7 is about 80 μm at the first stage and about 160 μm at the second and third stages. .
The MOSFET Q6 connected in series with the simulation FET Q7 is a diode connection in which a gate and a drain are coupled, and converts a current into a voltage.

  The bias correction circuit 13 includes a MOSFET Q5 connected to the MOSFET Q6 of the current simulation circuit 12, a MOSFET Q5 connected in a current mirror, a diode-connected FET Q2 connected in series with the MOSFET Q5, a drain voltage of the FET Q2, and the reference bias. It comprises a differential amplifier AMP that compares the drain voltage of the FET Q1 of the circuit 11 and outputs a voltage corresponding to the potential difference. The output voltage of the differential amplifier AMP is supplied to the gate terminals of the amplification FET Q0 and the simulation FET Q7 via the resistors R2 to R4, and the current flowing through them is controlled. The resistors R2 to R4 and the capacitors C3 and C4 prevent the high frequency signal RFin input to the external terminal P2 from sneaking into the differential amplifier AMP and the simulation FET Q7, and preventing overshoot of the output of the differential amplifier AMP. Is provided to do.

  In this embodiment, the MOSFET Q5 of the bias correction circuit 13 has the same size as the MOSFET Q6 of the current simulation circuit 12, and a current Iret that is the same as the current Idet simulated by the simulation FET Q7 is supplied to Q5. The voltage is converted to Vret and input to the differential amplifier AMP. Since the simulation FET Q7 has the same characteristics as the amplification FET Q0, when the amplification FET Q0 has a short channel effect and its threshold value varies and the drain current deviates from a desired value, the drain of the simulation FET Q7 The current is shifted in the same way. It is converted to a voltage Vret by Q2 and input to the differential amplifier AMP, and compared with a reference voltage Vref from the reference bias circuit 11, and the voltage corresponding to the potential difference is the gate of the amplification FET Q0 and the simulation FET Q7. To be supplied. Q2 has the same characteristics and the same size as Q1. In this embodiment, the size ratio of Q5 and Q6 is 1: 1, but if the size ratio of Q0 and Q7 and the size ratio of Q5 and Q6 are set so that the currents Iret and Iin have the same order of current. Good.

  Since the differential amplifier AMP operates (imaginary short) so that the voltage at the non-inverting input terminal matches the voltage at the inverting input terminal, the voltage Vret at the non-inverting input terminal matches the reference voltage Vref at the inverting input terminal. As a result, a current shift due to the short channel effect of the simulation FET Q7 is corrected. Since the output of the differential amplifier AMP is also supplied to the amplifying FET Q0, the current deviation due to the short channel effect of the amplifying FET Q0 is also corrected at this time.

  In the present embodiment, the bias correction circuit 13 is provided with a current source CS1 that allows a minute current Ioff to flow toward the FET Q2. The current source CS1 prevents an unnecessary current from flowing through the amplifying FET Q0 due to the potential of the inverting input terminal of the differential amplifier AMP floating and an unstable voltage being output when the power is turned on. It is provided for this purpose. The current Ioff is set to a magnitude such as 10 μA that can be ignored as compared with the current Iret that flows through the FET Q2 during normal operation. The minute current Ioff may be configured to be turned off after the input current Iin is stabilized.

The operation of the high frequency power amplifier circuit of this embodiment will be described in detail below in comparison with the conventional current mirror bias type high frequency power amplifier circuit shown in FIG.
In the circuit of FIG. 12, when the gate length of the amplifying FET Q0 and the biasing FET Q1 is 0.4 μm or more which does not cause a short channel effect, the threshold value There is almost no deviation. In the state where the power supply voltage Vdd and the threshold voltage Vth1 are set so that the bias FET Q1 operates in the saturation region, the current Iin is supplied from the constant current circuit including Q3, Q4 and the resistor R1 to the bias FET Q1. When flowing, a voltage Vgs1 represented by the following equation is generated between the gate and source of Q1.
Iin = K1 (Vgs1-Vth1) ² (1)

K1 is a constant represented by K1 = K (Wg1 / Lg1) where K is the unit conductance coefficient of Q1, and Wg1 is the gate width of the bias FET Q1. Since this voltage Vgs1 is applied to the gate terminal of Q0 that forms a current mirror with Q1, a drain current (idle current) Iout as expressed by the following equation flows through the amplifying FET Q0.
Iout = K0 (Vgs0−Vth0) ² Equation (2)

Vgs0 is the gate-source voltage of the amplifying FET Q0, and Vth0 is the threshold voltage of Q0. Further, if the gate width of the amplifying FET Q0 is Wg0 and the gate length Lg0, it is a constant represented by K0 = K (Wg0 / Lg0). Here, when the amplification FET Q0 and the bias FET Q1 are elements having the same characteristics and the gate length is 0.4 μm or more which does not cause the short channel effect, in the above two equations, Vgs1 = Vgs0, Vth1 = Vth0. It can be said. Thus, between the current Iin of Q1 and the current Iout of Q0,
Iout = (Wg0 / Wg1) Iin (3)
The relationship expressed by That is, the ratio between the input current Iin and the output current Iout is determined by the gate width ratio Wg0 / Wg1 between Q0 and Q1.

However, in the circuit of FIG. 12, when the gate lengths of the amplifying FET Q0 and the biasing FET Q1 are 0.3 μm or less causing the short channel effect, the threshold voltage The channel modulation coefficient λ also varies. Therefore, if the drain-source voltage of the amplifying FET Q0 is Vds0 and the drain-source voltage of the biasing FET Q1 is Vds1, the current Iin of Q1 and the current Iout of Q0 are expressed by the following formula Iout = (Wg0 / Wg1) · {(1 + λVds0) / (1 + λVds1)} · Iin Equation (4)
The relationship is expressed as In equation (4), Vds1 = Vgs1, but Vds0 ≠ Vgs0. From this, it can be seen that the ratio between the input current Iin and the output current Iout depends not only on the gate width ratio Wg0 / Wg1 of Q0 and Q1, but also on the channel modulation coefficient λ.

On the other hand, in the high frequency power amplifier circuit of this embodiment, when a current Iin flows from the constant current circuit composed of Q3, Q4 and resistor R1 to the bias FET Q1, it is expressed by the following equation between the gate and source of Q1. Such a voltage Vref is generated.
Vref = √ (Iin / K1) + Vth1 Formula (5)

Further, the current Idet flowing through the FET Q7 that simulates the current Iout flowing through the Q0 by applying the same voltage to the gate with the same characteristics as the amplification FET Q0 is set such that the channel modulation coefficient of the Q0 and Q7 is λ.
Idet = (Wg7 / Wg0) · {(1 + λVds7) / (1 + λVds0)} · Iout (6)
It is represented by Here, since Vds7 = Vdd−Vgs6, the equation (6) is transformed into the following equation.
Idet = (Wg7 / Wg0) · {(1 + λ (Vdd−Vgs6)) / (1 + λVds0)} · Iout (7)

Here, assuming that Vdd is sufficiently larger than Vgs6, the above equation is
Idet = (Wg7 / Wg0) · {(1 + λVdd) / (1 + λVds0)} · Iout (8)
It becomes. Since this current Idet is transferred to the MOSFET Q5 by a current mirror and flows to the FET Q2, the current Iret flowing through Q2 becomes Iret = (Wg5 / Wg6) · Idet + Ioff, but Ioff can be ignored compared to Iret. Since it is so small, it can be considered that Iret = (Wg5 / Wg6) · Idet. At this time, if the power supply voltage Vdd is sufficiently large so that Q2 operates in the saturation region, Iret is caused to flow through Q2, and the drain terminal has Vret = √ (Iret / K2) + Vth2 (9)
A voltage Vret represented by Here, assuming that Q1 and Q2 are elements having the same characteristics, K2 = K1 and Vth2 = Vth1. Therefore, the equation (9) is expressed by the following equation: Vret = √ (Iret / K1) + Vth1
become that way.

In the high frequency power amplifier circuit of this embodiment, the voltage Vret generated at the drain of Q2 and the reference voltage Vref generated at the drain of the FET Q1 are input to the differential amplifier AMP so that Vret matches the reference voltage Vref. Feedback is required. Therefore, even if the gate lengths of Q0 and Q7 are short and the channel modulation coefficient λ varies due to the short channel effect and the current Iout of Q0 deviates from a desired value, the current Idet of Q7 deviates in the same way and is corrected. Such a voltage is applied from the differential amplifier AMP to the gates of the FETs Q0 and Q7. As a result, even if the amplification FET Q0 is shortened to improve amplification characteristics, an idle current Iout that does not depend on element variations can be supplied to Q0. Between the current Iout flowing through the amplification FET Q0 and the current Idet flowing through the simulation FET Q7 at that time, the following expression Idet / Iout = Wg7 / Wg0
Thus, a current corresponding to the gate width ratio Wg7 / Wg0 flows through Q0 and Q7.

  A voltage corresponding to the gate voltage Vref of the diode-connected FET Q1 through which the constant current Iin flows is applied to the gate terminal of the amplifying FET Q0, and the power supply voltage Vdd when Q3 and Q4 operate in the saturation region. Since Iin does not change even if changes, the idle current Iout that does not depend on the power supply voltage Vdd can be supplied to the amplifying FET Q0.

  Here, the characteristics and sizes of the elements in the high-frequency power amplifier circuit of this embodiment will be summarized. For FETs other than the FETs described below (FETs constituting Q3, Q4, Q5, Q6 and amplifier AMP), elements formed by a general CMOS process are used. Also, regarding the gate length, if a short channel effect occurs in these FETs Q3, Q4, Q5, Q6, etc., the target feedback control itself breaks down, so that it is 0.5 μm or more (2 μm in the embodiment). .

  In the high frequency power amplifier circuit of this embodiment, the simulation FET Q7 is provided for simulating the output current Iout of the amplification FET Q0. Therefore, the simulation FET Q7 is formed by the same process as Q0 and produces the same short channel effect as Q0. The gate length is also the same as Q0 (0.3 μm). The gate width of the FET Q7 is selected to be, for example, about several tens of micrometers or hundreds of micrometers depending on the gate width of the Q0 so that the current consumption becomes too large if the same as the Q0, so that a desired current value is obtained.

  Voltages Vref and Vret generated at the drains of the FETs Q1 and Q2 are used as differential inputs of the differential amplifier AMP, and a gate voltage Vgs0 for causing a desired output current Iout to flow through the amplifying FET Q0 with respect to Vref is generated. Therefore, Q1 and Q2 have gate lengths that do not cause a short channel effect, and the gate lengths of Q1 and Q2 need to be the same. As such a gate length, a value such as 0.5 μm is conceivable. The gate widths of Q1 and Q2 are determined in consideration of the controllability of the output current Iout. As such a gate width, a value such as 100 to 200 μm is conceivable.

  Further, in this embodiment, the FETs Q1 and Q2 are elements (power MOS) formed by the same process as the amplifying FET, but may be constituted by standard N-channel MOSFETs. However, when the standard N-channel MOSFET is used, the gate length is larger than that of the power MOS. Therefore, the gate width must be designed larger than that of the power MOS in order to pass a desired current. From the viewpoint of lowering power consumption and reducing the chip area, it is desirable to use a power MOS as in the embodiment.

  FIG. 2A shows the relationship between the input current Iin flowing through the FET Q1 and the output current Iout flowing through the amplifying FET Q0 in response to the input current Iin on the horizontal axis and the mirror ratio on the vertical axis. (Iout / Iin) is shown. In FIG. 2A, the thick line shows the relationship between Iin and Iout when the gate length Lg of Q1 and Q0 is 0.3 μm, and the thin line shows the relationship between Iin and Iout when the gate length Lg of Q1 and Q0 is 0.34 μm. Each relationship is shown. For comparison, in FIG. 2B, when the gate length Lg of Q1 and Q0 is shifted from 0.3 μm to 0.34 μm in the conventional high-frequency power amplifier circuit that applies the bias in the conventional current mirror system of FIG. Similarly, the relationship between Iin and Iout is shown with the input current Iin on the horizontal axis and the mirror ratio (Iout / Iin) on the vertical axis. In FIG. 2B, the thick line shows the relationship between Iin and Iout when the gate length Lg of Q1 and Q0 is 0.3 μm, and the thin line shows the relationship between Iin and Iout when the gate length Lg of Q1 and Q0 is 0.34 μm. Each relationship is shown.

  2A and 2B, in the conventional circuit, when the gate length Lg varies due to variations in the manufacturing process, the ratio of Iin to Iout (Iout / Iin) depends on the magnitude of Iin due to the short channel effect. However, in the high-frequency power amplifier circuit of this example, it can be seen that the relationship between Iin and Iout remains almost unchanged even when the gate length Lg varies due to variations in the manufacturing process. Further, in the region where the current Iin is 0.2 mA or more, the relationship between Iin and Iout is almost linear, and according to the circuit format of the embodiment of FIG. 1, Iout can be changed linearly by changing Iin. I understand. However, in the high frequency power amplifier circuit of the embodiment of FIG. 1, the external resistor R1 is adjusted so that the current Iin flowing through the FET Q1 falls within the range of 0.4 to 1 mA, and amplification is performed with Iout fixed. Be made to work.

  The high frequency power amplifier circuit of the embodiment of FIG. 1 is a bias-fixed high frequency power amplifier circuit that does not have a power control terminal. Therefore, for example, the power control is performed at the gate of the amplifier FET Q0 in a circuit preceding the external terminal P2. It is effective when used in a system in which the output power is controlled by a fixed bias / variable input system in which the amplitude of the high-frequency signal RFin input to the terminal is changed according to the output control voltage Vapc. As such a system, for example, there is a mobile phone capable of communication of Enhanced Data Rates for GSM Evolution (EDGE) method or Wide-band Code Division Multiple Access (WCDMA) method.

Next, a second embodiment of the high frequency power amplifier circuit according to the present invention will be described with reference to FIG.
A GSM (Global System for Mobile Communication) mobile phone is configured such that the output power of a high-frequency power amplifier circuit is controlled by an output control voltage Vapc. FIG. 3 shows an embodiment of a high-frequency power amplifier circuit in which output power control by such Vapc is enabled. The difference from the high frequency power amplifier circuit of the embodiment of FIG. 1 is that in the embodiment of FIG. 1, the current Iin flowing from the constant current circuit (Q3, Q4) constituting the reference bias circuit 11 to the FET Q1 is a predetermined current value (fixed). In this embodiment (FIG. 3), the reference bias circuit 11 changes the current Iin corresponding to the output control voltage Vapc to the FET Q1. This is in the point that the idle current Iout passed through the amplifying FET Q0 is changed by flowing it.

  Therefore, in this embodiment, the voltage-current conversion circuit 141 that converts the output control voltage Vapc input from the external terminal P4 into a current, and the current that flows through the FET Q1 according to the current from the voltage-current conversion circuit 141 A current control circuit 14 including a variable current source 142 that changes Iin is provided. FIG. 4 shows the input / output characteristics of the current control circuit 14, that is, the relationship between the output control voltage Vapc and the current Iin flowing through the FET Q0.

  As shown in FIG. 4, in this embodiment, the current Iin is increased almost linearly from a certain voltage (starting point) Vsp according to the output control voltage Vapc. The current control circuit 14 is configured such that the start point Vsp at which the current Iin begins to increase is determined by the resistance value of the external resistor R1.

  A circuit that outputs a current Iin that changes in characteristics as shown in FIG. 4A according to the output control voltage Vapc can be designed relatively easily by conventional techniques, and various circuit types are considered. Therefore, although a specific circuit example is not illustrated, for example, the output power control voltage Vapc is applied to the gate terminal between the FET Q3 of the reference bias generation circuit 11 and the external terminal P3. It is conceivable to provide an FET. When the current Iin changes with the characteristics shown in FIG. 4A in accordance with the output control voltage Vapc, in the high frequency power amplifier circuit of the present embodiment, the idle current Iout passed through the amplifying FET Q0 is the output power. Depending on the control voltage Vapc, the characteristics change as shown in FIG.

  In FIG. 14A, in the high frequency power amplifier circuit of this embodiment, the gate width Wg of the amplifying FET Q0 is set to 16 mm, and the power supply voltage Vdd is changed to 2.8V, 3.5V, and 4.8V. The result of having calculated | required the relationship between the output power control voltage Vapc and the idle current Iout in the case by simulation is shown. For comparison, FIG. 14B shows the output power control voltage Vapc and the idle current Iout when the power supply voltage Vdd is similarly changed in the high-frequency power amplifier circuit that applies a bias in the conventional current mirror system of FIG. The relationship is shown. From FIG. 14, it can be seen that in the conventional high frequency power amplifier circuit (FIG. 12), the idle current Iout has power supply voltage dependency, but the high frequency power amplifier circuit of this embodiment does not have power supply voltage dependency.

Next, a third embodiment of the high frequency power amplifier circuit according to the present invention will be described with reference to FIG.
In this embodiment, the high frequency power amplifier circuit of the embodiment of FIG. 3 is constituted by two semiconductor chips, and a detection circuit (current sense circuit) for detecting output power (power) is provided. The output power detection circuit in this embodiment includes a detection FET Q9 in which the same voltage as the voltage input to the gate terminal of the amplification FET Q0 is input to the gate terminal via the resistor R5, and the FET The current mirror circuit 15 transfers the drain current flowing through Q9, and an external resistor R6 converts the current transferred by the current mirror circuit 15 into a voltage.

  The output power detection FET Q9 is an element having the same gate length formed by the same process as the amplification FET Q0 and having a gate width smaller than Q0. A current that is reduced in proportion to the ratio of the gate width to the current is caused to flow through Q9. With respect to the output power detection circuit of such a current detection system, several patent applications have already been filed by the applicant and are not a main part of the present invention, so that the detailed operation will not be described.

  In this embodiment, an amplifying FET Q0, a simulation FET Q7, and an output power detecting FET Q9 are formed, and other FETs (FETs constituting Q1, Q2, Q5, Q6 and the current control circuit 14 and the amplifier AMP) are formed. The semiconductor chip 110 is formed on a separate semiconductor chip 120. Further, the FET constituting the current mirror circuit 15 for transferring the drain current flowing through the FET Q9 is formed on the semiconductor chip 110 together with the FETs Q1, Q2, etc. constituting the bias circuit.

  The reason why the external resistor element is used as the resistor R6 for converting the current transferred by the current mirror circuit 15 into a voltage is to improve the accuracy of the output voltage Vsns. The mirror ratio of the current mirror circuit 15 and the resistance value of the resistor R6 are such that a voltage matching the voltage of the output terminal P1 to which the drain terminal of the amplifying FET Q0 is connected appears at the external terminal P5 to which the resistor R6 is connected. Is set.

  The detection voltage Vsns converted by the resistor R6 is input to an error amplifier 16 to which an output level instruction signal Vramp supplied from a baseband circuit (not shown) or the like is input according to the distance from the base station or the like. The error amplifier 16 outputs a voltage corresponding to the potential difference between the detection voltage Vsns and the output level instruction signal Vramp, and this is supplied as an output control voltage Vapc to the external terminal P4 of the semiconductor chip 110 on the bias circuit side. As a result, a feedback control loop is formed to control the bias current of the amplifying FET Q0 so that the detection voltage Vsns matches the output level instruction signal Vramp so that the output power is changed according to the output level instruction signal Vramp. Operate.

  In this embodiment, the amplification FET Q0, the simulation FET Q7, and the output power detection FET Q9 made of power FETs are formed on separate semiconductor chips. Thus, the characteristics of each element can be optimized and the process can be simplified as compared with the case of forming on one semiconductor chip. Therefore, there is an advantage that the total chip cost can be reduced.

FIG. 6 shows a fourth embodiment of the high-frequency power amplifier circuit according to the present invention.
In this embodiment, the amplifying transistor Q0 and the simulating transistor Q7 of the high frequency power amplifier circuit of the embodiment of FIG. 1 are configured by bipolar transistors instead of FETs, and the entire circuit is the same as that of the embodiment of FIG. It is composed of two semiconductor chips.

  Bipolar transistors do not have the short channel effect as in FETs, but if a bipolar transistor with a thin base is used as the amplifying transistor Q0 in order to improve the high frequency power amplification characteristics, the base-emitter voltage is kept constant. Even if the voltage is kept, an early effect appears in which the effective base width decreases and the collector current increases as the collector-emitter voltage increases. For this reason, if the base thickness of the amplifying transistor Q0 varies from chip to chip due to manufacturing variations, the base bias point varies from chip to chip due to Early effects, and the high-frequency power amplification characteristics may not be stable. .

  Therefore, in this embodiment, as in the embodiment of FIG. 1, the reference bias circuit 11 that generates the reference voltage Vref in the diode-connected transistor Q1 and the proportional current having the same characteristics as the amplifying transistor Q0. The current simulation circuit 12 including the simulation transistor Q7 through which the current flows, and the detected current converted into a voltage and compared with the reference voltage Vref to correct a current shift caused by the variation in the base thickness of the amplification transistor Q0. And a correction circuit 13 for generating a correct bias voltage. As a result, even if a bipolar transistor is used as the amplifying transistor Q0 and the base thickness of the amplifying transistor Q0 is reduced in order to improve the high frequency power amplification characteristics, the variation of the base bias point caused by the Early effect is reduced, The stability of the high frequency power amplification characteristic can be improved.

  Also in this embodiment, since the amplifying transistor Q0 and the simulating transistor Q7 made of bipolar transistors are formed on the semiconductor chip 120 different from the semiconductor chip 110 on which the FETs Q1 to Q6 are formed, 2 By forming each semiconductor chip by a separate optimum process, the process can be simplified as compared to the case of forming on one semiconductor chip. Therefore, there is an advantage that the chip cost can be reduced. Note that the bipolar transistor used in this embodiment may be formed on a silicon chip, but it is desirable to use a heterojunction bipolar transistor with better amplification characteristics.

Next, a modification of the high frequency power amplifier circuit according to the present invention will be described.
FIG. 7 shows a first modification. In this modification, resistors R7 and R8 are used instead of diode-connected FETs as a current-voltage converting FET Q1 constituting the reference bias circuit 11 and a current-voltage converting FET Q2 constituting the bias correction circuit 13. Is used. Although the resistors R7 and R8 may be on-chip elements, it is desirable to provide the resistors R7 and R8 as external elements in order to compensate for variations in characteristics of the amplifying FET Q0 due to the manufacturing process. FIG. 7 shows the second embodiment of FIG. 3 in which FETs Q1 and Q2 are replaced with resistors R7 and R8. In the embodiments of FIGS. A modification in which Q2 is replaced with resistors R7 and R8 is also possible.

  FIG. 8 shows a second modification. In this modification, a current-voltage conversion FET Q1 constituting the reference bias circuit 11 and a current-voltage conversion FET Q2 constituting the bias correction circuit 13 are replaced with a PN junction diode D1 instead of a diode-connected FET. , D2 is used. In order to compensate for variations in characteristics of the amplifying FET Q0 due to the manufacturing process, the diodes D1 and D2 may be on-chip elements, but are desirably provided as external elements.

  FIG. 8 shows the second embodiment of FIG. 3 in which FETs Q1 and Q2 are replaced by diodes D1 and D2. In the embodiments of FIGS. A modification in which Q2 is replaced with diodes D1 and D2 is also possible.

  As described above, by using an external resistance element or diode element instead of a diode-connected FET as the current-voltage conversion element through which the currents Iref and Iret flow, the characteristics of the FETs Q0 and Q1 vary due to manufacturing variations. However, by selecting and connecting the resistor elements R7 and R8 having the optimum resistance value and the diode elements D1 and D2 having the optimum forward voltage value accordingly, the characteristic deviation can be reduced. .

  FIG. 9 shows a third modification. In this modification, a three-stage high frequency power amplifier circuit is formed as a semiconductor integrated circuit on one semiconductor chip. The output terminal P11 of the first amplification stage 10A is connected to the input terminal P22 of the second amplification stage 10B via the capacitor C11 and the impedance matching circuit MN1, and the output terminal P12 of the second amplification stage 10B is the capacity. It is connected to the input terminal P23 of the third amplification stage 10C via C12 and the impedance matching circuit MN2. The FET Q9 and the current mirror circuit 15 constituting the output power detection circuit are provided corresponding to the third amplification stage 10C.

  The semiconductor integrated circuit of this embodiment is mounted on an insulating substrate such as ceramic together with DC cut capacitors C2, C11 to C13 and external resistors R11 to R13, inductors L1 to L3, impedance matching circuits MN0 to MN4, etc. Configured as The inductors L1 to L3 and the impedance matching circuits MN0 to MN4 can be configured using microstrip lines formed on the substrate of the module. Capacitors C2, C11 to C13 may be discrete components, but when using a laminate of a plurality of dielectric layers as an insulating substrate of the module, the capacitors C2, C11 to C13 are formed so as to face the front and back of any one of the dielectric layers, respectively. It may be a capacitor having the formed conductor layer as an electrode. As an example, the amplification stage of FIG. 4 is used as the amplification stage, but the embodiment of FIG. 1 or the modification of FIG. 7 or FIG. 8 may be used.

  In the high frequency power amplifier circuit of this embodiment, the FETs constituting the first, second and third amplifier stages are formed on one semiconductor chip. There is an advantage that it can be miniaturized.

  FIG. 10 shows a fourth modification. In this modification, a three-stage high frequency power amplifier circuit is formed on two semiconductor chips 110 and 120 as a semiconductor integrated circuit. Specifically, the first amplification stage 10A and the second amplification stage 10B are formed on the first semiconductor chip 110, and the third amplification stage 10C and the FET Q9 constituting the output power detection circuit and The current mirror circuit 15 is formed on the second semiconductor chip 120. Other than that is the same as the modification of FIG.

  In the high-frequency power amplifier circuit of this embodiment, the FETs constituting the first and second amplification stages are formed on one semiconductor chip 110, so that the other embodiments except the embodiment of FIG. There is an advantage that the module can be reduced in size. 9 is inferior to the embodiment of FIG. 9 in terms of miniaturization, but in the embodiment of FIG. 10, the amplification FET Q0 is formed so as to have different characteristics in the first, second and third stages. As shown in FIG. 9, there is an advantage that an amplifier having a better amplification characteristic than the embodiment of FIG.

  FIG. 11 shows a fifth modification. In this modification, a three-stage high-frequency power amplifier circuit is formed as a semiconductor integrated circuit on three semiconductor chips. Specifically, the current control circuit 14 of each stage is formed on the first semiconductor chip 130 as a common current control circuit, and the first amplification stage 10A and the second amplification stage excluding the current control circuit 14 are formed. 10B is formed on the second semiconductor chip 110, and the third amplification stage 10C, the FET Q9 constituting the output power detection circuit, and the current mirror circuit 15 are formed on the third semiconductor chip 120. Other than that is the same as the modification of FIG.

  In the high-frequency power amplifier circuit of this embodiment, the current control circuit 14 of each stage is formed on the independent semiconductor chip 130 as a common current control circuit, so that an amplifier stage is configured as compared with the embodiment of FIG. There is an advantage that the second and third semiconductor chips 110 and 120 in which the FET is formed can be reduced in size.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

  For example, in the embodiment of FIG. 6, the amplifying FET Q0 and the simulation FET Q7 are composed of bipolar transistors, and the diode-connected transistors Q1 and Q2 of the reference bias circuit 11 and the bias correction circuit 13 are composed of FETs. However, Q1 and Q2 may also be composed of bipolar transistors. 5 and 9 to 11 are configured as a semiconductor integrated circuit including the output power detection circuit (Q9, 15), but configured as a high frequency power amplifier circuit not including the output power detection circuit. You may do it.

  Further, in the above-described embodiment, the case where the amplifying transistor Q0 is composed of an FET or a bipolar transistor has been described. Even in the case of other transistors such as Mobility Transistor), the same effect can be obtained by applying the above embodiment.

  In the above description, the case where the invention made mainly by the present inventor is applied to a high frequency power amplifier circuit and a power module used in a mobile phone which is a field of use behind the present invention has been described, but the present invention is not limited thereto. It can be used for a high-frequency power amplifier circuit and a power module that constitute a wireless LAN.

1 is a circuit configuration diagram showing a first embodiment of a high-frequency power amplifier circuit according to the present invention. It is a characteristic view which shows the relationship between the electric current Iin of the bias circuit in the high frequency power amplifier circuit of an Example (A) and the conventional (B), and the electric current Iout sent through the amplification FET Q0 according to it. It is a circuit block diagram which shows the 2nd Example of the high frequency power amplifier circuit which concerns on this invention. (A) is a characteristic diagram showing the relationship between the output power control voltage Vapc and the current Iin of the bias circuit in the high-frequency power amplifier circuit of the third embodiment, and (B) is a current flowing through the control voltage Vapc and the amplifying FET Q0. It is a characteristic view which shows the relationship with lout. It is a circuit block diagram which shows the 3rd Example of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows the 4th Example of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows the 1st modification of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows the 2nd modification of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows the 3rd modification of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows the 4th modification of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows the 5th modification of the high frequency power amplifier circuit which concerns on this invention. It is a circuit block diagram which shows an example of the conventional high frequency power amplifier circuit. It is a graph which shows the relationship between channel length when shortening the channel length of FET, threshold voltage Vth, and channel length modulation coefficient (lambda). (A) is a graph showing the relationship between the output power control voltage Vapc and the idle current Iout in the high frequency power amplifier circuit of this embodiment, and (B) is the output power control voltage Vapc and the idle in the conventional high frequency power amplifier circuit of FIG. It is a graph which shows the relationship with the electric current Iout.

Explanation of symbols

11 Reference bias circuit 12 Current simulation circuit 13 Bias correction circuit 14 Current control circuit Q0 Amplifying transistor (short channel power transistor)
Q1 Biasing transistor (normal power transistor)
Q2 FET for current-voltage conversion
Q3, Q4, Q5, Q6 Transistors composing the current mirror circuit (standard transistors)
Q7 Transistor for simulation (short channel power transistor)
R1 Adjustment resistor (external resistor)
P1 to P5 External terminal (pad)

Claims (10)

An amplifying transistor for amplifying a high-frequency signal; and a current-voltage conversion element that converts a current into a voltage when a predetermined current is passed, the voltage corresponding to the voltage generated by the current-voltage conversion element being In the high-frequency power amplifier circuit configured such that a current proportional to a current flowing through the current-voltage conversion element is applied by being applied to the control terminal of the amplifying transistor,
A current simulating transistor having the same channel length or base width as the amplifying transistor and formed by the same process; and a diode-connected transistor connected in series with the transistor; A comparison is made between the voltage formed based on the current flowing through the transistor and the reference voltage generated by the current-voltage conversion element that converts the current from the constant current circuit into a voltage, and the idle current of the amplifying transistor is a short channel. A high frequency power amplifier circuit comprising: a bias generating circuit that applies a bias that suppresses a change due to an effect or an Early effect to the amplifying transistor and the current simulating transistor. An amplifying transistor for amplifying a high-frequency signal; and a current-voltage conversion element that converts a current into a voltage when a predetermined current is passed, the voltage corresponding to the voltage generated by the current-voltage conversion element being In the high-frequency power amplifier circuit configured such that a current proportional to a current flowing through the current-voltage conversion element is applied by being applied to the control terminal of the amplifying transistor,
A current simulating transistor having the same channel length or base width as the amplifying transistor and formed in the same process, a diode-connected transistor connected in series with the transistor, and a current flowing through the diode-connected transistor A bias generation circuit including a differential amplifier circuit that compares a voltage formed based on a current and a reference voltage generated by the current-voltage conversion element and outputs a voltage corresponding to a potential difference;
The differential amplifier circuit operates so that a voltage formed based on a current flowing through the diode-connected transistor matches the reference voltage, and an output voltage of the differential amplifier circuit is a control terminal of the amplifier transistor A high frequency power amplifier circuit in which an idle current is applied to the amplifying transistor. The amplifying transistor and the current simulating transistor are configured by a field effect transistor having a channel length such that a threshold voltage and a channel length modulation coefficient change due to manufacturing variations.
The diode-connected transistor connected in series with the current simulating transistor is composed of a field effect transistor having a channel length that does not change a threshold voltage and a channel length modulation coefficient due to manufacturing variations. The high frequency power amplifier circuit according to claim 2.   4. The current-voltage conversion element is a diode-connected field effect transistor, and the transistor has a channel length larger than a channel length of the amplifying transistor. The high-frequency power amplifier circuit described.   The diode-connected transistor connected in series with the current simulating transistor has a channel length equal to or larger than a channel length of the current-voltage converting transistor. Item 5. The high-frequency power amplifier circuit according to Item 4.   A voltage to be compared with the reference voltage in the differential amplifier circuit is generated by the first transistor connected in current mirror with the diode-connected transistor and the diode-connected second transistor connected in series with the first transistor. The high-frequency power amplifier circuit according to claim 2, wherein   The high frequency device according to claim 1, further comprising a detection transistor in which the amplification transistor and the control terminal are connected in common and a current proportional to a current flowing through the amplification transistor flows. Power amplifier circuit.   The bias generation circuit includes an external terminal to which an output power control signal is input, and a current flowing through the current-voltage conversion element is changed in accordance with the output power control signal, and the amplifier transistor is in response to the current. The high frequency power amplifier circuit according to claim 1, wherein the bias state is changed.   9. The high frequency power amplifier circuit according to claim 1, wherein the amplifying transistor and the transistor constituting the bias generating circuit are formed on the same semiconductor chip.   9. A high-frequency power amplification electronic component comprising the high-frequency power amplification circuit according to claim 1 mounted on an insulating substrate, wherein the bias generation circuit and the amplification transistor are provided on separate semiconductor chips. A first semiconductor chip formed with the bias generation circuit formed thereon, and a second semiconductor chip with the amplification transistor and the current simulation transistor formed on the insulating substrate. Electronic component for high frequency power amplification.

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