JP2005197271A - Field effect transistor employing ferromagnetic semiconductor and nonvolatile memory employing it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize lower power consumption rewriting and high density of information in a nonvolatile memory. <P>SOLUTION: An MISFET 1 employs an MIS structure having a multilayer structure of a gate electrode 15, a gate insulation film 11, and a ferromagnetic semiconductor 5 as a gate structure. A Shottky junction of a ferromagnetic body and a ferromagnetic semiconductor is employed in the source 7a and/or the drain 7b. Information is stored as the orientation of relative magnification between the ferromagnetic semiconductor (channel) 5 and the source 7a or the drain 7b, and information is read out as the difference in transmission characteristics of a transistor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a novel metal-insulator-semiconductor field effect transistor using a ferromagnetic semiconductor in a channel region, and high performance of a large capacity nonvolatile memory using the same.

  In recent years, the development of a highly information-oriented society, also called the IT revolution, continues to make further progress through “mobile devices”. It is recognized that this large demand for “mobile devices” can be the key to the future semiconductor industry. To meet this demand, conventional methods such as higher speed, lower power consumption, and higher capacity of semiconductor integrated circuits have been proposed. In addition to the improvement in performance, it is necessary to meet new requirements such as information non-volatility. In response to such a demand, a new memory device that combines a ferromagnetic storage technology excellent in nonvolatile high-density recording and a semiconductor integrated electronics technology has attracted attention.

  This device is called a magnetic random access memory (hereinafter referred to as “MRAM”), and has a structure in which a thin insulating tunnel barrier is sandwiched between ferromagnetic electrodes (magnetic tunnel junction; (Hereinafter referred to as “MTJ”) is used as the memory element (see, for example, Non-Patent Document 1).

  The MTJ has a tunneling magnetoresistance (hereinafter referred to as “TMR”) effect in which the tunnel resistance varies depending on the relative magnetization direction between the ferromagnetic electrodes. It becomes possible to electrically detect the magnetization state. Therefore, the presence of MTJ makes it possible to ideally incorporate information storage technology using ferromagnetic material into semiconductor integrated electronics.

  Hereinafter, a general memory cell using the MTJ will be described with reference to FIG. As shown in FIG. 7, a general MRAM memory cell includes a 1-bit memory cell including one MTJ 101 and one MOS transistor 103. The MTJ 101 is a tunnel junction that includes a first ferromagnetic material 105, a second ferromagnetic material 107, and a tunnel barrier 111 that is provided between the first ferromagnetic material 105 and the second ferromagnetic material 107.

  The source (S) 103 a of the MOS transistor 103 is grounded (GND), and the drain (D) 103 b is connected to one ferromagnetic electrode 107 of the MTJ 101. The other ferromagnetic electrode 105 of the MTJ 101 is connected to the bit line (BL), and the rewrite word line (WL (P)) is electrically connected to the MTJ 101 and other wirings and an insulating film directly above or immediately below the MTJ. It is arranged so as to cross the bit line (BL) in a state of being electrically insulated. The read word line WL (R) is connected to the gate electrode (G) 103 c of the MOS transistor 103.

  In ferromagnetic materials, the magnetization direction can be kept non-volatile, so in MTJ101, binary information can be made non-volatile by setting the relative magnetization state between the ferromagnetic electrodes to parallel magnetization or anti-parallel magnetization. Can be remembered. In MTJ 101, the tunnel resistance differs depending on the relative magnetization state between the two ferromagnetic electrodes 105 and 107 due to the TMR effect. Therefore, if a tunnel resistance corresponding to a magnetization state such as parallel magnetization or antiparallel magnetization is used, the magnetization state in the MTJ 101 can be electrically detected.

  Information is rewritten by changing the coercive force of the two ferromagnetic electrodes in the MTJ 101 or by fixing the magnetization direction of one of the ferromagnetic electrodes 105 or 107 and reducing the coercive force. Alternatively, it is performed by reversing the magnetization of a ferromagnetic electrode whose magnetization direction is not fixed. Hereinafter, a ferromagnetic electrode that performs magnetization reversal is referred to as a free layer, and a ferromagnetic electrode that does not perform magnetization reversal is referred to as a pinned layer. More specifically, a current is supplied to each of the bit line (BL) and the rewrite word line (WL (P)) intersecting on the selected cell, and the selected magnetic field is selected by a synthesized magnetic field induced by these currents. Only the magnetization state of the MTJ 101 in the memory cell is changed to parallel magnetization or antiparallel magnetization. At this time, in order to prevent magnetization reversal of unselected cells having the same bit line or rewrite word line as the selected cell, the MTJ 101 of the unselected cell does not reverse magnetization with a magnetic field from only one wiring. Set the current value to flow through the wiring.

  To read information, a voltage is applied to the read word line connected to the selected cell to turn on the MOS transistor 103, and then a read drive current is passed to the MTJ 101 via the bit line (BL). In MTJ101, the tunnel resistance in the magnetization state of parallel magnetization or antiparallel magnetization differs depending on the TMR effect, and therefore the magnetization state can be determined by detecting a voltage drop in MTJ101 due to the read drive current (see Non-Patent Document 1). ).

K. Inomata, "Present and future of magnetic RAM technology", IEICE Trans. Electron. Vol.E84-C, pp740-746, 2001.

The memory cell using the MTJ has a problem to be solved which will be described below.
1) Issues related to writing In the MRAM, information is rewritten by changing the magnetization state of the MTJ by using a magnetic field induced by the current of the bit line and the word line. Even in MRAM, high density integration and high performance can be realized by miniaturization of devices as in the case of normal semiconductor integrated memory. However, if MTJ is miniaturized, the demagnetizing field of the ferromagnetic electrode increases and magnetization reversal is achieved. The required magnetic field strength is increased. Therefore, the current required for rewriting increases. This increase in current is quite large, and as the wiring is miniaturized, even if the aspect ratio is increased, the reliability of the wiring cannot be secured. When the coercive force of the ferromagnetic material is reduced, the strength of the magnetic field necessary for rewriting decreases, but a fatal problem such as erroneous writing occurs. Therefore, there is a need for a new method that can easily rewrite magnetization information with a magnetic field generated at a low current value without reducing the coercivity of the ferromagnetic material.

2) Problems related to reading The MTJ takes a binary resistance value corresponding to whether the magnetization state of the ferromagnetic electrodes facing each other through the tunnel barrier is parallel magnetization or anti-parallel magnetization. In order to detect this binary information with high sensitivity, it is necessary to increase the ratio of the output signal between the two magnetization states. A large drive current is required to read information at a high speed, but the TMR ratio in the MTJ depends strongly on the bias voltage applied to the MTJ, and decreases rapidly with the bias voltage. Therefore, when a large current is used for reading, the voltage drop at the MTJ increases and the TMR ratio decreases. Therefore, the TMR ratio has a trade-off relationship with high-speed operation. Therefore, it is necessary to devise a technique that does not reduce the TMR ratio even if a large voltage drop occurs in the MTJ.

3) Issues related to integration density The memory cell of the MRAM has a simple structure, and the ferromagnetic material used in the MTJ can be miniaturized to a nanoscale size, so that it is a memory suitable for high-density integration. In order to achieve a high degree of integration of several gigabits or more, the channel length of the MOS transistor is expected to be smaller than about 0.1 μm. However, even if the MTJ is miniaturized in accordance with such a fine transistor, the arrangement of multilayer wiring such as a word line for rewriting rules the reduction of the cell area, and it is difficult to achieve high density integration. Therefore, a memory cell having a simpler structure is required.

  It is an object of the present invention to reduce the voltage for writing and reading in a memory and increase the degree of integration when integrated.

  In the present invention, the above-described problems are solved by using a metal-ferromagnetic-semiconductor field effect transistor (MISFET) in which a channel region is made of a ferromagnetic semiconductor.

1) Writing In a ferromagnetic semiconductor, if the number of carriers in the ferromagnetic semiconductor layer is decreased by applying an electric field, it is possible to change the magnetism from ferromagnetic to paramagnetic (referred to as field effect magnetic control). ). In the memory cell using the MISFET of the present invention, a voltage is applied to the source and drain to change the ferromagnetic semiconductor layer in the channel region from ferromagnetic to paramagnetic (or a state having a sufficiently small coercive force), and this state is changed. Magnetization reversal is carried out while keeping it. Therefore, writing can be performed with a magnetic field sufficiently smaller than the coercive force in the ferromagnetic state.

2) Reading In the MISFET of the present invention, the TMR (magnetic field) between the ferromagnetic channel and the ferromagnetic source (or the ferromagnetic channel and the ferromagnetic drain, or the ferromagnetic channel and the ferromagnetic source, and the ferromagnetic channel and the ferromagnetic drain). The magnetization state is read by the resistance effect. The bias applied between the source and the drain is divided at the source junction and the drain junction. Therefore, in the device according to the present invention, the ratio of the output signal (drain current) between the parallel magnetization and the antiparallel magnetization has a bias dependency weaker than that of a normal MTJ. In this device, it is possible to apply a bias for reading larger than MTJ. In particular, when the source is made of a ferromagnetic material, this bias dependency is remarkably weakened.

3) High-density integration In the MISFET of the present invention, one MISFET constitutes a 1-bit memory cell. Therefore, a very simple configuration can be achieved for the wiring. Since the memory cell can be configured by the simplest one transistor and three wirings, a layout suitable for miniaturization can be easily configured.

  In addition, the conventional MRAM memory cell has a structure of 1MTJ, 1 transistor, 4 wirings (see FIG. 7), and the cell area is shared by adjacent cells due to the presence of the MTJ and the word line for writing. However, in the memory cell of the present invention, a cell structure in which adjacent cells share a source is also possible.

  According to the MISFET of the present invention, the transistor has characteristics as a transistor capable of controlling the drain current by the gate voltage, and has the transfer conductance of the ferromagnetic channel and the ferromagnetic source (or both the ferromagnetic drain or the ferromagnetic source and the ferromagnetic drain). It also has a characteristic characteristic that it can be controlled by the relative magnetization direction. Therefore, binary information can be stored according to the relative magnetization direction, and the relative magnetization direction can be electrically detected. In addition, if the magnetic control based on the electric field effect of a channel made of a ferromagnetic semiconductor is used, the current required for rewriting information can be greatly reduced. Therefore, the MISFET can constitute a high-performance nonvolatile memory cell suitable for high-density integration.

  Hereinafter, a MISFET and a nonvolatile memory using the same according to a first embodiment of the present invention will be described with reference to the drawings. First, a configuration example of the MISFET according to the present embodiment will be described.

  FIG. 1A is a cross-sectional structure diagram of a MISFET according to the present embodiment, which uses a ferromagnetic semiconductor for a channel. The MISFET 1 according to the present embodiment uses a MIS structure having a stacked structure of a gate electrode 15, a gate insulating film 11, and a ferromagnetic semiconductor 5 as a gate structure. The source 7a or drain 7b (or both of the source 7a / drain 7b) made of a ferromagnetic material and the ferromagnetic semiconductor 5 are configured to form a Schottky junction.

  When a Schottky junction between a ferromagnetic material and a ferromagnetic semiconductor is used only on one side, a normal Schottky junction with a nonmagnetic metal is used on the other side. Further, impurities are appropriately introduced into the junction interfaces 5a and 5b (FIG. 1 (a)) between the channel region (5) and the ferromagnetic source 7a or the ferromagnetic drain 7b (or both are ferromagnetic). Or an intrinsic semiconductor may be inserted.

The ferromagnetic semiconductor 5 of the channel is formed on the semiconductor substrate 3 (or on the semiconductor layer thereon) or by introducing magnetic atoms into the semiconductor by a thermal diffusion method or an ion implantation method. Can do. The ferromagnetic material used for the source 7a or the drain 7b (or both 7a and 7b) can be an ordinary ferromagnetic metal (Fe, Ni, Co, permalloy, etc.), but a magnetic element is metallic (high concentration). Doped (added) ferromagnetic semiconductors (Ga _1-x M _x As, Si _1-x M _x , Ge _1-x M _x (M is a magnetic element)) and half-metal ferromagnets (CrO ₂ , Fe ₃ O ₄ , Heusler alloy, etc.) can also be used. Such a ferromagnetic source 7a and drain 7b may be grown or deposited on the ferromagnetic semiconductor layer 5, but are formed by introducing magnetic atoms into the semiconductor by thermal diffusion or ion implantation. Also good. As the MIS structure, a MOS structure in which the surface of the ferromagnetic semiconductor layer 5 is oxidized can be used, or an insulator layer can be grown or deposited on the ferromagnetic semiconductor layer 5 to form a MIS structure. As the substrate 3, a normal semiconductor substrate or SOI substrate can be used.

  The MISFET 1 according to the present embodiment operates in a storage channel type in which carriers of the same conductivity type as the ferromagnetic semiconductor 5 in the channel region are carriers. Although both electrons and holes can be used as carriers, an explanation will be given below with reference to a band structure by taking an n-channel device as an example. A p-channel device can be similarly configured and operated.

FIG. 1B is a diagram showing a band structure in the vicinity of the channel region of the n-channel device. FIG. 1B illustrates the case where a conductive ferromagnetic material is used for the source, but as described above, a structure using a ferromagnetic material for the drain or both of the source and the drain may be used. It indicated dotted line and the solid line and the n-type ferromagnetic semiconductor layer 5 shown in the source 7a and the drain 7b, represents the Fermi energy E _F. E _G represents the band gap of the ferromagnetic semiconductor. E _C and E _V represent the bottom of the conduction band and the top of the valence band of the ferromagnetic semiconductor 5, respectively. Although the ferromagnetic semiconductor layer 5 in the channel region in FIG. 1B is not degenerated, a magnetic element may be doped to such an extent that it degenerates. By the Schottky junction of the source 7a and the drain 7b, a Schottky barrier whose barrier height is φ _S and φ _D respectively is generated on the conduction band side.

  The arrows 4a and 4b shown on the Fermi energy of the channel made of the ferromagnetic material source 7a and the ferromagnetic semiconductor 5 indicate the direction of the majority spin in each region, and the direction of the arrow is upward. If it is, it is up spin, and if it is downward, it is down spin. Also, the display of minority spins is omitted. Further, the nonmagnetic conductor (7b) is expressed by simultaneously indicating upward and downward arrows. Hereinafter, the source 7a (or drain) made of a ferromagnetic material may be referred to as a ferromagnetic source 7a (or ferromagnetic drain). Similarly, a channel region made of a ferromagnetic semiconductor may be simply referred to as a ferromagnetic channel.

  Next, the operation principle of the MISFET according to this embodiment will be described with reference to the drawings. The channel region 5 of the MISFET according to the present embodiment is made of a ferromagnetic semiconductor. Regarding the source 7a and the drain 7b, as described above, when (i) only the source is ferromagnetic, (ii) drain When only the ferromagnet is used, (iii) when both the source and the drain are ferromagnets, there are three combinations. Hereinafter, the principle of operation of an n-channel device having a ferromagnetic source will be described, but the above-described other configurations and p-channel devices also operate in the same manner.

  Further, the case where the relative magnetization direction of the ferromagnetic channel with respect to the ferromagnetic source is the same direction is referred to as parallel magnetization, and the case where these relative magnetization directions are opposite to each other is referred to as anti-parallel magnetization. The channel length of the MISFET is sufficiently shorter than the spin relaxation distance, and the rush bar effect induced by the gate voltage is ignored.

FIG. 2A shows a band structure when the gate-source bias V _{GS is set} to V _GS = 0 and the bias V _DS (> 0) is applied between the drain and the source. By applying V _DS , a potential shape as shown in FIG. 2A is formed. The Schottky junction of the drain 7b is forward biased, and the Schottky junction of the ferromagnetic source 7a is reverse biased. At this time, the width d of the depletion layer due to the Schottky junction of the ferromagnetic source 7a is sufficiently thick, and almost no injection of electrons from the ferromagnetic source 7a toward the channel region 5 occurs due to the tunnel effect (d is the ferromagnetic source 7a). This is the distance until the Fermi level of 7a intersects the band edge of the Schottky barrier on the source side).

Further, since the Schottky junction on the source side is reverse-biased, the current is about the reverse saturation current of the Schottky junction derived from the thermal conduction of the conduction carrier of the ferromagnetic source 7a over the barrier of height φ _S. However, this current can be made sufficiently small by selecting φ _S appropriately. Accordingly, in the state where V _GS = 0, the MISFET is cut off (off). This blocking state does not depend on the relative magnetization direction between the ferromagnetic source 7a and the ferromagnetic channel 5.

When a bias V _GS (> 0) is applied to the gate electrode 15, the electric field near the Schottky barrier φ _S on the ferromagnetic source 7a side is strengthened by the lines of electric force from the gate electrode 15 toward the ferromagnetic source 7a. As shown in b), the barrier width of the Schottky barrier decreases (d ′ in the figure). Accordingly, electrons in the ferromagnetic source 7a are transmitted through the potential barrier φ _S by the tunnel effect and injected into the channel 5 immediately below the gate insulating film 11. The injected electrons are attracted to the insulator / semiconductor interface by V _{GS and} are transported to the drain 7b by V _DS to form a drain current. At this time, the transmission (mutual) conductance and drain current of the MISFET 1 according to the present embodiment depend on the relative magnetization directions of the ferromagnetic source 7 a and the ferromagnetic channel 5.

In the tunnel from the ferromagnetic source 7a to the ferromagnetic channel 5 via the electron Schottky barrier φ _S , an effect similar to the tunnel magnetoresistance (TMR) effect works. This will be referred to as the TMR effect). Therefore, the tunnel resistance is small when the ferromagnetic source 7a and the ferromagnetic channel 5 are in parallel magnetization, and the tunnel resistance is large in the case of antiparallel magnetization. Even when the influence of the TMR effect is small, electrons having a spin polarization depending on the spin polarizability of the source ferromagnet can be injected from the ferromagnetic source 7a. For this reason, electrons cause spin-dependent scattering in the ferromagnetic channel 5 due to the relative magnetization state of the ferromagnetic channel 5 and the ferromagnetic source 7a. Therefore, due to the TMR effect at the time of tunnel injection and spin-dependent scattering in the ferromagnetic channel 5, the relative magnetization directions of the ferromagnetic source 7a and the ferromagnetic channel 5 change, and the transfer conductance changes.

  As shown in FIG. 2B, if the ferromagnetic source 7a and the ferromagnetic channel 5 are in parallel magnetization, the transfer conductance increases and the drain current also increases. However, as shown in FIG. If the magnetic source 7a and the ferromagnetic channel 5 are antiparallel, the transfer conductance is small and the drain current is small.

As described above, in the MISFET according to the present embodiment, the transfer conductance can be controlled by the relative magnetization directions of the ferromagnetic source 7a and the ferromagnetic channel 5 even under the same bias. Further, in the MISFET according to the present embodiment, since the number of conductive carriers injected into the channel can be controlled by V _GS , the drain current can be controlled by V _GS . Therefore, the MISFET according to the present embodiment has a property as a normal transistor capable of controlling the drain current by the gate voltage, and can control the transfer conductance by the relative magnetization directions of the ferromagnetic source and the ferromagnetic channel.

  Next, the nonvolatile memory using the MISFET according to the present embodiment will be described. The MISFET according to the present embodiment stores binary information by setting the relative magnetization of the ferromagnetic source and the ferromagnetic channel to parallel magnetization or antiparallel magnetization, and outputs (drain) corresponding to these magnetization states. A nonvolatile memory that detects the magnetization state from the current) can be realized. Since only one MISFET according to this embodiment can be used to form a 1-bit memory cell, high-density integration is possible. In addition, the magnetic control by the field effect of the ferromagnetic semiconductor used for the channel is positively utilized, and the rewriting current, which is a big problem in the conventional MRAM, can be reduced.

  Hereinafter, the operation principle of this memory will be described using an n-channel type MISFET having a ferromagnetic source, but the MISFETs and p-channel type devices having other configurations described above operate in the same manner. Here, the ferromagnetic source is a pinned layer with a fixed magnetization direction, and the ferromagnetic channel is a free layer that changes the magnetization direction.

  FIG. 3 is a diagram showing a cell configuration of the nonvolatile memory according to the embodiment of the present invention. As shown in FIG. 3, the memory cell according to the present embodiment includes a memory cell 21 including one MISFET according to the above-described embodiment, a word line (WL) 23, a bit line (BL) 25, and a ground line (GND) 27. And have. In the rewrite operation of the nonvolatile memory cell, a relatively large bias is applied to the bit line 25 and the ground line 27 connected to the selected cell 21 (to the substrate potential or the gate electrode), and the ferromagnetism in the channel region disappears. Then, the number of carriers is reduced or depleted until it becomes paramagnetic (or a state in which the coercive force is sufficiently small). As shown in FIG. 3, if the bit line 25 and the ground line 27 are arranged so as to be orthogonal to each other, a bias is applied to the source and drain only in the selected cell 21 and connected to the bit line 25 or the ground line 27. In other unselected cells, only the drain or source is biased. Therefore, if the bias is set to such an extent that ferromagnetism cannot be annihilated over the entire channel with only one bias (for example, only the region not reaching the center from the source, or the region not reaching the center from the drain). Only so that the magnetization information of the unselected cells is not lost.

  In this state, a relatively small current is applied to the word line 23, a magnetic field is induced to change the magnetization direction of the paramagnetic channel, and then the bias between the bit line 25 and the ground line 27 is turned off. Rewrite the information by returning the channel to the ferromagnetic state.

FIG. 4 is a diagram showing an example of the rewriting operation on the magnetization curve. First, it is assumed that the channel magnetization is at point A on the magnetization curve. Consider rewriting from this state to point E in FIG. First, a bias is applied to the bit line and the ground line from the state of point A to change the ferromagnetism of the selected cell to paramagnetism. At this time, the magnetization of the channel becomes the B point. Next, if a current is passed through the word line connected to the gate electrode directly above the channel, even if the strength of the magnetic field induced by this current is equal to or less than the coercive force H _C of the channel region in the ferromagnetic state, as shown in FIG. Magnetization can be reversed like point C. Next, the channel region returns to the ferromagnetic state if the source and drain biases are turned off while a current is applied to the gate electrode. At this time, the magnetization direction in the paramagnetic state is preserved as indicated by point D in FIG. When the current of the word line is cut from this state, the rewriting is completed (point E in FIG. 4).

In the memory cell according to the present embodiment, since the magnetization can be reversed by a magnetic field smaller than the coercive force H _C of the channel region in the ferromagnetic state, the current required for the magnetization reversal can be greatly reduced. In the information read operation, a bias necessary for normal transistor operation is applied to the selected cell, and the relative magnetization state of the ferromagnetic source and the ferromagnetic channel is detected based on the magnitude of the drain current. Since the word lines and the bit lines are arranged orthogonally, the stored contents can be read only for the selected cell. In the read operation, a necessary bias may be applied by precharging.

  Next, a non-volatile memory according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a diagram showing a cell configuration example of a nonvolatile memory that is a nonvolatile memory according to the present embodiment and can collectively erase / rewrite a plurality of memory cells. Similar to the cell configuration example shown in FIG. 3, the memory cell according to the present embodiment includes a MISFET 31, a word line (WL) 33, a bit line (BL) 35, and a ground line (GND) 37. ing. However, the bit line 35 and the ground line 37 are arranged in parallel to each other. In this cell structure, the magnetization information of all the MISFETs 31 connected to the selected bit line 35 can be simultaneously erased and rewritten.

  In the rewriting operation, a bias is applied to the selected bit line 35 and the ground line 37 connected to the MISFET 31 connected thereto, and the channels of all the MISFETs 31 connected to the bit line 35 and the ground line 37 are made ferromagnetic. To paramagnetism (or a state in which the coercive force is sufficiently small). Next, a current in a direction corresponding to the rewrite content is supplied to each word line 33 connected to the gates of these MISFETs 31 to change the magnetization direction of the paramagnetic channel. Finally, by turning off the bias of the bit line 35 and the ground line 37, the channels of the respective MISFETs 31 are returned to ferromagnetic and information is rewritten. In the memory cell according to the present embodiment, by using the small current required for rewriting each memory cell, a rewrite current is simultaneously applied to a large number of word lines. It is possible to rewrite the magnetization information of the MISFET at the same time. Therefore, the rewriting speed can be increased. In the above cell configuration, since the word line and the bit line are arranged orthogonally, if a normal transistor bias is applied to the selected cell, the magnetization of the selected cell is based on the drain current corresponding to the magnetization state. The state can be detected. In addition, even with the cell configuration shown in FIG. 5, reading by precharge is possible.

  Next, a memory cell according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 shows a memory cell structure according to the present embodiment, which is a composite structure of a gate electrode and a word line using a yoke structure. FIG. 6 is a cross-sectional view of the MISFET as viewed from the source side. As shown in FIG. 6, the memory cell structure according to the present embodiment includes a stacked structure having a channel region 41, a gate oxide film 43, a gate electrode 45, and a word line 47, and a stacked structure of the stacked structure. Among them, a yoke 51 that covers at least the word line 47 and the gate 45 from the outside is provided.

  The yoke 51 is made of a material having high magnetic permeability. If the structure shown in FIG. 6 is used, the magnetic field by the current of the word line 47 can be effectively applied to the ferromagnetic channel 41. Therefore, the write current can be further reduced. The structure shown in FIG. 6 can be applied to the cell configuration shown in FIGS.

  As mentioned above, although it demonstrated along embodiment of this invention, this invention is not restrict | limited to these. It will be apparent to those skilled in the art that other various modifications, improvements, and combinations are possible.

  The present invention can achieve high integration and low power consumption in a nonvolatile memory device, and can be applied as a nonvolatile memory device for various electronic devices, particularly portable electronic devices.

FIG. 1A is a cross-sectional structure diagram of a MISFET according to the first embodiment of the present invention, which uses a channel region made of a ferromagnetic semiconductor and a source made of a ferromagnetic material. FIG. 1B is a diagram showing a band structure in the vicinity of the channel region of the n-channel device. FIGS. 2A to 2C are energy band diagrams showing the operation principle of the MISFET according to the present embodiment. It is a figure which shows the cell structure of the non-volatile memory by embodiment of this invention. It is the figure which showed on the magnetization curve the example of rewriting operation | movement of the non-volatile memory by embodiment of this invention. It is a figure which shows the cell structure of the non-volatile memory by the 2nd Embodiment of this invention. FIG. 10 is a diagram showing a composite structure of a gate electrode and a word line using a yoke structure, which is a memory cell structure according to a third embodiment of the present invention. It is sectional drawing which shows the structural example of the memory cell of a general MRAM.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... MISFET, 5 ... Ferromagnetic semiconductor, 7a ... Source, 7b ... Drain, 11 ... Gate insulating film, 15 ... Gate electrode.

Claims (42)

A source made of a ferromagnetic material and injecting carriers and a drain made of a ferromagnetic material and receiving the carrier, or the source and the drain made of either ferromagnetic material, and
A ferromagnetic semiconductor layer provided between the source and the drain and forming a Schottky junction having a Schottky barrier at each junction interface between the source and the drain;
A transistor having a gate electrode formed with respect to the ferromagnetic semiconductor layer;   2. The transistor according to claim 1, wherein the ferromagnetic semiconductor layer is formed of a ferromagnetic semiconductor obtained by adding a magnetic element to a semiconductor.   3. The transistor according to claim 1, wherein the source made of a ferromagnetic material or the drain made of a ferromagnetic material contains one of a ferromagnetic metal, a ferromagnetic semiconductor, and a half-metal ferromagnetic material.   4. The transistor according to claim 1, wherein the ferromagnetic semiconductor used for the source or the drain is a ferromagnetic semiconductor in which a magnetic element is added to a semiconductor. 5.   When the source made of a ferromagnetic material or the drain made of a ferromagnetic material is a ferromagnetic semiconductor, the source made of a ferromagnetic semiconductor or the drain made of a ferromagnetic semiconductor and the junction interface between the ferromagnetic semiconductor layer 5. The transistor according to claim 1, wherein a pseudo Schottky junction is formed by band discontinuity.   In the case where the source made of a ferromagnetic material or the drain made of a ferromagnetic material is a half-metal ferromagnet, a metallic spin band of the half-metal ferromagnet forms a Schottky junction at the junction interface. 5. The transistor according to claim 1, wherein the transistor is characterized in that:   When only one of the source and the drain is a ferromagnetic material, a Schottky junction is formed at the junction interface between the source or the drain that is a non-magnetic material and the ferromagnetic semiconductor layer. 7. The transistor according to any one of claims 1 to 6, wherein:   8. The transistor according to claim 1, further comprising a semiconductor layer at a junction interface between the ferromagnetic semiconductor layer and the source and drain.   9. The transistor according to claim 8, wherein the semiconductor layer at the junction interface is formed of a semiconductor layer to which an impurity is added or an intrinsic semiconductor layer.   The transistor according to claim 1, wherein an insulator layer is provided between the gate electrode and the ferromagnetic semiconductor layer.   The transistor according to claim 10, wherein the insulator layer includes a surface oxide layer formed by oxidizing the surface of the ferromagnetic semiconductor layer.   The transistor according to claim 11, wherein the insulator layer is an insulator layer grown or deposited on the ferromagnetic semiconductor layer.   13. The transistor according to claim 1, wherein the transistor is formed on a semiconductor substrate or an SOI (Silicon on Insulator) substrate.   The source made of a ferromagnetic material or the drain made of a ferromagnetic material is formed by growth or deposition on the ferromagnetic semiconductor layer or semiconductor layer or semiconductor substrate, or introduction of a magnetic element into the semiconductor layer or semiconductor substrate. The transistor according to claim 1, wherein the transistor is a transistor.   15. The transistor according to claim 1, wherein the ferromagnetic semiconductor layer is formed by growth or deposition on the semiconductor layer or introduction of a magnetic element into the semiconductor layer. .   When the source or the drain is a ferromagnet, the source or the ferromagnet is a ferromagnet by reversing the magnetization direction of the source or the ferromagnet that is a ferromagnet. The relative magnetization direction of the drain and the ferromagnetic semiconductor layer can be controlled in the same direction (hereinafter referred to as “parallel magnetization”) or in the opposite direction (hereinafter referred to as “anti-parallel magnetization”). 16. A transistor according to any one of the preceding claims, characterized in that it is a transistor.   When the source or the drain is a ferromagnetic material, the ferromagnetic semiconductor layer is reversed with respect to the source that is a ferromagnetic material or the drain that is a ferromagnetic material by reversing the magnetization direction of the ferromagnetic semiconductor layer. The transistor according to claim 1, wherein the direction of magnetization relative to the layer can be controlled to parallel magnetization or antiparallel magnetization.   When the source and the drain are ferromagnetic materials, either the magnetization direction of the source and the drain or the magnetization direction of the ferromagnetic semiconductor layer is fixed, and the magnetization of the non-fixed one is reversed. The transistor according to claim 1, wherein the direction of magnetization with respect to the fixed side can be controlled to parallel magnetization or antiparallel magnetization.   The Schottky barrier is generated on a conduction band side when the carrier is an electron, and the Schottky barrier is generated on a valence band side when the carrier is a hole. The transistor according to any one of the above items.   The carrier injection by the tunnel from the source to the ferromagnetic semiconductor layer is suppressed by the Schottky barrier in a state where no voltage is applied between the gate electrode and the source. 20. The transistor according to any one of up to 19.   By applying a voltage between the gate electrode and the source, the carriers reach the ferromagnetic semiconductor layer by tunneling the Schottky barrier at the junction of the source and the ferromagnetic semiconductor layer. 20. The transistor according to any one of claims 1 to 19, characterized in that:   In the case where the drain is a ferromagnetic material, the drain that is a ferromagnetic material and the ferromagnetic semiconductor layer have a relative magnetization state of parallel magnetization, whereas the drain that is a ferromagnetic material and the drain The transistor according to any one of claims 1 to 21, wherein the drain current is small when the direction of magnetization relative to the ferromagnetic semiconductor layer is antiparallel magnetization.   When the source is a ferromagnetic material, the source that is a ferromagnetic material and the ferromagnetic semiconductor layer have a relative magnetization state of parallel magnetization, and the source that is a ferromagnetic material and the source The transistor according to any one of claims 1 to 21, wherein the drain current is small when the direction of magnetization relative to the ferromagnetic semiconductor layer is antiparallel magnetization.   Relative magnetization of the ferromagnetic semiconductor layer and the source of ferromagnetic material or the drain of ferromagnetic material or the source of ferromagnetic material and the drain of ferromagnetic material under the same bias. The transistor according to any one of claims 1 to 23, wherein the transfer conductance can be controlled by the orientation of the transistor.   In the case where the source that is a ferromagnetic material, the drain that is a ferromagnetic material, or the source that is a ferromagnetic material and the drain that is ferromagnetic, and the ferromagnetic semiconductor layer have parallel magnetization, the gate electrode 25. A threshold defined as a gate voltage that produces a certain current defined between said source and said drain by a voltage applied to said source and said drain. The transistor described in 1.   The one transistor according to any one of claims 1 to 25, wherein the source is a ferromagnetic material, the drain is a ferromagnetic material, or the source is a ferromagnetic material and the ferromagnetic material. Information is stored according to the direction of relative magnetization between the drain and the ferromagnetic semiconductor layer, and the source that is a ferromagnet or the drain that is a ferromagnet or the source that is a ferromagnet or the ferromagnet A transistor that detects information stored in a transistor based on a transfer conductance of the transistor depending on a relative magnetization direction of the drain and the ferromagnetic semiconductor layer.   A bias is applied to the ferromagnetic semiconductor layer so that the ferromagnetic semiconductor layer is in a paramagnetic state or a ferromagnetic state having a sufficiently small coercive force to the source and the drain. On the other hand, after changing the magnetization direction of the ferromagnetic semiconductor layer that has become paramagnetic by applying a magnetic field, the bias of the source and the drain is turned off while the magnetic field is still applied, or 27. The information is rewritten by applying a voltage sufficient to return the ferromagnetic semiconductor layer to a ferromagnetic state, thereby bringing the ferromagnetic semiconductor layer into a ferromagnetic state having a large coercive force. Transistor. One transistor according to any one of claims 1 to 27;
A first wiring connected to the gate electrode;
A second wiring connected to the drain;
And a third wiring for grounding the source.   The first state in which the ferromagnetic semiconductor layer is in either the paramagnetic state or the ferromagnetic state having a sufficiently small coercive force in the second wiring and the third wiring. Is applied to the first wiring to cause a magnetic field that can change the magnetization direction of the ferromagnetic semiconductor layer in the first state. Or having information rewriting means for rewriting information by setting the ferromagnetic semiconductor layer to a ferromagnetic state having a large coercive force by turning the ferromagnetic semiconductor layer to a second voltage enough to return the ferromagnetic semiconductor layer to ferromagnetism. The memory element according to claim 28.   With respect to the third wiring, the second wiring and the third wiring when a predetermined voltage is applied to the second wiring and the first wiring, respectively. 29. The memory element according to claim 28, wherein information is read based on a magnitude of a current flowing therebetween. A plurality of transistors according to any one of claims 1 to 27;
A ground line commonly grounding sources of a first group of transistors selected from the plurality of transistors;
A word line commonly connecting the gates of the first group of transistors;
A bit line that is individually connected to the drains of the first group of transistors and that commonly connects the drains of the second group of transistors including transistors that do not belong to the first group;
A memory circuit. A plurality of transistors according to any one of claims 1 to 27;
A ground line for commonly grounding the sources of the transistors belonging to the transistor row composed of the plurality of transistors extending in one direction;
A word line commonly connecting the gates of the transistors belonging to the transistor row;
And a plurality of bit lines individually connecting the drains of the transistor rows. A plurality of transistors according to any one of claims 1 to 27 arranged in a matrix,
A plurality of ground lines commonly connecting the sources of the plurality of transistors arranged in a column direction;
A plurality of word lines commonly connecting gate electrodes of the plurality of transistors arranged in a column direction;
A memory circuit having a plurality of bit lines commonly connecting drains of the transistors arranged in a row direction.   The degree to which the bit line and the ground line are changed from a ferromagnetic state having a large coercive force to a paramagnetic state or a ferromagnetic state having a sufficiently small coercive force in the ferromagnetic semiconductor layer. A current that induces a magnetic field that can change the magnetization direction of the ferromagnetic semiconductor layer in the first state is passed through the word line, and the first voltage is turned off, Alternatively, the word line and the bit line are selected by setting the ferromagnetic semiconductor layer to a ferromagnetic state having a large coercive force by setting the ferromagnetic semiconductor layer to a second voltage that returns the ferromagnetic semiconductor layer to a ferromagnetic state. 34. The memory circuit according to claim 31, further comprising information rewriting means for rewriting information of the selection transistor.   Magnitude of current flowing between the bit line and the ground wiring when a predetermined voltage is applied to the bit line and the word line with respect to the ground wiring line, respectively. 34. The memory circuit according to claim 31, wherein information on a selection transistor selected by the word line and the bit line is read based on the data. A plurality of transistors according to any one of claims 1 to 27;
A ground line commonly grounding sources of a first group of transistors selected from the plurality of transistors;
A bit line commonly connecting drains of the first group of transistors;
A word line that is individually connected to the gates of the first group of transistors and that commonly connects the gates of the second group of transistors including transistors that do not belong to the first group;
A memory circuit. A plurality of transistors according to any one of claims 1 to 27;
A ground line for commonly grounding the sources of the transistors belonging to the transistor row composed of the plurality of transistors extending in one direction;
Bit lines commonly connecting drains of transistors belonging to the transistor rows;
A memory circuit having a plurality of word lines individually connected to the gates of the transistor rows. A plurality of transistors according to any one of claims 1 to 27 arranged in a matrix,
A plurality of grounding wires for commonly connecting the sources of the plurality of transistors arranged in a row direction;
A plurality of word lines commonly connecting gate electrodes of the plurality of transistors arranged in a column direction;
A memory circuit having a plurality of bit lines commonly connecting drains of the transistors arranged in a row direction.   The degree to which the bit line and the ground line are changed from a ferromagnetic state having a large coercive force to a paramagnetic state or a ferromagnetic state having a sufficiently small coercive force in the ferromagnetic semiconductor layer. A current that induces a magnetic field that can change the magnetization direction of the ferromagnetic semiconductor layer in the first state is passed through the word line, and the first voltage is turned off, Or a transistor group connected to the bit line and the ground line by setting the ferromagnetic semiconductor layer to a ferromagnetic state having a large coercive force by setting the second voltage to a level that returns the channel to ferromagnetic. The memory circuit according to any one of claims 36 to 38, further comprising information rewriting means for rewriting the information at once.   Based on the magnitude of current flowing between the bit line and the ground line when a predetermined voltage is applied to the bit line and the word line with respect to the ground line, The memory circuit according to any one of claims 36 to 38, wherein information of a selection transistor selected by the word line and the bit line is read.   41. The memory element or memory circuit according to claim 27, further comprising a yoke surrounding an outer periphery of the word line or the first wiring.   The memory according to any one of claims 27 to 41, further comprising another wiring that applies a magnetic field to the transistor while being electrically insulated on or near the transistor. Element or memory circuit.

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