JP2005191356A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device suitable for high integration in which the characteristics of a transfer gate transistor can be prevented from being deteriorated by suppressing the infiltration of P ions into the channel area of the transfer gate transistor. <P>SOLUTION: The sidewall of a trench formed on a semiconductor substrate 11 is coated with an insulating film 19, and P ions are injected into a 1st conductive film formed by doping As of the storage node electrode of a trench capacitor. The scattering or channeling of P ions on the sidewall and the infiltration of the P ions into the semiconductor substrate 11 are suppressed by the insulating film 19. Then the insulating film 19 with which the sidewall of the trench is coated is removed, and a 2nd conductive film is formed in the trench to form an embedded strap. After forming a separated insulating area 24 in the trench, As and P are diffused into the semiconductor substrate 11 by heat treatment and the storage node electrode is connected to the diffusion layer of the transfer gate transistor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device having a trench, and more particularly to a method of manufacturing a semiconductor device having a structure suitable for electrically connecting a storage node electrode of a trench capacitor and a diffusion layer of a transfer gate transistor.

  In a semiconductor device having a trench, for example, a semiconductor memory device composed of a DRAM (Dynamic Random Access Memory, hereinafter referred to as DRAM) cell having a trench capacitor, a wiring layer called a buried strap is formed to form a storage node electrode of the trench capacitor. The diffusion layer of the transfer gate transistor is electrically connected (for example, refer to Patent Document 1).

  A method of electrically connecting the storage node electrode of the trench capacitor and the diffusion layer of the transfer gate transistor disclosed in Patent Document 1 will be described with reference to the drawings. FIG. 21 is a cross-sectional view showing the structure of the embedded strap.

  As shown in FIG. 21, a trench 114 is formed in a semiconductor substrate 111, and a buried plate electrode 115 and a capacitor dielectric film 116 are formed in the trench 114.

  Next, an amorphous silicon film 117 doped with As serving as a storage node electrode is buried in the trench 114, the upper portion of the capacitor insulating film 116 is removed, and a buried plate electrode 115 and a diffusion layer (not shown) of the transfer gate transistor A color oxide film 118 is formed to electrically insulate them from each other.

  Next, an amorphous silicon film 119 doped with As is embedded in the trench 114, and the amorphous silicon film 119 is changed to a polysilicon thin film 119a by heat treatment.

  Next, the polysincon film 119a is removed to a predetermined position lower than the surface of the silicon substrate 111 to form the opening 120 of the buried strap.

  Next, an amorphous silicon film 121 doped with As is buried in the trench 114 to form a buried strap 120a.

  Next, the buried strap 120a is heat-treated and doped As is diffused into the semiconductor substrate 111 to form an n diffusion layer (not shown), and an amorphous silicon film 117 serving as a storage node electrode and a diffusion layer of the transfer gate transistor (Not shown) are electrically connected.

  However, the method disclosed in Patent Document 1 uses an amorphous silicon film doped with As in order to improve the filling property of the trench. In addition, since the impurity concentration distribution at the junction interface with the semiconductor substrate 111 is steep in the n layer in which As is diffused, the width of the depletion layer near the junction is narrow and the electric field strength is high.

  Therefore, there is a problem that junction leakage current due to tunneling or the like increases and cell data retention characteristics deteriorate.

  On the other hand, as a method for reducing the electric field at the junction interface, for example, in a MOS transistor, a drain region is formed of two types of impurity regions, a low concentration region and a high concentration region, to reduce the electric field in the vicinity of the drain. (For example, see Non-Patent Document 2).

  This method will be described with reference to the drawings. FIG. 22 is a sectional view showing a MOS transistor having a double drain structure. After the gate electrode 202 is formed on the semiconductor substrate 201, P ions are implanted to form a deep low-concentration impurity region 203, and then As ions are implanted to form a shallow high-concentration layer 204.

  However, in the method disclosed in Non-Patent Document 2, since ions are implanted into the surface of the semiconductor substrate 301, when ions are implanted into the bottom of a trench having a large aspect ratio, such as a trench, the ions are on the sidewalls of the trench. There is a problem of scattering or channeling and entering the semiconductor substrate.

  That is, as shown in FIG. 23, when P is ion-implanted into the conductive film 303 at the bottom of the trench 302 formed in the semiconductor substrate 301 using a mask material 304, the incident beam has a spread width, so In addition to the region 305 to be ion-implanted, P ions are scattered or channeled by the side wall 306 of the trench and enter the semiconductor substrate 301 by about 500 nm, for example, to form a P ion scattering region 307.

  Therefore, when a transfer gate transistor (not shown) is formed, there is a problem that P in the P ion scattering region 307 diffuses to the channel portion (not shown) of the transfer gate transistor of the adjacent cell by heat treatment.

As a result, the diffused P compensates for the p-type carrier in the channel portion, so that the carrier concentration in the channel portion is lowered and the threshold value of the transfer gate transistor is lowered. Therefore, the cell data retention characteristics may be deteriorated.
JP 2002-110951 A (page 3-4, FIG. 7) “Semiconductor Great Dictionary”, Industrial Research Council, December 20, 1999, p529

  In the conventional method for manufacturing a semiconductor device described above, when P ions are implanted into the bottom of the trench, the P ions are scattered or channeled at the sidewall of the trench and enter the semiconductor substrate, thereby deteriorating the characteristics of the transfer gate transistor. There is.

  Therefore, it becomes difficult to shorten the distance between the trench capacitor and the transfer gate transistor of the adjacent cell, which hinders high integration.

  The present invention has been made to solve the above problems, and prevents P ions from entering the channel region of the transfer gate transistor to prevent deterioration of the characteristics of the transfer gate transistor, which is suitable for high integration. An object is to provide a method for manufacturing a semiconductor device.

  In order to achieve the above object, in a method of manufacturing a semiconductor device according to an aspect of the present invention, a plate diffusion region is formed on an outer surface of a lower portion of a trench provided in a predetermined region in a semiconductor substrate of one conductivity type, and the inner wall of the trench is formed. Forming a capacitor insulating film in the trench, and embedding the storage node conductive film in the trench through the capacitor insulating film; and extending the storage node conductive film and the capacitor insulating film from the main surface of the semiconductor substrate to a predetermined depth Etch back to expose a part of the sidewall of the trench, cover the exposed sidewall of the trench with a color insulating film, and reverse conductivity type from the main surface of the semiconductor substrate to a predetermined depth in the trench Burying a first conductive film containing the first impurity, and ion-implanting the second impurity of the opposite conductivity type into the first conductive film. Forming a region; removing the collar insulating film to expose a side surface of the second impurity region; and burying a second conductive film containing the first impurity in the trench to form the second impurity. Forming a buried strap having a second conductive film on a side surface of the region; forming an element isolation region in a predetermined region in the semiconductor substrate; heat-treating the semiconductor substrate; Diffusing the first impurity and the second impurity of the second impurity region from the side wall of the trench not covered with the color insulating film into the semiconductor substrate to form first and second impurity diffusion regions; A transfer gate transistor for reading information stored in the capacitor such that a source or drain region partially overlaps the first and second impurity diffusion regions It is characterized by a step of forming.

  According to the method for manufacturing a semiconductor device of the present invention, the sidewall of the trench is covered with the insulating film, and the impurity ions are implanted into the bottom of the trench. Can be prevented from entering.

  As a result, even if the DRAM cell is highly integrated, the characteristics of the transfer gate transistor can be prevented from being deteriorated. Therefore, a semiconductor device with high reliability and high integration can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIGS. 1 to 11 are diagrams showing a manufacturing process of the semiconductor device according to the first embodiment of the present invention, and a process of electrically connecting the storage node electrode of the trench capacitor of the semiconductor device and the diffusion layer of the transfer gate transistor. It is sectional drawing shown in order.

  First, the steps until the storage node electrode of the trench capacitor is formed will be described with reference to FIGS.

  As shown in FIG. 1, a silicon oxide film 12 is formed on the surface of a semiconductor substrate, for example, a p-type silicon substrate 11, by a thermal oxidation method, for example, to a thickness of about 8 nm. Then, a silicon nitride film 13 is formed on the upper surface of the silicon oxide film 12 to a thickness of about 220 nm by, for example, a CVD method. Further, a TEOS film 14 is formed on the upper surface of the silicon nitride film 13 with a thickness of about 200 nm by, for example, a CVD method.

  Next, the trench opening is patterned by photolithography, and the TEOS film 14, the silicon nitride film 13, and the silicon oxide film 12 are etched into a predetermined shape by anisotropic etching, for example, RIE, to form a p-type silicon substrate 11 Expose part of the top surface of.

  Next, the p-type silicon substrate 11 is etched by anisotropic etching using the TEOS film 14 as a mask. Thereby, for example, a trench 15 having a depth of about 8 to 9 μm is formed.

  Next, as shown in FIG. 2, a silicon oxide film containing an impurity of a conductivity type opposite to that of the p-type silicon substrate 11, for example, an AsSG film (not shown) is formed on the entire surface by a CVD method, for example, to a thickness of about 30 nm. Further, a resist (not shown) is applied.

  Next, the AsSG film exposed after removing the resist to a predetermined depth by, for example, the CDE method is removed by using, for example, a hydrofluoric acid-based etchant, and the resist is removed by, for example, an ashing method.

  Next, heat treatment is performed at 900 ° C., for example, and As is diffused into the p-type silicon substrate 11 from the AsSG film, the buried plate diffusion region 16 to be a plate electrode is formed.

  Next, the AsSG film is removed by etching, for example, with a solution containing hydrofluoric acid, thereby completing the plate forming step.

  Next, as shown in FIG. 3, a composite film of silicon nitride film and silicon oxide film or a dielectric film having a thickness of about 5 nm is formed as a capacitor insulating film 17 on the entire surface including the inner wall of the trench 15 by, for example, the CVD method. To do.

  Next, a conductive film 18 serving as a storage node electrode, for example, a polysilicon film doped with As by a CVD method is embedded in the trench 15.

  Next, as shown in FIG. 4, the embedded storage node conductive film 18 is removed from the surface of the semiconductor substrate 11 to a predetermined depth by etching, for example, by RIE, and the exposed capacitor insulating film 17 is removed by, for example, phosphorous. Etching is performed using a solution of acid or the like.

  Next, a thick color insulating film 19 for electrically insulating the buried plate diffusion region 16 and the diffusion layer (not shown) of the transfer gate transistor, for example, a silicon oxide film having a thickness of about 40 nm is formed by CVD.

  Next, as shown in FIG. 5, the color insulating film 19 deposited on the storage node conductive film 18 is removed by etching, for example, by RIE, and then the first conductive film 20, for example, an As-doped polythincon film. Is buried in the trench 15, and the buried first conductive film 20 is removed from the surface of the semiconductor substrate 11 to a predetermined depth by, for example, RIE.

  Thus, the sidewall of the trench 15 can be covered with the thick collar insulating film 19 from the surface of the semiconductor substrate 11 to the upper portion of the storage node conductive film 18.

  Next, a process of forming a buried strap for electrically connecting the storage node conductive film 18 to the diffusion layer of the transfer gate transistor will be described with reference to FIGS.

  As shown in FIG. 6, P ions are implanted into the first conductive film 20 by, for example, accelerating voltage of 5 to 20 KeV and a dose of about 1E12 to 1E13 cm −2 to form a P ion implantation region 21.

  At this time, the thick collar insulating film 19 can prevent P ions from being scattered or channeled on the side wall of the trench 15 and entering the semiconductor substrate 11.

  Next, as shown in FIG. 7, the color insulating film 19 is removed to a depth at which the P ion implantation region 21 is exposed using, for example, a hydrofluoric acid-based etchant, and then the second conductive film 22, for example, As by CVD. A polysilicon film doped with is embedded in the trench 15.

  Next, as shown in FIG. 8, the buried second conductive film 22 is removed from the surface of the semiconductor substrate 11 to a predetermined depth by etching, for example, by the RIE method. Thereby, the embedded strap 23 is formed.

  Next, a process of forming the transfer gate transistor and connecting the diffusion layer of the transfer gate transistor and the storage node electrode will be described with reference to FIGS.

  9 is a plan view showing the DRAM cell, FIG. 10 is a cross-sectional view taken along the line AA in FIG. 9 and viewed from the direction of the arrow, and FIG. 11 is cut along the line BB in FIG. It is sectional drawing seen from the direction of the arrow.

  As shown in FIGS. 9 to 11, an element isolation region 24 having an STI (Shallow Trench Insulation) structure is embedded in a silicon oxide film by, for example, a CVD method to isolate individual DRAM cells.

  Next, the semiconductor substrate 11 is heat-treated at, for example, 1000 ° C. to activate the ion-implanted P, and As is diffused into the semiconductor substrate 11 from the side wall of the trench 15 not covered with the color insulating film 19. A region 26 in which the regions 25 and P are diffused deeper into the semiconductor substrate 11 is formed.

  As a result, an n-type double diffusion layer structure composed of a low concentration region and a high concentration region is formed, so that the electric field in the vicinity of the junction can be relaxed.

  Next, a gate oxide film 27 is formed in a region where the transfer gate transistor is to be formed, and a word line electrode 28 serving as a gate electrode is formed on the gate oxide film 27.

  Next, after a diffusion layer 29 to be a source or drain region is formed by, for example, P ion implantation, a surface protective film 30, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 11 by a CVD method.

  Next, a bit line contact electrode 31 and a bit line electrode 32 are formed through the surface protective film 30 to manufacture a semiconductor device.

  As described above, according to the manufacturing method of the semiconductor device of this embodiment, the sidewalls of the trench 15 are covered with the thick collar insulating film 19 and P is ion-implanted into the first conductive film 20, so that P ions Can be prevented from being scattered or channeled on the side wall of the trench 15 and entering the semiconductor substrate 11.

  Thereby, even if the DRAM cell is highly integrated, it is possible to prevent the deterioration of the characteristics of the transfer gate transistor. Therefore, a semiconductor device with high reliability and high integration can be obtained.

  12 to 14 are diagrams showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention for electrically connecting the storage node electrode of the trench capacitor of the semiconductor device and the diffusion layer of the transfer gate transistor. It is sectional drawing which shows the process of forming an embedding strap in order.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and only different portions are described.

  This embodiment is different from the first embodiment in that an insulating film covering the sidewall of the trench 15 is newly formed, and the thickness of the insulating film is set to a thickness sufficient to prevent P ion scattering or channeling. There is.

  That is, as shown in FIG. 12, after the steps shown in FIGS. 1 to 5, the color insulating film 19 is removed from the upper end surface of the first conductive film 20 to a predetermined depth.

  Next, a protective insulating film 41, for example, a silicon oxide film is formed in the trench 15 by CVD, and the protective insulating film 41 deposited on the first conductive film 20 is removed by etching, for example, by RIE. Then, the sidewall of the trench 15 is covered.

  Here, the protective insulating film 41 has a thickness that can prevent the ion-implanted P from impinging on the side wall of the trench 15 and scattering or channeling to enter the semiconductor substrate 11. There is an advantage that it can be appropriately set according to the manufacturing conditions.

  Next, as shown in FIG. 13, P ions are implanted into the first conductive film 20 at an acceleration voltage of 5 to 20 KeV and a dose of about 1E12 to 1E13 cm −2 to form a P ion implantation region 42.

  At this time, the protective insulating film 41 can prevent P ions from being scattered or channeled on the side wall of the trench 15 and entering the semiconductor substrate 11.

  Next, as shown in FIG. 14, after setting the etching rate of the protective insulating film 41 to be higher than the etching rate of the color insulating film 19 and removing the protective insulating film 41 by, for example, RIE, The second conductive film 43 is formed in the trench 15 by, for example, the CVD method, and the buried strap 44 is formed.

  Next, as shown in FIGS. 9 to 11, after forming the element isolation region 24 by STI, a transfer gate transistor is formed to manufacture a semiconductor device.

  As described above, according to the method for manufacturing a semiconductor device according to the second embodiment of the present invention, the collar insulating film 19 is removed and the sidewall of the trench 15 is newly covered with the protective insulating film 41. The thickness can be appropriately set according to the manufacturing conditions of the semiconductor device so that the thickness is sufficient to prevent the penetration of P ions.

  Thereby, even if the DRAM cell is highly integrated, it is possible to prevent the deterioration of the characteristics of the transfer gate transistor. Therefore, a semiconductor device with high reliability and high integration can be obtained.

  FIGS. 15 to 17 are views showing a manufacturing process of the semiconductor device according to the third embodiment of the present invention, and are embedded for electrically connecting the storage node electrode of the trench capacitor of the semiconductor device and the diffusion layer of the transfer gate transistor. It is sectional drawing which shows the process of forming a strap in order.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and only different portions are described.

  This embodiment differs from the first embodiment in that an embedded strap is formed in the vicinity of the substrate surface.

  That is, as shown in FIG. 15, after the steps shown in FIGS. 1 to 5, after the upper portion of the collar insulating film 19 is removed, the trench 15 is doped with the second conductive film 51, for example, As by CVD. The buried polysilicon film is embedded.

  Next, as shown in FIG. 16, after the second conductive film 51 is removed to a predetermined depth near the surface of the semiconductor substrate 11, a protective insulating film 52, for example, a silicon oxide film is formed in the trench 15 by a CVD method.

  Next, as shown in FIG. 17, after removing the protective insulating film 52 deposited on the second conductive film 51 using, for example, a hydrofluoric acid-based etchant, P ions are applied to the second conductive film 51, for example. The P ion implantation region 53 is formed by implantation at a low acceleration voltage of about 50 KeV. Thereby, the embedded strap 54 is formed.

  At this time, the protective insulating film 52 can prevent P ions from being scattered or channeled on the side wall of the trench 15 and entering the semiconductor substrate 11.

  Next, as shown in FIGS. 9 to 11, after forming the element isolation region 24 by STI, a transfer gate transistor is formed to manufacture a semiconductor device.

  As described above, according to the method for manufacturing a semiconductor device according to the third embodiment of the present invention, the buried strap is formed near the surface of the semiconductor substrate. This facilitates contact with the diffusion layer of the transfer gate transistor.

  Thereby, even if the DRAM cell is highly integrated, it is possible to prevent the deterioration of the characteristics of the transfer gate transistor. Therefore, a semiconductor device with high reliability and high integration can be obtained.

  FIGS. 18 to 20 are views showing a manufacturing process of the semiconductor device according to the fourth embodiment of the present invention, for electrically connecting the storage node electrode of the trench capacitor of the semiconductor device and the diffusion layer of the transfer gate transistor. It is sectional drawing which shows the process of forming an embedding strap in order.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and only different portions are described.

  The present embodiment is different from the first embodiment in that the side wall of the trench 15 is not covered with an insulating film, and the influence of P that has entered the semiconductor substrate 11 is obtained by implanting P ions after obliquely implanting B ions. Is compensated by B.

  18 is a plan view showing the DRAM cell, and FIGS. 19 and 20 are cross-sectional views taken along the line CC of FIG. 18 and viewed from the direction of the arrows.

  That is, as shown in FIGS. 18 to 19, after the steps shown in FIGS. 1 to 5, the upper portion of the collar insulating film 19 is removed from the surface of the semiconductor substrate 11 to a predetermined depth, and then into the trench 15. A second conductive film 61, for example, a polysilicon film doped with As by a CVD method is formed, and the second conductive film 61 is embedded from the surface of the semiconductor substrate 11 to a predetermined depth.

  Next, B ions are obliquely implanted into the trench 15 from two directions by tilting the ion beam by a predetermined angle θ from the vertical to the direction of the CC line where the word line electrode 28 is wired. B ions may be implanted by inclining the semiconductor substrate 11 by a predetermined angle θ, for example, 45 degrees, and implanting B ions, and then rotating the semiconductor substrate 11 180 degrees to inject B ions.

  As a result, the B ion implantation region 62 is formed in the second conductive film 61, and the sidewall of the trench 15 is not covered with the insulating film, so that the B ion implantation region 63 is simultaneously formed in the semiconductor substrate 11.

  Next, as shown in FIG. 20, when P is ion-implanted, a B + P ion-implanted region 64 in which P ions are further double-implanted into the B ion-implanted region 62 is formed in the second conductive film 61, thereby A strap 65 is formed.

  Since the sidewall of the trench 15 is not covered with an insulating film, P penetrates into the semiconductor substrate 11 due to scattering or channeling on the sidewall of the trench 15, and a P ion scattering region 66 is formed.

  Here, since the P ion scattering region 66 is included in the B ion implantation region 63, the B dose amount of the B ion implantation region 63 is set to be larger than the P dose amount of the P ion scattering region 66. , P can be compensated by B.

  Next, as shown in FIGS. 9 to 11, after forming the element isolation region 24 by STI, a transfer gate transistor is formed to manufacture a semiconductor device.

  As described above, according to the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention, since P ions are implanted after obliquely implanting B ions into the trench 15, P is introduced into the semiconductor substrate 11. Even if it penetrates, the influence of P can be compensated by B, and an insulating film covering the side wall of the trench 15 is unnecessary.

  Thereby, even if the DRAM cell is highly integrated, it is possible to prevent the deterioration of the characteristics of the transfer gate transistor. Therefore, a semiconductor device with high reliability and high integration can be obtained.

  Although the case where P ions are implanted after obliquely implanting B ions has been described here, B ions may be implanted obliquely after P ions are implanted.

Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 1 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 2 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 3 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 3 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 3 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 4 of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device concerning Example 4 of this invention. Sectional drawing which shows the manufacturing process of the conventional semiconductor device. The figure for demonstrating the method of relieving the electric field of a joining interface by a double diffused structure. Sectional drawing which shows the process of ion-implanting into a trench.

Explanation of symbols

11 p-type silicon substrate 12 silicon oxide film 13 silicon nitride film 14 TEOS film 15 trench 16 buried plate diffusion region 17 capacitor insulating film 18 storage node conductive film 19 color insulating film 20 first conductive film 21, 42, 53 P ion implantation region 22, 43, 51, 61 Second conductive film 23, 44, 54, 65 Buried strap 24 Element isolation region 25 As diffusion region 26 P diffusion region 27 Gate oxide film 28 Word line electrode 29 Source or drain diffusion layer 30 Surface protective film 31 Bit line contact electrode 32 Bit line electrodes 41 and 52 Protective insulating films 62 and 63 B ion implantation region 64 B + P ion implantation region 66 P ion scattering region

Claims (5)

A plate diffusion region is formed on the outer surface of the lower portion of the trench provided in a predetermined region in a semiconductor substrate of one conductivity type, a capacitor insulating film is formed on the inner wall of the trench, and a storage node is interposed in the trench via the capacitor insulating film. Embedding a conductive film;
Etching back the storage node conductive film and the capacitor insulating film from the main surface of the semiconductor substrate to a predetermined depth to partially expose the trench sidewalls;
Coating the exposed sidewall of the trench with a color insulating film;
Burying a first conductive film containing a first impurity of opposite conductivity type from the main surface of the semiconductor substrate to a predetermined depth in the trench;
Forming a second impurity region by ion-implanting the second impurity of the opposite conductivity type into the first conductive film;
Removing the color insulating film to expose a side surface of the second impurity region;
Burying a second conductive film containing the first impurity in the trench to form a buried strap having a second conductive film on a side surface of the second impurity region;
Forming an element isolation region in a predetermined region in the semiconductor substrate;
Heat-treating the semiconductor substrate to diffuse the first impurity of the second conductive film and the second impurity of the second impurity region into the semiconductor substrate from the side wall of the trench that is not covered with the color insulating film. Forming first and second impurity diffusion regions;
Forming a transfer gate transistor for reading information stored in the capacitor such that a source or drain region partially overlaps the first and second impurity diffusion regions;
A method for manufacturing a semiconductor device, comprising: A plate diffusion region is formed on the outer surface of the lower portion of the trench provided in a predetermined region in a semiconductor substrate of one conductivity type, a capacitor insulating film is formed on the inner wall of the trench, and a storage node is interposed in the trench via the capacitor insulating film. Embedding a conductive film;
Etching back the storage node conductive film and the capacitor insulating film from the main surface of the semiconductor substrate to a predetermined depth to partially expose the trench sidewalls;
Coating the exposed sidewall of the trench with a color insulating film;
Burying a first conductive film containing a first impurity of opposite conductivity type from the main surface of the semiconductor substrate to a predetermined depth in the trench;
Removing the collar insulating film from the main surface of the semiconductor substrate to the upper side surface of the first conductive film to expose the upper side surface of the first conductive film;
Covering the exposed sidewall of the trench with a protective insulating film;
Forming a second impurity region by ion-implanting the second impurity of the opposite conductivity type into the first conductive film;
Removing the protective insulating film to expose a side surface of the second impurity region;
Burying a second conductive film containing the first impurity in the trench to form a buried strap having a second conductive film on a side surface of the second impurity region;
Forming an element isolation region in a predetermined region in the semiconductor substrate;
Heat-treating the semiconductor substrate to diffuse the first impurity of the second conductive film and the second impurity of the second impurity region into the semiconductor substrate from the side wall of the trench that is not covered with the color insulating film. Forming first and second impurity diffusion regions;
Forming a transfer gate transistor for reading information stored in the capacitor so that a source or drain region partially overlaps the first and second impurity diffusion regions;
A method for manufacturing a semiconductor device, comprising: A plate diffusion region is formed on the outer surface of the lower portion of the trench provided in a predetermined region in a semiconductor substrate of one conductivity type, a capacitor insulating film is formed on the inner wall of the trench, and a storage node is interposed in the trench via the capacitor insulating film. Embedding a conductive film;
Etching back the storage node conductive film and the capacitor insulating film from the main surface of the semiconductor substrate to a predetermined depth to partially expose the trench sidewalls;
Coating the exposed sidewall of the trench with a color insulating film;
Burying a first conductive film containing a first impurity of opposite conductivity type from the main surface of the semiconductor substrate to a predetermined depth in the trench;
Removing the color insulating film above the first conductive film;
Burying a second conductive film containing the first impurity of the opposite conductivity type from the first conductive film to a predetermined position in the trench;
Covering the periphery of the upper surface of the second conductive film and the sidewall of the trench with a protective insulating film;
Forming a second impurity region by ion-implanting the second impurity of the opposite conductivity type into the exposed portion of the upper surface of the second conductive film;
Removing the protective insulating film;
Forming an element isolation region in a predetermined region in the semiconductor substrate;
Heat-treating the semiconductor substrate to diffuse the first impurity of the second conductive film and the second impurity of the second impurity region into the semiconductor substrate from the side wall of the trench that is not covered with the color insulating film. When,
Forming a transfer gate transistor for reading information stored in the capacitor such that a source or drain region partially overlaps the diffusion region of the first and second impurities;
A method for manufacturing a semiconductor device, comprising: A plate diffusion region is formed on an outer surface of a lower portion of a trench provided in a predetermined region in a semiconductor substrate of one conductivity type, a capacitor insulating film is formed on the inner wall of the trench, and storage is performed in the trench via the capacitor insulating film. Embedding a node conductive film;
Etching back the storage node conductive film and the capacitor insulating film from the main surface of the semiconductor substrate to a predetermined depth to partially expose the trench sidewalls;
Coating the exposed sidewall of the trench with a color insulating film;
Burying a first conductive film containing a first impurity of opposite conductivity type from the main surface of the semiconductor substrate to a predetermined depth in the trench;
Removing the color insulating film above the upper surface of the first conductive film;
Burying a second conductive film containing the first impurity of the opposite conductivity type from the first conductive film to a predetermined position in the trench;
Ion-implanting the first conductivity type impurity into the second conductive film from a direction oblique to the main surface of the semiconductor substrate;
Ion-implanting the second impurity of the opposite conductivity type into the second conductive film from a direction perpendicular to the main surface of the semiconductor substrate;
Forming an element isolation region in a predetermined region in the semiconductor substrate;
The semiconductor substrate is heat-treated, and the first conductive type impurity, the first and second impurities of the second conductive film are diffused into the semiconductor substrate from the side wall of the trench that is not covered with the color insulating film. And forming a second impurity diffusion region;
Forming a transfer gate transistor for reading information stored in the capacitor so that a source or drain region partially overlaps the first and second impurity diffusion regions;
A method for manufacturing a semiconductor device, comprising:   4. The method of manufacturing a semiconductor device according to claim 2, wherein the protective insulating film covering the sidewall of the trench is a silicon oxide film.

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