JP2005184654A - Current mirror circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a current mirror circuit whose operating speed can be increased while its power consumption is reduced. <P>SOLUTION: A current distribution circuit 1 for current distribution whose distribution factor can be arbitrarily set according to the resistance ratio with respect to a resistor of the current mirror circuit and which can be separated by a switch SW1 having a construction similar to a current receiving part of the current mirror circuit is connected with a connection point A between a current source and the current receiving part of the current mirror circuit. A load resistor R7 is constituted so that it can be separated by a SW2 for changing the resistance value of a load resistor R4 according to the current distribution ratio for maintaining a reference voltage Vref which is determined by the product of a current I3 mirrored by the current mirror circuit and the load resistor R4 constant in each mode where the current distribution circuit 1 is turned on or off. In this way, its high-speed recovery time can be realized while its power consumption is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention has a mode switching function including a low power consumption mode in a semiconductor integrated circuit, and a current corresponding to a fast recovery time (hereinafter referred to as a fast recovery time) at the time of mode switching and a fast recovery time with low power consumption. The present invention relates to a mirror circuit.

  A conventional low power consumption current mirror circuit will be described below.

  FIG. 3 shows a configuration diagram of a conventional current mirror circuit with a low power consumption function. In FIG. 3, reference numeral 2 denotes a current source, 3 denotes an amplifier, C1 denotes oscillation prevention of the current mirror circuit or parasitic capacitance attached to its node, and the current mirror circuit is generally well known. As shown in FIG. 3, the current source 2, the current receiving part of the current mirror circuit, and the parasitic capacitor C1 are connected, and further, in the low power consumption mode, the current of the current source 2 is supplied from the VCC without going through the current mirror circuit. One end of the SW (switch) 3 is connected, and the other end of SW3 is connected to VCC.

  A load resistor R6 for current / voltage conversion is connected between the collector and the ground (GND) of the transistor Q3 that outputs the mirrored current, and the voltage Vref converted by the load resistor R6 is used as a reference voltage of the amplifier 3. Used.

  The operation will be described below. SW3 is turned on / off by the control signal Vctrl. When SW3 is on, the potential at point A in FIG. 3 which is the current receiving part of the current mirror circuit is shorted to VCC, so that the current I0 of the current source 2 is All are supplied from VCC without going through the current mirror circuit.

  That is, I1 = 0 and the current in the SW3 portion is I2 = I0. At this time, since the mirror current I3 of the current mirror circuit becomes zero, the reference voltage of the input of the amplifier 3 is Vref = I3 × R6, and since I3 = 0, Vref = 0 and at the same time the amplifier 3 It becomes a non-operation state.

  Next, when SW3 changes to OFF mode, the current becomes zero at SW3, the current of the current mirror circuit becomes I0, and when the mirror ratio is considered as 1, I3 = I0 and Vref = I3 × R6 is restored. The amplifier 3 also operates as a normal amplifier.

  However, such a conventional configuration has a drawback in that the recovery time is slow when high speed recovery time (operation recovery time) at the time of mode switching is required. The operation will be described below.

  FIG. 4 is a timing chart showing the operations (a) to (g) of the conventional low power consumption type current mirror circuit shown in FIG. Here, for simplification of the operation description, it is assumed that the transistors Q1 and Q2 perform a switching operation (that is, a current flows only when the voltage VA at the point A reaches a certain value).

  First, FIG. 4A shows a control signal Vctrl of SW3, and SW3 inputs switching from on to off. As shown in FIG. 4B, after SW3 is switched from on to off, I1 is switched from zero to I0. Further, the potential at point A in FIG. 3 starts from VCC, and the charge stored in the parasitic capacitance C1 is discharged by the current I1. The discharge voltage until the potential at the point A becomes a constant value, that is, the voltage difference ΔVA between the initial value and the constant value is expressed by (Equation 1).

図４（ｃ）にＶＡのタイミングを示す。図４（ｄ）はカレントミラー回路の電流受部の電流Ｉ４であり、ＳＷ３がオフしてから電圧ＶＡが前述のとおり一定値になった時点で電流が流れＩ４＝Ｉ０となる。図４（ｅ）はミラーされた電流Ｉ３で、ここではミラー比を１と仮定してＩ３＝Ｉ４＝Ｉ０となる。図４（ｆ）にアンプ３の各入力を示す。Ｖrefは電流Ｉ３と抵抗Ｒ６の積で決まりアンプの基準電圧として働く、一方ＶＩＮは入力電圧であり任意の波形が入力される。本説明では解りやすくするために正弦波の入力とした。

FIG. 4C shows the timing of VA. FIG. 4D shows the current I4 of the current receiving portion of the current mirror circuit. When the voltage VA becomes a constant value as described above after SW3 is turned off, the current flows and I4 = I0. FIG. 4 (e) shows the mirrored current I3, where I3 = I4 = I0 assuming a mirror ratio of 1. FIG. 4F shows each input of the amplifier 3. Vref is determined by the product of the current I3 and the resistor R6, and serves as a reference voltage for the amplifier. On the other hand, VIN is an input voltage and an arbitrary waveform is input. In this description, a sine wave input is used for easy understanding.

  FIG. 4G shows the output of the amplifier 3, and the output signal begins to be output after the voltage Vref in the waveform of FIG. 4F has recovered to the original operating voltage. In FIG. 4G, t2 is the recovery time, and the determining factor is the recovery time of the voltage at the point A. This time is determined by the parasitic capacitance C1, the current I0, and the voltage difference ΔVA, and is expressed by (Expression 2).

本来はもっと複雑な式となるが本説明の目的は動作説明であるため前述のとおり簡素化のためＱ１及びＱ２はスイッチング動作を行うと仮定している。

Originally, the equation is more complicated, but the purpose of this description is to explain the operation. Therefore, it is assumed that Q1 and Q2 perform a switching operation for the sake of simplification as described above.

  As a result, the recovery time t2 determined by the voltage difference ΔVA becomes a large recovery time in a circuit that requires a fast recovery time.

  In addition, as one of the possible solutions for speeding up the recovery time, the speed can be increased by eliminating the SW3 and allowing the current to flow constantly through the current mirror circuit, but it has the disadvantage that the power consumption cannot be reduced. .

  The present invention is directed to solving the problems of the prior art, and an object of the present invention is to provide a current mirror circuit capable of speeding up while reducing power consumption.

  In order to achieve this object, the current mirror circuit of the present invention is a current mirror circuit that mirrors the current of the current source, and the resistance of the current mirror circuit is connected to the connection point between the current receiving portion of the current mirror circuit and the current source. The first current distribution means that can be separated by a first switch having the same configuration as the current receiving part of the current mirror circuit is provided for the purpose of current distribution in which the distribution ratio is arbitrarily set by the resistance ratio of A first load resistor for the purpose of current-voltage conversion is connected between the transistor that outputs the current mirrored by the mirror circuit and the ground, and the reference voltage generated by the first load resistor is set to a constant value in each mode. The second switch that varies the resistance value of the first load resistor according to the current distribution ratio is connected to one end of the first load resistor and the transistor. The other end is connected to a second load resistor whose other end is grounded, and the reference voltage is set to the same voltage regardless of whether each mode is on / off of the current distribution means by the first switch. It is characterized by that.

  According to the above configuration, the current of the current source is distributed by the current mirror circuit and the first switch at a distribution ratio arbitrarily set by the resistance ratio of the current mirror circuit, and the current of the current mirror circuit is reduced rather than eliminated. At the same time, the load resistance of the reference voltage is switched according to the current distribution ratio, and the reference voltage is kept almost constant without depending on the on / off mode of the current distribution means while reducing the current. Low power consumption and fast recovery time can be realized.

  As described above, according to the present invention, in the low power mode, the current mirror circuit is turned on rather than turned off by reducing the current of the current mirror circuit to zero. The recovery time can be realized at the same time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a configuration diagram showing a current mirror circuit corresponding to a fast recovery time with low power consumption in an embodiment of the present invention. Here, components having substantially the same functions corresponding to the components described in FIG. 3 showing the conventional example are denoted by the same reference numerals.

  In FIG. 1, 1 is a current distribution circuit of current distribution means, 2 is a current source, 3 is an amplifier, C1 is an oscillation prevention of a current mirror circuit or a parasitic capacitance attached to its node. It is a known one.

  The current mirror circuit shown in FIG. 1 includes a general current mirror circuit for mirroring the current of the current source 2 and a resistance ratio of a load resistance of the current mirror circuit at a connection point between the current source 2 and the current mirror circuit. A current distribution circuit 1 that can be separated by a first SW 1 having the same configuration as that of the current receiving portion of the current mirror circuit is connected for the purpose of current distribution capable of arbitrarily setting the distribution ratio.

  Further, a transistor Q3 that outputs a mirrored current and a load resistor for current-voltage conversion are connected between the ground and the reference voltage generated by the first load resistor R4 is a constant value in each mode. One end of the second SW2 that varies the load resistance in accordance with the current distribution ratio is connected to a connection point between the first load resistance R4 and the transistor Q3. The other end of the second SW2 is connected to the second load resistor R7, and the other end of the second load resistor R7 is grounded, and the current distribution circuit 1 is turned on / off by the first SW. Even so, by switching the first and second load resistors R4 and R7 by the second SW2, the current mirror circuit is configured so that the reference voltage becomes the same voltage and low power consumption and fast recovery time It is.

  The operation of the current mirror circuit configured as described above and corresponding to the fast recovery time with low power consumption will be described.

  SW1 ON / OFF control and SW2 OFF / ON control are performed by the control signal Vctrl. When SW1 is ON, SW2 is OFF, and the current I1 of the current receiving part of the current mirror circuit and the current I2 of the current distribution circuit 1 are The ratio is determined by the ratio of the resistor R1 and the resistor R5 when Vbe of the transistor is approximated by a constant voltage, and is expressed by (Expression 3) and (Expression 4).

さらに、この時ＳＷ２はオフ状態にあるため電圧Ｖrefの決定要因の負荷抵抗はＲ４となり、電流Ｉ３は定常状態でＩ１＝Ｉ４＝Ｉ３であるためＶrefは（数５）で表される。

Furthermore, since SW2 is in the off state at this time, the load resistance that determines the voltage Vref is R4, and the current I3 is steady and I1 = I4 = I3. Therefore, Vref is expressed by (Equation 5).

次に、ＳＷ１はオフ、ＳＷ２がオンの状態を考えると、電流源３の電流はすべてカレントミラー回路に流れるためＩ１＝Ｉ４＝Ｉ０となる。また、負荷抵抗はＳＷ２がオン状態のためＲ４とＲ７の並列抵抗をなりＶrefは（数６）で表される。

Next, considering the state in which SW1 is off and SW2 is on, all the current from the current source 3 flows through the current mirror circuit, so that I1 = I4 = I0. The load resistance is a parallel resistance of R4 and R7 because SW2 is on, and Vref is expressed by (Equation 6).

この２つの状態の電圧Ｖrefが同じ電圧となるようなＲ１とＲ５、Ｒ４とＲ７の比を決定することで各モードにおいて同電位にすることができる。

By determining the ratios of R1 and R5 and R4 and R7 so that the voltages Vref in the two states become the same voltage, the same potential can be obtained in each mode.

  FIG. 2 is a timing chart showing the operations (a) to (g) of the current mirror circuit shown in FIG. 1 in the present embodiment. It is assumed that the transistors Q1 and Q2 perform a switching operation (that is, a current flows only when the voltage VA at the point A reaches a certain value) for the sake of simplifying the operation description as in the conventional example described above.

  First, FIG. 2A is a control signal Vctrl of each SW, and SW1 is switched on and off and SW2 is switched on and off. As shown in FIG. 2B, after SW1 is switched from on to off, I1 is switched from the initial current to I0, and the potential at point A in FIG. 1 is expressed by (Equation 7) and (Equation 8). Start with the voltage

Ｃ１に蓄えられた電荷は電流Ｉ１によって放電される。このＡ点の電位が一定値になるところまでの放電電圧、すなわち初期値と一定値との電圧差ΔＶＡは（数９）で表される。

The charge stored in C1 is discharged by the current I1. The discharge voltage until the potential at the point A becomes a constant value, that is, the voltage difference ΔVA between the initial value and the constant value is expressed by (Equation 9).

図２（ｃ）にＡ点の電圧ＶＡのタイミングを示す。図２（ｄ）はカレントミラー回路の電流受部の電流Ｉ４でありＳＷ１がオフしてから電圧ＶＡが前述のとおり一定値になった時点で電流が流れＩ４＝Ｉ０となる。図２（ｅ）はミラーされた電流Ｉ３であり、ここではミラー比を１と仮定してＩ３＝Ｉ４＝Ｉ０となる。図２（ｆ）にアンプ３の各入力を示す。Ｖrefは電流Ｉ３とＳＷ２の状態によって決まる負荷抵抗の積で決まりアンプ３の基準電圧として働く、一方、ＶＩＮは入力電圧であり任意の波形が入力される。本説明では解りやすくするために正弦波の入力とした。

FIG. 2C shows the timing of the voltage VA at the point A. FIG. 2D shows the current I4 of the current receiving portion of the current mirror circuit. When SW1 is turned off and the voltage VA becomes a constant value as described above, the current flows and I4 = I0. FIG. 2 (e) shows the mirrored current I3. Here, assuming that the mirror ratio is 1, I3 = I4 = I0. FIG. 2F shows each input of the amplifier 3. Vref is determined by the product of the load resistance determined by the states of the currents I3 and SW2, and works as a reference voltage for the amplifier 3, while VIN is an input voltage and an arbitrary waveform is input. In this description, a sine wave input is used for easy understanding.

  FIG. 2G shows the output of the amplifier 3, and the output signal starts to be output after the voltage Vref in the waveform of FIG. In FIG. 2 (g), t1 is the recovery time, and the determining factor is the recovery time of the voltage at the point A. This time is determined by the parasitic capacitance C1, the current I0, and the voltage difference ΔVA, and is expressed by (Equation 10). .

本来はもっと複雑な式となるが本説明の目的は動作説明であるため前述のとおり簡素化のためＱ１及びＱ２はスイッチング動作を行うと仮定している。

Originally, the equation is more complicated, but the purpose of this description is to explain the operation. Therefore, it is assumed that Q1 and Q2 perform a switching operation for the sake of simplification as described above.

  Here, it is assumed that current, capacity, and resistance values are substituted and compared with the recovery time of the conventional example. For example, assuming that I0 = 100 μA, R1 = 1 KΩ, R5 = 9 KΩ, Vbe = 0.7 V, C1 = 10 pF, and ΔVA represented by (Equation 1) of the conventional example is substituted for ΔVAold, (Equation 11)

また、従来例の（数２）で表されたリカバリ時間ｔ２は（数１２）に代入すると、

Further, when the recovery time t2 represented by (Expression 2) in the conventional example is substituted into (Expression 12),

次に本実施の形態におけるリカバリ時間は、前述の（数９）で表されたΔＶＡをΔＶＡnewとする（数１３）に代入すると、

Next, the recovery time in the present embodiment is obtained by substituting ΔVA represented by the above (Equation 9) into ΔVAnew (Equation 13).

また、本実施の形態の（数１０）で表されたリカバリ時間ｔ１は（数１４）に代入すると、

Further, when the recovery time t1 represented by (Equation 10) of the present embodiment is substituted into (Equation 14),

となり、本計算における仮の定数でも従来例と比べ約７倍と早くなっていることが解る。また、ここではＳＷ１＝オン時のカレントミラー回路で消費される電流比はＩ１：Ｉ０＝１：１０となるように抵抗値の設定を行った。

Thus, it can be seen that the temporary constant in this calculation is about seven times faster than the conventional example. In addition, the resistance value is set so that the current ratio consumed by the current mirror circuit when SW1 = ON is I1: I0 = 1: 10.

  As described above, according to the present embodiment, it is possible to realize a fast recovery time while reducing power consumption.

  The current mirror circuit according to the present invention reduces the current mirror circuit current in the low power mode to simultaneously reduce power consumption and fast recovery time, and supports fast recovery time and low power consumption during mode switching. The current mirror circuit is useful as a semiconductor integrated circuit having a mode switching function including a low power consumption mode.

The block diagram which shows the current mirror circuit corresponding to high-speed recovery time with low power consumption in embodiment of this invention Timing chart showing the operations (a) to (g) of the current mirror circuit shown in FIG. Configuration diagram of conventional current mirror circuit with low power consumption function Timing chart showing operations (a) to (g) of the conventional low power consumption type current mirror circuit shown in FIG.

Explanation of symbols

1 Current distribution circuit 2 Current source 3 Amplifier

Claims (1)

  A current mirror circuit for mirroring a current of a current source, wherein a distribution ratio is arbitrarily set by a resistance ratio between a current receiving portion of the current mirror circuit and a resistance of the current mirror circuit at a connection point of the current source And a first current distribution means that can be separated by a first switch having the same configuration as the current receiving portion of the current mirror circuit, and outputs a current mirrored by the current mirror circuit A first load resistor for the purpose of current-voltage conversion is connected between the transistor and the ground, and the first load is set so that the reference voltage generated by the first load resistor becomes a constant value depending on each mode. A second switch that varies the resistance value of the resistor in accordance with the current distribution ratio has one end connected to the connection point between the first load resistor and the transistor, and the other end connected. The other end is connected to the second load resistor, and the first switch makes the reference voltage the same regardless of whether each mode is on or off of the current distribution means. Current mirror circuit.

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