JP2005078634A - Nonvolatile storage device and write method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To resolve the problem that write requires a long time due to difference between an external data management size and an internal data management size of a semiconductor memory card caused by an increase in the capacity of the semiconductor memory card. <P>SOLUTION: Partial physical blocks according with the external management size are used independently of a physical block size in a nonvolatile storage device. Data is written in a partial physical block unit, and erase blocks are secured in a physical block unit, so that the write speed is increased. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile memory device having a rewritable nonvolatile memory and a writing method thereof.

  A demand for a semiconductor memory having a rewritable nonvolatile memory is increasing as a memory card. The NAND flash memory, which is a non-volatile memory mainly used for the memory card, has used 16 KB as an erasing unit. Therefore, an external host device using a memory card uses a size of 16 KB as a writing management unit.

  However, in recent years, due to the increase in the capacity of memory cards, the capacity of built-in NAND flash memory has also increased, and accordingly, a NAND flash memory having an erase unit of 128 KB has been proposed. However, with respect to writing in 16 KB units from an external host device using a memory card, the controller inside the memory card handles it as 128 KB units, which is the erase unit of the NAND flash memory. There is a drawback that it takes time to write in 16 KB units.

  Next, a conventional semiconductor memory card will be described more specifically. FIG. 10 is a diagram showing a conventional memory card 100, which is provided with a controller 101 and flash memories FM0 to FM3 which are nonvolatile memories. Each of the flash memories FM0 to FM3 has a capacity of 128 MB, for example, and constitutes a 500 MB memory card as an effective data area. As shown in FIG. 10, the controller 101 includes a CPU 111, a temporary save buffer 112 having a capacity of 1KB, a data transfer buffer 113 having a capacity of 512B, an address conversion table 114 having a 12-bit 4K Word configuration, that is, a capacity of 6KB, And an entry table 115 having a capacity of 512 B in a 4K Word configuration with 1 bit.

  The flash memories FM0 to FM3 each have a capacity of 128 MB, as shown in FIG. As shown in FIG. 11A, each of the flash memories FM0 to FM3 is composed of 1024 physical blocks (PB0 to PB1023) each having a capacity of 128 KB. As a result, the total capacity of the nonvolatile memory of the memory card 100 is 512 MB, and the capacity that can be used as the data area by the host device 102 is 500 MB.

  FIG. 11B shows the configuration of one physical block PBi (i = 0 to 1023) in the flash memory. The physical block is composed of 64 physical pages from physical pages PP0 to PP63. As shown in FIG. 12, each physical page is composed of a data area having a capacity of 2 KB and a management area having a capacity of 64 B.

  The memory card 100 has a memory capacity of 500 MB as viewed from the external host device 102, and a logical address is assigned by a logical map as shown in FIG. That is, the 500 MB data area is divided into 4000 logical blocks (LB) from logical block 0 to logical block 3999, and each logical block has a capacity of 128 KB. This logical block address corresponds to an address designated by the host device.

  The address conversion table 114 shown in FIG. 10 specifies a flash memory and a physical block in the memory when a logical address indicating a logical group is given. Of these, the first 2 bits are bits indicating any one of the flash memories FM0 to FM3, and the subsequent 10 bits are bits indicating which physical block in the flash memory. The entry table 115 is a table composed of 1-bit flags corresponding to 4096 physical blocks. This flag is 1 if it has been erased and 0 if it has been written.

  Next, the data reading process will be described with reference to the schematic diagram of data reading in FIG. Of the logical addresses from the host device 102, an address in units of 128 KB is a logical block address, and an address less than 128 KB is a logical page address. A physical block is designated from the address conversion table 114 based on the logical block address, and this is set as a read source physical block. Then, the data of the logical page address of the read source physical block is read and transferred to the host device 102 via the data transfer buffer 113. Then, it is checked whether or not the reading is finished. If not finished, it is checked whether or not the logical page address is the last in the block. If it is not final, the logical page address is incremented and the same processing is repeated. If the logical page address is the last in the block, the logical page address is set to 0, the logical block address is incremented, and the same processing is repeated. In this way, data can be read from the designated logical address.

  Next, the writing process will be described with reference to the flowchart of FIG. When writing data, first, in step S301, among the logical addresses from the host device 102, addresses in 128 KB units are set as logical block addresses, and addresses less than 128 KB units are set as logical page addresses. In step S302, the entry table is searched to obtain an erased physical block as a write destination physical block. Then, the corresponding bit in the entry table 115 is updated to “0” written. Next, the process proceeds to step S303, where it is checked whether the logical page address is 0. If it is not 0, the first half winding process described later is performed (step S304). If the logical page address is 0, the process proceeds to step S305 without performing this process. move on. In step S305, write data from the host device is transferred to the flash memory via the page buffer, and written to the logical page address of the write destination physical block. At this time, management information for writing in the management area is written at the same time. In step S306, it is checked whether writing has been completed. If not, it is checked in step S307 whether the logical page address is the last in the block. If it is not final, the logical page address is incremented in step S308, and the process returns to step S305. If the logical page address is the last block, erase and table update are performed in step S309, the logical page address is incremented by 0 and the logical block address is incremented in step S310, and the process returns to step S302. If writing is completed in step S306, it is checked in step S311 whether the logical page address is the last in the block. If it is not final, the latter half of the entrainment process is performed in step S312, and if it is final in the block, the process proceeds to step S313 without performing this process, and erase and table update are performed to finish the process.

Thus, according to the conventional data writing method of the nonvolatile storage device, as shown in FIG. 16, the reading source physical block 120 is 128 KB, and new data 122 of 16 KB managed by the host device is written. However, the write destination physical block 121 performs writing in units of 128 KB. Of the read source physical block 120, the first half area 120-1 that is not written to the physical block is copied to the write destination physical block 121-1 of the flash memory by the first half winding process. Similarly, in the latter half area 120-2, the logical page addresses after the write page address are copied to the write destination physical block 121-2 by the latter half of the winding process. Therefore, according to the conventional data writing process, even if the data processing unit managed by the external host device is 16 KB as shown in FIG. 16, data is written in the physical block unit of the writing destination.
Issued by Transistor Technology Co., Ltd., “Interface” December 1999 issue, pages 108-119

  As described above, according to the conventional data writing method of the nonvolatile memory device, when writing data smaller than the erase size of the flash memory, the data equivalent to the erase size of the flash memory is written inside the memory card. There was a drawback that the speed was reduced.

  The present invention has been made in view of such a conventional problem, and enables writing at a high speed by reducing the unit of writing and by collecting written data. An object of the present invention is to secure an erased block so that the secured erased area can be easily written next.

  In order to solve this problem, the present invention is a non-volatile storage device that includes a non-volatile memory and a controller, and writes and reads data to and from the non-volatile memory based on a logical address given from outside. The nonvolatile memory is composed of a plurality of nonvolatile memory elements paired with each other, each nonvolatile memory is composed of a plurality of banks, each bank is composed of the same number of physical blocks, and each physical block is It is composed of a plurality of partial physical blocks, and from the outside, a logical address including a series of logical group addresses and a series of logical block addresses belonging to each logical group is given. A set of physical blocks selected one by one from the bank is defined as a physical block group, and its common part Address conversion having an address conversion area for writing a logical block at a logical block position and converting a logical group address among logical addresses given from the outside into a partial physical block address in which the logical block to which the logical group belongs is recorded A table, an entry table that indicates whether each physical block has been written or erased, and a valid data table that describes whether or not a logical block that constitutes a logical block group is valid data. When data and its logical address are given from the outside, the data is written in an unwritten area in units of partial physical block groups based on the valid data table, and the logical block belongs to the address conversion table Logical glue It is characterized in that to register the partial physical block, and updates the entry table and the valid data table for.

  Here, the controller searches the valid data table, sets a physical block with a small amount of valid data contained in the physical block as a to-be-erased physical block, and erases the logical block if there is no valid logical block in the to-be-erased physical block If there is a valid logical block, there may be provided an erase block securing means for securing an erase block by consolidating data of valid logical blocks into other physical blocks that have been erased.

  Here, the data capacity of the physical block group of the nonvolatile memory is equal to the data capacity of the logical group, and the data capacity of the partial physical block group is the data capacity of the logical block and the data outside the nonvolatile storage device. It may be equal to the management unit.

  According to the present invention having such characteristics, the writing unit at the time of data writing is made the same as the data writing unit used in the host device, and the erase unit of the nonvolatile memory in the memory card is increased in capacity. Even in the case of enlargement, data can be written in a short time as viewed from the external host device. Further, even when a part of the writing area is used, an effect that a writable area can be formed by performing the process of securing the erased block can be obtained.

  FIG. 1 is a block diagram showing a configuration of a memory card according to an embodiment of the present invention. As shown in the figure, the memory card 21 includes a controller 22 and a nonvolatile memory, for example, flash memories FM0 to FM3 having a capacity of 128 MB. The controller 22 includes a temporary save buffer 32 having a capacity of the CPU 31, 512B, a data transfer buffer 33 having a capacity of 512B, a 15-bit 4K Word configuration, that is, an address conversion table 34 having a 7.5 KB capacity, and a 1-bit 32K Word. , That is, an entry table 35 having a capacity of 4 KB and an 8 bit 4 KWord structure, that is, an effective data table 36 having a capacity of 4 KB.

  As shown in FIG. 2A, the flash memories FM0 to FM3 are configured by 8092 physical blocks PB0 to PB8191 each having a data capacity of 16 KB. One flash memory is composed of four banks 0 to 3, and each bank is composed of 2048 physical blocks. Bank 0 includes physical blocks PB0, PB4... PB8188 that are multiples of four. Bank 1 includes physical blocks that are multiples of 4 + 1, that is, PB1, PB5... PB8189, bank 2 includes physical blocks PB2, PB6. Includes physical blocks PB3, PB7... PB8191 that are multiples of 4 + 3.

  FIG. 2B shows the configuration of one physical block PBi (i = 0 to 8191) in the memory. Each physical block is composed of 32 physical pages, physical pages PP0 to PP31. Each physical page has a data capacity of 512B. This physical page is a data writing unit, and 4 pages, that is, 2 KB, is a partial physical block. One physical block includes eight partial physical blocks. The four flash memories 0 to 3 are paired with the flash memories FM0 and FM1, and FM2 and FM3 to form two groups. One erased physical block is selected from each of the eight banks included in each of these groups to form a physical block group composed of eight physical blocks.

  As in the first embodiment, logical blocks of logical blocks LB0 to LB32767 are configured for the logical groups LG0 to LG3999. The address translation table 34 specifies partial physical blocks with a 15-bit configuration for a logical group. Of these, 1 bit specifies a flash memory pair, 11 bits specify a physical block group, and 3 bits specify a partial physical block in a physical block of the first bank in the physical block group. Is a bit. In the second embodiment, since a plurality of physical blocks are grouped, this address table also shows only the head of the group. The entry table has a 1-bit, 32 KW configuration and indicates whether each physical block has been erased or written.

  FIG. 3 is a diagram showing a flash memory and a logical block formed thereon. The physical page of the physical block included in the physical block group is divided into eight partial physical blocks in units of four pages, partial physical blocks at the same position are taken out from each physical block, and these are used as one unit as a logical block. For example, for all the banks 0 to 3 of the flash memories FM0 and FM1, the physical pages PP0 to PP3 are taken out to form a logical block (LB). In other words, a logical block belongs to one physical block group, and consists of eight physical blocks. Four physical pages are selected from the physical blocks, that is, one partial physical block is selected, and relative physical pages within the physical block are selected. The position is the same. In this way, data of a certain logical block is written to the partial physical block group.

  The controller 22 writes and manages data in units of logical blocks. In order to aggregate valid data or erase invalid blocks, it is necessary to recognize whether valid data is written in logical block units or whether it is already invalid data. Therefore, the effective data table 36 has 1-bit information indicating whether the data of the logical group is valid or invalid with respect to the head of the logical group. FIG. 4 is a diagram showing the configuration of the effective data table 36. As shown in FIG. The head of the logical block exists only in the bank 0 of the flash memories FM0 and FM2. Accordingly, 1 word (8 bits) is assigned to all of the physical blocks 2 × 8K / 4 banks in the bank 0 of the flash memories FM0 and FM2, and 1 bit indicates whether each partial physical block in the physical block is valid data. Therefore, an erasure target can be found by selecting a word in which all the valid data tables are not 1.

  Here, the CPU 31 of the controller 22 searches the valid data table, sets a physical block with less valid data contained in the physical block as a to-be-erased physical block, and erases the logical block if there is no valid logical block in the to-be-erased physical block. If there is a valid logical block, it has a function of an erase block securing means for securing an erase block by aggregating data of valid logical blocks into another physical block that has been erased.

  Next, the operation of this embodiment will be described using a flowchart. First, when the power is turned on, the last write logical group address is set to an invalid value and the entry counter is set to zero. The entry counter is used to designate the position of the partial physical block in the physical block group. At the time of write processing, as shown in the flowchart of FIG. 5, among the logical addresses from the host device 3, 128 KB unit addresses are logical group addresses, 16 KB unit addresses are logical block addresses, and less than 16 KB unit addresses are logical page addresses. To do. In step S202, the partial physical block obtained from the address conversion table 34 based on the logical group address is set as a table partial physical block. In step S203, the address table of the table partial physical block is read and held. In step S204, a write destination determination process described later is performed. In step S205, an address corresponding to the logical block address in the address table held in the controller is held as a read-source partial physical block. In the second embodiment, since a plurality of physical blocks are grouped, this address table also shows only the head of the group. In step S206, the address corresponding to the logical block address in the address table held in the controller is replaced with the first partial physical block in the write destination partial physical block group. In step S207, it is checked whether the logical page address is 0. If it is not 0, the first half winding process step S208 is performed. If the logical page address is 0, the process proceeds to step S209, where the write data from the host device is transferred to the flash memory via the data transfer buffer 33 and written to the write destination partial physical block. At this time, management information to be written in the management area is also written at the same time. In the second embodiment, since writing is performed in parallel in eight blocks of two flash memories, writing processing can be performed at high speed.

  Then, in step S210 of FIG. 6, it is checked whether or not the writing has been completed. If not, the process proceeds to step S211 to check whether or not the writing up to the logical block boundary has been completed. If writing has not been completed up to the block boundary, the process returns to step S209 in FIG. 5 to repeat the same processing. If writing to the block boundary has been completed in step S211, the table is updated in step S212, and it is checked in step S213 whether the logical block address is the last in the logical group. If not final, the logical page address is incremented by 0 and the logical block address is incremented in step S214, and the process returns to step S204. If it is the last in the logical group, the logical page address is incremented by 0, the logical block address and the logical group address are incremented in step S215, and the process returns to step S202. On the other hand, if writing has been completed in step S210, it is checked in step S216 whether the logical page address is the last in the block. If it is not final, the second half entrainment process is performed in step S217. If it is final, the table is updated in step S218 and the process is terminated.

  FIG. 7 is a flowchart showing the write destination determination process in step S204. When this process is started, it is first checked in step S221 whether the logical group address is the same as the final group address. If they are the same, it is checked in step S222 if the entry counter is less than 8. If the logical group address is not the same as the last written logical group address or if the entry counter is 8 or more, the process proceeds to step S223 to check the free area. If there is no free area, an erase block securing process described later is performed in step S224. If there is a free area, the entry table is searched in step S225 to obtain an erased physical block group as a write destination physical block group. Then, the corresponding bit in the entry table is updated to “0” which has been written, and the entry counter is set to 0 (step S222). On the other hand, if the entry counter is less than 8 in step S222, the entry counter is incremented in step S227. In step S228, the write physical block group entry counter-th partial physical block group is set as a write destination partial physical block group.

  Next, the erase block securing process in step S224 will be described with reference to the flowchart of FIG. When the operation is started, first, in step S231, the effective data table is sequentially searched to obtain a physical block having the least effective data contained in the physical block and set as a first erasure scheduled block. Next, in step S232, it is checked whether or not a valid logical block is included in the first block to be erased. If there is no valid logical block, the first erase-scheduled physical block is erased in step S233, and the data corresponding to this erase-scheduled block in the entry table is updated to erased “1” in step S234. On the other hand, if there is a valid logical block included in the first block to be erased in step S232, the process proceeds to step S235. Then, the address table is read from the address conversion table based on the logical group of logical addresses written in the logical block included in the physical block. Next, in step S236, it is checked from the address table which physical block contains a valid logical block of the logical group, and the second to-be-erased physical block is sequentially ordered up to the eighth to-be-erased physical block. In this case, the minimum is only the first erase-scheduled physical block. In step S237, the entry table is searched to obtain an erased physical block, and the top partial physical block is set as a write destination physical block. Also, the corresponding bit of the entry table is updated to “0” which has been written. In step S238, data is copied from the address table to the write destination physical block based on the physical address of the valid logical block. As a result, data is aggregated to the aggregation destination. Next, in step S239, the to-be-erased physical blocks are sequentially erased from the first to the eighth to-be-erased physical block. As a result, distributed physical blocks can be erased. Next, the process proceeds to step S240, and the process of securing the erase block is performed by sequentially erasing “1” from the data corresponding to the first erase-scheduled physical block to the data corresponding to the maximum eighth erase-scheduled physical block in the entry table. Finish.

  Next, the table update processing in steps S212 and S218 will be described with reference to the flowchart of FIG. In the table update process, in step S251, the data of the logical group address in the address conversion table is rewritten to the first partial physical block of the write destination partial physical block group. In step S252, the process ends with the last write logical group address as the logical group address.

  It should be noted that the numerical values such as the data capacity in each embodiment described here are merely examples, and it goes without saying that other numerical values may be used.

  The present invention relates to a nonvolatile memory device having a rewritable nonvolatile memory and a writing method thereof, and the writing speed can be increased as compared with the conventional example even when the capacity is increased. Therefore, it can be used for various uses of a nonvolatile memory that requires a large capacity and high speed writing.

1 is a block diagram showing an overall configuration of a nonvolatile memory device according to an embodiment of the present invention. It is a figure which shows the structure of the flash memory by the embodiment, and its physical block. 1 is a diagram illustrating a flash memory and a logical block configured thereon according to an embodiment. FIG. It is a figure which shows an example of the effective data table by embodiment. It is a flowchart (the 1) which shows the data write-in process by embodiment. It is a flowchart (the 1) which shows the data write-in process by embodiment. It is a flowchart which shows the write-destination determination process by embodiment. It is a flowchart which shows the erasure block reservation process by embodiment. It is a flowchart which shows the table update process by embodiment. It is a figure which shows the structure of the conventional non-volatile memory. It is a figure which shows the structure of the conventional flash memory and its physical block. It is a figure which shows the structure of the logical page written in the conventional physical block. It is a figure which shows the structure of the conventional logic block. It is the schematic which shows the operation | movement at the time of the data reading of the conventional non-volatile memory. It is a flowchart which shows the data write-in process of the conventional non-volatile memory device. It is the schematic which shows the operation | movement at the time of the conventional data writing.

Explanation of symbols

21 Memory Card 21 Controller 31 CPU
32 Temporary save buffer 33 Data transfer buffer 34 Address conversion table 35 Entry table 36 Valid table FM0 to FM3 Flash memory

Claims (6)

Non-volatile memory;
A controller, and
A nonvolatile storage device that writes data to and reads data from the nonvolatile memory based on a logical address given from the outside,
The nonvolatile memory includes a plurality of nonvolatile memory elements paired with each other, each nonvolatile memory includes a plurality of banks, each bank includes the same number of physical blocks, and each physical block includes a plurality of Consisting of partial physical blocks,
From the outside, a logical address including a series of logical group addresses and a series of logical block addresses belonging to each logical group is given,
The controller is
A set of physical blocks selected one by one from each bank for each pair is used as a physical block group, and a logical block is written at the position of the common partial physical block.
An address conversion table having an address conversion area for converting a logical group address among logical addresses given from the outside into a partial physical block address in which a logical block to which the logical group belongs is recorded;
An entry table indicating either written or erased for each physical block;
A valid data table that describes whether or not the logical blocks constituting the logical block group are valid data;
When data for writing and its logical address are given from the outside, based on the effective data table, the data is written in an unwritten area in units of partial physical block groups, and the data is written to the address conversion table. A non-volatile storage device, wherein a partial physical block is registered for a logical group to which a logical block belongs, and an entry table and an effective data table are updated.   The controller searches the valid data table, sets a physical block with less valid data contained in the physical block as a physical block to be erased, and erases a logical block if there is no valid logical block in the physical block to be erased. 2. The non-volatile memory device according to claim 1, further comprising erase block securing means for securing erase blocks by aggregating valid logical block data in other erased physical blocks if there are logical blocks. .   The data capacity of the physical block group of the nonvolatile memory is equal to the data capacity of the logical group, and the data capacity of the partial physical block group is the data capacity of the logical block and the data management unit outside the nonvolatile storage device. The nonvolatile memory device according to claim 1, wherein the nonvolatile memory devices are equal. Non-volatile memory;
A controller, and
A data writing method for a nonvolatile storage device that writes data to and reads data from the nonvolatile memory based on a logical address given from the outside,
The nonvolatile memory includes a plurality of nonvolatile memory elements paired with each other, each nonvolatile memory includes a plurality of banks, each bank includes the same number of physical blocks, and each physical block includes a plurality of Consisting of partial physical blocks,
From the outside, a logical address including a series of logical group addresses and a series of logical block addresses belonging to each logical group is given,
The controller is
A set of physical blocks selected one by one from each bank for each pair is used as a physical block group, and a logical block is written at the position of the common partial physical block.
An address conversion table having an address conversion area for converting a logical group address among logical addresses given from the outside into a partial physical block address in which a logical block to which the logical group belongs is recorded;
An entry table indicating either written or erased for each physical block;
A valid data table that describes whether or not the logical blocks constituting the logical block group are valid data;
When data for writing and its logical address are given from the outside, the data is written in the unit of partial physical block group in an unwritten area based on the valid data table,
Register the partial physical block for the logical group to which the logical block belongs in the address translation table;
A data writing method for a nonvolatile memory device, wherein the entry table and the valid data table are updated.   The effective data table is searched, a physical block with a small amount of valid data contained in the physical block is set as a physical block to be erased, and if there is no valid logical block in the physical block to be erased, the logical block is erased. 5. The method of writing data in a nonvolatile storage device according to claim 4, further comprising a process of securing an erase block by aggregating data of valid logical blocks into another physical block that has been erased. The data capacity of the physical block group of the nonvolatile memory is equal to the data capacity of the logical group, and the data capacity of the partial physical block group is the data capacity of the logical block and the data management unit outside the nonvolatile storage device. The data writing method for a nonvolatile memory device according to claim 4, wherein

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