JP2005073124A - Pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit in which stability and responsiveness are enhanced while ensuring low voltage operation and a wide oscillation range. <P>SOLUTION: An output signal of a phase comparator that received a frequency signal formed on the basis of an oscillation signal of a current controlled oscillator and a reference signal is made into DC by a loop filter, a first current included in a control current of the current controlled oscillator is formed by a voltage/current converter to configure a PLL, and a calibration circuit is provided to change a self-oscillation frequency of the current controlled oscillator in accordance with the reference signal. A plurality of different reference voltages are then supplied to one input of each of a plurality of differential amplifiers as the voltage/current converter, an output voltage formed by the loop filter is supplied to the other input of each of the plurality of differential amplifiers, and output currents of the plurality of differential amplifiers are composed by a first current mirror path to form the first current. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a PLL circuit, and more particularly to a technique effective when used in a circuit having a calibration circuit.

  Since the VCO (Voltage Controlled Oscillator) used in the PLL has its oscillation frequency variable depending on the voltage, the voltage variable range is theoretically less than the power supply voltage. Therefore, when the power supply voltage is lowered, the variable range of the VCO is narrowed and the oscillation range is also reduced. We examined a high-performance PLL circuit that realizes the conflicting requirements of low-voltage operation and a wide oscillation range.

As a technique for realizing a low-voltage operation and a wide oscillation range, a PLL having a self-calibration function of an oscillation frequency is disclosed in the following documents 1 and 2. This is a method of performing calibration by digital control of the oscillation frequency of the VCO in the vicinity of the target frequency as the first stage of the PLL pull-in operation process. PFC (phase comparator), CP (charge pump), LF (loop filter) ), VIC (Voltage-Current Converter), CCO (Current Controlled Oscillator), a conventional PLL circuit consisting of a feedback counter, and a calibration circuit (all-digital circuit) and the digital code of the calibration output are converted into analog quantities The D / A converter is added. By adjusting the frequency by self-calibration, since the initial oscillation frequency is in the vicinity of the target frequency, the frequency variable range after calibration can be designed to be narrow. In addition, a wide frequency adjustment range by calibration can meet a wide frequency range requirement.
IEEE Journal of Solid-State Circuits, vol.35, NO.10, pp1437-1444, October 2000 IEEE 2001 A 1.0V GHz Range 0.13um CMOS Frequency Synthesizer

  When the calibration is executed, the control voltage of the VCO is set to an arbitrary reference voltage. In Non-Patent Document 1, a switch is provided at the VCO control node, and is connected to a filter node during normal operation and to a reference power supply during calibration. In Non-Patent Document 2, a switch is provided at the reference power supply node, which is open during normal operation and connected to the filter node during calibration. The VCO control node is a high resistance and sensitive node. If a switching element (noise source) is inserted here as in Non-Patent Document 1, it causes deterioration of jitter characteristics. After calibration, the filter voltage (VCO control voltage) is boosted from 0 V, so that phase pull-in time is required.

  Further, in Non-Patent Document 2, in order to drive the capacitance of the loop filter with a reference power source to obtain a desired voltage, calibration cannot be started unless waiting for a time longer than the filter time constant (usually several tens of μs or more). It takes time. In addition, the operating range of the VIC becomes narrow due to variations in the threshold voltage Vth of the MOS transistor and temperature variations. As a result, the gain of the VCO increases and noise resistance deteriorates. When a low Vth MOS is used to ensure the operating range of the D / A converter under low power supply voltage conditions, the leakage current of the MOS transistor that is turned off results in a conversion value error, and the frequency fluctuates due to temperature fluctuations and the target. The frequency may be out of the lock range.

  In Non-Patent Documents 1 and 2, after calibration, phase pull-in is completed and the frequency changes due to environmental fluctuations or the like from the steady operation state, and the operation cannot be performed within the variable range. Even if there is a function to increment / decrement the calibration control code in order to change the frequency outside the variable range, if the oscillation characteristic does not increase monotonously with respect to the calibration control code, the monotonic increase in the first calibration If the boundary of a code that has not been selected is selected, incrementing / decrementing from that code will greatly change the frequency and impair the normal operation of the system. When the user changes the frequency out of the variable range, the stable operation state is not restored unless the calibration is executed again.

  An object of the present invention is to provide a PLL circuit that has improved stability and responsiveness while ensuring low voltage operation and a wide oscillation range. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the output signal of the phase comparator that receives the frequency signal and the reference signal formed on the basis of the oscillation signal of the current control oscillator is converted into a direct current by a loop filter, and this is controlled by the voltage-current converter. A PLL circuit is formed by forming a first current included in the current, a calibration circuit is provided for changing the self-excited oscillation frequency of the current controlled oscillator corresponding to the reference signal, and the voltage-current converter is Supply a plurality of different reference voltages to one input of a plurality of differential amplifiers, supply an output voltage formed by the loop filter to the other input of the differential amplifiers, and output the plurality of differential amplifiers The first current is formed by combining the currents through the first current mirror path.

  While realizing a wide oscillation range with low voltage operation, the jitter characteristics are improved and the clock quality can be improved. Alternatively, the PLL pull-in time can be shortened. Alternatively, continuous stability against environmental changes can be enhanced.

  FIG. 1 is an overall schematic block diagram of a PLL circuit according to the present invention. Each circuit block of this embodiment is formed on one semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique. A PLL loop is configured by the phase comparator PFC, the charge pump CP, the loop filter LF composed of resistance / capacitance, and the voltage controlled oscillator (hereinafter simply referred to as VCO) composed of the voltage-current converter VIC and the current controlled oscillator CCO.

  That is, the output signal fvco of the VCO is divided by the counter PC and the counter NC, and is used as the feedback signal fdbk of the phase comparator PFC. The reference clock ckref supplied from the outside is supplied to the phase comparator PC as a reference signal fref divided by the M counter MC. The phase comparator PFC forms a phase comparison output in which the phases (frequency) of both the signals fref and fdbk coincide with each other, and the charge pump circuit and the loop filter convert it into a DC voltage and control the oscillation frequency of the VCO.

  The calibration circuit is provided to increase the frequency control range of the PLL by switching the self-excited oscillation frequency of the VCO. The digital output selofs of the calibration circuit is input to a D / A converter iDAC1 that converts a digital signal into an analog current. The D / A converter iDAC1 is added as a part of a control current for converting the digital signal selofs into an analog current signal Iof to control the oscillation frequency of the current control oscillator CCO. The current control oscillator CCO is formed by adding the analog current Iof obtained by converting the digital output selofs of the calibration circuit by the D / A converter iDAC1 and the output current Icnt of the voltage-current converter VIC constituting the signal PLL loop. It is configured to oscillate at a frequency determined by the controlled current.

  The calibration circuit outputs a flag signal pbsend indicating that it is in the calibration period, and controls the operation of the charge pumps CP and VCO in the PLL loop to be different from the normal PLL operation. For example, the voltage-current converter VIC is configured to switch between the reference current Irefcal during calibration and the current Icnt during normal operation by the flag signal pbsend. The VCO of this embodiment includes Vdet for converting the voltage at the resistance-capacitance node into a current in addition to the VIC / CCO. In this embodiment, as will be described later, by using a reference current source instead of a reference voltage source at the time of calibration, a switch is not required at the VCO control node, and the circuit setup time is shortened.

  The counters MC, PC, and NC constituting the frequency dividing circuit can be programmed to set the frequency dividing ratio by preset signals setm, setp, and setn supplied from the outside. That is, in a system in which the PLL circuit of this embodiment is mounted, a required frequency signal such as a clock is set by a combination of the preset signals. Incidentally, fref = fdbk when the PLL is in the phase locked state. fref = M × ckref and fdbk = P × N × fvco. Further, fout = P × fvco or 2P × fvco. From M × ckref = P × N × fvco, the relationship fvco = ckref M / (P × N) is established, and fout = ckref M / N is set.

  Although not particularly limited, the digital output selofs of the calibration circuit is also supplied to the bias circuit, where the reference voltage Irefdac for D / A conversion corresponding to the digital output selofs, the bias current Irefamp for the differential amplifier, the charge A bias current Irefcp for the pump is formed. Further, the PLL circuit of this embodiment is provided with a test signal supplied to the charge pump CP and a test signal supplied to the calibration circuit, but the description thereof is omitted because it is not directly related to the present invention. The calibration circuit includes a frequency comparator FC, a frequency search state circuit FSCONT, and a control timing generation circuit CTG in order to form the output selofs.

  FIG. 2 shows a circuit diagram of an embodiment of the voltage-current converter VIC of FIG. In this embodiment, it is devised to realize a voltage-current conversion operation capable of operating in a wide range irrespective of Vth variation of MOSFET and temperature fluctuation. The voltage-current converter VIC of this embodiment is constituted by two sets of P-channel MOSFET input and N-channel MOSFET input differential amplifiers DP1, DP2, DN1, and DN2. Bias (reference) voltages Vr1, Vr2, Vr3, and Vr4 are supplied to the gates of one differential MOSFET of the differential amplifiers DP1, DP2, DN1, and DN2, respectively. The input voltage Vcnt is commonly supplied to the gates of the other differential MOSFETs of the differential amplifiers DP1, DP2, DN1, and DN2. The bias voltages Vr1 to Vr4 are generated by resistance division (VDD / K) between the power supply VDD and the ground (VSS). Current source MOSFETs for supplying a bias current Ib are respectively provided at common sources of the differential amplifiers DP1, DP2, DN1, and DN2.

  Among the bias voltages Vr1 to Vr4, the lowest voltage Vr1 is supplied to the gate of one differential MOSFET of the differential amplifier DP1 configured with a P-channel MOSFET, and the second lowest voltage Vr2 is configured with a P-channel MOSFET. Is supplied to the gate of one differential MOSFET of the differential amplifier DP2. On the contrary, the highest voltage Vr4 is supplied to the gate of one differential MOSFET of the differential amplifier DN1 composed of an N channel MOSFET, and the second highest voltage Vr3 is applied to the differential amplifier DN2 composed of an N channel MOSFET. It is supplied to the gate of one differential MOSFET. The bias current Ib flowing through the common source of each differential MOSFET is not particularly limited, but is formed by a current mirror circuit that receives the current of the bias current source Irefvic.

  The voltage-current converter VIC includes an output current (drain current) of a P-channel MOSFET connected to the Vr1 side of the differential amplifier DP1, and a P-channel MOSFET connected to the Vr2 side of the differential amplifier DP2. The output current, the output current of the N-channel MOSFET connected to the Vcnt side of the differential amplifier DN1, and the output current of the N-channel MOSFET connected to the Vcnt side of the differential amplifier DN2 are respectively output by the current mirror circuit. The added current (synthetic current) is output from the P-channel MOSFET P3.

  The gate of the P-channel MOSFET P3 is connected to the gate and drain of the diode-type P-channel MOSFET P4 or P-channel MOSFET P5 via the switch S1 or S2 to form a current mirror. A combined current of the differential amplifiers DP1, DP2, DN1, and DN2 flows through the P-channel MOSFET P4, and the bias current Irefvic (Ib) flows through the P-channel MOSFET P5. The gate of the MOSFET P3 is connected to the power supply voltage VDD via a switch S3 that is turned on at the time of power down (pdn = L).

  During the calibration period of the flag signal pbsend = L (/ pbsend = H), the switch S1 is turned off and the switch S2 is turned on, so the gate-source voltage Vgs of the MOSFET P3 is between the gate and source of the MOSFET P5. Biased to the same potential as Vgs. At this time, if the W / L ratio of the MOSFETs P5 and P3 is 1: 2, the output current of the MOSFET P3 is 2Ib, and a current value half of the maximum output current 4Ib of the voltage-current converter VIC is output. This current value 2Ib is approximately the center of the variable range of Vcnt.

  Therefore, calibration is performed at the frequency of the current-controlled oscillator CCO that oscillates at the center of the operating range of the voltage-current converter VIC. The voltage of Vcnt in the PLL locked state is also near the center of the operating range of the voltage-current converter VIC, so that the lock range margin can be secured most. In addition, since calibration is performed by switching the control current Icnt to the reference current (2Ib), it does not require the time required to charge the capacity of the loop filter LP of the PLL loop and set the control voltage Vcnt to the reference voltage. In addition, the switch of the control voltage Vcnt node is unnecessary. As a result, it is possible to eliminate the deterioration factor of the jitter characteristic caused by inserting the switch element (noise source) in the control voltage Vcnt node as in the prior art. When the calibration is completed, the flag signal pbsend = H (/ pbsend = L) is set, the switch S1 is turned on, and the switch S2 is turned off. Thus, the voltage-current converter VIC outputs a current determined by the voltage of the control voltage Vcnt.

  FIG. 3 shows a voltage-current characteristic diagram of the voltage-current converter VIC of FIG. As the control voltage (input voltage) Vcnt rises from 0V, the drain-source current Ids of the N-channel MOSFET N1 connected to the differential amplifier DP1 increases. When Vcnt = Vr1, the source-drain current Ids = Ib of the MOSFET N1. / 2. The control voltage Vcnt further increases, and the current Ids of the N-channel MOSFET N2 connected to the differential amplifier DP2 increases. When Vcnt = Vr2, the source-drain current Ids = Ib / 2 of the MOSFET N2. Similarly, for the differential amplifiers DN1 and DN2, when Vcnt = Vr3, the source-drain current Ids of the P-channel MOSFET P1 = Ib / 2. When Vcnt = Vr4, the source-drain current Ids = Ib / 2 of the P-channel MOSFET P2.

  The voltage-current converter VIC outputs a current obtained by adding the currents obtained by copying the drain-source current Ids of the N-channel MOSFETs N1 and N2 and the P-channel MOSFETs P1 and P2 by the current mirror. When Vr4−Vr3 = Vr3−Vr2 = Vr2−Vr1 = ΔV, if the linear range of the differential amplifiers DP1, DP2, DN1, DN2 is designed to be ΔV, the voltage range of the sum of the output currents of the differential amplifiers Can be as large as 4ΔV. Since the bias voltages Vr1 to Vr4 are generated by resistance division between the power supply and the ground (VDD-VSS), the bias voltages Vr1 to Vr4 are not affected by variations in the threshold voltage Vth of the MOSFET and temperature fluctuations. Therefore, when the power supply voltage VDD is determined, one side of the differential pair MOSFETs of the differential amplifiers DP1, DP2, DN1, and DN2 is always biased with the same reference voltage, and therefore, as shown in FIG. 3 regardless of MOSFET Vth variations and temperature fluctuations. A wide range of input / output characteristics.

  FIG. 4 shows a circuit diagram of an embodiment of the D / A converter iDAC1 of FIG. In this embodiment, a MOSFET having a low threshold voltage Vth is used in order to ensure the operating range of the D / A converter under low power supply voltage conditions. However, when a low threshold voltage MOSFET is used, a leak current flows between the drain and source even in an off-state MOSFET, affecting the D / A conversion operation. Therefore, in this embodiment, a device for eliminating the influence of leakage current is used while using a low threshold voltage MOSFET.

  The basic cell of the D / A converter iDAC of this embodiment is composed of N-channel MOSFETs Q2 to Q4 and an inverter circuit IV1 as shown in FIG. The gate of the MOSFET Q2 is connected to the connection point between the sources and drains of the MOSFETs Q3 and Q4 acting as switch MOSFETs, and the source of the MOSFET Q2 is connected to the output of the inverter circuit IV1. The drain of the MOSFET Q3 is connected to the gate of the diode-connected MOSFET Q1 that mirrors the reference current Irefdac of the D / A converter iDAC, and the source of the MOSFET Q4 is connected to the circuit ground potential VSS (GND). The digital code D0 is input to the gate of the MOSFET Q3 and the input of the inverter circuit IV1, and the digital code D0 is inverted and input to the gate of the MOSFET Q4 by the inverter circuit IV2.

  The drain-source current Ids of the MOSFET Q2 is the output of the D / A converter iDAC basic cell, and the presence or absence of the output of the basic cell is controlled by the high level / low level of the input digital signal D0. A basic cell weighted by 2 to the power of n, specifically, a circuit in which a plurality of MOSFETs having the number of 1, 2, 4,... There are as many bits as there are bits, and the sum of the output currents of the basic cells is the output current of the D / A converter iDAC. Alternatively, the size of the MOSFET (W / L ratio, W: channel length, L: channel width) is set to 2, 4,... Corresponding to weighting by the nth power of 2, and these correspond to D0 to Dn. A configuration in which the sum of the output currents is selected to be the output current of the D / A converter iDAC, or a product of the size of the MOSFET multiplied by the number corresponding to the weighting by the nth power of 2 is added. There are as many bits as 1, 2, 4... Connected to each other in parallel, and the total output current of the basic cells is the output current of the D / A converter iDAC. Such a configuration may be used.

  The MOSFET Q2 uses a MOSFET having a low threshold voltage in order to secure an operating point at the low power supply voltage VDD. Similarly, the switch MOSFET Q3 and the MOSFET Q2 and the diode-connected MOSFET Q1 in the form of a current mirror are also set to a low threshold voltage. In order to increase the current mirror accuracy, the source of the MOSFET Q1 is given a low level formed by the dummy inverter circuit IV0. When the D / A converter iDAC is in the non-operating state, the input signal of the inverter circuit IV0 may be set to a low level, the output signal may be set to a high level, and the MOSFET Q1 may be turned off to reduce power consumption.

  FIG. 5 is an equivalent circuit diagram for explaining an example of the operation of the D / A converter iDAC basic cell of this embodiment. In the figure, the MOSFETs that are turned off are indicated by dotted lines. When the digital code D0 = H (high level), the MOSFET Q3 is turned on, the MOSFET Q4 is turned off, and the gate of the MOSFET Q2 is connected to the gate of the MOSFET Q1 (not shown) via the MOSFET Q3. Further, since the output of the inverter circuit IV1 is at a low level, the source of the MOSFET Q2 is connected to VSS via the N-channel MOSFET constituting the inverter circuit IV1, and the current iout corresponding to the current Id0 is output.

  FIG. 6 shows an equivalent circuit diagram for explaining another example of the operation of the D / A converter iDAC basic cell of this embodiment. Also in this figure, MOSFETs that are turned off are indicated by dotted lines. When the digital code D0 = L (low level), the MOSFET Q3 is turned off, the MOSFET Q4 is turned on, and the gate of the MOSFET Q2 is connected to VSS via the MOSFET Q4. Since the output of the inverter circuit IV1 is at a high level, the source of the MOSFET Q2 is connected to VDD via the P-channel MOSFET constituting the inverter circuit IV1, so that the MOSFET Q2 is cut off and the source of the MOSFET Q2 is in the high impedance state. It becomes.

  A MOSFET having a low threshold voltage Vth may be in a depletion mode due to manufacturing variations of the threshold voltage Vth and temperature variations. At this time, even if the gate of the N-channel MOSFET is at a low level (0 V), a relatively large leak current such as Ids >> 0 flows. This causes a conversion error of the D / A converter. As described above, when the MOSFET Q2 is turned off, the voltage Vgs between the gate and the source of the MOSFET Q2 can be set to Vgs <0 by setting the potential to the power supply voltage VDD on the source side, and the depleted MOSFET is also completely turned off. The leakage current can be suppressed.

  FIG. 7 shows a circuit diagram of an embodiment of the charge pump CP and the loop fill LF of FIG. In this embodiment, a device is devised to shorten the phase pull-in time after calibration by precharging the capacitance of the loop filter LF of the PLL loop during the calibration period. A VCO is constituted by the V / I (voltage-current) converter and the current controlled oscillator CCO as described above. A filter unit serving as a voltage input source to the voltage controlled oscillator VCO, a MOS switch unit constituting the charge pump CP, and a calibration logic for sending a signal to the MOS switch are provided.

  Flag signals / pbsend and pbsend indicating the calibration period are output from the calibration logic. The gate circuits G1 and G2 that receive the signals / pbsend and pbsend turn on the MOSFETs P1 and N1 of the MOS switch section constituting the charge pump CP regardless of the phase comparison output (not shown). That is, as shown in FIG. 8, the output signal of the gate circuit G1 is set to the low level (VSS) by the high level (logic 1) of the flag signal / pbsend to turn on the P-channel MOSFET P1, and the gate circuit is set to the low level of the flag signal pbsend. The output signal of G2 is set to high level (VDD) to turn on the N-channel MOSFET N1.

  In this state, the characteristics of the current I1 flowing through the MOSFET P1 and the current I2 flowing through the MOSFET N1 with respect to the output voltage are shown in FIG. When the output voltage is low, I1> I2 and current flows from VDD to the output. Therefore, the output voltage is raised. When the output voltage is high, I2> I1, and the output voltage is lowered by drawing current into VSS. The voltage is fixed at a stable point where I1 and I2 are equal. From the above, the MOS switch unit receives the calibration start signal and fixes the voltage VA of the node A to the intermediate voltage between VDD and VSS (V1 in FIG. 9).

  FIG. 10 is a waveform diagram for explaining an example of the PLL pull-in operation of the PLL circuit according to the present invention. Before start-up, the voltage VA at the node A is the circuit ground potential VSS. When the calibration is started, the MOS switch unit starts operating, and the voltage VA is fixed at the stable point V1. After the calibration is completed, pull-in by normal operation is started and the voltage rises to the target voltage Vsat for obtaining the final target frequency. This time is referred to as normal pull-in time Tset. Pull-in time = calibration time + Tset = calibration time + (Vsat−V1) / Icp. Here, Icp is a current during normal operation. When the circuit of the embodiment is not used, the voltage VA of the node A is pulled in by a normal operation after the calibration period ends. Therefore, pull-in time = calibration time + Tset = calibration time + Vsat / Icp. From this comparison, the lead-in time can be shortened by (V1 / Icp) by employing the circuit of the embodiment.

  FIG. 11 is a block diagram showing another embodiment of a PLL circuit with a calibration function according to the present invention. In this embodiment, a frequency variable range over / underflow detector is provided in order to ensure continuous stable operation even when the oscillation range of the PLL is outside the variable range. The PLL circuit of this embodiment includes a VCODAC unit controlled by a digital code, a VCO digital control unit that controls the VCODAC unit, a V / I converter that receives an output from the VCODAC unit, and performs voltage-current conversion, and V / I conversion The detection V / I converter having the same configuration as the detector, the I / V converter for detecting the comparison by comparing the output currents of the detection V / I converter, the comparator, and the output of the comparator are operated. It consists of a current output unit.

  In the VCODAC section, the digital code is fixed (N) at the stage of initial search, and a constant current Is = N × Iref is output during normal operation. As shown in the voltage-current characteristic diagram of FIG. 12, the V / I converter outputs a current obtained by adding the variable current ± Ivi proportional to the voltage of the node A and the fixed current Is from the VCODAC to the current control oscillator CCO. To do. During normal operation, the current Is is fixed to one corresponding to the calibration result, and the output current of the V / I converter has a maximum value of Is + Ivi and a minimum value of Is−Ivi. Since one of a plurality of reference current controls is selected as the calibration result, a wide range of output currents, that is, a wide range of PLL operations can be performed.

  In FIG. 11, the detection V / I converter has the same input / output characteristics as the V / I converter, and the loop filter voltage Vsen is inputted. The node A input to the current controlled oscillator CCO cannot be used for detection because the voltage fluctuates at a high frequency during normal operation. The voltage Vsen outputs an average voltage of the node A. As shown in the voltage-current characteristic diagram of FIG. 13, the detection V / I converter using the voltage Vsen as an input has a current IH smaller than the output maximum value by 0.2 × Ivi as an upper limit current, and an output minimum value. A current Icnt which is determined by the voltage Vsen and equal to the output current to the current controlled oscillator CCO is output to the I / V converter as an operating current, with the current IL larger by 0.2 × Ivi as the lower limit current. When the operating current Icnt is larger than the specified upper limit current IH (IH <Icnt), the overflow state is set. When the operating current Icnt is smaller than the specified lower limit current IL (Icnt <IL), the underflow state is set.

  FIG. 14 shows a circuit diagram of an embodiment of the I / V converter of FIG. The I / V converter is composed of two N-channel MOSFETs Q10 and Q11. Output voltages Vgs1 and Vgs2 of MOSFETs Q10 and Q11 are determined by the following equations, respectively.

Vgs1 = sqrt (IH or IL / β) + Vth
Vgs2 = sqrt (Icnt / β) + Vth
However, β: coefficient, Vth: threshold voltage of N-channel MOSFET, sqrt (A) = (A) ^1/2 .

  In FIG. 14, when IH <Icnt, Vgs1 <Vg2, and this potential difference is input to the comparator to detect an overflow and output the up signal shown in FIG. When IL> Icnt, Vgs1> Vg2, and this potential difference is input to the comparator to detect underflow and output the dn signal shown in FIG.

  FIG. 15 is a characteristic diagram for explaining the operation when an overflow is detected. When the voltage Vsen moves to the overflow range, that is, when the voltage Vsen changes from (A) to (B) in FIG. 15, the relationship of IH <Icnt is established and the signal up is formed as described above. The VCO digital control unit in FIG. 11 raises the code from N to N + 1 by receiving the signal up, and the maximum current increases from Is + Ivi = N × Iref + Ivi to (N + 1) × Iref + Ivi.

  That is, the code is carried up at (B) shown in FIG. 15 and moved to (C) on the output current characteristic at code N + 1, and the maximum current increases by Iref. Based on the above, the VCODAC unit controlled by the digital code, the VCO digital control unit that controls the VCODAC unit, and the system having the V / I converter that receives the output from the VCODAC unit and performs voltage-current conversion are determined by the digital code. Even if the current range (N × Iref−Ivi to N × Iref + Ivi) is exceeded, the code is automatically incremented, and the maximum current can be increased by Iref, enabling continuous PLL operation. Become.

  FIG. 16 shows a circuit diagram of an embodiment of the current output unit of FIG. The current output unit has gates G10 and G11 in which the logical threshold is adjusted to the levels VL and VH for determining the end of pullback, and the current that is turned on in the overflow state upon receiving the determination levels VL and VH and the detection signals up · dn. It has an N-channel MOSFET N1 as a source and a P-channel MOSFET P1 as a current source that is turned on in an underflow state, and has a function of automatically stopping current output when the voltage Vsen returns to the end of pullback. The pullback end range is set inside the normal operation range.

The logical value table at the time of overflow is as follows.
┌───┬───┬───┬───────┐
│dn │Vsen │ out1 │State │
├───┼───┼───┼───────┤
│0 │0 │0 │ (E) │
│0 │1 │0 │ (A) ↑ │
│1 │0 │0 │ ↓ (D) │
│1 │1 │1 │ (B) → (C) │
└───┴───┴───┴───────┘

  FIG. 17 is a characteristic diagram for explaining the pull-in operation to the normal operation range by the current output unit of FIG. In the state immediately before the overflow, Vsen> VH and the signal dn is not output, so that the state of the logical value table (A) is obtained. When overflow occurs, the dn signal is output and the code of iDAC1 is carried up, and the state (B) → (C) is entered. From the logical value table, out1 outputs a high level (1), and the N-channel MOSFET N1 in FIG. 16 is turned on. As a result, the current is drawn and the voltage Vsen is reduced. When the voltage decreases and Vsen <VH, the state of (D) in the logical value table is obtained. In this state, the N-channel MOSFET N1 of the current source is turned off, and the voltage Vsen stops at VH. By having the current output section as described above, as shown in FIG. 17, it is possible to return the voltage Vsen to the normal operating range at the same time that the code is advanced from the overflow state. When such a circuit function is not added, the overflow state continues even if the logic value table (B) → (C) is raised in the overflow state, and the code is continuously raised to the normal state. Will not return.

  FIG. 18 shows a frequency characteristic diagram of the calibration circuit according to the present invention. In this embodiment, a contrivance is made to select an optimal control code from oscillation characteristics that do not increase monotonously with respect to the control code. In consideration of frequency fluctuations due to variations in semiconductor integrated circuit devices (devices), the VCO oscillation frequency characteristic with respect to the calibration code is designed not to monotonously increase between codes having an oscillation frequency as shown in FIG. In other words, adjacent categories have oscillation frequencies that overlap each other for each calibration code.

  In the example of FIG. 18, the calibration output code is composed of 7 bits, and the upper 2 bits of the code are switched to be a combination of categories (1) to (4). Each of the categories (1) to (4) is monotonically increased, but the total of the four categories is not monotonically increased. For example, when such an oscillation characteristic is exhibited when the target frequency is 300 MHz, several calibration output codes can be taken. Which point to select is determined by the search algorithm according to the present invention.

  In the binary search algorithm that simply determines whether the target frequency and the oscillation frequency are higher or lower by comparing only the bit stages from the most significant bit MSB, the optimum point cannot be selected as shown in FIG. A code boundary without a monotonic increase in frequency is selected. That is, in FIG. 19, if category (1) in which the upper 2 bits are set to 00 is selected, PLL control is performed at the right end of category (1) when the oscillation frequency of 300 MHz is obtained.

  The search algorithm proposed in the present application is not the determination result of each bit stage alone, but the determination that the frequency is low (or high) twice continuously in the search process from the most significant bit MSB as shown in FIG. The third frequency setting code is set to the lower (upper) monotonically increasing category (the upper 2 bits are 00 in FIG. 20), and the lower 5 bits are set to 3/4 code, that is, 11000 (0011000). If the oscillation frequency is lower than the target frequency, the upper 2 bits are determined as 00, and if higher, it is determined as 01 (returns to the monotonically increasing category one level higher).

  In this method, the presence / absence of a margin in the higher direction can be confirmed by comparing with 3/4 codes of the lower 5 bits. If the judgment is high, the upper monotone increase category (upper 2 bits 01) has a larger margin in the higher direction. If the judgment is lower, the compared monotone increase category (upper 2 bits 00) is the most. It can be determined that there is a large margin in the downward direction. Once the upper 2 bits (bits that have been divided into categories (1) to (4) with no monotonic increase) are determined, the monotonic increase characteristic is guaranteed for the lower 5 bits, so a simple binary search algorithm is used. determine. The calibration code thus determined can select an optimum point in the VCO oscillation frequency characteristic. The optimum point means that the selected calibration code is the point closest to the center in the monotonically increasing category.

  FIG. 21 is a timing chart for explaining the irregular frequency binary search according to the present invention. 22 and 23 are flowcharts for explaining the irregular frequency binary search. The status counter bscount forms status 0-12 by forming a pulse obtained by dividing the reference clock ckref by 32. The period from status 0 to 3 is the PLL initialization time. In the calibration code, the code selofs1 is the upper 2 bits and selofs2 is the lower 5 bits so that the total is 7 bits. Calibration is started by the reset signal reset-n. In the statuses 0 to 3, the code selofs1 is provisionally determined, and the code selofs2 is set to the center value of 10,000.

  Periods of status 4 and 5 (sequences 1 and 2 in FIG. 22) are provisional confirmation sequences, and the upper 2 bits of the offset code selofs1 are searched. In the period of status 6 (sequence 3 in FIG. 22), upper 2-bit margin determination and upper 2-bit resetting are performed. The lower 5 bits are searched from status 7 to 12 (sequences 4 to 9 in FIG. 23). Whether the feedback clock (VCO oscillation frequency) ckfbin is fast or not at this time is determined by whether the count value of ckfbin is larger or smaller than 32 in 32 period periods (one state period) of the reference clock ckref. . When the count value of ckfbin is larger than 32, it is determined to be early.

  FIG. 24 shows a block diagram of an embodiment of the calibration circuit of FIG. In this embodiment, the division ratio (M, N, P) of each frequency divider of the PLL is set, and after inputting the reference clock ckref, reset-n = 0 → 1. This circuit detects the rising edge of the reset signal and starts searching for the PLL oscillation frequency adjustment optimum code. The PLL oscillation frequency band code is given by 7 bits of the adjustment code register selofs [6: 0], and the frequency band from 0 to 127 can be changed. The PLL in the initial state is not in the phase lock state, but is set at the center of the adjustable range as shown in FIG.

  The PLL set at the center of the adjustable range starts oscillating at a certain frequency. The frequency is divided by a frequency divider, input to ckfbin of this circuit, and compared with the reference clock ckref. However, if the comparison is made for each cycle of ckref, the error becomes enormous, so the number of cycles of ckfbin is compared with 32 cycles of the reference clock ckref to increase the determination accuracy. The compared result signal don is reflected in the adjustment code register selofs [6: 0]. This reflection method is a 7-bit binary search (sequential comparison) method. By doing so, the adjustment code register is determined in seven comparison sequences in order from the upper bit. The actual circuit has an anomaly part, and is set to a comparison sequence of 8 times as described above.

  The internal clock generation circuit generates a code switching signal ck-d. The PLL oscillation frequency adjustment optimum code is searched by the irregular frequency binary search circuit, the adder circuit add (± 1, 0) and the multiplexer MUX1. The multiplexer MUX2 is for manually setting the adjustment code register selofs [6: 0].

  FIG. 25 shows a circuit diagram of an embodiment of an internal clock generation circuit used in the calibration circuit of FIG. In this embodiment, as shown in the timing chart of FIG. 26, every thirty-two cycles of the reference clock ckref, it is compared whether there are 28 ckfbins among 28 reference clocks ckref. Since it is necessary to design a temporal switching sequence for that purpose, the internal clock generation circuit is designed in consideration of the latency of the circuits related to them. The 32 divider connected by the reference clock ckref outputs a reference signal for operation every 32 cycles. This is a synchronous counter that alternately outputs a low level of 16 cycles and a high level of 16 cycles with respect to the rising edge of the reference clock ckref. All timing references become the rising edge of this output.

  The output ck-d of the register (flip-flop circuit) ck2 generates a timing for switching the offset code selofs [6: 0]. The register Idv is a load enable signal for starting the feedback clock frequency comparison count, and has a hold time free timing at the falling enable timing with respect to the rising operation counter. Only in 3.5 to 4.5 cycles, Idv = H (high level) and the comparison value 28 is loaded.

  FIG. 27 shows a block diagram of an embodiment of the frequency comparison counter of FIG. Since a synchronous load signal is obtained from the reference clock ckref and the feedback clock ckfbin from the internal clock generation circuit of FIG. 25, it is determined whether or not there are 28 ckfbin cycles in 28 cycles of the reference clock ckref. The idea of this embodiment circuit is a synchronous down counter with a load function. When Idv = H (high level), the fixed value 28 is loaded, and when the cycle count value xcount is 0, the value is held as it is. The transfer between fcomp and down is asynchronous, and hold time errors are handled as frequency determination errors. When down = 1, it is determined that the frequency is fast, and the offset code is lowered.

  FIG. 28 shows an operation explanatory diagram of the irregular frequency binary search circuit of FIG. In order to search for the optimum frequency of the 7-bit offset code selpfs [6: 0] as described above, the fastest search can be made by making seven determinations from the upper bit to the lower bit as shown in FIG. However, the upper 2 bits of the PLL offset code are not smoothly connected to the lower bits (FIG. 18). In such a case, there are a plurality of lock points depending on conditions, and none of them is an error.

  However, I would like to select the point with the most margin in case a carry of the upper bit code occurs in the PLL adjustment range. Therefore, a sequence for determining whether the upper 2 bits of the code have the most margin after the upper 2 bits of the frequency binary search is added. The circles in FIG. 28B are determination points, the timing chart is as shown in FIG. 21, and the flowcharts are as described in FIGS. That is, the reflection function shown in the figure checks whether or not the upper 2 bits of the adjustment range are sufficient in the third sequence, and reselects one having a margin.

  FIG. 29 shows a circuit diagram of another embodiment of the voltage-current converter VIC of FIG. This embodiment is a modification of FIG. 2, and the differential pair inputs of the differential amplifiers DP2 and DN2 are connected to the output of DP1 and the output of DN1, respectively. By setting the W / L size ratio of the P-channel MOSFET differential pair of the differential amplifier DP2 to 1: m and the W / L size ratio of the N-channel MOSFET differential pair of the differential amplifier DN2 to 1: n, Ib The potential of Vcnt which becomes' / 2 is set in the vicinity of the reference voltages Vr2 and Vr3 in FIG. This is because of the influence of the low power supply voltage, even when the operating point of the differential amplifier cannot be secured at the intermediate potential of the power supply voltages such as the reference voltages Vr2 and Vr3, the P-channel MOSFETs P1, P6, N The operating point can be secured by designing the gate-source voltage Vgs of the channel MOSFETs N1 and N3.

FIG. 30 is a circuit diagram showing another embodiment of the charge pump CP of the charge pump CP and the loop fill LF shown in FIG. This embodiment is a modification of the charge pump CP of FIG. 7, and resistors are respectively inserted between P1 and N1 and the output node. At this time, the resistance values of the on-resistance Ronp of P1 and the inserted resistor R1 and the on-resistance Ronn of N1 and the inserted resistor R2 are:
Ronp << R1, Ron << R2 Formula (1)
R1 = R2 Formula (2)
The values of R1 and R2 are determined so that

  In the charge pump CP of FIG. 7, the stable point V1 varies greatly due to variations in Vth between P1 and N1 (for example, about Vdd / 2 ± 200 mV), and therefore the phase pull-in time may be increased accordingly. In the circuit of the present embodiment, if R1 (= R2) is determined so as to satisfy the expressions (1) and (2), the output stable voltage is determined by the divided voltage of R1 and R2. The variation at Vdd / 2 is smaller than that of the charge pump CP of FIG. (For example, considering the relative variation of R1 and R2, Vdd / 2 ± 50 mV or less) Although the MOSFET on-resistance generally varies widely, the resistance generated by wiring resistance, polysilicon, etc. is generally This is because there is little variation. The settling period to the stable voltage is determined by the time constant of R1 (= R2) and C1, but if Ronp / n≈100Ω, R1 = 2 kΩ is sufficient, and if C1 = 300 pF, settling is possible in about 3 μs. The settling is performed in a time sufficiently shorter than the calibration time (6 μs).

  As described above, the present application proposes a circuit system in which a reference current source is used instead of a reference voltage source at the time of calibration, so that no switch is required at the VCO control node and the setup time of the circuit is shortened. . In addition, a voltage-current conversion circuit that can operate over a wide range regardless of variations in the threshold voltage Vth of the MOSFET and temperature fluctuations has been proposed. A D / A converter circuit that is not affected by the leakage current of the MOSFET in the off state even when a MOSFET having a low threshold voltage Vth is used to secure the operating range of the D / A converter under the low power supply voltage condition Proposed configuration. Furthermore, a circuit is proposed that shortens the phase pull-in time after calibration by precharging the filter capacitance during the calibration period. Furthermore, in order to utilize the calibration function, a PLL circuit with a frequency variable range over / underflow detection function is proposed to ensure continuous stable operation even when the oscillation range of the PLL is outside the variable range. ing. A calibration for selecting an optimal control code from oscillation characteristics that do not increase monotonously with respect to the control code is also proposed.

  In the present application, since the noise from the VCO can be reduced and the jitter characteristics are improved, the clock quality is improved. The reason is that the VCO control node does not have a switching element that becomes a noise source and uses a voltage-current conversion circuit that can operate in a wide range regardless of variations in the threshold voltage Vth and temperature fluctuation of the MOSFET. The gain (K [MHz / V]) can be designed to be small, the noise sensitivity superimposed on the VCO control node is lowered, and the jitter characteristics are improved, so that the clock quality is improved.

  The pull-in time is shortened for a PLL circuit with a calibration function. A frequency variable range over / underflow detection function + a calibration method that selects an optimal control code from oscillation characteristics that do not increase monotonously with respect to the control code makes it possible to supply a stable frequency against environmental fluctuations. In addition, it is possible to follow a change in the user's frequency setting within the oscillation range of the VCO. The reason is that calibration can be performed regardless of the VCO control node voltage, so there is no need to wait for filter voltage setup. For this reason, the calibration time can be shortened. Since the filter capacitance is precharged during the calibration period, the filter voltage can start phase pull-in from the vicinity of the voltage in a substantially stable state, so that the time until the pull-in is completed can be shortened.

  In the PLL circuit according to the present invention, when jitter characteristics are improved (when jitter is small), a logic setup margin such as a flip-flop circuit that operates using this clock can be secured, and stable operation of the logic and high-speed operation are guaranteed. It becomes possible. And system setup is quicker.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, a configuration that uses a low threshold voltage for a D / converter that generates a control signal for calibration and prevents the leakage current itself constitutes the invention. It may be a calibration circuit. Since the configuration in which the voltage of the path of the loop filter and the voltage-current conversion circuit is charged to some extent during the calibration period constitutes the invention in itself, the circuit for performing the calibration is other than the above-described embodiment. May be. Since the configuration for detecting the overflow and underflow of the frequency variable range in the PLL loop and resetting the calibration itself constitutes the invention, the calibration circuit is other than the circuit of the above-described embodiment. It may be. In the search algorithm for specifying the calibration output code, the configuration that monotonically increases the output code of the frequency to be set, and the upper and lower output codes that are separated from the predetermined code from there constitutes the invention by itself. The circuit for performing calibration may be other than the circuit of the above embodiment. In the embodiment, the specific configuration of each circuit block constituting the PLL circuit itself and the calibration circuit can be variously modified.

  In the present invention, system-on-chip LSIs in various fields equipped with analog functions such as large-scale logic, memory, A / D converters, D / A converters equipped with PLL circuits must be equipped with PLL circuits. It is applicable to.

1 is an overall schematic block diagram showing an embodiment of a PLL circuit according to the present invention. FIG. 2 is a circuit diagram showing an example of the voltage-current converter VIC of FIG. 1. FIG. 3 is a voltage-current characteristic diagram of the voltage-current converter VIC of FIG. 2. FIG. 2 is a circuit diagram illustrating an example of a D / A converter iDAC1 of FIG. 1. It is an equivalent circuit diagram for demonstrating an example of operation | movement of the D / A converter iDAC basic cell of this Example. It is an equivalent circuit diagram for demonstrating another example of operation | movement of the D / A converter iDAC basic cell of this Example. FIG. 2 is a circuit diagram showing an embodiment of the charge pump CP and loop fill LF of FIG. 1. It is a circuit diagram for demonstrating operation | movement of charge pump CP of FIG. FIG. 8 is a characteristic diagram for explaining the operation of the charge pump CP of FIG. 7. It is a wave form diagram for demonstrating an example of PLL pull-in operation | movement of the PLL circuit based on this invention. It is a block diagram which shows another Example of the PLL circuit with a calibration function based on this invention. It is a characteristic view for demonstrating the operation | movement of the VCODAC of FIG. 11, and a V / I converter. It is a characteristic view for demonstrating operation | movement of the detection V / I converter of FIG. FIG. 12 is a circuit diagram illustrating an example of an I / V converter of the overflow / underflow detection unit in FIG. 11. FIG. 12 is a characteristic diagram for explaining an operation when an overflow / underflow detection unit in FIG. 11 detects an overflow. It is a circuit diagram which shows one Example of the current output part of FIG. It is a characteristic view for demonstrating the drawing-in operation | movement to the normal operation range by the electric current output part of FIG. It is a frequency characteristic figure of one Example of the calibration circuit based on this invention. It is a frequency characteristic diagram for demonstrating an example of PLL calibration operation | movement. It is a frequency characteristic diagram for demonstrating an example of PLL calibration operation | movement which concerns on this invention. It is a timing diagram for demonstrating the irregular frequency binary search which concerns on this invention. It is a partial flowchart figure for demonstrating the irregular frequency binary search which concerns on this invention. It is a flowchart of the remaining part for demonstrating the irregular frequency binary search which concerns on this invention. FIG. 2 is a block diagram illustrating an embodiment of the calibration circuit of FIG. 1. FIG. 25 is a circuit diagram showing an embodiment of an internal clock generation circuit used in the calibration circuit of FIG. 24. FIG. 25 is a timing chart for explaining a calibration operation using the internal clock generation circuit of FIG. 24. FIG. 25 is a block diagram illustrating an example of a frequency comparison counter in FIG. 24. FIG. 25 is an operation explanatory diagram of the irregular frequency binary search circuit of FIG. 24. FIG. 3 is a circuit diagram showing another embodiment of the voltage-current converter VIC of FIG. 1. FIG. 8 is a circuit diagram showing another embodiment of the charge pump CP of the charge pump CP and the loop fill LF of FIG. 7.

Explanation of symbols

FC ... frequency comparator, FSCONT ... frequency search state circuit, CTG ... control timing generation circuit, SEL1 to SEL4 ... selector, iDAC1, iDAC2 ... current D / A converter, MC, NC, PC ... frequency divider, PFC ... phase Comparator, CP ... charge pump, VIC ... voltage-current converter, CCO ... current controlled oscillator, VCO ... voltage controlled oscillator, S1-S3 ... switch, DP1, DP2, DN1, DN2 ... differential amplifier (differential vs. MOSFET) ), P1 to P5... P channel MOSFET, N1 to N2... N channel MOSFET, Q1 to Q4... MOSFET, IV0 to IV2... CMOS inverter circuit, G1, G2, G10 to G12.

Claims (19)

A current-controlled oscillator whose oscillation frequency is controlled in response to the control current;
A phase comparator that receives a frequency signal and a reference signal formed based on an oscillation signal of the current-controlled oscillator, and forms a phase comparison signal;
A loop filter for extracting a low frequency component of the phase comparison signal;
A voltage-current converter that receives an output voltage formed by the loop filter and converts the output voltage into a first current included in the control current;
A calibration circuit for changing the self-excited oscillation frequency of the current-controlled oscillator according to the reference signal;
The voltage-current converter includes a plurality of differential amplifiers,
A reference voltage generation circuit that forms a plurality of different reference voltages,
An output voltage formed by the loop filter is supplied to one differential input element of the plurality of differential amplifiers,
Different reference voltages generated by the reference voltage generation circuit are respectively supplied to the other differential input elements of the plurality of differential amplifiers,
A PLL circuit comprising the output currents of the plurality of differential amplifiers combined to form the first current. The differential input elements of the plurality of differential amplifiers include one or more first circuits configured by P-channel MOSFETs and one or more second circuits configured by N-channel MOSFETs,
The first circuit corresponds to the reference voltage on the low voltage side,
The PLL circuit according to claim 1, wherein the second circuit corresponds to a reference voltage on a high voltage side. In claim 2,
A second current mirror circuit for transmitting a second current corresponding to the self-excited oscillation operation;
The first current mirror path for transmitting the first current is connected to the gate of the current mirror output MOSFET via the first switch,
The second current mirror path is connected to the gate of the current mirror output MOSFET through a second switch,
When the operation of the calibration circuit is enabled, the first switch path is turned off and the second switch path is turned on.
After the self-excited oscillation frequency corresponding to the reference signal is set by the operation of the calibration circuit, the second switch path is turned off and the first switch path is turned on. PLL circuit. In claim 3,
2. The PLL circuit according to claim 1, wherein the reference voltage generation circuit generates the different reference voltages based on voltages divided by a plurality of resistors connected between a first power source and a lower second power source. In claim 3,
The current-controlled oscillator performs an oscillation operation by combining the third current formed by the D / A converter and the first or second current,
The calibration circuit
The reference signal and the frequency signal are counted for a certain period, and the digital signal supplied to the input of the D / A converter that forms the third current is sequentially formed from the most significant bit according to the magnitude comparison result. PLL circuit characterized by the above. In claim 5,
A PLL circuit having a monotonically increasing relationship in which the current value of the control current increases as the first current value increases. In claim 5,
The D / A converter is
A first MOSFET in the form of a diode through which a reference current flows;
A plurality of second MOSFETs connected to the first MOSFET and the current mirror form according to the ON state of the first switch MOSFET are provided corresponding to the input digital signal,
The sum of the size of the second MOSFET multiplied by the number is set corresponding to the binary weight of the input digital signal,
The first switch MOSFET is switch-controlled by a corresponding digital signal,
An output current is formed by synthesizing currents flowing through the plurality of second MOSFETs,
The source of the second MOSFET is connected to the output terminal of the first CMOS inverter circuit that receives the corresponding digital signal,
A second switch MOSFET is connected between the gate of the second MOSFET and the ground potential,
The first switch MOSFET and the second switch MOSFET are complementarily controlled by an input digital signal,
When the digital signal is logic 1, the first switch MOSFET is turned on and the second switch MOSFET is turned off, and the first CMOS inverter circuit forms a low level output signal,
When the digital signal is logic 0, the first switch MOSFET is turned off and the second switch MOSFET is turned on, and the first CMOS inverter circuit forms a high level output signal,
The PLL circuit according to claim 1, wherein the first MOSFET, the second MOSFET, and the first switch MOSFET are set to a lower threshold voltage than the second switch MOSFET. In claim 7,
The source of the first MOSFET is connected to the output terminal of the second CMOS inverter circuit,
The PLL circuit according to claim 2, wherein the second CMOS inverter circuit forms a low-level output signal at least when the D / A converter is in an operating state. In claim 3,
When the operation of the calibration circuit is enabled and the first switch path is turned off and the second switch path is turned on, the loop filter is controlled to form an intermediate voltage of the maximum control voltage. A PLL circuit characterized by that. In claim 9,
The loop filter includes a charge pump circuit that is switch-controlled by an up signal and a down signal formed by the phase comparator,
A PLL circuit characterized in that when the operation of the calibration circuit is enabled, two switch MOSFETs constituting a charge pump circuit are turned on to form the intermediate voltage. In claim 5,
A PLL circuit characterized by having an overflow / underflow detection function for a PLL frequency variable range, resetting a predetermined bit of the calibration circuit, and continuously operating a PLL operation. In claim 5,
A PLL circuit comprising a function of temporarily setting a plurality of high-order bits including the most significant bit and selecting a variable frequency range controlled by the low-order bits in a monotonically increasing manner. A current-controlled oscillator whose oscillation frequency is controlled in response to the control current;
A phase comparator that receives a frequency signal and a reference signal formed based on an oscillation signal of the current-controlled oscillator, and forms a phase comparison signal;
A loop filter for extracting a low frequency component of the phase comparison signal;
A voltage-current converter that receives an output voltage formed by the loop filter and converts the output voltage into a first current included in the control current;
A calibration circuit for changing the self-excited oscillation frequency of the current-controlled oscillator according to the reference signal;
The output signal of the loop filter is constantly transmitted without interposing a switch in the voltage-current converter,
The voltage-current converter uses a MOSFET to convert an input voltage into a current signal to form an output current through a current mirror circuit, and at the same time, a calibration is applied to the gate of the current mirror type output MOSFET that forms the output current. The switch switches the voltage corresponding to the current for calibration and the voltage corresponding to the current for PLL operation during the operation of changing the self-excited oscillation frequency of the current controlled oscillator according to the reference signal by the circuit. A PLL circuit characterized by being conveyed. A current-controlled oscillator whose oscillation frequency is controlled in response to the control current;
A phase comparator that receives a frequency signal and a reference signal formed based on an oscillation signal of the current-controlled oscillator, and forms a phase comparison signal;
A loop filter for extracting a low frequency component of the phase comparison signal;
A voltage-current converter that receives an output voltage formed by the loop filter and converts the output voltage into a first current included in the control current;
A calibration circuit for changing the self-excited oscillation frequency of the current-controlled oscillator according to the reference signal;
The current-controlled oscillator performs an oscillation operation by combining the third current formed by the D / A converter and the first current.
The D / A converter is
A first MOSFET in the form of a diode through which a reference voltage flows;
A plurality of second MOSFETs connected to the first MOSFET and the current mirror form according to the ON state of the first switch MOSFET are provided corresponding to the input digital signal,
The sum of the size of the second MOSFET multiplied by the number is set corresponding to the binary weight of the input digital signal,
The first switch MOSFET is switch-controlled by a corresponding digital signal,
An output current is formed by synthesizing currents flowing through the plurality of second MOSFETs,
The source of the second MOSFET is connected to the output terminal of the first CMOS inverter circuit that receives the corresponding digital signal,
A second switch MOSFET is connected between the gate of the second MOSFET and the ground potential,
The first switch MOSFET and the second switch MOSFET are complementarily controlled by an input digital signal,
When the digital signal is logic 1, the first switch MOSFET is turned on and the second switch MOSFET is turned off, and the first CMOS inverter circuit forms a low level output signal,
When the digital signal is logic 0, the first switch MOSFET is turned off and the second switch MOSFET is turned on, and the first CMOS inverter circuit forms a high level output signal,
The PLL circuit according to claim 1, wherein the first MOSFET, the second MOSFET, and the first switch MOSFET are set to a lower threshold voltage than the second switch MOSFET. In claim 14,
The source of the first MOSFET is connected to the output terminal of the second CMOS inverter circuit,
The PLL circuit according to claim 2, wherein the second CMOS inverter circuit forms a low-level output signal at least when the D / A converter is in an operating state. A current-controlled oscillator whose oscillation frequency is controlled in response to the control current;
A phase comparator that receives a frequency signal and a reference signal formed based on an oscillation signal of the current-controlled oscillator, and forms a phase comparison signal;
A loop filter for extracting a low frequency component of the phase comparison signal;
A voltage-current converter that receives an output voltage formed by the loop filter and converts the output voltage into a first current included in the control current;
A calibration circuit for changing the self-excited oscillation frequency of the current-controlled oscillator according to the reference signal;
When the self-excited oscillation frequency of the current controlled oscillator is changed corresponding to the reference signal by the operation of the calibration circuit, the loop filter is controlled to form an intermediate voltage of a maximum control voltage. PLL circuit. In claim 16,
The loop filter includes a charge pump circuit that is switch-controlled by an up signal and a down signal formed by the phase comparator,
A PLL circuit characterized in that when the operation of the calibration circuit is enabled, two switch MOSFETs constituting a charge pump circuit are turned on to form the intermediate voltage. A current-controlled oscillator whose oscillation frequency is controlled in response to the control current;
A phase comparator that receives a frequency signal and a reference signal formed based on an oscillation signal of the current-controlled oscillator and forms a phase comparison signal;
A loop filter for extracting a low frequency component of the phase comparison signal;
A voltage-current converter that receives an output voltage formed by the loop filter and converts the output voltage into a first current included in the control current;
A calibration circuit for changing the self-excited oscillation frequency of the current-controlled oscillator according to the reference signal;
A PLL having a function of detecting an overflow or underflow with respect to a PLL frequency variable range in a PLL loop, resetting a predetermined bit of the calibration circuit, and continuously operating a PLL operation. circuit. A current-controlled oscillator whose oscillation frequency is controlled in response to the control current;
A phase comparator that receives a frequency signal and a reference signal formed based on an oscillation signal of the current-controlled oscillator, and forms a phase comparison signal;
A loop filter for extracting a low frequency component of the phase comparison signal;
A voltage-current converter that receives an output voltage formed by the loop filter and converts the output voltage into a first current included in the control current;
A calibration circuit for changing the self-excited oscillation frequency of the current-controlled oscillator according to the reference signal;
The current controlled oscillator forms a digital signal supplied to the input of the D / A converter that forms the third current formed by the D / A converter in order from the most significant bit, and includes the uppermost bit including the most significant bit. A PLL circuit having a function of temporarily setting a plurality of bits and selecting a variable frequency range controlled by a lower bit monotonically increasing.

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