JP2005057103A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure a heat treatment for recovering the etching damage of a capacitance insulating film and to prevent the characteristic degradation of a capacitive element due to the reduction of hydrogen generated at the capacitance insulating film, in a semiconductor device provided with the capacitive element having a ferroelectric or a high dielectric in the capacitance insulating film. <P>SOLUTION: A spacer insulating film 13 is deposited on the entire surface on a first hydrogen barrier layer 12 so as to embed the capacitive element 11 by a CVD method. Then, by polishing the upper part of the spacer insulating film 13 and the upper side of the capacitive element 11 in the first hydrogen barrier layer 12 until the upper electrode 10 of the capacitive element 11 is exposed by a CMP method, the upper surface of the upper electrode 10, the upper end face on the side face of the capacitive element 11 in the first hydrogen barrier layer 12 and the upper surface of the spacer insulating film 13 are flattened so as to be the same height. Thereafter, on the flattened spacer insulating film 13 and upper electrode 10, a conductive second hydrogen barrier layer 14 is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a capacitive element having a ferroelectric or high dielectric as a capacitive insulating film, and a method for manufacturing the same.

  In recent years, with the advancement of digital technology, the need to process and store large volumes of data has become increasingly demanding, and electronic devices have become more sophisticated, and the miniaturization of elements in semiconductor devices that are being used has been rapidly increasing. Is going on.

  Along with this, in order to realize high integration in dynamic random access memory (DRAM) devices, a technology that uses a high dielectric material for a capacitor insulating film in place of conventional silicon oxide or silicon nitride has been widely researched and developed. Has been. Furthermore, research and development on a ferroelectric film having spontaneous polarization characteristics are actively conducted with the aim of putting a nonvolatile RAM device capable of high-speed writing and high-speed reading at a low operating voltage, which has not been conventionally used.

  One of the most important issues in a semiconductor device having a capacitive element having a high dielectric material or a ferroelectric material as a capacitor insulating film is to suppress the deterioration of characteristics due to reduction of hydrogen generated in the capacitor insulating film. It is to be realized, and furthermore, to be realized at low cost and easily.

  Hereinafter, the first and second conventional examples will be described with reference to the drawings.

(First conventional example)
A first conventional example will be described with reference to FIG. 7 (see, for example, Patent Document 1).

FIG. 7 shows a cross-sectional configuration of a main part of a conventional semiconductor device provided with a capacitive element having a ferroelectric or high dielectric as a capacitive insulating film. As shown in FIG. 7, on a semiconductor substrate 101, a diffusion barrier layer 103 made of silicon oxide first interlayer insulating film 102 and titanium oxide consisting of (SiO ₂₎ (TiO ₂₎ are sequentially formed, an interlayer insulating A plug contact 104 is formed in the film 102 and the diffusion barrier film 103 so as to penetrate the film 102 and the diffusion barrier film 103 and to be electrically connected to the semiconductor substrate 101.

On the diffusion barrier 103, a lower conductive diffusion barrier film 105 made of titanium aluminum nitride (TiAlN) is formed so as to be in contact with the plug contact 104. On the lower conductive diffusion barrier layer 105, iridium ( A lower electrode 106 made of Ir), a capacitive insulating film 107 made of lead zirconium titanate (Pb (Zr _x Ti _1-x ) O ₃ (where 0 ≦ x ≦ 1)), which is a ferroelectric, and iridium ( An upper electrode 108 made of a laminated film of Ir) and iridium oxide (IrO ₂ ) and an upper conductive diffusion barrier film 109 made of titanium aluminum nitride (TiAlN) are sequentially formed to form a capacitive element 110.

On the capacitor element 110, that is, on the upper conductive diffusion barrier film 109, an etching mask 111 made of silicon oxide (SiO ₂ ) used for patterning the capacitor element 110 is formed, and on the side surface of the capacitor element 110. An insulating diffusion barrier film 112 made of a laminated film of silicon nitride (Si ₃ N ₄ ) and titanium oxide (TiO 2) is formed.

  The capacitive element 110 is covered with a second interlayer insulating film 113, and a wiring 114 is formed on the second interlayer insulating film 113 so as to be connected to the upper conductive diffusion barrier 109.

(Second conventional example)
Next, a second conventional example will be described with reference to FIG. 8 (see, for example, Patent Document 2).

FIG. 8 shows a cross-sectional configuration of a main part of another conventional semiconductor device provided with a capacitive element having a ferroelectric or high dielectric as a capacitive insulating film. As shown in FIG. 8, a first interlayer insulating film 102 is formed on a semiconductor substrate 101, and a first layer made of silicon nitride (Si ₃ N ₄ ) is formed on the first interlayer insulating film 102. A hydrogen barrier film 116, a lower electrode 117 made of a laminated film of titanium (Ti) and platinum (Pt), a capacitive insulating film 118 made of strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ ) as a ferroelectric, A capacitive element 120 constituted by an upper electrode 119 made of platinum (Pt) is formed.

  A second hydrogen barrier film 121 made of silicon nitride is formed so as to cover the upper surface and side surfaces of the capacitor element 120, and the lower end portion thereof is in contact with the peripheral edge portion of the first hydrogen barrier film 116. The second hydrogen barrier film 121 is provided with a contact hole 121a exposing the upper electrode 119, and the second hydrogen barrier film 121 is made of titanium nitride (TiN), tantalum nitride (TaN), or the like. A third hydrogen barrier film 122 is filled in the contact hole 121a and is electrically connected to the upper electrode 119.

The capacitor element 120 including the third hydrogen barrier film 122 is covered with a second interlayer insulating film 123, and a wiring 124 is connected to the third hydrogen barrier film 122 on the second interlayer insulating film 123. It is formed to be connected.
JP 2000-133633 A (pages 7-9, FIGS. 6a-6f) No. 3098474 (Page 4, Figure 4)

  However, as in the first and second conventional examples, it is difficult to realize high performance of a semiconductor device including a capacitive element including a capacitive insulating film made of a ferroelectric or a high dielectric material at low cost. There's a problem.

  Hereinafter, the reason will be described in detail.

  In general, after patterning the capacitive element by dry etching, the capacitive insulating film made of a ferroelectric material is destroyed in its crystal structure due to damage received during the etching, so that the temperature is 500 ° C. to 800 ° C. in order to recrystallize. Heat treatment in an oxygen atmosphere at 0 ° C. is required.

  However, the first conventional example cannot perform heat treatment for recrystallization. This is because, in FIG. 7, the surface of the upper conductive diffusion barrier film 109 is oxidized by heat treatment in an oxygen atmosphere, thereby causing the following two problems. The first problem is that the contact resistance cannot be lowered as a result of the formation of a high-resistance insulating layer at the interface between the wiring 113 and the upper conductive diffusion barrier 109 film. The second problem is that the upper conductive diffusion barrier film 109 is oxidized and expanded by heat treatment in an oxygen atmosphere, and the expanded upper conductive diffusion barrier film 109 is peeled off from the upper electrode 108.

  In the second embodiment, in order to solve the problem in the first conventional example, the second hydrogen barrier film 121 covering the upper surface and the side surface of the capacitive element 120 is formed, and the contact hole 121a is formed in the formed hydrogen barrier film 121. After the formation, heat treatment is performed in an oxygen atmosphere at a temperature of 500 ° C. to 800 ° C. to perform recrystallization, and then a third hydrogen barrier film 122 is formed. In this configuration, the third hydrogen barrier film 122 made of TiN or the like is not oxidized by the heat treatment in an oxidizing atmosphere for recrystallization. However, in order to process each of the second hydrogen barrier film 121, the contact hole 121a, and the third hydrogen barrier film 122, three mask processes are required separately from the processing (patterning) of the capacitor element 120. Become. That is, in the second conventional example, although heat treatment for recrystallization can be performed on the capacitive insulating film 118 damaged by dry etching, the manufacturing process becomes complicated instead. In addition, it is impossible to form a semiconductor device having a capacitive element, in particular, a capacitive film made of a ferroelectric or high dielectric, at a low cost.

  The present invention solves the above-mentioned conventional problems, and in a semiconductor device including a capacitor element having a ferroelectric or high dielectric as a capacitor insulating film, heat treatment for recovering etching damage of the capacitor insulating film can be performed, and the capacitor It is an object of the present invention to prevent deterioration of characteristics of a capacitor element due to reduction of hydrogen generated in an insulating film.

  In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device comprising: forming a first hydrogen barrier layer and a buried insulating film (spacer insulating film) so as to cover a capacitive element after patterning the capacitive element; And forming the spacer insulating film and the upper portion of the capacitor element in the first hydrogen barrier layer so that the capacitor element is exposed, and then the second hydrogen barrier layer is formed with the upper electrode and the first hydrogen barrier layer. It is set as the structure formed so that it may touch.

  Specifically, the method for manufacturing a semiconductor device according to the present invention includes a lower electrode, a capacitive insulating film made of a ferroelectric or a high dielectric, and an upper electrode on a first insulating film (interlayer insulating film). A first step of forming a capacitive element, and a second step of forming a first hydrogen barrier layer for preventing diffusion of hydrogen to the capacitive insulating film so as to cover the capacitive element on the first insulating film. A third step of forming a second insulating film (spacer insulating film) on the first hydrogen barrier layer, and an upper portion of the capacitor element in the second insulating film and the first hydrogen barrier layer. A fourth step of planarizing the upper electrode so that the upper electrode is exposed; and a second hydrogen barrier layer having conductivity on the planarized second insulating film, the upper electrode and the first hydrogen barrier layer And a fifth step of forming so as to be in contact with each other.

  According to the method for manufacturing a semiconductor device of the present invention, after forming (patterning) a capacitor element, a first hydrogen barrier layer and a second insulating film (spacer insulating film) are formed so as to cover the capacitor element. The upper portion of the capacitor element in the second insulating film and the first hydrogen barrier layer is flattened so that the capacitor element is exposed, and then the second hydrogen barrier layer is formed into an upper electrode and a first hydrogen barrier layer. Form to touch. Therefore, after the capacitor element is formed, the side surface of the capacitor element is covered with the first hydrogen barrier layer, and the planarized upper surface is covered with the second hydrogen barrier layer. Accordingly, a mask process for forming the hydrogen barrier layer covering the capacitor element is not necessary, and the manufacturing process can be simplified. In addition, heat treatment for recovering the etching damage of the capacitor insulating film can be performed, and the capacitor is covered with the hydrogen barrier layer, so that deterioration of characteristics of the capacitor insulating film due to hydrogen can be prevented.

  In the method of manufacturing a semiconductor device according to the present invention, the first step is a step of depositing a lower electrode formation film over the entire surface of the first insulation film, and a capacitor insulation film formation film is deposited on the lower electrode formation film. A step of depositing a formation film for the upper electrode on the capacitor insulating film formation film, a step of forming a mask pattern for patterning the capacitor element on the upper electrode formation film, and an upper portion using the mask pattern By etching the electrode forming film, the capacitive insulating film forming film, and the lower electrode forming film, the upper electrode, the capacitive insulating film, and the lower electrode are respectively formed from the upper electrode forming film, the capacitive insulating film forming film, and the lower electrode forming film. Preferably, the process of forming is included.

  In this case, the first step forms a third hydrogen barrier layer for preventing hydrogen diffusion to the capacitive insulating film over the entire surface of the first insulating film before depositing the lower electrode forming film. It is preferable that the process to include is included.

  The method for manufacturing a semiconductor device of the present invention further includes a sixth step of performing heat treatment in an oxidizing atmosphere on the capacitive insulating film after the first step and before the fifth step. It is preferable. In this case, since the heat treatment is performed on the capacitive insulating film before the second hydrogen barrier layer is formed, it is possible to prevent problems caused by the oxidation of the second hydrogen barrier layer.

  In this case, the temperature range of the heat treatment in the sixth step is preferably 500 ° C to 800 ° C.

  In the method for manufacturing a semiconductor device of the present invention, the fourth step is preferably performed by a chemical mechanical polishing method, an etch back method, or a combination thereof.

In the semiconductor device manufacturing method of the present invention, the first hydrogen barrier layer is made of at least one material selected from the group consisting of SiN, SiON, Al ₂ O ₃ , TiAlO, TaAlO, TiSiO, and TaSiO. It is preferable.

  In the semiconductor device manufacturing method of the present invention, the second hydrogen barrier layer is made of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TaAl, TiSiN, TaSiN, Ti and Ta. Is preferred.

  In the semiconductor device manufacturing method of the present invention, the third hydrogen barrier layer is preferably made of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TiSiN, and TaSiN.

In the method for manufacturing a semiconductor device of the present invention, the capacitive insulating film is made of SrBi ₂ (Ta _x Nb _{1 -x} ) ₂ O ₉ , Pb (Zr _x Ti _{1 -x} ) O ₃ , (Ba _x Sr _{1 -x} ) TiO. _{3, (Bi x La 1-} x) 4 Ti 3 O 12 ( where both x is 0 ≦ x is ≦ 1.) and is composed of one material selected from the group of Ta ₂ O ₅ Preferably it is.

  A semiconductor device according to the present invention includes a plurality of capacitive elements, each of which is sequentially formed on a first insulating film and includes a lower electrode, a capacitive insulating film made of a ferroelectric or a high dielectric, and an upper electrode; A plurality of first hydrogen barrier layers that are formed on the side surfaces of each capacitive element so that the upper end surface thereof substantially coincides with the upper surface of the upper electrode, and prevents diffusion of hydrogen into the capacitive insulating film, and on the upper electrode And a plurality of second hydrogen barrier layers formed to be in contact with the respective upper end surfaces of the first hydrogen barrier layer and having conductivity to prevent diffusion of hydrogen into the capacitive insulating film.

  Since the semiconductor device of the present invention includes the hydrogen barrier layer obtained by the manufacturing method according to the present invention and protecting the capacitive element from hydrogen, the semiconductor device is easy to manufacture and is excellent in electrical characteristics such as retention characteristics.

  In the semiconductor device of the present invention, each second hydrogen barrier layer preferably constitutes a cell plate line by being connected to upper electrodes of a plurality of capacitive elements.

  The semiconductor device of the present invention preferably further includes a conductive layer electrically connected to each second hydrogen barrier layer.

  In this case, the conductive layer is preferably formed by being laminated on each second hydrogen barrier layer. In this way, the range of selection of the material constituting the second hydrogen barrier layer can be expanded. In addition, since the electric resistance is reduced, the operation speed of the semiconductor device can be increased.

  In the semiconductor device of the present invention, it is preferable that the plurality of capacitor elements are formed with a space therebetween, and a region between the capacitor elements on the first insulating film is buried with the second insulating film.

  In the semiconductor device of the present invention, the capacitor element is preferably formed such that the lower electrode, the capacitor insulating film, and the upper electrode have the same planar shape.

  In the semiconductor device of the present invention, a plurality of third hydrogen barrier layers for preventing diffusion of hydrogen to the respective capacitive insulating films are formed below each lower electrode, and the side of each third hydrogen barrier layer is formed. The end face is preferably in contact with the first hydrogen barrier layer. In this way, the lower side of the capacitive element can be covered with the hydrogen barrier layer.

  In this case, it is preferable that each third hydrogen barrier layer has the same planar shape as each lower electrode.

  In the semiconductor device of the present invention, a fourth hydrogen barrier layer having insulating properties for preventing diffusion of hydrogen to each capacitive insulating film is formed between the first insulating film and each lower electrode. The hydrogen barrier layer is preferably in contact with the lower surface of the first hydrogen barrier layer. In this way, hydrogen diffusion from the lower side of the capacitive element can be prevented more reliably.

  The semiconductor device of the present invention preferably further includes a plurality of plug contacts formed on the first insulating film so as to be electrically connected to each lower electrode.

In the semiconductor device of the present invention, the first hydrogen barrier layer is preferably made of at least one material selected from the group consisting of SiN, SiON, Al ₂ O ₃ , TiAlO, TaAlO, TiSiO, and TaSiO. .

  In the semiconductor device of the present invention, the second hydrogen barrier layer is preferably composed of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TaAl, TiSiN, TaSiN, Ti, and Ta.

  In the semiconductor device of the present invention, the conductive layer is preferably made of at least one material selected from the group consisting of TiAl, TiN, Ti, TaN, Ta, Al, W, and Cu.

  In the semiconductor device of the present invention, the third hydrogen barrier layer is preferably made of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TiSiN, and TaSiN.

In the semiconductor device of the present invention, the fourth hydrogen barrier layer is preferably composed of at least one material selected from the group consisting of SiN, SiON, Al ₂ O ₃ , TiAlO, TaAlO, TiSiO, and TaSiO. .

In the semiconductor device of the present invention, the capacitive insulating film includes SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ , Pb (Zr _x Ti _1-x ) O ₃ , (Ba _x Sr _1-x ) TiO ₃ , ( Bi _x La _1-x ) ₄ Ti ₃ O ₁₂ (where x is 0 ≦ x ≦ 1) and one material selected from the group consisting of Ta ₂ O ₅ preferable.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, the manufacturing process can be simplified because the mask process for forming the hydrogen barrier layer covering the capacitor element is not necessary. In addition, the heat treatment for recovering the etching damage of the capacitor insulating film can be surely performed, and the capacitor element is covered with the hydrogen barrier layer, so that deterioration of characteristics of the capacitor insulating film due to hydrogen can be prevented.

(Embodiment)
An embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a plan configuration of a main part of a semiconductor device according to an embodiment of the present invention, FIG. 2 (a) shows a cross-sectional configuration taken along line IIa-IIa in FIG. 1, and FIG. The cross-sectional structure in the IIb-IIb line | wire is shown.

  As shown in FIGS. 1 and 2A and 2B, for example, a plurality of element isolation regions 2 made of shallow trench isolation (STI) or the like are formed on the main surface of a semiconductor substrate 1 made of silicon (Si). And a plurality of element active regions 3 partitioned by the element isolation region 2 are formed.

  Each element active region 3 is formed with a transistor (not shown) that can selectively access a plurality of capacitance elements described later.

On the semiconductor substrate 1, an interlayer insulating film 4 as a first insulating film mainly composed of silicon oxide (SiO ₂ ) is formed so as to cover the element isolation region 2 and the element active region 3. On the interlayer insulating film 4, a fourth hydrogen barrier layer 5 mainly composed of silicon nitride (SiN) having a thickness of 10 nm to 200 nm is formed.

  A plug contact 6 electrically connected to the element active region 3 is formed above each element active region 3 in the interlayer insulating film 4 and the fourth hydrogen barrier layer 5. Here, a conductive material such as polysilicon or tungsten (W) is used for the plug contact 6.

  A third hydrogen barrier layer 7 mainly composed of titanium aluminum nitride (TiAlN) having a thickness of 50 nm to 200 nm is formed on the fourth hydrogen barrier layer 5 and connected to the plug contacts 6. . The third hydrogen barrier layer 7 can also function as an oxygen barrier layer that prevents the diffusion of oxygen and prevents the plug contact 6 from oxidizing and increasing the contact resistance.

On the third hydrogen barrier 7, films are sequentially formed from the substrate side. For example, the conductive oxygen is composed of a first barrier layer made of iridium (Ir) and a second barrier layer made of iridium oxide (IrO ₂ ). A lower electrode 8 composed of a barrier layer and an electrode material such as platinum (Pt) is formed. Here, the thickness of the first barrier layer is 50 nm to 200 nm, the thickness of the second barrier layer is 30 nm to 200 nm, and the thickness of the lower electrode 8 is 30 nm to 100 nm.

On the lower electrode 8, an insulating metal oxide and a ferroelectric material, for example, strontium bismuth tantalum niobate (SrBi ₂ (Ta _x , Nb _{1 -x} ) ₂ O ₉ ) (where x is 0 ≦ x ≦ 1), and a capacitor insulating film 9 having a thickness of 50 nm to 150 nm is formed. The capacitor insulating film 9 is not limited to SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ , but is lead zirconium titanate (Pb (Zr _x Ti _1-x ) O ₃ ), barium strontium titanate ((Ba _{x Sr 1-x) TiO 3} ), bismuth lanthanum titanate _{((Bi x La 1-x} ) 4 Ti 3 O 12) ( where both, x is a 0 ≦ x ≦ 1.), or pentoxide Tantalum (Ta ₂ O ₅ ) can be used.

  On the capacitor insulating film 9, an upper electrode 10 mainly composed of platinum (Pt) having a thickness of 30 nm to 150 nm is formed. The lower electrode 8, the capacitive insulating film 9 and the upper electrode 10 constitute a capacitive element 11.

  In the capacitive element 11 according to the present embodiment, as described later, the third hydrogen barrier layer 7, the lower electrode 8, the capacitive insulating film 9, and the upper electrode 10 are all patterned using one mask. Each end is substantially linear.

On the side end face of the third hydrogen barrier layer 7 and the side face of the capacitor element 11, for example, an insulating property having a thickness of 10 nm to 50 nm and made of titanium aluminum oxide (TiAlO) or aluminum oxide (Al ₂ O ₃ ). A first hydrogen barrier layer 12 is formed.

  Here, the first hydrogen barrier layer 12 is in contact with the fourth hydrogen barrier layer 5 in the peripheral region of the capacitive element 11, but there is a region where the fourth hydrogen barrier layer 5 is not formed. In this case, the interlayer insulating film 4 is contacted.

The first hydrogen barrier layer 12 is not limited to TiAlO and Al ₂ O ₃ , but is silicon nitride (SiN), silicon oxynitride (SiON), tantalum aluminum oxide (TaAlO), titanium silicide oxide (TiSiO), or silicide. Tantalum oxide (TaSiO) can be used.

  Further, a spacer insulating film 13 as a second insulating film mainly composed of silicon oxide or silicon nitride is formed between the adjacent capacitive elements 11 so as to cover the first hydrogen barrier layer 12. ing.

  As a feature of the present embodiment, the upper surface of the upper electrode 10, the upper end surface of the first hydrogen barrier layer 12 located on the side surface of the capacitive element 11, and the upper surface of the spacer insulating film 13 have substantially the same height. It has been flattened. On the planarized spacer insulating film 13, a conductive second hydrogen barrier layer 14 mainly composed of titanium aluminum nitride (TiAlN) having a thickness of 20 nm to 300 nm is formed between the upper electrode 10 and the first electrode. It is selectively formed so as to be in contact with the hydrogen barrier layer 12. Here, the second hydrogen barrier layer 14 is not limited to TiAlN, titanium aluminum (TiAl), tantalum aluminum nitride (TaAlN), tantalum aluminum (TaAl), silicified titanium nitride (TiSiN), silicified tantalum nitride (TaSiN), Titanium (Ti) or tantalum (Ta) can be used.

  As shown in FIG. 1 and FIG. 2B, the second hydrogen barrier layer 14 is discontinuously arranged depending on the direction even between the capacitive elements 11 adjacent to each other. Further, the second hydrogen barrier layer 14 can have a function as a cell plate line.

  As described above, according to the present embodiment, in the manufacturing process, only the mask for patterning the second hydrogen barrier layer 14 is required in addition to the mask for patterning the capacitive element 11. Since each capacitive element 11 is completely covered by the first hydrogen barrier layer 12, the second hydrogen barrier layer 14, the third hydrogen barrier layer 7, and the fourth hydrogen barrier layer 5, it is very easy, that is, at low cost. It is possible to prevent deterioration in characteristics of the capacitor element 11 due to reduction of hydrogen generated in the capacitor insulating film 9.

  FIG. 3 shows the result of evaluating the remanent polarization (2Pr) of the capacitive element 11 according to this embodiment before and after the heat treatment (hydrogen sintering) in a hydrogen atmosphere. The conditions of hydrogen sintering are as follows: atmosphere is 100% hydrogen, temperature is 400 ° C., and time is 10 minutes. As shown in FIG. 3, the residual polarization of the capacitive element 11 according to the present embodiment hardly changes before and after the heat treatment in the hydrogen atmosphere. Therefore, the semiconductor device including the capacitive element according to the present invention is Very excellent device characteristics can be exhibited.

(First modification)
Next, a first modification of the semiconductor device according to the present embodiment will be described with reference to the drawings. As means for reducing the resistance of the second hydrogen barrier layer 14, a conductive layer 15 electrically connected in parallel with the second hydrogen barrier layer 14 is disposed. Specifically, as shown in FIG. 4A, an inter-wiring insulating film 16 including a via 17 connected to the second hydrogen barrier layer 14 is formed above the second hydrogen barrier layer 14 to form a wiring. A conductive layer 15 is provided on the intermediate insulating film 16 so as to be connected to the via 17. In this way, the selection range of the material used for the second hydrogen barrier layer 14 can be expanded. In addition, the conductive layer 15 can be used as a cell plate line, and if a material having a lower resistivity than the second hydrogen barrier layer 14 is selected for the conductive layer 15, the electric resistance of the cell plate line itself is reduced. Therefore, the operation speed of the semiconductor device can be improved.

  For example, the conductive layer 15 includes titanium aluminum (TiAl), titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), aluminum (Al), tungsten (W), or copper. (Cu) can be used.

(Second modification)
As a second modification of the semiconductor device according to the present embodiment, as shown in FIG. 4B, a conductive layer 15 may be directly laminated on the second hydrogen barrier layer 14.

(Method for manufacturing semiconductor device)
The semiconductor device manufacturing method according to the present embodiment will be described below with reference to the drawings.

  5 (a) to 5 (c) and FIGS. 6 (a) to 6 (c) are semiconductor device manufacturing methods according to an embodiment of the present invention, and are cross-sections taken along the line IIa-IIa in FIG. The configuration is shown in the order of steps. Here, in FIG.5 and FIG.6, the same code | symbol is attached | subjected to the structural member same as the structural member shown in FIG.1 and FIG.2.

First, as shown in FIG. 5A, an element isolation region 2 is formed on the main surface of a semiconductor substrate 1 made of Si, and the main surface of the semiconductor substrate 1 is partitioned into a plurality of element active regions 3. Subsequently, a gate electrode (not shown) is formed over the element isolation region 2 and the plurality of element active regions 3, and impurity ions are ion-implanted using the formed gate electrode as a mask to form a diffusion layer. And thereby forming a plurality of transistors. Subsequently, an interlayer insulating film 4 containing SiO ₂ as a main component is formed on the entire surface of the semiconductor substrate 1 by, for example, a chemical vapor deposition (CVD) method. Subsequently, a fourth hydrogen barrier layer 5 mainly composed of SiN is formed to a thickness of 10 nm to 200 nm on the interlayer insulating film 4 by a CVD method. Subsequently, contact holes that expose the device active regions 3 are selectively formed in the interlayer insulating film 4 and the fourth hydrogen barrier layer 5 by lithography and dry etching. Thereafter, a conductive material such as polysilicon or tungsten is deposited on the entire surface by CVD or sputtering so that each contact hole is filled on the fourth hydrogen barrier layer 5, and chemical mechanical polishing (CMP) is performed. : The plug contact 6 made of the deposited conductive material is formed by the Chemical Mechanical Polish) method or the etch back method.

Next, as shown in FIG. 5B, TiAlN having a thickness of, for example, 50 nm to 200 nm so as to be connected to each plug contact 6 on the entire surface of the fourth hydrogen barrier layer 5 by, for example, sputtering. A third hydrogen barrier layer forming film is deposited. Subsequently, a lower electrode formation film is deposited on the entire surface of the third hydrogen barrier layer formation film by sputtering. Here, the formation film for the lower electrode includes, in order from the lower layer, a first barrier layer made of Ir, which is a conductive material having an oxygen barrier property with a thickness of 50 nm to 200 nm, and an oxygen barrier property with a thickness of 30 nm to 200 nm. A second barrier layer made of IrO ₂ which is a conductive material having a thickness of Pt and an electrode material having a thickness of 30 nm to 100 nm. Subsequently, a thickness of 50 nm to 50 nm is formed on the entire surface of the lower electrode formation film by a metal organic decomposition (MOD) method, a sputtering method, or a metal organic chemical vapor deposition (MOCVD) method. A capacitor made of, for example, (SrBi ₂ (Ta _x , Nb _1-x ) ₂ O ₉ ) (where x is 0 ≦ x ≦ 1), which is a 150 nm insulating metal oxide and a ferroelectric material. An insulating film forming film is deposited. Subsequently, an upper electrode forming film made of Pt having a thickness of 30 nm to 100 nm is deposited on the entire surface of the capacitive insulating film forming film by, eg, sputtering. Subsequently, a resist pattern having a capacitive element pattern is formed on the upper electrode formation film by a lithography method. Alternatively, a hard mask pattern having a capacitive element pattern made of SiO ₂ , Ti, TiN, TiAlN, or the like is formed by lithography and etching. Subsequently, dry etching is performed on the upper electrode formation film, the capacitor insulating film formation film, the lower electrode formation film, and the third hydrogen barrier layer formation film using the formed resist pattern or hard mask pattern. Thereby, the third hydrogen barrier layer 7 is formed from the third hydrogen barrier layer forming film, the lower electrode 8 is formed from the lower electrode forming film, the capacitive insulating film 9 is formed from the capacitive insulating film forming film, and the upper part The upper electrode 10 is formed from the electrode formation film, and the capacitor element 11 can be obtained with one mask. In this dry etching, a gas containing chlorine is used as an etching gas in the step of patterning the third hydrogen barrier layer 7, the lower electrode 8, and the upper electrode 10, and fluorine is used in the step of patterning the capacitive insulating film 9. Alternatively, a gas containing chlorine is used.

  Here, after the dry etching for obtaining the capacitor element 11, a heat treatment for recrystallization by repairing the disorder of the crystal structure generated at the pattern edge portion of the capacitor insulating film 9 by the dry etching may be performed. The heat treatment conditions are such that the atmosphere is oxygen, the temperature is 500 ° C. to 800 ° C., and the time is about 0.5 to 60 minutes.

Next, as shown in FIG. 5C, the upper surface and the side surface of each capacitive element 11 are formed on the fourth hydrogen barrier layer 5 by the CVD method, the atomic layer deposition (ALD) method, or the sputtering method. A first hydrogen barrier layer 12 made of an insulating material such as TiAlO or Al ₂ O ₃ with a thickness of 10 nm to 50 nm, for example, is deposited over the entire surface so as to cover the surface.

Next, as shown in FIG. 6A, a spacer insulating film 13 mainly composed of SiO ₂ or SiN is deposited on the entire surface of the first hydrogen barrier layer 12 so as to embed the capacitor element 11 by CVD. To do.

  Next, as shown in FIG. 6B, the upper portion of the spacer insulating film 13 and the upper portion of the capacitor element 11 in the first hydrogen barrier layer 12 are polished by CMP, and the upper electrode of the capacitor element 11 is polished. 10 is exposed so that the upper surface of the upper electrode 10, the upper end surface of the first hydrogen barrier layer 12 on the side surface of the capacitive element 11, and the upper surface of the spacer insulating film 13 have substantially the same height. Flattened. Here, after performing the CMP process, oxygen deficiency due to reduction of the capacitive insulating film 9 by hydrogen or moisture generated when the first hydrogen barrier layer 12 and the spacer insulating film 13 are deposited or planarized is compensated. As described above, the temperature may be set to 500 ° C. to 800 ° C. in an atmosphere containing oxygen, and heat treatment for recrystallization for about 0.5 minutes to 60 minutes may be performed.

  Next, as shown in FIG. 6C, a second conductive material mainly composed of TiAlN having a thickness of 20 nm to 300 nm is formed on the spacer insulating film 13 including the upper electrode 10 by sputtering. A hydrogen barrier layer 14 is deposited. As a result, the upper end surface of the first hydrogen barrier layer 12 on the side surface of the capacitive element 11 comes into contact with the lower surface of the second hydrogen barrier layer 14. As a result, the capacitive element 11 has an upper surface formed by the second hydrogen barrier layer 14, a side surface formed by the first hydrogen barrier layer 12, and a lower surface formed by the third hydrogen barrier layer 7 and the fourth hydrogen barrier layer 5. Covered by. Thereafter, as shown in FIG. 1, the second hydrogen barrier layer 14 may be patterned in a stripe shape extending in the IIa-IIa line direction of FIG.

  As described above, according to the present embodiment, when the first hydrogen barrier layer 12 is processed, it is not necessary to use a mask because the CMP method or the etch back method is used, and the capacitor element 11 body is formed. In addition to the masks necessary for the purpose, the only mask required is the mask for patterning the second hydrogen barrier layer 14. Therefore, the structure in which the capacitor element 11 is covered with at least the first hydrogen barrier layer 12 and the second hydrogen barrier layer 14 can be realized very easily and at low cost. It is possible to prevent the deterioration of the characteristics of the capacitor element 11 due to the reduction of the generated hydrogen.

  Further, before the second hydrogen barrier layer 14 is formed on the upper electrode 10 and the spacer insulating film 13, the second hydrogen barrier layer 14 is subjected to heat treatment in an oxygen atmosphere for recrystallization of the capacitor insulating film 9. Compared to the case where the heat treatment for recrystallization of the capacitive insulating film 9 in the oxygen atmosphere is performed after the barrier layer 14 is formed, defects due to oxidation of the second hydrogen barrier layer 14, such as high resistance and film peeling, etc. Can be prevented.

  The semiconductor device and the manufacturing method thereof according to the present invention can simplify the manufacturing process, reliably perform the heat treatment for recovering the etching damage of the capacitor insulating film, and prevent the deterioration of the characteristics of the capacitor insulating film due to hydrogen. Therefore, it is useful for a method of manufacturing a semiconductor device having a capacitive element having a ferroelectric or high dielectric as a capacitive insulating film.

It is a top view which shows the principal part of the semiconductor device which concerns on one Embodiment of this invention. (A) is the structure sectional drawing in the IIa-IIa line | wire of FIG. 1, (b) is the structure sectional drawing in the IIb-IIb line | wire of FIG. It is a graph which shows the result of having evaluated the value of the remanent polarization (2Pr) of the capacitive element in the semiconductor device concerning one embodiment of the present invention before and after hydrogen sintering processing. (A) And (b) shows the principal part of the semiconductor device which concerns on the modification of one Embodiment of this invention, (a) is a structure sectional drawing which concerns on a 1st modification, (b) is a 2nd modification. It is a composition sectional view concerning an example. (A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (A)-(c) is the structure sectional drawing of the order of a process which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. It is a cross-sectional view showing a capacitive element according to a first conventional example. FIG. 10 is a structural cross-sectional view showing a capacitive element according to a second conventional example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 Element active region 4 Interlayer insulation film (1st insulation film)
5 Fourth hydrogen barrier layer 6 Plug contact 7 Third hydrogen barrier layer 8 Lower electrode 9 Capacitive insulating film 10 Upper electrode 11 Capacitor element 12 First hydrogen barrier layer 13 Spacer insulating film (second insulating film)
14 Second hydrogen barrier layer 15 Conductive layer 16 Inter-wiring insulating film 17 Via

Claims (26)

A first step of forming a capacitive element including a lower electrode, a capacitive insulating film made of a ferroelectric or a high dielectric, and an upper electrode on the first insulating film;
A second step of forming a first hydrogen barrier layer for preventing diffusion of hydrogen to the capacitive insulating film so as to cover the capacitive element on the first insulating film;
A third step of forming a second insulating film on the first hydrogen barrier layer;
A fourth step of planarizing the upper portion of the capacitive element in the second insulating film and the first hydrogen barrier layer so that the upper electrode is exposed;
And a fifth step of forming a conductive second hydrogen barrier layer on the planarized second insulating film so as to be in contact with the upper electrode and the first hydrogen barrier layer. A method for manufacturing a semiconductor device. The first step includes
Depositing a lower electrode formation film over the entire surface of the first insulating film;
Depositing a capacitive insulating film forming film on the lower electrode forming film;
Depositing an upper electrode forming film on the capacitor insulating film forming film;
Forming a mask pattern for patterning the capacitive element on the upper electrode formation film;
Using the mask pattern, by etching the upper electrode forming film, the capacitive insulating film forming film and the lower electrode forming film, from the upper electrode forming film, the capacitive insulating film forming film and the lower electrode forming film, The method of manufacturing a semiconductor device according to claim 1, further comprising forming an upper electrode, a capacitor insulating film, and a lower electrode. Before the first step, the lower electrode formation film is deposited,
3. The method of manufacturing a semiconductor device according to claim 2, further comprising a step of forming a third hydrogen barrier layer that prevents diffusion of hydrogen into the capacitive insulating film over the entire surface of the first insulating film. . After the first step and before the fifth step,
The method for manufacturing a semiconductor device according to claim 1, further comprising a sixth step of performing a heat treatment in an oxidizing atmosphere on the capacitive insulating film.   5. The method of manufacturing a semiconductor device according to claim 4, wherein a temperature range of the heat treatment is 500 ° C. to 800 ° C. in the sixth step.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the fourth step is performed by a chemical mechanical polishing method, an etch back method, or a combination thereof. The first hydrogen barrier layer is made of at least one material selected from the group consisting of SiN, SiON, Al ₂ O ₃ , TiAlO, TaAlO, TiSiO, and TaSiO. The manufacturing method of the semiconductor device of description.   The second hydrogen barrier layer is made of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TaAl, TiSiN, TaSiN, Ti, and Ta. Semiconductor device manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the third hydrogen barrier layer is made of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TiSiN, and TaSiN. . The capacitor insulating _{film, SrBi 2 (Ta x Nb 1} -x) 2 O 9, Pb (Zr x Ti 1-x) O 3, (Ba x Sr 1-x) TiO 3, (Bi x La 1-x ₄ ) Ti ₃ O ₁₂ (where x is 0 ≦ x ≦ 1) and Ta ₂ O _5, and one material selected from the group consisting of Ta ₂ O ₅ The manufacturing method of the semiconductor device as described in any one of Claims 1-3. A plurality of capacitive elements each formed sequentially on the first insulating film and including a lower electrode, a capacitive insulating film made of a ferroelectric or a high dielectric, and an upper electrode;
A plurality of first hydrogen barrier layers formed on the side surfaces of each of the capacitive elements so that an upper end surface thereof substantially coincides with an upper surface of the upper electrode, and preventing diffusion of hydrogen into the capacitive insulating film;
A plurality of second hydrogen barrier layers formed on the respective upper electrodes so as to be in contact with the respective upper end surfaces of the first hydrogen barrier layer and having conductivity to respectively prevent diffusion of hydrogen into the capacitive insulating film; A semiconductor device comprising:   12. The semiconductor device according to claim 11, wherein each of the second hydrogen barrier layers constitutes a cell plate line by being connected to the upper electrodes of the plurality of capacitive elements.   The semiconductor device according to claim 11, further comprising a conductive layer electrically connected to each of the second hydrogen barrier layers.   The semiconductor device according to claim 13, wherein the conductive layer is formed by being stacked on the second hydrogen barrier layers.   The plurality of capacitive elements are formed to be spaced from each other, and a region between the capacitive elements on the first insulating film is embedded with a second insulating film. Semiconductor device.   12. The semiconductor device according to claim 11, wherein the capacitor element is formed so that the lower electrode, the capacitor insulating film, and the upper electrode have the same planar shape. A plurality of third hydrogen barrier layers that prevent diffusion of hydrogen into the capacitive insulating films are formed under the lower electrodes.
The semiconductor device according to claim 11, wherein a side end surface of each third hydrogen barrier layer is in contact with the first hydrogen barrier layer.   18. The semiconductor device according to claim 17, wherein each of the third hydrogen barrier layers has the same planar shape as each of the lower electrodes. Between the first insulating film and each of the lower electrodes, a fourth hydrogen barrier layer having an insulating property to prevent diffusion of hydrogen to each of the capacitive insulating films is formed,
The semiconductor device according to claim 11, wherein the fourth hydrogen barrier layer is in contact with a lower surface of the first hydrogen barrier layer.   20. The semiconductor device according to claim 19, further comprising a plurality of plug contacts formed on the first insulating film so as to be electrically connected to the lower electrodes. The first hydrogen barrier layer is made of at least one material selected from the group consisting of SiN, SiON, Al ₂ O ₃ , TiAlO, TaAlO, TiSiO, and TaSiO. The semiconductor device described.   12. The second hydrogen barrier layer is made of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TaAl, TiSiN, TaSiN, Ti, and Ta. Semiconductor device.   The semiconductor device according to claim 13, wherein the conductive layer is made of at least one material selected from the group consisting of TiAl, TiN, Ti, TaN, Ta, Al, W, and Cu.   18. The semiconductor device according to claim 17, wherein the third hydrogen barrier layer is made of at least one material selected from the group consisting of TiAlN, TiAl, TaAlN, TiSiN, and TaSiN. The fourth hydrogen barrier layer is made of at least one material selected from the group consisting of SiN, SiON, Al ₂ O ₃ , TiAlO, TaAlO, TiSiO, and TaSiO. The semiconductor device described. The capacitor insulating _{film, SrBi 2 (Ta x Nb 1} -x) 2 O 9, Pb (Zr x Ti 1-x) O 3, (Ba x Sr 1-x) TiO 3, (Bi x La 1-x ) ₄ Ti ₃ O ₁₂ (where both x is 0 ≦ x ≦ 1.) and Ta ₂ claim 11, characterized in that O has ₅ is composed of one material selected from the group consisting of and A semiconductor device according to 1.

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