JP2005057064A - Group iii nitride semiconductor layer and growth method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor layer capable of effectively preventing through dislocation from occurring in a GaN growth layer and obtaining a high-quality GaN crystal without increasing the number of processes, and to provide a method for growing the group III nitride semiconductor layer. <P>SOLUTION: A thin film 5D containing Si is formed on the irregular surface of a first GaN layer 5C. The thin film 5D containing Si simultaneously supplies NH<SB>3</SB>and SiH<SB>4</SB>to a reactor, which grows on the irregular surface of the first GaN layer 5C at a growth temperature of 1,050°C to a thickness of approximately one to several atom layers. In this manner, the thin film 5D that is formed on the irregular surface of the first GaN layer 5C and contains Si suppresses the propagation of the through dislocation as a minute mask. More specifically, the thin film 5D containing Si has a number of penetrated voids. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a group III nitride semiconductor layer and a growth method thereof, and more particularly to a group III nitride semiconductor layer capable of reducing dislocations and a growth method thereof.

  Conventionally, GaN-based compound semiconductors (hereinafter referred to as “Group III nitride semiconductors”) are known as materials for light-emitting elements in the blue and short wavelength regions. Group III nitride semiconductors are attracting attention because of their direct transition type, high luminous efficiency, and the fact that one of the three primary colors of light is blue.

  Since GaN has a very high melting point and an extremely high equilibrium vapor pressure of nitrogen, there is a problem that it is difficult to produce a high-quality, large-area bulk GaN single crystal substrate. For this reason, GaN semiconductors are formed by heteroepitaxial growth using sapphire or silicon carbide (SiC) as a substrate, but in this case, many threading dislocations are generated in the epitaxial thin film due to lattice / thermal mismatch. It is known. Since this threading dislocation affects optical / electronic device characteristics, various attempts have been made to realize low dislocation.

  For producing a low dislocation GaN substrate, for example, a mask having a window is provided on a substrate such as sapphire, and GaN is vapor-phase grown through this window (see, for example, Patent Document 1). .

  FIG. 4 is a diagram showing a method for manufacturing a single crystal GaN substrate described in Patent Document 1. In FIG.

According to this manufacturing method, as shown in FIG. 4A, a mask 11 having a window 11A is attached to the surface of a substrate 10 made of sapphire or the like, and GaN 12 is vapor-phase grown through the window 11A. As shown in FIG. 4, the GaN 12 having a concavo-convex surface on which a large number of facet surfaces 12A appear is vapor-phase grown. By grinding and polishing the concavo-convex surface of the GaN 12 obtained in this way, a flat and smooth surface as shown in FIG. 4C is obtained, so that the double layer of the GaN 12 / substrate 10 with few threading dislocations. A structure substrate is obtained.
JP 2001-102307 A (FIG. 18)

  However, according to the semiconductor substrate manufacturing method described in Patent Document 1, it is necessary to provide a plurality of masks in order to improve the crystal quality by suppressing the propagation of threading dislocations passing through the window. There is a problem that the number of steps to be formed is increased and the substrate manufacturing cost is increased. Further, since a mask having a window is provided, an etching process for forming the window is required.

  Therefore, an object of the present invention is to effectively prevent the occurrence of threading dislocations in the GaN growth layer, and to obtain a high-quality GaN crystal without increasing the number of steps, a group III nitride semiconductor layer And providing a method for its growth.

  In order to achieve the above object, the present invention provides a first group III nitride semiconductor layer having a predetermined dislocation density and a plurality of voids formed on the surface of the first group III nitride semiconductor layer. And a second group III nitride having a dislocation density smaller than the predetermined dislocation density, grown from the first group III nitride semiconductor layer through the plurality of voids of the thin film containing Si. There is provided a group III nitride semiconductor layer characterized by including a nitride semiconductor layer.

  The first group III nitride semiconductor layer may have a plurality of recesses on the surface.

  The first group III nitride semiconductor layer may be a buffer layer formed on a substrate or a group III nitride semiconductor layer formed on the buffer layer.

  The first group III nitride semiconductor layer may be one of GaN, AlGaN, GaInN, or AlGaInN.

  The second group III nitride semiconductor layer may be one of GaN, AlGaN, GaInN, or AlGaInN.

  The second group III nitride semiconductor layer may be a light emitting element forming semiconductor substrate or a light emitting element semiconductor layer.

  In order to achieve the above object, the present invention provides a first step of forming a first group III nitride semiconductor layer having a predetermined dislocation density, and a surface of the first group III nitride semiconductor layer. A second step of forming a thin film containing Si having a plurality of voids, and growing from the first group III nitride semiconductor layer on the surface of the thin film containing Si via the plurality of voids, And a third step of forming a second group III nitride semiconductor layer having a dislocation density lower than the dislocation density. A method for forming a group III nitride semiconductor layer is provided.

  The first and third steps can be performed by MOVPE or HVPE.

  In the first step, a plurality of recesses may be formed on a surface of the first group III nitride semiconductor layer by controlling a growth rate and a growth temperature.

  In the first step, a plurality of recesses may be formed on the surface of the base layer by etching to form a groove.

  In the first step, a buffer layer may be formed on the substrate as the first group III nitride semiconductor layer, or a group III nitride semiconductor layer may be formed on the buffer layer.

  In the first and third steps, GaN, AlGaN, GaInN, or AlGaInN can be formed as the first and second group III nitride semiconductor layers.

  According to the group III nitride semiconductor layer and the growth method thereof of the present invention, a thin film containing Si having a plurality of voids is formed on the surface of the base group III nitride semiconductor layer, and the plurality of voids are interposed therebetween. Since the target group III nitride semiconductor layer is grown from the group III nitride semiconductor layer, a high-quality group III nitride semiconductor layer with a low dislocation density can be obtained. This group III nitride semiconductor layer is used as a light emitting element forming substrate or a light emitting element semiconductor layer.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic configuration diagram of a group III nitride semiconductor layer manufacturing apparatus according to an embodiment of the present invention. The manufacturing apparatus 1 is for vapor phase growth of GaN based on a hydride vapor phase epitaxy (HVPE), a reactor 2, a susceptor 3 provided in the reactor 2, and a reactor 2. It has the structure which supplies raw material gas and carrier gas via piping 4A-4E. In the following embodiment, a MOVPE apparatus is also used, but the illustration is omitted.

  The reactor 2 performs vapor phase growth based on a source gas supplied by a carrier gas to a Si substrate 5 disposed on the susceptor 3.

In the HVPE apparatus of FIG. 1, the pipes 4A and 4B supply H ₂ or N ₂ as a carrier gas, and either H ₂ or N ₂ is selectively used at the same time. The pipes 4C and 4D supply ammonia as the N source and silane as the Si source. The pipe 4E supplies HCl as a halide material, and supplies HCl to the metal Ga portion 4F to cause reaction to supply GaCl.

  In the present invention, when AlGaN, GaInN, or AlGaInN is grown, metal Al is used as the Al source, and metal In is used as the In source, but description thereof is omitted here.

  Examples of the present invention will be described below.

  FIGS. 2A to 2G show the manufacturing process of the group III nitride semiconductor layer according to the first embodiment.

  The manufacture of the group III nitride semiconductor layer according to Example 1 includes an AlGaN underlayer growth step, a GaN buffer layer growth step, a first GaN layer growth step, an etching step, a Si-containing thin film growth step, 2 based on the GaN layer growth step. In the following description, a thin film containing Si is a layer containing Si at a high concentration and means a layer made of Si, a nitride of Si, or a compound of Si and GaN.

FIG. 2A: AlGaN underlayer growth step First, the surface-cleaned Si substrate 5 is mounted on a susceptor of a MOVPE apparatus (not shown). Next, an AlGaN foundation layer 5A is formed on the Si substrate 5 based on a MOVPE apparatus (not shown). The AlGaN underlayer 5A is supplied with TMA and TMG while supplying NH ₃ to the reactor, and is grown on the underlayer Si substrate 5 to have an Al composition of 20% and a thickness of 0.3 μm.

FIG. 2B: GaN Underlayer Growth Step Next, a GaN underlayer 5B is formed based on a MOVPE apparatus (not shown). The GaN foundation layer 5B is grown to a thickness of 0.5 μm on the AlGaN foundation layer 5A by supplying TMG while supplying NH ₃ to a MOVPE apparatus (not shown). This growth is transferred to the HVPE apparatus of FIG.

FIG. 2C: first GaN layer growth step Next, the first GaN layer 5C is formed based on the HVPE apparatus shown in FIG. The first GaN layer 5C is supplied with NH ₃ to the reactor 2 by supplying GaCl formed by the reaction of Ga in the metal Ga portion 4F provided in the middle of the pipe 4E and HCl in the pipe 4E. The GaN base layer 5B is grown to a thickness of 200 μm at a growth temperature of 0 ° C. The first GaN layer 5C is grown so as to have irregularities on the surface. This unevenness is formed by controlling the growth rate by setting the growth temperature to 900 ° C. and the V group / III ratio of the raw material to 50, for example.

FIG. 2D: Etching Step Next, an etching gas is supplied to the Si substrate 5 mounted on the susceptor 3 based on an etching mechanism (not shown) to leave the first GaN layer 5C, and the Si substrate 5 and AlGaN. The underlayer 5A and the GaN underlayer 5B are removed by etching.

FIG. 2E: Thin Film Growth Step Containing Si Next, a thin film 5D containing Si is provided on the uneven surface of the first GaN layer 5C. The thin film 5D containing Si is supplied with SiH ₄ while supplying NH ₃ to the reactor 2, and has a thickness of about one atomic layer to several atomic layers on the uneven surface of the first GaN layer 5C at a growth temperature of 1050 ° C. To grow. Thus, the thin film 5D containing Si formed on the uneven surface of the first GaN layer 5C suppresses the propagation of threading dislocations as a micro mask. That is, the thin film 5D containing Si has a large number of through holes.

FIG. 2F: Second GaN layer growth step Next, the second GaN layer 5E is formed based on the HVPE apparatus. The second GaN layer 5E is supplied with GaCl in the same manner as the first GaN layer 5C while supplying NH ₃ to the reactor 2, and has a thickness of 50 μm on the thin film 5D containing Si at a growth temperature of 1075 ° C. To grow. In this way, a group III nitride semiconductor layer composed of a low dislocation GaN crystal part is formed.

When the second GaN layer 5E formed on the Si-containing thin film 5D was observed for the GaN crystal of Example 1 described above, the dislocation density was 1 × 10 ⁶ cm ⁻² . Further, in Example 1 in which the Si-containing thin film 5D was not formed, the dislocation density was 3 × 10 ⁷ cm ⁻² , and the Si-containing thin film 5D was effective in suppressing the propagation of threading dislocations. Was confirmed.

  In Embodiment 1, the thin film 5D containing Si is provided on the uneven surface of the first GaN layer 5C. For example, as shown in FIG. 2G, the surface of the GaN foundation layer 5B contains Si. A thin film 5D may be provided, and the first GaN layer 5C may be vapor-phase grown thereon.

  In Example 1, the AlGaN foundation layer 5A and the GaN foundation layer 5B are removed by etching, but the AlGaN foundation layer 5A and the GaN foundation layer 5B may not be removed. In addition, Si tends to collect in the recesses due to the surface energy, and the penetrated voids can be easily formed into protrusions with relatively few threading dislocations. Therefore, threading dislocations can be more efficiently reduced.

  In Example 1, dislocations tend to concentrate in the recesses A of the first GaN layer 5C shown in FIG. Accordingly, when the thin film 5D containing Si is formed thereon, the second GaN layer 5E grows in the vertical direction from the gap of the thin film 5D containing Si. The dislocation density of the second GaN layer 5E grown in the vertical direction from the voids of the Si-containing thin film 5D located other than the recess A of the first GaN layer 5C decreases. For this reason, the dislocation density of the portion of the second GaN layer 5E that grows in the horizontal direction from the vertical growth portion decreases.

  FIGS. 3A to 3G show the manufacturing process of the group III nitride semiconductor layer according to the second embodiment.

  The manufacture of the group III nitride semiconductor layer according to Example 2 includes an AlN buffer layer growth step, a first GaN layer growth step, a substrate processing step, a second GaN layer growth step, and a Si-containing thin film growth step. And a third GaN layer growth step and a GaN layer separation step.

FIG. 3A: AlN buffer layer growth step First, the surface-cleaned sapphire substrate 6 is mounted on a susceptor of a MOVPE apparatus (not shown). Next, an AlN buffer layer 6A is formed based on a MOVPE apparatus (not shown). The AlN buffer layer 6A is grown to a thickness of 0.02 μm on the sapphire substrate 6 by supplying TMA while supplying NH ₃ to a reactor of a MOVPE apparatus (not shown) at a growth temperature of 400 ° C.

FIG. 3B: First GaN layer growth step Next, a first GaN layer 6B is formed based on a MOVPE apparatus (not shown). The first GaN layer 6B is supplied with TMG while supplying NH ₃ to a reactor of a MOVPE apparatus (not shown), and is grown on the AlN buffer layer 6A to a thickness of 1.5 μm at a growth temperature of 1000 ° C.

FIG. 3C: Substrate Processing Step Next, the AlN buffer layer 6A and the first GaN layer 6B are striped by etching on the sapphire substrate 6 provided with the AlN buffer layer 6A and the first GaN layer 6B. To process. Note that the etching process is preferably performed by dry etching. This substrate processing is performed so that the width of the first GaN layer 6B serving as a seed is 5 μm, the groove 6a formed between adjacent seeds is 15 μm, and the etching depth of the sapphire substrate 6 is 0.1 μm. Is done.

FIG. 3D: Second GaN Layer Growth Step Next, the second GaN layer 6C is formed based on the HVPE apparatus of FIG. The second GaN layer 6C is supplied with GaCl in the same manner as in Example 1 while supplying NH ₃ to the reactor 2 so as to have a thickness of 100 μm on the first GaN layer 6B at a growth temperature of 900 ° C. To grow. The second GaN layer 6C grows based on the lateral growth, thereby forming a recess 6b at a position corresponding to the groove 6a. Further, the portion of the groove 6a where the sapphire is exposed becomes a cavity without growing GaN.

FIG. 3E: Thin Film Growth Process Containing Si Next, a thin film 6D containing Si is provided on the surface of the second GaN layer 6C based on the HVPE apparatus shown in FIG. The Si deposition layer 6D supplies SiH ₄ while supplying NH ₃ to the reactor 2,
It is provided on the surface of the second GaN layer 6C at a growth temperature of 1050 ° C. so as to have a thickness of about one atomic layer to several atomic layers. Propagation of threading dislocations is suppressed by acting as a Si mask having a large number of minute voids penetrating such a thin film containing Si on the uneven surface of the second GaN layer 6C.

FIG. 3F: Third GaN layer growth step Next, a third GaN layer 6E is formed based on the HVPE apparatus of FIG. The third GaN layer 6E is supplied with GaCl in the same manner as the second GaN layer while supplying NH ₃ to the reactor 2, and has a thickness of 300 μm on the thin film 6D containing Si at a growth temperature of 1050 ° C. To grow.

FIG. 3G: GaN layer separation step After the vapor phase growth of GaN by the above-described procedure, the sapphire substrate 6 and the GaN crystal part are separated based on the strain caused by the difference in thermal expansion coefficient between GaN and sapphire when the temperature is lowered. . This separation is realized because the stress is concentrated on other portions due to the presence of the groove 6a. In this way, a group III nitride semiconductor layer made of a low dislocation GaN crystal is formed.

In the group III nitride semiconductor layer of Example 2 described above, the recess 6b is formed on the surface by growing the AlN buffer layer 6A and the first GaN layer 6B on the sapphire substrate 6 and then growing GaN. . Since dislocations are reduced in the recesses 6b, the propagation of threading dislocations can be more effectively suppressed by locally depositing Si in portions other than the recesses 6b. It was confirmed that the dislocation density of the third GaN layer 6E in Example 2 was 1 × 10 ⁶ cm ⁻² , which was equivalent to that in Example 1.

  In Example 2, since the second GaN layer 6C on the groove 6a is formed by lateral growth, the dislocation density decreases. Accordingly, when the thin film 6D containing Si is locally formed in the concave portion 6b, the third GaN layer 6E grows from the other gap portion, and further lateral growth is performed from the vertical growth portion. For this reason, dislocations are concentrated in the recesses 6b due to the lateral growth, and the dislocation density in the lateral growth portion of the third GaN layer 6E is further reduced.

  The present inventor has produced an LED provided with a layer for reducing threading dislocation as described above, and has confirmed that the light output is improved as compared with an LED not provided with a layer for reducing threading dislocation. Moreover, the dislocation density can be further reduced by forming a plurality of Si-containing thin films 6D at intervals of 10 to 100 μm in the middle of the first GaN layer 6B.

  The group III nitride semiconductor layer of the present invention can also be applied to semiconductor light emitting devices such as semiconductor lasers and light emitting diodes, and semiconductor light receiving devices.

It is a schematic block diagram of the HVPE manufacturing apparatus used for manufacture of the group III nitride semiconductor layer which concerns on embodiment of this invention. The manufacturing process of the group III nitride semiconductor layer which concerns on Example 1 is shown, (a) is a figure which shows an AlGaN foundation layer growth process, (b) is a figure which shows a GaN foundation layer growth process, (c) is 1st The figure which shows a GaN layer growth process, (d) is a figure which shows an etching process, (e) is a figure which shows the thin film growth process containing Si, (f) is a figure which shows the 2nd GaN layer growth process, (g) Is another method for forming a thin film growth region containing Si. The manufacturing process of the group III nitride semiconductor layer which concerns on Example 2 is shown, (a) is a figure which shows an AlN buffer layer growth process, (b) is a figure which shows a 1st GaN layer growth process, (c) is a board | substrate. The figure which shows a process process, (d) is a figure which shows the 2nd GaN layer growth process, (e) is a figure which shows the thin film growth process containing Si, (f) is a figure which shows the 3rd GaN layer growth process, (G) is a diagram showing a GaN layer separation step. It is a figure which shows the manufacturing method of the single crystal GaN substrate described in patent document 1. FIG.

Explanation of symbols

1. Semiconductor manufacturing apparatus 2, reactor 3, susceptor 4A, hydrogen supply pipe 4B, nitrogen supply pipe 4C, ammonia supply pipe 4D, silane gas supply pipe 4E, HCl supply part 4F, metal Ga part 5, Si substrate 5A, AlGaN underlayer 5B, a GaN foundation layer 5C, a first GaN layer 5D, a thin film 5E containing Si, a second GaN layer 6, a sapphire substrate 6A, an AlN buffer layer 6B, a first GaN layer 6C, a second GaN layer 6D, Thin film 6E containing Si, third GaN layer 6a, groove 6b, recess 10, substrate 11, mask 11A, window 12, GaN
12A, faceted surface

Claims (12)

A first group III nitride semiconductor layer having a predetermined dislocation density;
A thin film containing Si having a plurality of voids formed on the surface of the first group III nitride semiconductor layer;
A second group III nitride semiconductor layer grown from the first group III nitride semiconductor layer through the plurality of voids of the Si-containing thin film and having a dislocation density lower than the predetermined dislocation density; A group III nitride semiconductor layer characterized by the above.   The group III nitride semiconductor layer according to claim 1, wherein the first group III nitride semiconductor layer has a plurality of recesses on a surface thereof.   The first group III nitride semiconductor layer is a buffer layer or a base layer formed on a substrate, or a group III nitride semiconductor layer formed on the buffer layer or the base layer. The group III nitride semiconductor layer according to claim 1.   2. The group III nitride semiconductor layer according to claim 1, wherein the first group III nitride semiconductor layer is one of GaN, AlGaN, GaInN, or AlGaInN.   2. The group III nitride semiconductor layer according to claim 1, wherein the second group III nitride semiconductor layer is one of GaN, AlGaN, GaInN, or AlGaInN.   2. The group III nitride semiconductor layer according to claim 1, wherein the second group III nitride semiconductor layer is a light emitting element forming semiconductor substrate or a light emitting element semiconductor layer. A first step of forming a first group III nitride semiconductor layer having a predetermined dislocation density;
A second step of forming a thin film containing Si having a plurality of voids on the surface of the first group III nitride semiconductor layer;
A second group III nitride semiconductor layer grown from the first group III nitride semiconductor layer through the plurality of voids on the surface of the Si-containing thin film and having a dislocation density smaller than the predetermined dislocation density And a third step of forming a group III nitride semiconductor layer.   8. The method of forming a group III nitride semiconductor layer according to claim 7, wherein the first and third steps are performed by MOVPE or HVPE.   8. The group III nitride according to claim 7, wherein the first step forms a plurality of recesses on a surface of the first group III nitride semiconductor layer by controlling a growth rate and a growth temperature of the first group III nitride semiconductor layer. A method for forming a semiconductor layer.   8. The method of forming a group III nitride semiconductor layer according to claim 7, wherein in the first step, a plurality of recesses are formed on the surface of the first group III nitride semiconductor layer by etching.   The first step includes forming a buffer layer on the substrate as the first group III nitride semiconductor layer, or forming a group III nitride semiconductor layer on the buffer layer. 8. A method for forming a group III nitride semiconductor layer according to 7. 8. The group III nitride semiconductor according to claim 7, wherein the first and third steps form GaN, AlGaN, GaInN, or AlGaInN as the first and second group III nitride semiconductor layers. Layer formation method.

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