JP2005049402A - Electrooptical device, method for driving electrooptical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide novel driving control of a pixel containing a memory. <P>SOLUTION: The access of the memory 27 is performed through a data line X in a first period being a part of a selection period (1H) when a scanning line Y is selected. Also, different second data is supplied to the data line X in the state of holding the contents of the first data stored in the memory 27 in a second period which is a part of 1H and follows the first period, by which the pixel 2 is driven based on the second data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus, and more particularly to drive control of a pixel with a built-in memory.
[0002]
[Prior art]
In recent years, in order to further reduce the power consumption of portable electronic devices, a device in which a memory is built in each pixel constituting a display unit has been put into practical use. By holding the display data in the memory in the pixel, it is possible to drive the liquid crystal with AC without rewriting (scanning) the data via the data line, so that low power consumption can be realized. For example, Patent Document 1 discloses a configuration of such a pixel circuit with a built-in memory.
[0003]
Further, Patent Document 2 discloses a display panel driving method capable of setting a memory state for displaying a still image while performing subfield driving which is a kind of time-axis modulation method. In this driving method, when switching between the gradation display mode and the binary display mode, the most significant bit data is written last so that the image displayed in the gradation display mode remains even in the binary display mode. Has been devised.
[0004]
[Patent Document 1]
JP 2001-264814 A
[Patent Document 2]
Japanese Patent No. 3316297.
[0005]
[Problems to be solved by the invention]
An object of the present invention is to provide a novel drive control of a pixel having a built-in memory.
[0006]
Another object of the present invention is to reduce the number of scans of data writing to such pixels and to reduce power consumption.
[0007]
Furthermore, another object of the present invention is to reduce the memory of an electronic device by using a memory in a pixel as a working memory such as a CPU.
[0008]
[Means for Solving the Problems]
In order to solve such a problem, the first invention is provided corresponding to the intersection of a plurality of scanning lines, a plurality of data lines, a scanning line, and a data line, and the first data An electro-optical device is provided that includes a plurality of pixels including a memory to store, a scanning line driving circuit that sequentially selects a plurality of scanning lines, and a driving unit that cooperates with the scanning line driving circuit. The drive unit accesses the memory incorporated in the pixel corresponding to the scan line via the data line in the first period which is a part of the selection period in which the scan line is selected. In addition, the drive unit is a part of the selection period, and in a second period different from the first period, the first data stored in the memory is held in the second period. By supplying different second data to the data line, the pixel corresponding to the scanning line is driven based on the second data.
[0009]
Here, in the first invention, the first data and the second data may be display data defining the luminance of the pixel. In this case, the drive unit writes the first data, which is display data in the next cycle, to the memory in the first period, and based on the second data, which is display data in the current cycle, in the second period. Then, the pixel is driven. In addition, the driving unit reads out the first data stored in the memory in the previous cycle in the third period that is at least a part of the selection period in which the scanning line is selected next, and uses the first data as the first data. Based on this, it is preferable to drive the pixels.
[0010]
In the first invention, a predetermined period is divided into a first sub-period and a second sub-period, and the first scanning line group is selected in the first sub-period, and the second sub-period is selected. The present invention can also be applied to interlaced driving in which a second scanning line group different from the first scanning line group is selected in the period. In this case, in the first sub period, the driving unit sets the first period and the second period within each selection period of the first scanning line group, and each of the second scanning line groups. It is preferable to set the third period within the selection period. At the same time, in the second sub-period, the driving unit sets the third period within each selection period of the first scanning line group, and within each selection period of the second scanning line group. It is preferable to set the first period and the second period.
[0011]
The first invention is applicable to sub-field driving in which gradation display of pixels is performed using a plurality of sub-periods defined by dividing a predetermined period and having different weights. In this case, it is preferable that the driving unit sets the third period within each selection period of the plurality of scanning lines in the minimum sub period having the smallest weight among the plurality of sub periods.
[0012]
In the first invention, the first data may be non-display data that does not define the luminance of the pixel, and the second data may be display data that defines the luminance of the pixel. In this case, in the first period, the driving unit reads either the first data that is non-display data stored in the memory or the first data that is non-display data to be stored in the memory. It is preferable to perform one of these via a data line and drive the pixel based on the second data which is display data in the second period.
[0013]
According to a second aspect of the present invention, there is provided an electronic apparatus in which the electro-optical device according to the first aspect described above is mounted.
[0014]
According to a third aspect of the present invention, a plurality of pixels are provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and each of the pixels has a built-in memory for storing the first data. Provided is a method for driving an optical device. In this electro-optical device driving method, in a first period which is a part of a selection period in which a scanning line is selected, a memory incorporated in a pixel corresponding to the scanning line is accessed via the data line. The first data is different from the first data in a state in which the contents of the first data stored in the memory are held in a second period that is a part of the selection period and is different from the first period. A second step of driving the pixels corresponding to the scanning lines based on the second data by supplying the second data to the data lines.
[0015]
Here, in the third invention, the first data and the second data may be display data defining the luminance of the pixel. In this case, the first step is a step of writing the first data, which is display data in the next cycle, to the memory in the first period. The second step is a step of driving the pixel based on the second data that is display data in the current cycle in the second period. Further, in the third period which is at least a part of the selection period in which the scanning line is selected next, the first data stored in the memory in the previous cycle is read, and the pixel is based on the first data. It is preferable that the method further includes a third step of driving.
[0016]
In the third invention, the predetermined period is divided into a first sub-period and a second sub-period, and the first scanning line group is selected in the first sub-period, and the second sub-period is selected. The present invention can also be applied to interlaced driving in which a second scanning line group different from the first scanning line group is selected in the period. In this case, in the first sub-period, the first period and the second period are set within each selection period of the first scanning line group, and within the respective selection period of the second scanning line group. In the second sub-period, the third period is set within each selection period of the first scanning line group, and each of the second scanning line group is set in the second sub-period. It is preferable to further include a step of setting the first period and the second period within the selection period.
[0017]
The third invention is also applicable to sub-field driving in which gradation display of pixels is performed using a plurality of sub-periods defined by dividing a predetermined period and having different weights. In this case, it is preferable to further include a step of setting a third period within each selection period of the plurality of scanning lines in the minimum sub period having the minimum weight among the plurality of sub periods.
[0018]
Further, in the third invention, the first data may be non-display data that does not define the luminance of the pixel, and the second data may be display data that defines the luminance of the pixel. In this case, in the first step, the first data that is non-display data stored in the memory or the first data that is non-display data to be stored in the memory is written in the first period. This is a step of performing either one of them through a data line. The second step is a step of driving the pixel based on the second data that is display data in the second period.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a block diagram of the electro-optical device according to the present embodiment. The display unit 1 is an active matrix display panel in which a liquid crystal element is driven by a switching element such as a TFT (thin film transistor). In the display unit 1, pixels 2 for m dots × n lines are arranged in a matrix (in a two-dimensional plane). The display unit 1 also includes n scanning lines Y1 to Yn each extending in the row direction (X direction) and m pieces of data each extending in the column direction (Y direction). Lines X1 to Xm are provided, and the pixels 2 are arranged corresponding to these intersections. Although not shown in FIG. 1, the display unit 1 is provided with two types of signal lines ya1 to yan and yb1 to ybn in units of scanning lines, which extend in parallel with the scanning lines Y1 to Yn. Exist.
[0020]
FIG. 2 is an equivalent circuit diagram of the pixel 2 using liquid crystal. One pixel 2 includes four transistors 21 to 24 functioning as switching elements, a liquid crystal capacitor 25, a storage capacitor 26, and a pair of inverters 27a and 27b. In this embodiment, the transistors 21 to 23 are n-channel type and the transistor 24 is p-channel type, but the channel type is not limited to this. However, since the transistors 22 and 23 are in an exclusive conductive relationship, when they are controlled by the same control signal, they must be set to different channel types.
[0021]
The source of the first transistor 21 is connected to one data line X, and the gate thereof is connected to one scanning line Y. Regarding the pixels 2 arranged in the same column, the sources of the respective transistors 21 are connected to the same data line X. For the pixels 2 arranged in the same row, the gates of the respective transistors 21 are connected to the same scanning line Y. The drain of the first transistor 21 is commonly connected to a liquid crystal capacitor 25 and a storage capacitor 26 provided in parallel. The liquid crystal capacitor 25 includes a pixel electrode 25a, a counter electrode 25b to which a potential Vlcom is applied, and a liquid crystal (liquid crystal layer) sandwiched between the electrodes 25a and 25b. The storage capacitor 26 is formed between the pixel electrode 25a and a common capacitor electrode (not shown), and is applied with the potential Vcs. The storage capacitor 26 suppresses the leakage of charges accumulated in the liquid crystal. A potential corresponding to data is applied to the pixel electrode 25 a side through the first transistor 21. When data is supplied from the data line X to the pixel 2 in the data writing period, the liquid crystal capacitor 25 and the storage capacitor 26 are charged and discharged. Thereby, the transmittance of the liquid crystal layer is set according to the potential difference between the pixel electrode 25a and the counter electrode 25b, and the gradation of the pixel 2 is set.
[0022]
The pixel 2 has a built-in memory 27 including a pair of inverters 27a and 27b. Specifically, the output terminal of one inverter 27a is connected to the input terminal of the other inverter 27b, and the output terminal of the other inverter 27b is connected to one inverter 27a via the fourth transistor 24. Is connected to the input terminal. The conduction of the fourth transistor 24 is controlled by a control signal supplied via the first signal line ya. The input terminal of one inverter 27 a is connected to the drain of the first transistor 21 through the second transistor 22. The conduction of the second transistor 22 is controlled by a control signal supplied via the first signal line ya. The second transistor 22 is turned on when the fourth transistor 24 is turned off, and turned off when the fourth transistor 24 is turned on. The input terminal of the other inverter 27 b is connected to the drain of the first transistor 21 via the third transistor 23. The conduction of the third transistor 23 is controlled by a control signal supplied via the second signal line yb. With such a flip-flop configuration, the pair of inverters 27a and 27b functions as a memory 27 that stores 1-bit data.
[0023]
The control circuit 5 synchronously controls the scanning line driving circuit 3 and the data line driving circuit 4 based on external signals such as a vertical synchronizing signal Vs, a horizontal synchronizing signal Hs, and a dot clock signal DCLK input from a host device (not shown). . Under this synchronization control, the scanning line driving circuit 3 and the data line driving circuit 4 perform display control of the display unit 1 in cooperation with each other. The control circuit 5 performs write control for writing image data input from a host device (not shown) to the frame memory 6 and read control for reading data stored in the frame memory 6.
[0024]
The scanning line driving circuit 3 is mainly configured by a shift register, an output circuit, and the like, and performs line sequential scanning of the scanning lines Y1 to Yn by outputting scanning signals to the scanning lines Y1 to Yn. The scanning signal takes a binary signal level of a high potential level (hereinafter referred to as “H level”) or a low potential level (hereinafter referred to as “L level”), and scan corresponding to a pixel row to which data is to be written. The line Y is set to the H level, and all other scanning lines Y are set to the L level. Thereby, in a predetermined period (one vertical scanning period), line sequential scanning is performed in which pixel rows to which data is to be written are sequentially selected in a predetermined scanning direction (generally from the top to the bottom). Done.
[0025]
On the other hand, the data line driving circuit 4 is mainly composed of a shift register, a line latch circuit, an output circuit, and the like, and functions as a driving unit that cooperates with the scanning line driving circuit 3. The data line driving circuit 4 outputs the data for the pixel row to which the current data is written and the data for the pixel row to be written in the next 1H in one selection period (1H) in which one scanning line Y is selected. The dot sequential latching is performed simultaneously. In a certain 1H, m pieces of data corresponding to the number of data lines X serially supplied from the frame memory 6 are sequentially latched. In the next 1H, the latched m pieces of data are output in parallel and supplied to the data lines X1 to Xm all at once. Note that the present invention can also be applied to a configuration in which data is sequentially input from the frame memory 6 to the data line driving circuit 4, but in this case, the operation of the main portion of the present invention is the same. In such a configuration, it is not necessary to provide the data line driving circuit 4 shift register.
[0026]
FIG. 3 is a timing chart of interlaced driving according to the present embodiment. Here, “Write” shown in the figure means a period during which data is written, and “Read” means a period during which data is read. “Mi” (i = 1 to n), which is the first half period of “Write”, means a period for writing data to each memory 27 in the i-th pixel row (memory writing period), and the entire period of “Read” The “Mi” corresponding to means a period for reading data from each memory 27 in the i-th pixel row (memory reading period). Furthermore, “Pi”, which is the latter half period of “Write”, means a period for writing data to each pixel 2 in the i-th pixel row (pixel writing period). In a broad sense, not only data writing to the liquid crystal capacitor 25 or the like but also data writing in the memory 27 can be regarded as data writing in the pixel 2. In this specification, in order to distinguish between the two, "Refers only to the former writing.
[0027]
One frame (1F) is divided into an odd field FLD1 and an even field FLD2 corresponding to a sub-period. In relation to the gradation to be displayed, these fields FLD1 and FLD2 are set to a length that gives a weight of 1: 1, that is, at equal intervals. When a liquid crystal element (the liquid crystal capacitor 25 shown in FIG. 2) is used as the electro-optic element, data is supplied to the pixel 2 at a voltage level. In order to improve the life of the liquid crystal, AC driving is performed to reverse the voltage polarity every predetermined period (for example, one field).
[0028]
First, the data writing process will be described. In the odd field FLD1, the odd-numbered scanning lines Y1, Y3,..., Yn-1 are selected in order. In the first selection period (1H), the scanning line driving circuit 3 sets the scanning signal of the uppermost scanning line Y1 to the H level, and selects the pixel row corresponding to the scanning line Y1. As a result, the first transistor 21 (see FIG. 2) in the uppermost pixel row is turned on. In addition, two periods M1 and P1 are set in 1H. In the memory writing period M1, the control signal of the first signal line ya1 corresponding to the scanning line Y1 becomes H level, and in the pixel writing period P1, this control signal becomes L level.
[0029]
FIG. 4 is an explanatory diagram of a data path in the memory writing period M1. In the memory writing period M1, the second transistor 22 in the uppermost pixel row is turned on and the fourth transistor 24 is turned off. In this period M1, since the control signal of the second signal line yb1 is at the L level, the third transistor 23 is turned off. In this state, the data line driving circuit 4 outputs data Dmem to be supplied to the selected pixel 2 to the data line X. This data Dmem is data to be written to the pixel 2 in the next cycle (ie, FLD2), not the current cycle (ie, FLD1), in other words, display data that defines the luminance of the pixel 2 in the next cycle. The data Dmem supplied to the data line X is supplied to the input terminal of the inverter 27a via the first transistor 21 and the second transistor 22, and is written in the memory 27 as data to be stored.
[0030]
FIG. 5 is an explanatory diagram of a data path in the pixel writing period P1. In the pixel writing period P1 following the memory writing period M1, the second transistor 22 in the uppermost pixel row is turned off and the fourth transistor 24 is turned on. Similarly to the previous period M1, the third transistor 23 remains off because the control signal of the second signal line yb1 is at the L level also in this period P1. Therefore, the memory 27 constituted by the pair of inverters 27a and 27b continues to store the data Dmem supplied in the previous period M1, and is electrically separated from the liquid crystal capacitor 25 and the like in the previous stage. In this state, the data line driving circuit 4 outputs data Dpix to be supplied to the selected pixel 2 to the data line X. This data Dpix is data to be written to the pixel 2 in the current cycle (that is, FLD1). Data Dpix supplied to the data line X is supplied to the pixel electrode 25 a of the liquid crystal capacitor 25 and one electrode of the storage capacitor 26 via the first transistor 21. Thereby, charging / discharging (data writing of the pixel 2) of the liquid crystal capacitor 25 and the like is performed, and the gradation of the pixel 2 in the odd field FLD1 is set. The supply of the data Dmem in the previous period P1 also causes charging / discharging of the liquid crystal capacitor 25 and the like, but immediately after that, charging / discharging by the data Dpix is performed again, so that the influence of the data Dmem on the display gradation is not so much. Absent.
[0031]
Following the selection of the uppermost pixel row, the scanning signal of the third scanning line Y3 is set to the H level, and the third pixel row from the top corresponding to this is selected. The writing process of this pixel row is the same as that of the uppermost pixel row. Data Dmem is written to the memory 27 in the memory writing period M3, and data Dpix is written to the pixel 2 in the subsequent pixel writing period P3. Hereinafter, until the selection of the last scanning line Yn−1 in the odd field FLD1 is completed, the memory writing and the pixel writing are sequentially performed on the pixel rows corresponding to the odd scanning lines Y.
[0032]
In the subsequent even field FLD2, the same writing process as that in the odd field FLD1 is basically performed except that the selection target is replaced by the even-numbered scanning lines Y2, Y4,. The second pixel row corresponding to the scanning line Y2 will be described as an example. In the memory writing period M2, data to be written to the pixel 2 in the next cycle (FLD1 of the next frame) is not the current cycle (FLD2). , Data Dmem is written in the memory 27. In the subsequent pixel writing period P2, data Dpix to be written to the pixel 2 in the current cycle (FLD2) is written to the pixel 2. In the even field FLD2, since the polarity of the potential Vlcom applied to the counter electrode 25b is inverted, the polarity of the data Dpix supplied to the pixel 2 is also inverted accordingly. The voltage polarity is defined based on the direction of the electric field acting on the liquid crystal layer, in other words, based on the forward and reverse of the applied voltage.
[0033]
Next, a process for reading data Dmem stored in the memory 27 will be described. In the odd field FLD1, the data Dmem stored in the memory 27 is read for the even-numbered scanning lines Y2, Y4,. This data Dmem is data stored in the memory 27 in the previous cycle (FLD2 of the previous frame), and is data to be written in the pixel 2 in the current cycle. For even-numbered pixel rows i, the entire 1H is set to the memory read period Mi, and the control signal for the second signal line ybi is set to the H level during this period Mi. Note that the memory reading period Mi may be set for the entire 1H, but may be set for the memory writing period Mi or for the pixel writing period Pi.
[0034]
FIG. 6 is an explanatory diagram of a data path in the memory read period Mi. The second pixel row in the odd field FLD1 will be described as an example. In this memory read period M2, the control signal of the second signal line yb2 is set to the H level. Therefore, in this period M2, the third transistor 23 is turned on for the second pixel row. In this period M2, since the scanning signal of the scanning line Y2 and the control signal of the first signal line ya2 are both at the L level, the first and second transistors 21 and 22 are both off, Transistor 24 is on. Therefore, the data Dmem stored in the memory 27 is supplied to the pixel electrode 25 a of the liquid crystal capacitor 25 and one electrode of the storage capacitor 26 via the third transistor 23. Thereby, charge / discharge of the liquid crystal capacitor 25 and the like (in other words, writing of the pixel 2) is performed, and the gradation of the pixel 2 in the odd field FLD1 is set. This reading process is the same for even-numbered pixel rows. That is, the writing of the even-numbered pixel rows is performed by the data Dmem read from the memory 27, not the data supply from the data line X. The reason why reading from the memory 27 is performed through the third transistor 23 is that the stored contents of the memory 27 are inverted and output so as to correspond to the polarity inversion of the potential Vlcom for each field.
[0035]
In the even-numbered field FLD2, the odd-numbered scanning lines Y1, Y3,..., Yn−1 that are not subject to line-sequential scanning are subjected to the reading process similar to that in the odd-numbered field FLD1, and the data Dmem stored in the memory 27 is stored. Reading is performed. The data Dmem read out here is data stored in the memory 27 in the previous cycle (FLD1 of the same frame) and should be written to the pixel 2 in the current cycle (FLD2).
[0036]
As described above, in this embodiment, in the memory writing period which is a part of one selection period (1H), data writing to the memory 27 built in the pixel 2 corresponding to the selected scanning line Y is performed on the data line. Via X. The data written in the memory 27 is display data in the next cycle. In the next cycle, the data stored in the memory 27 is read and the pixels 2 are driven. In the pixel writing period subsequent to the memory writing period, the display data in the current cycle is supplied to the data line X while the contents of the data stored in the memory 27 are held, and the pixel 2 is driven. In this way, by supplying data for a plurality of consecutive cycles to the pixel 2 in a certain cycle, it is possible to reduce the number of scans for writing (the number of times of line sequential scanning) and to reduce power consumption. Become.
[0037]
Further, according to the present embodiment, it is possible to reduce the cost and improve the display quality in interlace driving. In general, in interlaced driving, it is necessary to convert an interlaced signal into a progressive signal, so that a memory and a controller for that purpose are required. On the other hand, in the drive control according to the present embodiment, interlaced driving can be realized without providing such a memory. In addition, since the refresh cycle of each pixel row can be made constant, flicker or the like hardly occurs.
[0038]
In the present embodiment, a 1-bit memory is used as the memory 27. Therefore, in the field where data is read from the memory 27, only black and white binary display can be performed. Therefore, the field is more suitable for character display than for moving picture display on a television or the like. However, if a memory capable of storing intermediate gradation data is used as the memory 27, multi-gradation display such as moving image display is possible.
[0039]
(Second Embodiment)
The present embodiment relates to an application example to subfield driving. Sub-field driving is a type of time-axis modulation method, and can display multiple gradations even if the memory 27 is a 1-bit memory. FIG. 7 is a timing chart of subfield driving according to the present embodiment.
[0040]
As an example, the data defining the gradation of the pixel 2 is 16 gradation data composed of 4 bits. One frame, which is the minimum display unit of an image, is divided into four subfields SF1 to SF4. In relation to the gradation to be displayed, the subfields SF1 to SF4 corresponding to the sub-periods are set to a length that gives a weight of 1: 2: 4: 8. The display gradation of the pixel 2 is determined according to the combination of the subfields SF that sets the pixel 2 to the ON state, and this combination is uniquely specified by the gradation value of the data. Hereinafter, the subfield SF that supplies the on-voltage Von for driving the pixel 2 when performing a certain gradation display is referred to as “on-subfield SFon”. A subfield SF that supplies an off voltage Voff different from the on voltage Von is referred to as an “off subfield SFoff”. For example, when the gradation value is 9, the on subfield SFon is SF1 with weight 1 and SF4 with weight 8, and the off subfield SFoff is SF2 with weight 2 and SF3 with weight 4. In this case, the total weighting of the two subfields SF1 and SF4 is 9, and gradation display corresponding to this weighting is performed. The effective voltage acting on the pixel 2 depends on the length of the on-subfield SFon occupying one frame, and the longer this is, the higher the effective voltage is. As a result, for example, in the case of a liquid crystal operating in a normally black mode, the luminance becomes higher (white display) as the on-subfield SFon becomes longer. The data line driving circuit 4 determines either the on voltage Von or the off voltage Voff in each of the subfields SF1 to SF4 according to the gradation to be displayed, and the data line X as binary digital data. Output to.
[0041]
Since the first subfield SF1 is in the “Read” period, the writing scan by the line sequential scanning is not performed, and instead, the data stored in the memory 27 in the pixel 2 is read. Then, the pixel 2 is driven based on the read data. The data held in the memory 27 is data written in the previous cycle (SF4 of the previous frame). Since the second subfield SF2 is a “Write” period, a write scan by line sequential scanning is performed. In the memory write period Mi that is a part of 1H, data in the next cycle (SF3) is written in the memory 27, and in the subsequent pixel write period Pi, data in the current cycle (SF2) is written in the pixel 2. . Since the third subfield SF3 is in the “Read” period, the data stored in the memory 27 in the pixel 2 is read, and the pixel 2 is driven based on the read data. The data held in the memory 27 is data written in the previous cycle (SF2 of the previous frame). Since the last subfield SF4 is a “Write” period, a write scan by line sequential scanning is performed. In the memory writing period Mi, which is a part of 1H, data in the next cycle (SF1 of the next frame) is written to the memory 27, and in the subsequent pixel writing period Pi, data in the current cycle (SF4) is written to the pixel 2 Is written to.
[0042]
According to the present embodiment, by supplying data for a plurality of consecutive cycles at a time in a certain cycle to the pixel 2, the number of scans for writing can be reduced and the power consumption can be reduced, as in the first embodiment. It becomes possible to plan.
[0043]
In the present embodiment, in the subfield SF1 having the minimum weight, the pixel 2 is driven based on the data read from the memory 27 without performing the write scan. Therefore, with respect to the minimum subfield SF1, the scan time restriction is eliminated. As a result, it is possible to easily cope with multi-gradation by setting the period of the minimum subfield SF1 short, improvement in reliability by securing a margin for data writing time, or high definition.
[0044]
(Third embodiment)
FIG. 8 is a block diagram of the electro-optical device according to the present embodiment. In the present embodiment, the memory 27 built in the pixel 2 is used as a working memory such as a CPU. For example, in the case of a color panel having a resolution of the display unit 1 of QVGA, a memory space of 230,400 bits (= 320 × 240) can be secured. In this case, unlike the first or second embodiment, the data stored in the memory 27 is non-display data (work data) that does not define the luminance of the pixel 2. The difference from the configuration shown in FIG. 1 is that a column decoder 7 that functions as a drive unit is added together with the data line drive circuit 4, and the rest is basically the same as the configuration shown in FIG. is there. The column decoder 7 cooperates with the scanning line driving circuit 3 that also functions as a row decoder to access the memory space of the display unit 1 and perform bidirectional data transfer with the upper CPU 8.
[0045]
FIG. 9 is a timing chart in the write mode in which work data is written to the memory 27. In the figure, regarding the waveform of the data line X, the H level indicates a state where work data is supplied, and the L level indicates a state where display data is supplied. In one selection period (1H) in which one scanning line Y is selected, two periods MW and PW are set. In the first half of the memory write period MW, the control signal of the first signal line yai corresponding to the scanning line Yi becomes H level. In this period MW, the column decoder 7 outputs the work data supplied from the CPU 8 to the data line X (the display data is not output from the data line driving circuit 4). The work data output to the data line X is written into the memory 27 of the pixel row to be written through the data path shown in FIG. In the subsequent pixel writing period PW, the control signal of the first signal line ya1 corresponding to the scanning line Yi becomes L level. In this period PW, the data line driving circuit 4 outputs the display data to be written to the pixels 2 in the current cycle to the data line X (work data is not output from the column decoder 7). The display data output to the data line X is written into the liquid crystal capacitors 25 of the pixel row to be written through the data path shown in FIG.
[0046]
FIG. 10 is a timing chart in the read mode for reading work data from the memory 27. Two periods MR and PW are set for 1H. In the first half memory read period MR, the control signal of the first signal line yai corresponding to the scanning line Yi becomes H level. During this period MR, the work data stored in the memory 27 is read and this data is output to the data line X. At this time, the data line X is not driven, and the input signal becomes high impedance (high resistance). The work data output to the data line X is transferred to the CPU 8 by the column decoder 7. In the subsequent pixel writing period PW, display data is written to the liquid crystal capacitors 25 and the like of the pixel row to be written, as in the write mode.
[0047]
Thus, in the present embodiment, the memory 27 is accessed via the data line X in the memory write period MW / memory read period MR, which is a part of 1H. In the subsequent pixel writing period PW, the display data in the current cycle is supplied to the data line X while the contents of the work data stored in the memory 27 are held, and the pixels 2 are driven. As a result, the memory 27 built in the pixel 2 can be used as a working memory such as a CPU, and the memory of the electronic device can be saved.
[0048]
In each of the above-described embodiments, the case where a liquid crystal element is used has been described as an example. However, the present invention is not limited to this, and an organic EL element, a digital micromirror device (DMD), an FED (Field Emission) is used. It can also be applied to a display, a surface-conduction electron-emitter display (SED) and the like.
[0049]
In addition, the electro-optical device according to each of the embodiments described above can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.
[0050]
【The invention's effect】
According to the present invention, the number of scans for data writing can be reduced and the power consumption can be reduced by a novel drive control of a pixel having a built-in memory. In addition, the memory in the pixel can be used as a working memory for a CPU or the like, and the memory of the electronic device can be saved.
[Brief description of the drawings]
FIG. 1 is a block configuration diagram of an electro-optical device according to a first embodiment.
FIG. 2 is an equivalent circuit diagram of a pixel.
FIG. 3 is a timing chart of interlaced driving according to the first embodiment.
FIG. 4 is an explanatory diagram of a data path in a memory writing period.
FIG. 5 is an explanatory diagram of a data path in a pixel writing period.
FIG. 6 is an explanatory diagram of a data path in a memory read period.
FIG. 7 is a timing chart of subfield driving according to the second embodiment.
FIG. 8 is a block diagram of an electro-optical device according to a third embodiment.
FIG. 9 is a timing chart of a write mode.
FIG. 10 is a timing chart in a read mode.
[Explanation of symbols]
1 Display section
2 pixels
3 Scanning line drive circuit
4 Data line drive circuit
5 Control circuit
6 frame memory
7 column decoder
8 CPU
21 First transistor
22 Second transistor
23 Third transistor
24 Fourth transistor
25 LCD capacity
25a Pixel electrode
25b Counter electrode
26 storage capacity
27 memory
27a, 27b inverter

Claims (13)

In an electro-optical device,
A plurality of scan lines;
Multiple data lines,
A plurality of pixels provided corresponding to the intersections of the scanning lines and the data lines and having a memory for storing first data;
A scanning line driving circuit for sequentially selecting the plurality of scanning lines;
A driving unit that cooperates with the scanning line driving circuit;
The drive unit is
In the first period which is a part of the selection period in which the scanning line is selected, the memory incorporated in the pixel corresponding to the scanning line is accessed through the data line,
In the second period that is a part of the selection period and different from the first period, the first data is stored in the state where the contents of the first data stored in the memory are retained. An electro-optical device that drives the pixels corresponding to the scanning lines based on the second data by supplying different second data to the data lines. The first data and the second data are display data that defines the luminance of the pixel,
The drive unit is
In the first period, the first data which is the display data in the next cycle is written to the memory,
2. The electro-optical device according to claim 1, wherein in the second period, the pixel is driven based on the second data that is the display data in the current cycle. The driving unit reads the first data stored in the memory in the previous cycle in a third period that is at least a part of a selection period in which the scanning line is next selected, The electro-optical device according to claim 2, wherein the pixel is driven based on data. The predetermined period is divided into a first sub period and a second sub period. In the first sub period, a first scanning line group is selected, and in the second sub period, the first sub period is selected. In interlaced driving in which a second scanning line group different from one scanning line group is selected,
The drive unit is
In the first sub-period, the first period and the second period are set within the selection period of each of the first scanning line groups, and each of the second scanning line groups is set. Setting the third period within the selection period;
In the second sub-period, the third period is set within the selection period of each of the first scanning line groups, and the third scanning period is set within the selection period of the second scanning line group. The electro-optical device according to claim 3, wherein a first period and the second period are set. In sub-field driving that performs gradation display of pixels using a plurality of sub-periods that are defined by dividing a predetermined period and have different weights,
The drive unit is
The third period is set in the selection period of each of the plurality of scanning lines in a minimum sub period having a minimum weight among the plurality of sub periods. Electro-optical device. The first data is non-display data that does not define the luminance of the pixel, and the second data is display data that defines the luminance of the pixel,
The drive unit is
In the first period, either reading of the first data which is the non-display data stored in the memory or writing of the first data which is the non-display data to be stored in the memory Either through the data line,
2. The electro-optical device according to claim 1, wherein the pixel is driven based on the second data which is the display data in the second period. An electronic apparatus comprising the electro-optical device according to claim 1 mounted thereon. A driving method of an electro-optical device in which a plurality of pixels are provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and each of the pixels includes a memory for storing first data In
A first step of accessing the memory incorporated in the pixel corresponding to the scanning line via the data line in a first period that is a part of a selection period in which the scanning line is selected;
In the second period that is a part of the selection period and different from the first period, the first data is stored in the state where the contents of the first data stored in the memory are retained. And a second step of driving the pixel corresponding to the scanning line based on the second data by supplying different second data to the data line. Driving method. The first data and the second data are display data that defines the luminance of the pixel,
The first step is a step of writing the first data, which is the display data in the next cycle, in the memory in the first period,
The second step is a step of driving the pixel based on the second data which is the display data in the current cycle in the second period. Driving method for the electro-optical device. In a third period that is at least a part of a selection period in which the scanning line is selected next, the first data stored in the memory in the previous cycle is read, and based on the first data, The method for driving the electro-optical device according to claim 9, further comprising a third step of driving the pixels. The predetermined period is divided into a first sub period and a second sub period. In the first sub period, a first scanning line group is selected, and in the second sub period, the first sub period is selected. In interlaced driving in which a second scanning line group different from one scanning line group is selected,
In the first sub-period, the first period and the second period are set within the selection period of each of the first scanning line groups, and each of the second scanning line groups is set. Setting the third period within the selection period;
In the second sub-period, the third period is set within the selection period of each of the first scanning line groups, and the third scanning period is set within the selection period of the second scanning line group. The method of driving an electro-optical device according to claim 10, further comprising a step of setting a first period and the second period. In sub-field driving that performs gradation display of pixels using a plurality of sub-periods that are defined by dividing a predetermined period and have different weights,
The method further comprises the step of setting the third period within the selection period of each of the plurality of scanning lines in a minimum sub period having a minimum weight among the plurality of sub periods. 10. The driving method of the electro-optical device according to 10. The first data is non-display data that does not define the luminance of the pixel, and the second data is display data that defines the luminance of the pixel,
In the first period, in the first period, the first data that is the non-display data stored in the memory is read, or the non-display data that is to be stored in the memory. Performing any one of the data writing of 1 through the data line,
9. The electro-optic according to claim 8, wherein the second step is a step of driving the pixel based on the second data which is the display data in the second period. Device driving method.

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