JP2004319725A - Magnetic random access memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the deterioration of a magneto-resistance effect property by reducing process damages to a magneto-resistive memory element in a magnetic random access memory device. <P>SOLUTION: The random access memory device has, on a semiconductor substrate, magneto-resistive memory elements 5, each of which is located in an intersection area of first word lines 4 and bit lines 3 which are located in directions crossing each other, and has such a structure that a first magnetic material layer 6 with a variable magnetization direction and a second magnetic material layer 8 with a fixed magnetization direction are stacked via a non-magnetic intermediate layer 7; and an access transistor 1 which uses a second word line 2 located in a direction which crosses the bit lines 3, as the gate. For an insulator for surrounding sides of the magneto-resistive memory elements 5, anti-water penetration film 10 which has an anti-water penetration performance superior to that of SiO<SB>2</SB>is used. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a magnetic random access memory device, and more particularly to a magnetic random access memory device (MRAM: magnetic random access memory) having a write word line, which is characterized by a structure of an interlayer insulating film for preventing characteristic deterioration. And a magnetic random access memory device having the same.
[0002]
[Prior art]
An MRAM is a memory device that utilizes the fact that a current flows through a magnetic structure and a resistance value changes according to the direction of electron spin in a magnetic material. A magnetic structure constituting a memory cell is a GMR (Giant Magneto resistive) element Alternatively, a TMR (Tunneling Magneto Resistive) element has been studied (for example, see Patent Document 1 or Patent Document 2).
[0003]
Since a large resistance change is required for such an MRAM, a TMR element structure is mainly used for research and development. Here, an example of a conventional MRAM will be described with reference to FIG.
FIG. 8 is a schematic cross-sectional view of a principal part of a conventional MRAM. First, a p-type well region 12 is formed in a predetermined region of an n-type silicon substrate 11, and the n-type silicon substrate 11 is selectively oxidized. After the element isolation oxide film 13 is formed, a gate electrode 15 made of WSi serving as a read word line is formed in the element formation region via the gate insulating film 14, and ions such as As are implanted using the gate electrode 15 as a mask. By doing so, an n ^- type LDD (Lightly Doped Drain) region 16 is formed.
[0004]
Next, a SiO ₂ film or the like is deposited on the entire surface, and a sidewall 17 is formed by performing anisotropic etching. Then, ion implantation of As or the like is performed again to thereby form the n ⁺ -type drain region 18 and the n ⁺ -type source region. After forming a first interlayer insulating film 20 made of a thick SiO ₂ film or the like such as a TEOS (Tetra-Ethyl-Ortho-Silicate) -NSG film, an n ⁺ -type drain region 18 and an n ⁺ -type A contact hole reaching the source region 19 is formed, and the contact hole is filled with W to form W plugs 21 and 22.
[0005]
Next, by depositing Ti / TiN / Al / Ti / TiN over the entire surface and then patterning, a connection conductor 23 and a source wiring layer 24 are formed, and then a thick SiO ₂ film such as a TEOS-NSG film is again formed. Then, a contact hole reaching the connection conductor 23 is formed, and the contact hole is filled with W to form a W plug 26.
Normally, the source wiring layer 24 is connected to the GND line.
[0006]
Next, a connection conductor 27 and a write word line 28 are formed by depositing Ti / TiN / Al / Ti / TiN on the entire surface again and then patterning. Then, a thin SiO ₂ film such as a TEOS-NSG film is formed again. A third interlayer insulating film 29 made of a film or the like is formed, a contact hole reaching the connection conductor 27 is formed, and the contact hole is filled with W via Ti / TiN to form a W plug 30.
[0007]
Next, a lower electrode 31 is formed by depositing Al on the entire surface again and then patterning, and then a fourth interlayer insulating film 32 made of a thin SiO ₂ film such as a TEOS-NSG film is deposited again. Next, the lower electrode 31 is planarized by CMP (chemical mechanical polishing) until the lower electrode 31 is exposed.
[0008]
Next, a Ta base layer 33, a NiFe free layer 34, a tunnel insulating layer 35 made of Al ₂ O ₃ , a CoFe pinned layer 36, an IrMn pin layer 37, and a Ta cap layer 51 are sequentially deposited on the entire surface, and then ion milling is performed. Thereby, for example, the TMR element 52 having a size of 0.15 μm × 0.1 μm is formed.
In this case, since the TMR element 52 has a rectangular shape long in the bit line direction, it is easy for the spin direction of the NiFe free layer 34 to be oriented in the direction in which the bit line 54 extends.
[0009]
Then, again, after depositing a fifth interlayer insulating film 53 made of another TEOS-NSG film thin SiO ₂ film or the like having such, Ta capping layer 51 is planarized by CMP (chemical mechanical polishing) to expose.
[0010]
Next, after depositing a multilayer conductive layer having a Ti / TiN / Al / Ti / TiN structure on the entire surface, patterning is performed so as to extend in a direction orthogonal to the write word line 28 to form the bit line 54. Thereby, the basic structure of the MRAM is completed.
[0011]
In this case, writing to the TMR element 52 is performed by applying a current to the bit line 54 and the writing word line 28, and the generated magnetic field determines the spin direction of the NiFe free layer 34. "1" or "0" data is written in the same direction or in the opposite direction.
[0012]
On the other hand, when reading from the TMR element 52, a voltage is applied between the NiFe free layer 34 and the CoFe pinned layer 36, and a voltage is applied to the gate electrode 15, which is a read word line, to turn on the access transistor and reduce the current flowing therethrough. This is done by reading.
[0013]
When the spin direction of the NiFe free layer 34 is the same as the spin direction of the CoFe pinned layer 36, the resistance becomes low, and when the spin direction is the opposite direction, the resistance becomes high, for example, increases by 10 to 100% at the time of low resistance. Therefore, it is possible to read 1-bit recording by determining the magnitude of the current.
[0014]
In such an MRAM, the larger the change in resistance in the TMR element, the higher the data retention reliability. However, this change in resistance is due to the change in resistance of the free layer and the pinned layer such as NiFe, CoFe, CoFeB, Co, Fe, Ni, etc. Since it depends on the combination of the magnetic material and Al ₂ O ₃ , AlO _x , or HfO _x constituting the tunnel insulating layer and the thin film structure, it is required to reduce the process damage due to the film forming process and the wiring process.
[0015]
[Patent Document 1]
JP 2003-031776 A [Patent Document 2]
JP-A-2002-299584
[Problems to be solved by the invention]
However, the above-described magnetic material is a metal material, and is easily oxidized in an oxidizing atmosphere, which causes an increase in resistance, and eventually causes a decrease or disappearance of spin electrons and a deterioration in resistance change characteristics.
[0017]
In particular, the TMR element 52 is covered only by the fifth interlayer insulating film 53 having a planarizing function, and this fifth interlayer insulating film 53 is generally a TEOS-NSG film, that is, an O ₃ -TEOS-SiO ₂ film. Alternatively, an SOG (Spin on Glass) -SiO ₂ film is used, but the SiO ₂ film using such an organic silane has a high hygroscopicity and a large amount of gas is generated in a heating process in a manufacturing process. _{(mainly, H} 2 O) that be released has been known (if necessary, 1993VIMC, see p.287-289,1993).
[0018]
In such a situation, it is easy to guess that the magnetic material constituting the TMR element 52 is oxidized and the characteristics are deteriorated. In particular, the element size becomes finer as the integration becomes higher. This is an important item for suppressing characteristic variations.
The same applies to the case where a GMR element is used instead of the TMR element 52 as the magnetoresistive storage element.
[0019]
Therefore, an object of the present invention is to reduce the process damage of the magnetoresistive storage element and prevent the magnetoresistive effect characteristics from deteriorating.
[0020]
[Means for Solving the Problems]
FIG. 1 is a block diagram showing the principle of the present invention, and means for solving the problems in the present invention will be described with reference to FIG.
FIG. 1 shows a magnetic random access memory device according to the present invention. In the magnetic random access memory device, a first word line 4 and a bit line 3 are arranged on a semiconductor substrate at intersections of first word lines 4 and bit lines 3, respectively. A magnetoresistive storage element 5 in which a first magnetic layer 6 having a variable magnetization direction and a second magnetic layer 8 having a fixed magnetization direction are stacked via a nonmagnetic intermediate layer 7; In a magnetic random access memory device including an access transistor 1 having a gate formed by a second word line 2 arranged in a direction intersecting with the line 3, the insulator surrounding the side of the magnetoresistive storage element 5 is made of SiO ₂ . It is characterized by using a water permeation prevention film 10 having excellent water permeation prevention performance.
[0021]
As described above, since the side portion of the magnetoresistive storage element 5 is covered with the water permeation prevention film 10, the first magnetic layer 6 and the second magnetic layer 8 constituting the magnetoresistive storage element 5 are processed during the process. In addition, since oxidation after the process is suppressed, stability and reliability of electric characteristics can be improved.
[0022]
As the water permeation prevention film 10 in this case, any of Al ₂ O ₃ , SiN such as plasma SiN, or SiON such as plasma SiON, which is more excellent in water permeation prevention performance than SiO ₂ , is preferable.
[0023]
The magnetoresistive storage element 5 may be a giant magnetoresistance effect element (GMR element) in which the nonmagnetic intermediate layer 7 is a nonmagnetic conductive layer, but may be a tunnel magnetoresistance effect in which the nonmagnetic intermediate layer 7 is a tunnel insulating layer. An element (TMR element) is desirable, so that the resistance change rate can be further increased.
[0024]
Further, it is desirable that the upper electrode 9 constituting the magnetoresistive memory element 5 is made of a metal whose oxide is also conductive, for example, either Ru or Ir, so that the upper electrode 9 enters during and after the process. O ₂ or H ₂ O is blocked by the sacrificial oxidation of the upper electrode 9, and the oxidized portion of the upper electrode 9 also has good conductivity, so that the electrical characteristics do not deteriorate.
[0025]
In this case, it is desirable to bury the side portion of the magnetoresistive storage element 5 with a planarization insulating film via the water permeation prevention film 10, thereby facilitating planarization.
[0026]
The bit line 3 may be provided directly on the flattening insulating film. However, the bit line 3 is electrically connected to the upper electrode 9 through an opening provided in the insulating film having better water permeation prevention performance than SiO ₂ covering the upper electrode 9. It is preferable that the upper portion of the magnetoresistive storage element 5 is covered with an insulating film having excellent water permeation prevention performance, so that the water permeation prevention effect can be further enhanced.
[0027]
When manufacturing the above-described magnetic random access memory device, after providing a water permeation prevention film 10 having better water permeation prevention performance than SiO ₂ so as to cover the magnetoresistive storage element 5, a flattening insulating film is provided. Next, it is desirable to remove and planarize the planarizing insulating film and the water permeation preventing film 10 until at least the upper layer portion of the upper electrode 9 constituting the uppermost layer of the magnetoresistive storage element 5 is removed. Since the oxidized portion of the upper electrode 9 that has been oxidized can be removed, an increase in element resistance can be further prevented.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
Here, the manufacturing process of the MRAM according to the embodiment of the present invention will be described with reference to FIGS.
Referring to FIG. 2A, first, a p-type well region 12 is formed in a predetermined region of an n-type silicon substrate 11, and an element isolation oxide film 13 is formed by selectively oxidizing the n-type silicon substrate 11. A gate electrode 15 made of WSi serving as a read word line is formed in the region via a gate insulating film 14, and As ions are implanted using the gate electrode 15 as a mask to form an n ⁻ type LDD region 16.
[0029]
Next, a SiO ₂ film is deposited on the entire surface, a sidewall 17 is formed by performing anisotropic etching, and then an n ⁺ -type drain region 18 and an n ⁺ -type source region 19 are formed by implanting As ions again. Then, after forming a thick first interlayer insulating film 20 made of an O ₃ -TEOS-SiO ₂ film, a contact hole reaching the n ⁺ -type drain region 18 and the n ⁺ -type source region 19 is formed. Are embedded in W to form W plugs 21 and 22.
The O ₃ -TEOS-SiO ₂ film is deposited at 400 ° C. by a CVD method using TEOS + O ₃ as a source gas, and the same applies to the following steps.
[0030]
See FIG. 2 (b) Then, by patterning after depositing the TiN / Al / TiN on the entire surface by a sputtering method, after forming the connection conductor 23 and the source wiring layer 24, _again, O 3 -TEOS- A second interlayer insulating film 25 made of a SiO ₂ film is formed, a contact hole reaching the connection conductor 23 is formed, and the contact hole is filled with W to form a W plug 26.
Normally, the source wiring layer 24 is connected to the GND line.
[0031]
Figure 3 (c) refer then again followed by patterning the deposition of TiN / Al / TiN on the entire surface by a sputtering method, after forming the connection conductor 27 and the write word line 28, again, _{O 3} forming a third interlayer insulating film 29 made of -TEOS-SiO ₂ film, then forming a contact hole reaching the connection conductor 27, the W plug 30 by embedding the contact holes with W, with Ti / TiN Form.
[0032]
Next, referring to FIG. 3D, the lower electrode 31 is formed by depositing TiN / Al / TiN over the entire surface again by using the sputtering method and then patterning the same, and then again forming the O ₃ -TEOS-SiO ₂ film. Then, a thin fourth interlayer insulating film 32 made of is deposited, and then planarized by CMP until the lower electrode 31 is exposed.
[0033]
Next, referring to FIG. 4E, a tunnel insulating layer 35 made of, for example, a Ta underlayer 33 having a thickness of 20 nm, a NiFe free layer 34 having a thickness of 10 nm, and Al ₂ O ₃ having a thickness of 1 nm is formed on the entire surface by using a sputtering method. A 10 nm CoFe pinned layer 36, a 30 nm IrMn pinned layer 37, and a 100 nm thick Ru cap layer 38 serving as an upper electrode are sequentially deposited in vacuum.
[0034]
Referring to FIG. 4F, the TMR element 39 having a size of, for example, 0.2 μm × 0.13 μm is formed by performing ion milling.
In this case, since the TMR element 39 has a rectangular shape long in the bit line direction, the spin direction of the NiFe free layer 34 can easily be directed to the extending direction of the bit line.
[0035]
Referring to FIG. 5 (g), the TMR element 39 is again covered with the Al ₂ O ₃ waterproof film 40 having a thickness of, for example, 100 nm by using the sputtering method, and then the whole surface is covered with O ₃ -TEOS-SiO ₂ again. A fifth interlayer insulating film 41 made of a film is deposited so that the thickness on the TMR element 39 becomes, for example, 400 nm.
The condition of the sputtering process at this time is that the power of 2 kW is applied to the Al ₂ O ₃ target while flowing Ar gas at 20 sccm, and the refraction of the obtained Al ₂ O ₃ waterproof film 40 is performed. the rate from 1.62 to 1.66, for example, 1.64, and film density 3.0~3.2g / cm ^3, for example, a 3.1 g / cm ^3.
[0036]
Next, referring to FIG. 5H, the surface of the Ru cap layer 38 is polished by, for example, 50 nm by using the CMP method, and the whole is planarized.
At this time, the surface of the Ru cap layer 38 oxidized during the process is removed, but even if an oxide such as RuO ₂ remains, there is no problem because RuO ₂ has good conductivity. .
[0037]
Next, after a p-SiN film 42 having a thickness of, for example, 100 nm is deposited by using a plasma CVD method, a contact hole for the TMR element 39 is provided. For example, after a 100 nm TiN layer, an 800 nm thick Al layer, and a 100 nm thick TiN layer, for example, are sequentially deposited to deposit a multilayer conductive layer having a TiN / Al / TiN structure. By patterning the bit line 43 so as to extend in a direction orthogonal to the write word line 28, the basic structure of the MRAM is completed.
[0038]
FIG. 7 is an explanatory diagram of the water permeation prevention performance of Al ₂ O _{3. In} the case of the conventional TEOS-NSG film alone, a large amount of H ₂ O is released at about 300 ° C. It is understood that when the NSG film is covered with Al ₂ O ₃ , H ₂ O is hardly released at 600 ° C. or lower.
[0039]
As described above, in the process and device structure according to the embodiment of the present invention, since the Ru cap layer 38 is provided on the TMR element 39, even if O ₂ or H ₂ O tries to enter during the process. , Ru prevents sacrificial oxidation of oxygen from entering the TMR element 39. Further, since RuO ₂ has good conductivity, the electrical conductivity can be maintained.
[0040]
In addition, since the side wall of the TMR element 39 is covered with the Al ₂ O ₃ waterproof film 40, the oxidation reaction from the side of the TMR element 39 is suppressed during and after the process, so that the electrical characteristics are stable. It greatly contributes to improvement in reliability and reliability.
[0041]
Further, since the upper part of the TMR element 39 is also covered with the p-SiN film 42 having excellent water permeation prevention performance, the oxidation reaction from the upper part of the TMR element 39 after the process is suppressed, so that the stability of the electric characteristics is improved. It greatly contributes to improving reliability.
[0042]
The embodiments of the present invention have been described above. However, the present invention is not limited to the configurations and conditions described in the embodiments, and various changes can be made.
For example, in each of the above embodiments, a sputtered Al ₂ O ₃ film is used as a water permeation prevention insulating film, but it can be formed at a low temperature of 300 ° C. or less without damaging the TMR element, and has a water permeation prevention performance. It is also possible to use a SiN film or a SiON film which has excellent characteristics, particularly, a p-SiN film or a p-SiON film formed by plasma CVD (see 1993 VIMC, pp. 287-289, 1993, if necessary).
[0043]
Further, in the above embodiment, the fifth interlayer insulating film is planarized by CMP, but the present invention is not limited to CMP, and is not limited to CMP, and may be a chlorine-based gas such as Cl ₂ or CCl ₄ , or CF ₄ or by performing flattening by etch-back using a fluorine-based gas F _2, etc. it is permissible.
At this time, the Ru cap layer 38 constituting the upper electrode or RuO ₂ , which is an oxide thereof, is inactive against these etching gases, and thus also functions as an etching stopper film.
[0044]
Further, in the above-described embodiment, Ru is used as the upper electrode. However, the present invention is not limited to Ru, and its oxide may be a metal having good conductivity like Ru, for example, Ir may be used.
[0045]
In the above-described embodiment, the bit line 43 is formed of sputtered Al. However, the bit line 43 is not limited to Al, and Cu wiring by a damascene method may be used.
[0046]
In the above embodiment, the magnetoresistive storage element is a TMR element using a tunnel insulating layer. However, the present invention is not limited to the TMR element, and a local current path is formed by partially oxidizing Al. The GMR element may be a conventional GMR element using a nonmagnetic conductive layer of Cu or the like instead of the Al ₂ O ₃ film.
[0047]
In the above embodiment, IrMn is used as the antiferromagnetic pinned layer. However, the present invention is not limited to IrMn, and another antiferromagnetic material such as FeMn or PdPtMn may be used. .
When PdPtMn is used, it is necessary to fix the magnetization direction of the PdPtMn pinned layer by performing an annealing process while applying a magnetic field after forming PdPtMn.
[0048]
Further, the free layer and the pinned layer in the above-described embodiment are merely examples, and the free layer or the pinned layer may have a multilayer structure such as NiFe / CoFe or CoFe / Ru / CoFe. .
[0049]
Further, in the above-described embodiment, the magnetoresistive storage element is constituted by a multilayer film of a type laminated from a free layer, but may be constituted by a multilayer film of a type laminated from an antiferromagnetic pinned layer. It is.
[0050]
Further, in the above embodiment, the write word line 28 is arranged below the magnetoresistive storage element due to the temperature condition in the film forming process, but the formation of the interlayer insulating film and the formation of the conductive layer in the low temperature process are performed. If it is formed, it may be arranged above the magnetoresistive storage element.
[0051]
In the above embodiment, the bit line 43 is deposited via the p-SiN film 42. However, the bit line 43 is directly deposited on the fifth interlayer insulating film 41 in the same manner as the principle configuration shown in FIG. It is also possible to make it.
[0052]
Further, in the above-described embodiment, each interlayer insulating film is formed of an O ₃ -TEOS-SiO ₂ film, but is formed of another easy-to-flatten film such as an SOG-SiO ₂ film or a BPSG film. Is also good.
[0053]
Further, in the above-described embodiment, the ion milling method is used when patterning the TMR element, but reactive ion etching (RIE) may be used.
[0054]
Here, referring to FIG. 1 again, the detailed features of the present invention will be described again.
Again, see FIG. 1 (Supplementary Note 1). The first magnetic field is arranged on the semiconductor substrate in the intersection region of the first word line 4 and the bit line 3 arranged in the direction intersecting each other, and the magnetization direction is variable. A magnetoresistive storage element 5 in which a body layer 6 and a second magnetic layer 8 having a fixed magnetization direction are stacked via a nonmagnetic intermediate layer 7, and a second magnetic layer 8 arranged in a direction crossing the bit line 3. A random access memory device having an access transistor 1 having a word line 2 as a gate, and a water permeation preventive which is more excellent in water permeation preventive performance than SiO ₂ as an insulator surrounding a side portion of the magnetoresistive storage element 5. A magnetic random access memory device using the film 10.
(Supplementary Note 2) The magnetic random access memory device according to Supplementary Note 1, wherein any one of Al ₂ O ₃ , SiN, and SiON is used as the water permeation prevention film 10.
(Supplementary note 3) The magnetic random access memory device according to supplementary note 1 or 2, wherein the magnetoresistive storage element 5 is a tunnel magnetoresistive element in which the nonmagnetic intermediate layer 7 is a tunnel insulating layer.
(Supplementary Note 4) The magnetic random access according to any one of Supplementary notes 1 to 3, wherein the upper electrode 9 constituting the magnetoresistive storage element 5 is formed of a metal having a conductive oxide. Memory device.
(Supplementary note 5) The magnetic random access memory device according to any one of Supplementary notes 1 to 4, wherein the metal is one of Ru and Ir.
(Supplementary Note 6) The magnetic random access according to any one of Supplementary Notes 1 to 5, wherein a side portion of the magnetoresistive storage element 5 is buried with a planarization insulating film via the water permeation prevention film 10. Memory device.
(Supplementary Note 7) The bit line 3 is electrically connected to the upper electrode 9 through an opening provided in an insulating film having better water permeation prevention performance than SiO ₂ covering the upper electrode 9. 7. The magnetic random access memory device according to any one of supplementary notes 1 to 6.
(Supplementary Note 8) The first magnetic layer 6 having a variable magnetization direction and a first magnetic layer 6 arranged in a crossing region of a first word line 4 and a bit line 3 arranged in a direction crossing each other on a semiconductor substrate. A magnetoresistive storage element 5 in which a second magnetic layer 8 whose direction is fixed is stacked with a nonmagnetic intermediate layer 7 interposed therebetween, and a second word line 2 arranged in a direction crossing the bit line 3 In a method for manufacturing a magnetic random access memory device having an access transistor 1 having a gate as a gate, a water permeation prevention film 10 having better water permeation prevention performance than SiO ₂ is provided so as to cover the magnetoresistive storage element 5. Providing a planarizing insulating film, and planarizing by removing the planarizing insulating film and the water permeation preventing film 10 until at least the upper layer portion of the upper electrode 9 constituting the uppermost layer of the magnetoresistive memory element 5 is removed. Process Method of manufacturing a magnetic random access memory device which is characterized in that.
[0055]
【The invention's effect】
According to the present invention, an oxide such as Ru is provided with a conductive metal on the upper part of the magnetoresistive storage element, and a water permeation prevention insulating film such as Al ₂ O ₃ is provided on the side wall. Oxidation of the magnetic layer constituting the element is suppressed during and after the process, thereby greatly improving the stability and reliability of the electrical characteristics and contributing to the practical use of a highly integrated MRAM. large.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of the present invention.
FIG. 2 is an explanatory diagram of a manufacturing process of an MRAM according to an embodiment of the present invention up to a certain point;
FIG. 3 is an explanatory diagram of a manufacturing process of the MRAM according to the embodiment of the present invention up to the middle of FIG. 2;
FIG. 4 is an explanatory diagram of a manufacturing process of the MRAM according to the embodiment of the invention up to the middle of FIG. 3;
FIG. 5 is an explanatory diagram of a manufacturing process of the MRAM according to the embodiment of the present invention up to the middle of FIG. 4;
FIG. 6 is an explanatory diagram of a manufacturing process of the MRAM according to the embodiment of the present invention after FIG. 5;
FIG. 7 is an explanatory diagram of water permeation prevention performance of Al ₂ O ₃ .
FIG. 8 is a schematic cross-sectional view of a main part of a conventional MRAM.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 access transistor 2 second word line 3 bit line 4 first word line 5 magnetoresistive storage element 6 first magnetic layer 7 nonmagnetic intermediate layer 8 second magnetic layer 9 upper electrode 10 water permeation prevention layer Reference Signs List 11 n-type silicon substrate 12 p-type well region 13 element isolation oxide film 14 gate insulating film 15 gate electrode 16 n ⁻ type LDD region 17 sidewall 18 n ⁺ type drain region 19 n ⁺ type source region 20 first interlayer insulating film 21 W plug 22 W plug 23 Connection conductor 24 Source wiring layer 25 Second interlayer insulation film 26 W plug 27 Connection conductor 28 Write word line 29 Third interlayer insulation film 30 W plug 31 Lower electrode 32 Fourth interlayer insulation film 33 Ta Underlayer 34 NiFe free layer 35 Tunnel insulating layer 36 CoFe pinned layer 37 IrMn pin layer 38 Ru cap layer 39 TMR element 40 Al ₂ O ₃ waterproof film 41 Fifth interlayer insulating film 42 p-SiN protective film 43 Bit line 51 Ta cap layer 52 TMR element 53 Fifth interlayer insulating film 54 Bit line

Claims (5)

A first magnetic layer whose magnetization direction is variable and a second magnetic layer whose magnetization direction is fixed are arranged on a semiconductor substrate at intersection regions of first word lines and bit lines arranged in directions intersecting each other. A magnetic random access memory comprising: a magnetoresistive storage element in which a magnetic layer is stacked with a non-magnetic intermediate layer interposed therebetween; and an access transistor having a gate formed by a second word line disposed in a direction crossing the bit line. A magnetic random access memory device according to an access memory device, wherein a water permeation prevention film having better water permeation prevention performance than SiO ₂ is used as an insulator surrounding a side portion of said magnetoresistive storage element. _2. The magnetic random access memory device according to claim 1, wherein any one of Al ₂ O ₃ , SiN, and SiON is used as the water permeation preventing film. 3. The magnetic random access memory device according to claim 1, wherein an upper electrode of the magnetoresistive storage element is made of a metal whose oxide is also conductive. 4. The magnetic random access memory device according to claim 1, wherein a side portion of the magnetoresistive storage element is buried with a planarizing insulating film via the water permeation preventing film. 5. 5. The bit line according to claim 1, wherein the bit line is electrically connected to the upper electrode through an opening provided in an insulating film having better water permeation prevention performance than SiO ₂ covering the upper electrode. The magnetic random access memory device according to claim 1.

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