JP2004319645A - Multilayer printed wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To propose a multilayer printed wiring board in which a malfunction or an error never occurs even if the frequency exceeds 3 GHz. <P>SOLUTION: A distance D1 between a conductor layer 34P of the surface of a multilayer core substrate 30 and an inner conductor layer 16E thereof, a distance D2 between the inner conductor layer 16E and a metal plate 12, a distance D3 between the metal plate 12 and an inner conductor layer 16P, and a distance D4 between the inner conductor layer 16P and a conductor layer 34E of the rear surface, are made uniform. By arranging the conductor layers so that the distances are uniform, mutual inductance among the conductor layers is made constant and the overall inductance component is reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer printed wiring board, and improves electrical characteristics and reliability without causing malfunction or error even when a high-frequency IC chip, particularly an IC chip in a high-frequency region of 3 GHz or more, is mounted. The present invention relates to a multilayer printed wiring board that can be used.
[0002]
[Prior art]
In a build-up type multilayer printed wiring board constituting a package for an IC chip, as shown in FIG. 23, a conductor circuit 34 and a conductor layer 34P are provided on an upper surface of a core substrate 30 provided with a through hole 36, and a conductor circuit 34 is provided on a back surface. , A conductor layer 34E is formed. The upper conductor layer 34P is formed as a power supply plane layer, and the lower conductor layer 34E is formed as a ground plane layer. On the conductor layers 34P and 34E on the surface of the core substrate 30, the interlayer resin insulation layer 50 having the via hole 60 and the conductor circuit 58 formed thereon and the interlayer resin insulation layer 150 having the via hole 160 and the conductor circuit 158 formed thereon And are arranged. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 </ b> U and 76 </ b> D are formed in the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing. An IC chip (not shown) is electrically connected by performing C4 (flip chip) mounting on the bumps 76U.
[0003]
Conventional techniques of such a build-up type multilayer printed wiring board include Patent Literature 1 and Patent Literature 2. In both cases, a land is formed on a core substrate filled with a through-hole with a filling resin, an interlayer insulating layer having via holes on both surfaces is applied, a conductor layer is applied by an additive method, and the land is connected, It is possible to obtain a multilayer printed wiring board on which high density and fine wiring are formed.
[0004]
[Patent Document 1]
JP-A-6-260756
[Patent Document 2]
JP-A-6-275959
[0005]
[Problems to be solved by the invention]
However, as the frequency of the IC chip becomes higher, the generated noise becomes higher. In particular, the degree has been increasing since the frequency exceeded 3 GHz. Further, when the frequency exceeds 5 GHz, the tendency further increases.
As a result, the desired function cannot be performed due to a defect such as a delay in an operation that should be performed (for example, image recognition, switching of a switch, transmission of data to the outside, etc.).
When IC chips and substrates that cannot perform desired functions are to be nondestructively inspected or disassembled, problems such as short circuits and open circuits do not occur in the IC chips and substrates themselves, and ICs with low frequencies (especially less than 1 GHz) When the chip was mounted, no malfunction or error occurred.
[0006]
That is, the high-frequency IC chip intermittently increases or decreases the power consumption, thereby enabling high-speed calculation while suppressing heat generation. For example, although the power consumption is usually about several watts, several tens of watts of power are consumed instantaneously. At the time of power consumption of several tens of watts, if the impedance of the power line of the package substrate is high, it is considered that the supply voltage decreases at the time of rising power at which power consumption increases, which causes a malfunction.
[0007]
An object of the present invention is to propose an IC chip in a high-frequency region, in particular, a multilayer printed wiring board or a package substrate which does not cause a malfunction or an error even if it exceeds 3 GHz.
[0008]
[Means for Solving the Problems]
The inventors of the present invention have intensively studied for realizing the above object, and as a result, have conceived an invention having the following features as the main constitution. That is, on a multilayer core substrate having a plurality of through-holes and having at least three or more conductor layers having a conductor layer on both surfaces and a conductor layer on the inner layer, an interlayer insulating layer and a conductor layer are provided on both surfaces or one surface. In the multilayer printed wiring board formed and electrically connected via via holes, the conductor layer on the surface of the multilayer core substrate and the conductor layer on the adjacent inner layer are arranged at a uniform distance from each other. Is a technical feature.
In addition, an interlayer insulating layer and a conductor layer are formed on both surfaces or one surface on a multilayer core substrate having a plurality of through holes and having at least three or more conductor layers having a conductor layer on both surfaces and a conductor layer on the inner layer. In a multi-layer printed wiring board that is electrically connected through via holes,
A technical feature is that the distance between adjacent conductor layers of the multilayer core substrate is arranged at a uniform distance.
[0009]
By arranging adjacent conductor layers of a multilayer core substrate having three or more conductor layers at a uniform distance, the mutual inductance between the conductor layers can be kept constant, and the inductance of the entire core substrate can be reduced. In this case, it means that the distance between two or more conductor layers is the same. For example, the distance between the conductor layer of the surface layer (front surface) and the conductor layer of the inner layer and the distance between the conductor layer of the surface layer (rear surface) opposite to the inner conductor layer, and the distance between the conductor layer of the surface layer and the conductor layer of the inner layer are different. And the distance between the inner conductor layer and another inner conductor layer. It is preferable to make the distance between adjacent conductor layers uniform at least at two or more places. It is most desirable that the distance between three or more adjacent conductor layers or the distance between all adjacent conductor layers be uniform.
Therefore, by using the conductor layer as a power supply layer, the ability to supply power to the IC chip can be improved. In addition, by using the conductor layer as a ground layer, a signal to an IC chip and noise superimposed on a power supply can be reduced. That is, the reduction of the inductance of the conductor layer does not hinder the power supply. Therefore, when the IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the board to the power supply can be reduced. Therefore, power shortage during the initial operation is reduced, and power shortage is unlikely to occur. Therefore, even if an IC chip in a high frequency region is mounted, a malfunction or an error in the initial startup does not occur. Further, by using a multilayer core substrate, the area of the conductor layer can be increased as compared with a conventional double-sided core substrate. Furthermore, if the conductor layer is used as a power supply layer or a ground layer, the area of each conductor layer can be increased. For this reason, factors that hinder the resistance are reduced, and the electrical characteristics are improved.
[0010]
The distance between the conductor layers means the distance between the conductor layers of two adjacent conductor layers in the conductor layer formed on the multilayer core substrate. As shown in FIG. 21A, in the case of a multilayer core substrate 30 in which three layers (a surface conductor layer A, an inner conductor layer B, and a surface conductor layer C) are arranged via an insulating layer 15, a conductor on the surface is provided. The distance L between the layer A and the inner conductor layer B, and the distance L between the inner conductor layer B and the surface conductor layer C.
[0011]
On the other hand, as shown in FIG. 21B, four or more conductor layers (surface conductor layer A, inner conductor layers B1, BX-n,... BX-N + 1, BX, surface conductor layer C) In the case of the multilayer core substrate 30, the distance L1 between the conductor layer A on the surface and the conductor layer B1 on the inner layer, and the distance LX-n between the conductor layer BX-n on the inner layer and the conductor layer BX-n on the inner layer (LX-n ( 0 ≦ n <Xn, X: integer), and is the distance LX between the inner conductor layer BX and the surface conductor layer C on the opposite surface. Here, it is most desirable that L1 = L2... LX-n = LX-n + 1... = LX-1 = LX.
[0012]
In addition, it is desirable that adjacent conductor layers of the multilayer core substrate are arranged in a row of a conductor layer for a power supply layer and a conductor layer for a ground. By arranging the power supply layer and the ground at adjacent positions, the directions of the induced electromotive forces generated respectively are opposite to each other, and the respective induced electromotive forces are canceled. Therefore, noise is reduced and the function as a substrate is not reduced. Further, malfunction and delay are eliminated. In other words, the mutual inductance can be reduced. In this case, it is desirable that the distance between both conductor layers is as short as possible. That is, the relative inductance can be reduced by shortening the distance.
[0013]
It is desirable that a conductor layer adjacent to the power supply layer (or the ground layer) be a ground layer (or a power supply layer), and another ground layer (or a power supply layer) be disposed on the other conductor layer. By arranging the conductor layer of the power supply layer and the conductor layer of the ground layer, it is possible to reduce the inductance of the entire core substrate.
[0014]
The distance between the conductor layers of the multilayer core substrate is desirably 15 to 300 μm. If the thickness is less than 15 μm, it is difficult to maintain insulation, causing a problem in electrical connectivity. If the thickness is more than 300 μm, the multilayer core substrate becomes thicker, the through hole becomes longer, and the inductance in the through hole increases. Further, the relative decrease in inductance depending on the distance between the conductor layers is offset, and the effect is not exhibited. More preferably, the distance between the conductor layers is 30 to 250 μm. During this time, the inductance can be reduced, and the insulation between the conductor circuits is ensured.
[0015]
In this case, it is desirable to increase the conductor thickness of the ground (GND) layer and the conductor thickness of the power supply (VCC) layer formed on the core substrate. It is desirable that the thickness exceeds 50 μm. In particular, it is more desirable that the thickness of the conductor layer of the core substrate is larger than the thickness of the conductor layer on the interlayer insulating layer.
[0016]
By increasing the thickness of the conductor layer of the core substrate, the thickness of the conductor layer of the power supply layer of the core substrate increases, thereby increasing the strength of the core substrate. Can be reduced by the substrate itself.
Further, the volume of the conductor itself can be increased. By increasing the volume, the resistance of the conductor can be reduced. Therefore, electric transmission of a flowing signal line or the like is not hindered. Therefore, no loss occurs in the transmitted signal and the like. That effect is achieved by increasing the thickness of only the core portion of the substrate.
Further, by using the conductor layer as a power supply layer, the ability to supply power to the IC chip can be improved. In addition, by using the conductor layer as a ground layer, a signal to an IC chip and noise superimposed on a power supply can be reduced. That is, the reduction in the resistance of the conductor does not hinder the power supply. Therefore, when the IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the board to the power supply can be reduced. Therefore, power shortage during the initial operation is reduced, and power shortage is unlikely to occur. Therefore, even if an IC chip in a high frequency region is mounted, a malfunction or an error in the initial startup does not occur.
The same effect is obtained when power is supplied to the IC chip via the IC chip-substrate-capacitor or power supply layer-power supply. The aforementioned loop inductance can be reduced.
[0017]
In particular, when the thickness of the conductor layer used as the power supply layer of the core substrate is thicker than the thickness of the conductor layer on the interlayer insulating layer on one or both surfaces of the core substrate, the above effects can be maximized. is there. In this case, the conductor layer on the interlayer insulating layer is formed with a via hole which is a non-through hole for connecting the layers in an interlayer resin insulating layer formed of a resin in which the core material is not impregnated in the insulating layer. It mainly means a conductor layer formed by plating, sputtering or the like. There is no particular limitation other than this, but if the via hole is formed, it corresponds to the above conductor layer.
[0018]
The power supply layer of the core substrate may be disposed on the surface layer, the inner layer, or both of the substrate. In the case of the inner layer, the inner layer may be multi-layered over two or more layers. Basically, if the power supply layer of the core substrate is thicker than the conductor layer of the interlayer insulating layer, the effect is obtained. However, it is desirable to form it in the inner layer.
[0019]
It is desirable that α2 <α1 ≦ 40α2, where α1 is the thickness of the conductor layer on the core substrate and α2 is the thickness of the conductor layer on the interlayer insulating layer.
If α1 ≦ α2, there is no effect on the power shortage. In other words, in other words, it is not clear that the degree of voltage drop that occurs during the initial operation is suppressed.
Although the case where α1> 40α2 was also examined, the electrical characteristics are basically almost the same as 10α2. That is, it can be understood that this is a critical point of the effect. Even if it is thicker than this, improvement of the electrical effect cannot be expected. However, if the thickness exceeds this, it becomes difficult to form lands or the like for connection with the core substrate when the conductor layer is formed on the surface layer of the core substrate. Further, when an upper interlayer insulating layer is formed, the unevenness becomes large, and undulation occurs in the interlayer insulating layer, so that impedance cannot be matched.
[0020]
More preferably, the thickness α1 of the conductor layer is 1.2α2 ≦ α1 ≦ 20α2. In this range, it has been confirmed that malfunction or error of the IC chip due to insufficient power (voltage drop) does not occur.
[0021]
It is desirable to use a multilayer core substrate having three or more conductor layers.
At this time, it is preferable that two or more GND layers or VCC layers are formed, and a VCC layer or a GND layer is formed between the layers. Furthermore, it is preferable that each distance between the GND layer (or VCC layer) and the VCC layer (or GND layer) is uniform. Thereby, since the action of lowering both inductances works uniformly, it is easy to lower the overall inductance. Further, impedance matching can be easily achieved, and electrical characteristics can be improved.
More preferably, both the VCC layer and the GND layer are two or more layers. The effect that the inductance which is the GND layer arranged in the inner layer and which is the VCC layer lowers the mutual inductance as compared with the surface layer can be obtained. The effect is more pronounced.
[0022]
It is desirable that the distance between the GND layer and the VCC layer is between 15 and 300 μm. If it is less than 15 μm, it is easy to ensure insulation regardless of the material, and if a reliability test such as a heat cycle is performed, a short circuit may occur between the conductor layers. If it exceeds 300 μm, the effect of lowering the inductance will be reduced. In other words, the effect of the mutual inductance is offset by the large distance. More preferably, the distance between the GND layer and the VCC layer is between 30 and 250 μm. In the meantime, the inductance can be reduced, and the insulation between the conductor circuits is ensured.
[0023]
It is preferable that both the GND layer and the VCC layer have thicker conductor layers. This is because the effect of reducing the resistance value is easily obtained by increasing the volume of both. The thickness of the conductor is desirably 25 to 300 μm. If it is less than 25 μm, the effect of reducing the resistance value tends to be thin. If the thickness exceeds 300 μm, a swell may occur in a conductor circuit such as a signal line formed thereon, which causes a problem in impedance matching. It is difficult to meet the demand for a thinner substrate because the substrate itself becomes thicker. In this case, it is desirable that the thickness be larger than the thickness of the conductor layer of the interlayer insulating layer.
[0024]
The material of the core substrate was verified using a resin substrate, but it was found that the same effect was obtained with a ceramic or metal core substrate. The conductor layer was also made of a metal made of copper.However, it has not been confirmed that the effects of other metals are canceled out and the occurrence of malfunctions and errors increases. It is considered that the difference or the difference in the material forming the conductor layer has no effect on the effect. More preferably, the conductor layer of the core substrate and the conductor layer of the interlayer insulating layer are formed of the same metal. This effect can be achieved because the characteristics such as the electrical characteristics and the thermal expansion coefficient and the physical properties do not change.
[0025]
Further, the through-holes of the multilayer core substrate may include two or more ground through-holes and two or more power supply through-holes, each of which is arranged in a lattice or staggered pattern at adjacent positions. desirable.
[0026]
The ground (or power supply) is arranged at diagonal positions, and the power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force in the X direction and the Y direction is canceled.
[0027]
The ground (or power supply) is arranged at diagonal positions, and the power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force in the X direction and the Y direction is canceled.
This will be described with reference to FIG. 11A schematically showing an example in which through holes are arranged in a lattice. In the through holes arranged in a lattice, power supply through holes VCC1 and VCC2 are arranged at equal intervals of the ground through hole GND1, and the power supply through hole GND2 is arranged on a diagonal line of the ground through hole GND1. Set up. With this 4-core (quad) structure, the induced electromotive force generated by two power supply through-holes VCC (or ground through-hole GND) for one ground through-hole GND (or power supply through-hole VCC). Negation is made. For this reason, the mutual inductance in the through hole can be reduced, and there is no influence of the induced electromotive force, so that a malfunction or a delay hardly occurs.
[0028]
An explanation will be given with reference to FIG. 11B schematically showing an example in which through holes are arranged in a staggered manner. In the staggered through-holes, ground through-holes GND2 and GND3 are arranged at equal intervals of the ground through-hole GND1, and the power supply through-holes VCC1 and VCC2 are arranged at the same distance as the ground through-hole GND2. Is arranged. With this structure, two power supply through-holes VCC (or ground through-hole GND) cancel out induced electromotive force for one ground through-hole GND (or power supply through-hole VCC). Therefore, the mutual inductance of the through-hole can be reduced, and there is no influence of the induced electromotive force, so that a malfunction or a delay is less likely to occur.
[0029]
The inductance can be reduced by arranging the elements in a lattice pattern than by arranging the elements in a staggered pattern. Even when two or more equal numbers of ground through holes and power supply through holes are provided, a grid is required to provide a maximum of four with respect to one ground through hole GND (or power supply through hole VCC). It is possible to arrange the locations at equal intervals, and also to arrange the opposing through holes for power supply VCC at a maximum of four locations at equal intervals, canceling out the induced electromotive force in each case. It can be reduced.
[0030]
Originally, the ground through hole GND and the power supply through hole VCC are easily affected by a magnetic field or the like. For this reason, when the frequency and speed of the IC chip increase, the inductance increases, which causes a problem in the operation as a substrate. Therefore, it is necessary to consider an arrangement for suppressing the influence of the inductance of the ground through-hole GND and the power supply through-hole VCC. For example, in response to a demand for higher density (higher density, fine wiring), it is not necessary to simply arrange the through holes narrower. The arrangement as described above can reduce the respective inductances.
[0031]
The distance between the ground through-hole and the power supply through-hole (pitch shown in FIG. 11C: the distance between the center of the ground through-hole GND and the center of the power supply through-hole VCC) is between 60 and 600 μm. It is desirable that By reducing the distance between the through-holes and the walls of the through-holes, the mutual inductance can be reduced. At this time, if it is less than 60 μm, it is not possible to secure an insulating gap between the through-holes, causing problems such as a short circuit. In addition, due to an insulation gap or the like, it may be difficult to keep the mutual inductance within the allowable design range. The effect of reducing the mutual inductance exceeding 600 μm is reduced. When the thickness is between 60 and 550 μm, an insulating gap can be secured in the through hole, the mutual inductance can be reduced, and the electrical characteristics can be improved.
[0032]
The diameter of the through hole for the grant (the outer diameter of the through hole shown in FIG. 11D) is 50 to 500 μm, and similarly, the diameter of the through hole for the power supply is desirably 50 to 500 μm.
If it is less than 50 μm, it is likely to be difficult to form a conductor layer in the through hole. Also, the self-inductance increases.
If it exceeds 500 μm, the self-inductance component per line is reduced, but the number of ground lines and power lines that can be arranged in a limited area is reduced, and the total number of ground lines and power lines is increased by multi-wires. Cannot be reduced. This is because, in particular, when the electrodes are arranged in a lattice or in a zigzag pattern, problems such as short circuits may occur depending on the pitch of the through holes. That is, it is difficult to form the through hole itself.
More desirably, it is formed between 75 and 485 μm. In the meantime, the self-inductance can be reduced, and by increasing the number of wirings, the overall inductance can be reduced and the electrical characteristics can be improved. Further, the pitch of the through holes can be reduced.
[0033]
It is desirable that the through holes have an all-layer stack structure from one or more directly above the through holes or from the lands of the through holes to the outermost layer. It is desirable to form it right above the through hole. The connection of the through-hole is such that a land having a lid structure is formed on the through-hole by lid plating or the like, and a via-on-through hole in which via holes are formed in a stack on the land is an IC chip. This is because the distance from the terminal to the external terminal or the capacitor becomes a straight line, the shortest distance is obtained, and the inductance can be further reduced. In this case, it is more desirable to form a through hole for GND and a through hole for VCC on a lattice or staggered. Ideally, all four of the through holes arranged in a lattice or in a staggered pattern have a stack structure.
[0034]
It is desirable that the through hole for the grant and the through hole for the power supply be disposed immediately below the IC chip.
By arranging the IC immediately below the IC chip, the distance between the IC and an external terminal or a capacitor can be shortened, and the inductance can be reduced.
[0035]
In this case, the core substrate is a resin substrate impregnated with a core material such as a glass epoxy resin, a ceramic substrate, a metal substrate, a composite core substrate using a composite of resin, ceramic and metal, and an inner layer of these substrates (power supply For example, a substrate provided with a conductor layer and a multilayer core substrate formed with three or more multilayered conductor layers can be used.
In order to increase the thickness of the conductor of the power supply layer, on a substrate in which a metal is embedded, plating, a method formed by a printed wiring board method of forming a conductor layer which is generally performed such as sputtering may be used. Good.
[0036]
In the case of a multi-layer core substrate, the thickness of the core conductor layer is the sum of the outer and inner conductor layers of the core substrate. In other words, even if the number of layers is increased, it is essential to increase the thickness of the conductor layer of the core substrate, and the effect itself does not change at all.
In this case, a core substrate composed of three layers (outer layer + inner layer) may be used.
If necessary, an electronic component storage core substrate formed by embedding components such as a capacitor, a dielectric layer, and a resistor in the inner layer of the core substrate may be used. The insulating material of the core may be a dielectric material.
[0037]
The core substrate in the present invention is defined as follows. A hard base material impregnated with a core material or the like, on both surfaces or one surface thereof, using an insulating resin layer not containing a core material or the like, forming a via hole by a photo via or a laser, forming a conductor layer, This is for making electrical connection between layers. Relatively, the thickness of the core substrate is larger than the thickness of the resin insulating layer. Basically, the core substrate is formed with a conductor layer mainly including a power supply layer, and other signal lines and the like are formed only for making front and back connection.
[0038]
In the case of a multilayer printed wiring board formed of materials having the same thickness, a layer or a substrate having a power supply layer as a conductor layer in the printed board is defined as a core board.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
First Embodiment A multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIGS.
[First Embodiment-1] Four-layer multilayer core substrate
First, the configuration of the multilayer printed wiring board 10 according to the first embodiment will be described with reference to FIGS. FIG. 8 is a cross-sectional view of the multilayer printed wiring board 10, and FIG. 9 shows a state in which an IC chip 90 is mounted on the multilayer printed wiring board 10 shown in FIG. As shown in FIG. 8, the multilayer printed wiring board 10 uses a multilayer core substrate 30. The conductor circuit 34 and the conductor layer 34P are formed on the front side of the multilayer core substrate 30, and the conductor circuit 34 and the conductor layer 34E are formed on the back side. The upper conductor layer 34P is formed as a power supply plane layer, and the lower conductor layer 34E is formed as a ground plane layer. Further, the inner conductor layer 16E is formed on the inner surface side of the multilayer core substrate 30, and the conductor layer 16P is formed on the back surface. The upper conductor layer 16E is formed as a ground plane layer, and the lower conductor layer 16P is formed as a power supply plane layer. The connection to the power supply plane layers 34P and 16P is made by power supply through holes 36P and via holes. The connection to the ground plane layers 34E and 16P is made by ground through holes 36E and via holes. Signal connection between the upper and lower sides of the multilayer core substrate 30 is performed by signal through holes 36S and via holes. The plane layer may be a single layer on only one side or a layer arranged in two or more layers. It is desirable to form two to four layers. No improvement in electrical characteristics has been confirmed with four or more layers, so even with more layers, the effect is about the same as with four layers. Particularly, in the case where the multilayer core substrate is formed in two layers, the elongation ratio of the substrate is uniform in terms of rigidity matching of the multilayer core substrate, and therefore, it is difficult for the substrate to be warped. An electrically isolated metal plate 12 is accommodated in the center of the multilayer core substrate 30 (the metal plate 12 also serves as a core material, but any electrical connection such as a through-hole or a via-hole is required). This is mainly because the rigidity against warpage of the substrate is improved). The metal plate 12 has an inner conductor layer 16E on the front side via the insulating resin layer 14, a conductor layer 16P on the back side, and a conductor circuit 34 and a conductor layer 34P on the front side via the insulating resin layer 18. On the back surface, a conductor circuit 34 and a conductor layer 34E are formed. A multilayer core substrate without the metal plate 12 can also be used (see FIGS. 14 and 15).
[0040]
On the conductor layers 34P and 34E on the surface of the multilayer core substrate 30, the interlayer resin insulation layer 50 with the via hole 60 and the conductor circuit 58 formed thereon and the interlayer resin insulation layer with the via hole 160 and the conductor circuit 158 formed thereon 150 are provided. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 </ b> U and 76 </ b> D are formed in the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.
[0041]
As shown in FIG. 9, the bumps 76U on the upper surface of the multilayer printed wiring board 10 are connected to the signal lands 92S, the power lands 92P, and the ground lands 92E of the IC chip 90. Further, a chip capacitor 98 is mounted. On the other hand, the lower external terminal 76D is connected to the signal land 96S, the power supply land 96P, and the ground land 96E of the daughter board 94. The external terminals in this case indicate PGA, BGA, solder bumps, and the like.
[0042]
Here, as shown in FIG. 8, the distance D1 between the conductor layer 34P on the surface of the multilayer core substrate 30 and the inner conductor layer 16E and the distance D3 between the conductor layer 34P on the inner layer and the conductor layer 34E on the back surface are made uniform. ing. By arranging the conductor layers so that the distance between the conductor layers is uniform, the mutual inductance between the conductor layers can be kept constant, and the entire inductance of the core substrate can be reduced. Therefore, the ability to supply power to the IC chip 90 can be improved by using the conductor layers 34P and 16P as the power supply layer. In addition, by using the conductor layers 34E and 16E as ground layers, it is possible to reduce noise to be superimposed on a signal to the IC chip 90 and a power supply. That is, the reduction of the inductance of the conductor layer does not hinder the power supply. Therefore, when the IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the multilayer printed wiring board to the power supply can be reduced. Therefore, power shortage during the initial operation is reduced, and power shortage is unlikely to occur. Therefore, even if an IC chip in a high frequency region is mounted, a malfunction or an error in the initial startup does not occur. The core substrate has a multilayer structure in which the power supply layer and the ground layer are each two layers.
[0043]
It is desirable that the distances D1 and D3 between the conductor layers of the multilayer core substrate 30 be 15 to 300 μm. If it is less than 15 μm, it is difficult to maintain insulation. If it exceeds 300 μm, the effect of reducing the inductance between the conductor layers is offset, and the thickness of the multilayer core substrate becomes thicker, the through hole becomes longer, and the through hole becomes longer. This is because the inductance at the point increases. As an example, the distance between the conductor layers was formed at 220 μm.
[0044]
FIG. 10 shows a cross section XX of the multilayer printed wiring board 10 of FIG. That is, FIG. 10 shows a cross section of the multilayer core substrate 30. In the figure, for convenience of understanding, the power supply through-hole 36P is marked with an upward mark (black circle in the center in the figure), and the ground through-hole 36E is marked with a downward mark (+ in the figure). No mark is provided on the through hole 36S. FIG. 11A is an explanatory diagram showing a part indicated by a dotted line I in FIG. 10A in an enlarged manner. In the first embodiment, the power supply through-holes 36P and the ground through-holes 36E are arranged in a grid at adjacent positions. That is, the ground (or power supply) is arranged at diagonal positions, and the power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force in the X direction and the Y direction is canceled.
[0045]
In the through holes arranged in a lattice as described above with reference to FIG. 11A, power supply through holes 36P (VCC1, VCC2) are arranged at equal intervals of the ground through holes 36E (GND1). Then, the ground through hole 36E (GND2) is arranged on the diagonal line of GND1. With this four-core (quad) structure, two GNDs (or GNDs) cancel out induced electromotive force for one GND (or VCC). Therefore, the mutual inductance can be reduced, and the influence of noise can be reduced because there is no influence of the induced electromotive force. Furthermore, by reducing the inductance, the IC chip whose power consumption increases and decreases intermittently can be reduced. Therefore, no voltage drop occurs even when the power consumption increases, and malfunctions and delays are less likely to occur.
[0046]
Further, as shown in FIG. 8, the power supply through-hole 36P and the ground through-hole 36E arranged at the center of the multilayer core substrate 30 have a stacked structure in which the via hole 60 and the via hole 160 are provided immediately above the through hole. Has become. The connection between the through holes 36E and 36P and the via holes 60 is performed by forming lands 25 having a lid structure on the through holes 36E and 36P by lid plating or the like, and forming the via holes 60 thereon in a stack. You. Further, a via hole 160 is provided immediately above the upper via hole 60, and the via hole 160 is connected to the power supply land 92E and the ground land 92E of the IC chip 90 via the bump 76U. Similarly, a via hole 160 is provided immediately below the lower via hole 60, and the via hole 160 is connected to the power supply land 96P and the ground land 96E of the daughter board 94 via the bump 76D.
[0047]
This is because the via-through-hole and the stacked structure form a straight line from the IC chip 90 to the bumps (external terminals) 76E and 76P of the daughter board or a capacitor (not shown), so that the distance becomes the shortest and the inductance can be further reduced. . In this case, ideally, all four locations of the through holes arranged in a lattice form have a stack structure.
[0048]
The distance (pitch) between the through holes 36E, 36P, and 36S was set to 60 to 600 μm, and the signal through hole diameter 36S (outer diameter) was formed to 50 to 500 μm. The distance (pitch) between the ground through-hole 36E and the power supply through-hole 36P is set to 60 to 600 μm, the diameter (outer diameter) of the ground through-hole 36E is 50 to 500 μm, and the diameter of the power supply through-hole 36P is It was formed in a thickness of 50 to 500 μm. The through holes 36E, 36P, and 36S formed the conductor layers of the through holes formed in the core substrate 30, and the gaps were filled with an insulating resin. In addition, the inside of the through hole may be completely filled with a conductive paste or plating.
[0049]
The through hole 36 </ b> E for the grant and the through hole 36 </ b> P for the power supply are disposed directly below the IC chip 90. By disposing the IC 90 directly below the IC chip 90, the distance between the IC 90 and the bumps (external terminals) 96E and 96P of the daughter board 94 or a capacitor (not shown) can be reduced. Therefore, the inductance can be reduced.
[0050]
Here, the conductor layers 34P and 34E of the surface layer of the core substrate 30 are formed to have a thickness of 5 to 300 μm, the conductor layers 16P and 16E of the inner layer are formed to have a thickness of 5 to 300 μm. The conductor 58 on the circuit 58 and the interlayer resin insulation layer 150 is formed to have a thickness of 5 to 25 μm.
[0051]
In the multilayer printed wiring board of the first embodiment, the power supply layer (conductor layer) 34P, the conductor layer 34, the power supply layer (conductor layer) 16P of the inner layer, the conductor layer 16E, and the metal plate 12 of the core substrate 30 are thickened. This increases the strength of the core substrate. As a result, even if the core substrate itself is thinned, warpage and the generated stress can be reduced by the substrate itself.
[0052]
Further, by increasing the thickness of the conductor layers 34P and 34E and the conductor layers 16P and 16E, the volume of the conductor itself can be increased. By increasing the volume, the resistance of the conductor can be reduced.
[0053]
Furthermore, by mounting the capacitor 98, the power stored in the capacitor can be used in an auxiliary manner, so that power shortage is less likely to occur.
[0054]
In the first embodiment, the multilayer core substrate 30 has the thick conductor layers 16P and 16E on the inner layer and the thin conductor layers 34P and 34E on the surface, and the inner conductor layers 16P and 16E and the conductor layers 34P and 34E on the surface. Are used as a conductor layer for the power supply layer and a conductor layer for the ground. That is, even if the thick conductor layers 16P and 16E are arranged on the inner layer side, the resin layer covering the conductor layer is formed. Therefore, the surface of the multilayer core substrate 30 can be made flat by offsetting the unevenness due to the conductor layer. For this reason, even if the thin conductor layers 34P and 34E are arranged on the surface of the multilayer core substrate 30 so that the conductor layers 58 and 158 of the interlayer insulating layers 50 and 150 do not undulate, the inner conductor layers 16P and 16E With the added thickness, a sufficient thickness for the conductor layer of the core can be secured. Since no undulation occurs, no problem occurs in the impedance of the conductor layer on the interlayer insulating layer. By using the conductor layers 16P and 34P as conductor layers for the power supply layer and the conductor layers 16E and 34E as conductor layers for the ground, it becomes possible to improve the electrical characteristics of the multilayer printed wiring board.
[0055]
That is, the thickness of the conductor layers 16P and 16E of the inner layer of the core substrate is made larger than the conductor layers 58 and 158 on the interlayer insulating layers 50 and 150. Accordingly, even when the thin conductor layers 34E and 34P are arranged on the surface of the multilayer core substrate 30, a sufficient thickness can be secured as the core conductor layer by adding the inner conductor layers 16P and 16E. The ratio is desirably 1 <(total thickness of conductor layers of core substrate / conductor layer of interlayer insulating layer) ≦ 40. More preferably, 1.2 ≦ (total thickness of conductor layers of core substrate / conductor layer of interlayer insulating layer) ≦ 20. Further, in this case, it is desirable that the ratio of the total of the conductor layers serving as the power supply layer of the core substrate to the conductor layer of the interlayer resin insulating layer has the above relationship. That is, it is desirable that 1 <(total thickness of power supply conductor layers of core substrate / conductor layer of interlayer insulating layer) ≦ 40. More preferably, 1.2 ≦ (total thickness of power supply conductor layers of core substrate / conductor layer of interlayer insulating layer) ≦ 20. As a result, the inductance can be reduced, and a malfunction of the IC chip is hardly caused.
[0056]
The multilayer core substrate 30 has an inner conductor layer 16P, 16E with a resin layer 14 interposed on both surfaces of the electrically isolated metal plate 12, and a resin layer on the outer side of the inner conductor layer 16P, 16E. The conductor layers 34P and 34E on the front surface are formed with the intermediary 18 interposed therebetween. By arranging the electrically isolated metal plate 12 at the center, sufficient mechanical strength can be ensured. Further, the inner conductor layers 16P and 16E are provided on both surfaces of the metal plate 12 with the resin layer 14 interposed therebetween, and the outer conductor layers 34P and 16P are provided on the outer surfaces of the inner conductor layers 16P and 16E with the resin layer 18 interposed therebetween. By forming the 34E, the metal plate 12 is provided with symmetry on both sides, and it is possible to prevent the occurrence of warpage and undulation in a heat cycle or the like.
[0057]
FIG. 10B shows a through-hole arrangement according to a modification of the first embodiment. FIG. 11B is an explanatory diagram showing a part indicated by a dotted line II in FIG. 10B in an enlarged manner. In a modification of the first embodiment, the power supply through-holes 36P and the ground through-holes 36E are arranged in a staggered manner at adjacent positions. That is, the ground (or power supply) is arranged at diagonal positions, and the power supply (or ground) is arranged at other positions. With this configuration, the induced electromotive force in the X direction and the Y direction is canceled.
[0058]
That is, as described above with reference to FIG. 11B, in the through holes 36P and 36E arranged in a zigzag pattern, GND2 and GND3 are arranged at equal intervals of GND1 so that GND2 and GND3 have the same distance. VCC1 and VCC2 are provided. With this structure, two GNDs (or GNDs) cancel out the induced electromotive force for one GND (or VCC). For this reason, the mutual inductance can be reduced, and there is no influence of the induced electromotive force, so that a malfunction or a delay hardly occurs.
[0059]
Subsequently, a method of manufacturing the multilayer printed wiring board 10 shown in FIG. 8 will be described with reference to FIGS.
(1) Formation of metal layer
An opening 12a is formed in the inner metal layer (metal plate) 12 having a thickness of 50 to 400 μm shown in FIG. 1A (see FIG. 1B). As a material of the metal layer, a material containing a metal such as copper, nickel, zinc, aluminum, and iron can be used. The opening 12a is formed by punching, etching, drilling, laser or the like. In some cases, the entire surface of the metal layer 12 in which the opening 12a is formed may be covered with the metal film 13 by electrolytic plating, electroless plating, displacement plating, or sputtering (FIG. 1C). In addition, the metal plate 12 may be a single layer or a multilayer of two or more layers. It is desirable that the metal film 13 has a curved surface. As a result, there is no point at which stress concentrates, and defects such as cracks around the point hardly occur.
[0060]
(2) Formation of inner insulating layer
An insulating resin is used to cover the entire metal layer 12 and fill the opening 12a. As a forming method, for example, an insulating resin layer 14 can be formed by sandwiching a B-stage resin film having a thickness of about 30 to 200 μm with a metal plate 12, thermocompression bonding, and then curing (FIG. 1D )). Depending on the case, application, a mixture of application and film press bonding, or application of only the unopened area may be followed by film formation.
As a material, it is desirable to use a prepreg in which a core material such as a glass cloth is impregnated with a thermosetting resin such as a polyimide resin, an epoxy resin, a phenol resin, and a BT resin. In addition, a resin may be used.
[0061]
(3) Pasting of metal foil
An inner metal layer 16α is formed on both surfaces of the metal layer 12 covered with the resin layer 14 (FIG. 1E). As an example, a metal foil having a thickness of 12 to 350 μm was laminated. As a method other than forming a metal foil, a single-sided copper-clad laminate is laminated. It is formed on a metal foil by plating or the like.
[0062]
(4) Circuit formation of inner metal layer
Two or more layers may be used. The metal layer may be formed by an additive method.
The inner conductor layers 16P and 16E were formed from the inner metal layer 16α through a tenting method, an etching step, and the like (FIG. 1F). At this time, the thickness of the inner conductor layer was 5 to 300 μm. The metal layer may be formed of a copper foil or the like which has been processed in advance to open a region where a through hole is to be formed.
[0063]
(5) Formation of outer insulating layer
An insulating resin is used to cover the entire inner conductor layers 16P and 16E and to fill the gap between the outer metal layers and its circuits. As a forming method, for example, a B-stage resin film having a thickness of about 25 to 200 μm is sandwiched between metal plates, thermocompression-bonded, and then cured to form an outer insulating resin layer 18 (FIG. 2A). . Depending on the case, you may form with a film, after apply | coating, the mixture of application and film press bonding, or apply | coating only an opening part. The surface can be flattened by pressing.
[0064]
(6) Pasting the outermost metal foil
The outermost metal layer 34α is formed on both surfaces of the substrate covered with the outer insulating resin layer 18 (FIG. 2B). As an example, a metal foil having a thickness of 12 to 350 μm is laminated. As a method other than forming a metal foil, a single-sided copper-clad laminate is laminated. Two or more layers may be formed on the metal foil by plating or the like. The metal layer may be formed by an additive method. At this time, the thickness of the outermost metal layer 34α is desirably formed between 5 and 300 μm.
[0065]
(7) Through-hole formation
A through hole 36α having an opening diameter of 50 to 400 μm penetrating the front and back of the substrate is formed (FIG. 2C). As a forming method, it is formed by a drill, a laser or a combination of a laser and a drill (an opening in the outermost insulating layer is made with a laser, and in some cases, the opening with the laser is used as a target mark, and then a drill is made. Open and penetrate). The shape is desirably one having straight side walls. In some cases, it may be tapered.
[0066]
In order to secure the conductivity of the through-hole, the plating film 22 is formed (formed by electroless plating, electrolytic plating, or the like) in the through-hole 36α, and the surface is roughened (FIG. 2D). ), It is desirable to fill the filling resin 23 (FIG. 2E). As the filling resin, electrically insulated resin materials (for example, those containing a resin component, a curing agent, particles, and the like), and conductive materials for electrically connecting metal particles (for example, One containing metal particles such as gold and copper, a resin material, a curing agent, etc.).
As plating, electrolytic plating, electroless plating, panel plating (electroless plating and electrolytic plating) and the like can be used. As a metal, it is formed by containing copper, nickel, cobalt, phosphorus, and the like. It is desirable that the thickness of the plating metal is formed between 5 and 30 μm.
[0067]
As the filling resin 23 filled in the through-hole 36α, it is desirable to use an insulating material made of a resin material, a curing agent, particles and the like. As the particles, inorganic particles such as silica and alumina, metal particles such as gold, silver and copper, resin particles and the like may be used alone or in combination. Particles having a particle diameter of 0.1 to 5 μm having the same diameter or a mixture having a composite diameter can be used. The resin material may be a single or a mixture of an epoxy resin (for example, a bisphenol-type epoxy resin, a novolak-type epoxy resin, etc.), a thermosetting resin such as a phenolic resin, a photosensitive ultraviolet-curing resin, and a thermoplastic resin. Can be used. As the curing agent, an imidazole-based curing agent, an amine-based curing agent, or the like can be used. In addition, a curing stabilizer, a reaction stabilizer, particles and the like may be contained. A conductive material may be used. In this case, a conductive paste composed of metal particles, a resin component, a curing agent, and the like is a conductive material. In some cases, a conductive metal film formed on a surface layer of an insulating material such as solder or insulating resin may be used. It is also possible to fill the through holes 36α with plating. This is because the conductive paste undergoes hardening and shrinkage, and may form a concave portion in the surface layer.
[0068]
(8) Formation of outermost conductive circuit
The cover plating 25 may be formed just above the through holes 36S, 36E, and 36P by covering the entire surface with a plating film (FIG. 3A). Thereafter, through a tenting method, an etching step, and the like, outer conductor circuits 34, 34P, and 34E are formed (FIG. 3B). Thus, the multilayer core substrate 30 is completed.
At this time, although not shown, the electrical connection with the inner conductor layers 16P, 16E and the like of the multilayer core substrate may be made by via holes, blind through holes, and blind via holes. At this time, it is preferable that the thickness of the multilayer core substrate is formed between 500 μm and 800 μm. In this case, it was formed at 700 μm.
[0069]
(9) The multilayer core substrate 30 on which the conductor circuit 34 is formed is subjected to a blackening process and a reduction process to form a roughened surface 34β on all surfaces of the conductor circuit 34 and the conductor layers 34P and 34E (FIG. 3 (C)). )).
[0070]
(10) A layer of the resin filler 40 is formed in a portion of the multilayer core substrate 30 where no conductor circuit is formed (FIG. 4A).
[0071]
(11) Polishing one surface of the substrate after the above-described processing by polishing with a belt sander or the like so that the resin filler 40 does not remain on the outer edges of the conductor layers 34P and 34E, and then removing scratches due to the polishing. Then, the entire surfaces (including the land surfaces of the through holes) of the conductor layers 34P and 34E were further polished with a buff or the like. Such a series of polishing was similarly performed on the other surface of the substrate. Next, heat treatment was performed at 100 ° C. for 1 hour and at 150 ° C. for 1 hour to cure the resin filler 40 (FIG. 4B).
Note that the resin filling between the conductor circuits may not be performed. In this case, an insulating layer is formed with a resin layer such as an interlayer insulating layer, and filling between conductive circuits is performed.
[0072]
(12) An etching solution is sprayed on both surfaces of the multilayer core substrate 30 by spraying to etch the surfaces of the conductor circuits 34, the conductor layers 34P and 34E, and the land surfaces and inner walls of the through holes 36S, 36E and 36P. Thus, a roughened surface 36 was formed on the entire surface of the conductor circuit (FIG. 4C).
[0073]
(13) On both surfaces of the multilayer core substrate 30, a resin film for an interlayer resin insulating layer 50 is placed on the substrate, temporarily compressed and cut, and then adhered using a vacuum laminator device to form an interlayer resin. An insulating layer was formed (FIG. 5A).
[0074]
At this time, a thermosetting resin, a thermoplastic resin, a photosensitive resin, or a resin composite thereof (for example, a resin composite of a thermosetting resin and a thermoplastic resin) is used as the resin film for the interlayer resin insulating layer. Can be used. As the thermosetting resin, an epoxy resin, a polyimide resin, a phenol resin, or the like can be used. Phenoxy resin, polyether sulfone (PES), or the like can be used as the thermoplastic resin. As the photosensitive resin, a resin mixed with a (meth) acryl group can be used. In addition to the resin, if necessary, a hardening agent, resin, inorganic, metal, etc. particles having a particle size of about 0.1 μm to 20 μm, a reaction stabilizer, and the like are added.
[0075]
(14) Next, through a mask in which a through hole having a thickness of 1.2 mm was formed on the interlayer resin insulating layer, a CO2 gas laser having a wavelength of 10.4 μm was used, and a beam diameter of 4.0 mm, a top hat mode, A via hole opening 50a having a diameter of 80 μm was formed in the interlayer resin insulating layer 50 under the conditions of a pulse width of 7.9 μs, a diameter of the through hole of the mask of 1.0 mm, and one shot (FIG. 5B).
[0076]
(15) A roughened layer is provided on the surface of the multilayer core substrate 30. As the roughening solution, an acid such as sulfuric acid or acetic acid or an oxidizing agent such as chromic acid or permanganic acid can be used. As an example, the multilayer core substrate 30 is immersed in a solution containing 60 g / l of permanganic acid at 80 ° C. for 10 minutes, and the surface of the interlayer resin insulating layer 50 including the inner wall of the via hole opening 50 a is roughened 50α. Was formed (FIG. 4C). The roughened surface was formed between 0.1 and 5 μm.
[0077]
(16) Next, the multilayer core substrate 30 after the above treatment was immersed in a neutralizing solution (manufactured by Shipley) and washed with water. Further, a catalyst such as palladium is applied to the surface of the substrate which has been subjected to the surface roughening treatment (roughening depth: 3 μm), so that catalyst nuclei adhere to the surface of the interlayer resin insulating layer and the inner wall surface of the via hole opening. Was.
[0078]
(17) Next, the substrate provided with the catalyst is immersed in an aqueous electroless copper plating solution to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm on the entire rough surface. A substrate having the electroless copper plating film 52 formed on the surface of the interlayer resin insulating layer 50 including the inner wall of the opening 50a is obtained (FIG. 4D).
[0079]
(18) A commercially available photosensitive dry film was attached to the substrate on which the electroless copper plating film 52 was formed, a mask was placed, and development was performed to provide a plating resist 54 (FIG. 6A). . The thickness of the plating resist was between 10 and 30 μm.
[0080]
(19) Then, the multilayer core substrate 30 was subjected to electrolytic plating, and an electrolytic copper plating film 56 having a thickness of 7 to 25 μm was formed in the portion where the plating resist 54 was not formed (FIG. 6B).
[0081]
(20) Further, after the plating resist is stripped and removed with about 5% KOH, the electroless plating film under the plating resist is etched and dissolved and removed with a mixed solution of sulfuric acid and hydrogen peroxide to form an independent conductor. A circuit 58 and a via hole (filled via hole) 60 were formed (FIG. 6C).
[0082]
(21) Then, the same processing as in the above (12) was performed to form roughened surfaces 58α and 60α on the surfaces of the conductor circuit 58 and the via hole 60. The thickness of the upper conductive circuit 58 was 5 to 25 μm. The thickness this time was 15 μm (FIG. 6D).
[0083]
(22) By repeating the above steps (14) to (21), an upper interlayer resin insulation layer 150, a conductor circuit 158, and a via hole 160 are further formed to obtain a multilayer wiring board (FIG. 7A). ).
[0084]
(23) Next, the solder resist composition 70 is applied on both surfaces of the multilayer wiring board at a thickness of 12 to 30 μm, and dried at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes ( (FIG. 7B), a 5 mm-thick photomask on which a pattern of the solder resist opening is drawn is brought into close contact with the solder resist layer 70 to be 1000 mJ / cm. ² And developed with a DMTG solution to form an opening 71 having a diameter of 200 μm (FIG. 7C).
Further, the solder resist layer 70 is cured by performing heat treatment at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours. A solder resist pattern layer 70 having a thickness of 10 to 25 μm was formed. Further, a commercially available film type may be used for the solder resist layer.
[0085]
(24) Next, the substrate on which the solder resist layer 70 was formed was immersed in an electroless nickel plating solution to form a nickel plating layer 72 having a thickness of 5 μm in the opening 71. Further, the substrate was immersed in an electroless gold plating solution to form a 0.03 μm-thick gold plating layer 74 on the nickel plating layer 72 (FIG. 7D). In addition to the nickel-gold layer, a single layer of tin or a noble metal layer (such as gold, silver, palladium, or platinum) may be formed.
[0086]
(25) After that, a solder paste containing tin-lead is printed on the opening 71 of the solder resist layer 70 on the surface of the substrate on which the IC chip is mounted, and tin-lead is further printed on the opening of the solder resist layer on the other surface. After printing a solder paste or the like containing antimony, external terminals were formed by reflow at 200 ° C. to manufacture a multilayer printed wiring board having solder bumps 76U and 76D (FIG. 8).
[0087]
[First Example-2]
This is the same as the first embodiment, except that the distance between the conductors of the surface layer and the inner layer is 300 μm.
[0088]
[First Example-3]
This is the same as the first embodiment, except that the distance between the conductors of the surface layer and the inner layer is 100 μm.
[0089]
[First Example-4]
It is the same as the first embodiment, except that the distance between the conductors of the surface layer and the inner layer is 30 μm.
[0090]
[First Example-5]
This is the same as the first embodiment, except that the distance between the conductors of the surface layer and the inner layer is 15 μm.
[0091]
[Second Embodiment-1] Three-layer multilayer core substrate
A multilayer printed wiring board according to a second embodiment will be described with reference to FIG.
In the first embodiment described above with reference to FIG. 8, the core substrate is formed of four layers (the ground layers 16E and 34E: 2, the power layers 16P and 34P: 2). On the other hand, in the second embodiment, as shown in FIG. 12, the multilayer core substrate 30 is formed of three layers (the ground layers 34E, 34E: 2, and the power supply layer 15P: 1).
[0092]
As shown in FIG. 12, in the multilayer printed wiring board 10 according to the second embodiment, a conductor circuit 34 and a ground conductor layer 34 </ b> E are formed on the front and back surfaces of a multilayer core substrate 30, and a power supply conductor is provided in the core substrate 30. The layer 15P is formed. The ground conductor layer 34E is formed as a ground plane layer, and the power supply conductor layer 15P is formed as a power supply plane layer. The ground through hole 36E is connected to the ground conductor layer 34E on both sides of the core substrate, and the power supply through hole 36P is connected to the power supply conductor layer 15P at the center of the core substrate. The signals are connected on both surfaces of the multilayer core substrate 30 via the signal line through holes 36S. The interlayer resin insulation layer 50 having the via hole 60 and the conductor circuit 58 formed thereon and the interlayer resin insulation layer 150 having the via hole 160 and the conductor circuit 158 formed thereon are arranged on the ground conductor layer 34E. A solder resist layer 70 is formed on the via hole 160 and the conductor circuit 158, and bumps 76 </ b> U and 76 </ b> D are formed in the via hole 160 and the conductor circuit 158 through the opening 71 of the solder resist layer 70. ing.
[0093]
Here, the distance D8 between the conductor layer 34E on the front surface of the multilayer core substrate 30 and the inner conductor layer 15P is the same as the distance D9 between the conductor layer 15P on the inner layer and the conductor layer 34E on the back surface. The distance at this time was formed between 15 and 300 μm. In this case, as an example, it was formed at 300 μm. By arranging the conductor layers so that the distance between them is uniform, the mutual inductance between the conductor layers is kept constant, and the overall inductance is reduced. Therefore, the ability to supply power to the IC chip 90 can be improved by using the conductor layer 15P as a power supply layer. Further, by using the conductor layer 34E as a ground layer, it is possible to reduce noise to be superimposed on a signal to the IC chip 90 and a power supply. That is, the reduction of the inductance of the conductor layer does not hinder the power supply. Therefore, when the IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the multilayer printed wiring board to the power supply can be reduced. Therefore, power shortage during the initial operation is reduced, and power shortage is unlikely to occur. Therefore, even if an IC chip in a high frequency region is mounted, a malfunction or an error in the initial startup does not occur.
[0094]
Also in the second embodiment, as in the first embodiment described above with reference to FIGS. 10A and 10B, the power supply through-hole 36E and the ground through-hole 36E are formed in a lattice or They are arranged in a staggered manner to reduce mutual inductance.
[0095]
Here, the conductor circuit 34 and the conductor layer 34E are formed on the core substrate 30, and the conductor layer 15P is formed in the core substrate. On the other hand, the conductor circuit 58 is formed on the interlayer resin insulation layer 50 and the conductor circuit 158 is formed on the interlayer resin insulation layer 150. The thickness of the conductor layer 34E on the core substrate is formed between 5 and 300 μm, and the thickness of the conductor layer 15P serving as a power supply layer formed in the core substrate is formed between 5 and 300 μm. I have. The thickness of the conductor layer in this case is the sum of the thicknesses of the power supply layers of the core substrate. This means that both the conductor layer 15P as the inner layer and the conductor layer 34E as the surface layer are added. It doesn't add up to what plays the role of signal line. Also in the second embodiment, the same effect as in the first embodiment can be obtained by adjusting the thicknesses of the three conductor layers 34E and 15P. The thickness of the power supply layer may exceed the above range.
[0096]
[Modification of Second Embodiment]
FIG. 13 shows a cross section of a multilayer printed wiring board according to a modification of the second embodiment. In the second embodiment described above with reference to FIG. 12, the multilayer core substrate 30 is formed of three layers (the ground layers 34E, 34E: 2 and the power supply layer 15P: 1). In a modification of the embodiment, the multilayer core substrate 30 is formed of three layers (the ground layer 15E: 1 and the power supply layers 34P and 34P: 2).
[0097]
[Second embodiment-2]
The second embodiment is the same as the first embodiment, except that the distance between the conductors of the surface layer and the inner layer is 250 μm.
[0098]
[Second embodiment-3]
The second embodiment is the same as the first embodiment, except that the distance between the conductors of the surface layer and the inner layer is 100 μm.
[0099]
[Second embodiment-4]
It is the same as the second embodiment-1, except that the distance between the conductors of the surface layer and the inner layer is 30 μm.
[0100]
[Second Example-5]
This is the same as the second embodiment-1, except that the distance between the conductors of the surface layer and the inner layer is 15 μm.
[0101]
[Third Example-1]
FIG. 14 shows a multilayer printed wiring board according to the third embodiment. The multilayer printed wiring board of the third embodiment was formed by the same manufacturing method as that of the second embodiment-1. In the third embodiment, similarly to the first embodiment, the conductor circuit 34 and the conductor layer 34P are formed on the front surface side of the multilayer core substrate 30, and the conductor circuit 34 and the conductor layer 34E are formed on the back surface. The upper conductor layer 34P is formed as a power supply plane layer, and the lower conductor layer 34E is formed as a ground plane layer. Further, the inner conductor layer 16E is formed on the inner surface side of the multilayer core substrate 30, and the conductor layer 16P is formed on the back surface. The upper conductor layer 16E is formed as a ground plane layer, and the lower conductor layer 16P is formed as a power supply plane layer. In the third embodiment, the distances S1, S2, S3 between all the conductor layers 34P, 16E, 16P, 34E are uniform. It follows that S1 = S2 = S3. As one example, a conductor circuit having a distance of 300 μm was formed.
[0102]
[Third Example-2]
This is the same as the third embodiment-1, except that the distance between the conductors of the surface layer and the inner layer is 200 μm.
[0103]
[Third Example-3]
This is the same as the third embodiment-1, except that the distance between the conductors of the surface layer and the inner layer is 100 μm.
[0104]
[Third embodiment-4]
This is the same as the third embodiment-1, except that the distance between the conductors of the surface layer conductor circuit and the inner layer conductor circuit is 25 μm.
[0105]
[Third Example-5]
The third embodiment is the same as the first embodiment, except that the distance between the conductors of the surface layer and the inner layer is 15 μm.
[0106]
[Fourth embodiment]
FIG. 15 shows a fourth embodiment. In the first embodiment described above with reference to FIG. 8, the metal plate 12 is arranged at the center of the multilayer core substrate 30. On the other hand, in the fourth embodiment, a resin or ceramic core material 13 is disposed at the center of the multilayer core substrate 30. In the fourth embodiment, the capacitor 98 is disposed immediately below the IC chip 90, and the conductive connection pins 99 are attached to the lower surface. Since the capacitor 98 is disposed immediately below the IC chip 90, the effect of making the power shortage unlikely to occur is remarkable. This is because the wiring length on the multilayer printed wiring board can be shortened immediately below the IC chip.
[0107]
Here, the distance D5 between the conductor layer 34P on the front surface of the multilayer core substrate 30 and the inner conductor layer 16E, the distance D6 between the conductor layer 16E and the conductor layer 16P, the conductor layer 16P on the inner layer and the conductor layer 34E on the back surface. Is made uniform. By arranging the conductor layers so that the distance between them is uniform, the mutual inductance between the conductor layers is kept constant, and the overall inductance is reduced. Therefore, the ability to supply power to the IC chip 90 can be improved by using the conductor layers 34P and 16P as the power supply layer. In addition, by using the conductor layers 34E and 16E as ground layers, it is possible to reduce noise to be superimposed on a signal to the IC chip 90 and a power supply. That is, the reduction of the inductance of the conductor layer does not hinder the power supply. Therefore, when the IC chip is mounted on the multilayer printed board, the loop inductance from the IC chip to the multilayer printed wiring board to the power supply can be reduced. Therefore, power shortage during the initial operation is reduced, and power shortage is unlikely to occur. Therefore, even if an IC chip in a high frequency region is mounted, a malfunction or an error in the initial startup does not occur.
[0108]
It is desirable that the distances D5, D6, D7 between the conductor layers of the multilayer core substrate 30 be 15 to 300 μm. If the thickness is 15 μm or less, it is difficult to maintain insulation. If the thickness is 300 μm or more, the thickness of the multilayer core substrate becomes large, the through hole becomes long, and the inductance in the through hole increases.
[0109]
[Comparative Example 1]
A printed wiring board (800 μm in thickness of a core substrate) having conductor circuits arranged on both sides (surfaces) according to the conventional technique described above with reference to FIG.
[0110]
[Comparative Example 2]
Same as the first embodiment-1, except that the distance between the conductor circuit on one side (front side) and the conductor circuit on the inner layer is 300 μm, and the distance between the conductor circuit on the opposite side (rear side) and the conductor circuit on the inner layer is Was set to 350 μm.
[0111]
[Reference Example 1]
This is the same as the first embodiment-1, except that the distance between the conductors of the surface layer and the inner layer is 350 μm.
[0112]
[Reference Example 2]
It is the same as the first embodiment-1, except that the distance between the conductors of the surface layer and the inner layer is 10 μm.
[0113]
[Reference Example 3-1]
Same as the first example-1, except that the arrangement of the through holes is formed in a staggered manner, and the distance between the ground through hole and the power supply through hole is 600 μm, 500 μm, 400 μm, 300 μm, 100 μm, 75 μm, and 60 μm. A total of seven types were formed. All are the same except for this through hole.
[0114]
[Reference Example 3-2]
As in the first embodiment-1, the through holes are arranged in a staggered manner, and the distance between the ground through hole and the power supply through hole is 650 μm. All are the same except for this through hole.
[0115]
[Reference Example 3-3]
Same as the first example-1, except that the arrangement of the through holes was formed in a staggered manner, and the distance between the ground through hole and the power supply through hole was 50 μm. All are the same except for this through hole.
[0116]
[Reference Example 3-4]
Same as Example 1 except that the through holes were arranged randomly and the shortest distance between the ground through hole and the power supply through hole was 650 μm, 600 μm, and 550 μm. All are the same except for this through hole.
[0117]
[Reference Example 4-1]
Same as the first embodiment-1, except that the arrangement of the through holes is formed in a lattice shape, and the distance between the ground through hole and the power supply through hole is 600 μm, 500 μm, 400 μm, 300 μm, 100 μm, 75 μm, and 60 μm. 7 types were formed. All are the same except for this through hole.
[0118]
[Reference Example 4-2]
The same as the first example 1, except that the arrangement of the through holes was formed in a lattice shape, and the distance between the ground through hole and the power supply through hole was 650 μm. All are the same except for this through hole.
[0119]
[Reference Example 4-3]
As in the first example-1, the arrangement of the through-holes was formed in a lattice pattern, and the distance between the ground through-hole and the power supply through-hole was 50 μm. All are the same except for this through hole.
[0120]
The first example group, the second example group, the third example group, the comparative example, and the reference example group were subjected to loop inductance and reliability tests under high temperature and high humidity, respectively. The results are shown in the chart in FIG. 16 and the graph in FIG. In the figure, the value of the loop inductance is a value per 10 mm square, and the reliability test (heat cycle: (−65 ° C./3 minutes) ⇔ (1 cycle of 135 ° C./3 minutes, 1500 cycles and 3000 cycles) In the results of the continuity test, は indicates a good one and X indicates a defective one.However, the measurement results in FIG. Next, the measurement was performed by selecting a region where no through hole was formed, thereby eliminating the factor due to the through hole pitch.
[0121]
Here, the lattice arrangement of the through-holes of the multilayer printed wiring board in the first embodiment, the staggered arrangement of the modification of the first embodiment, the through-holes for the random arrangement of the through-holes of Reference Example 1, Reference Example 3, and Comparative Example 1 are shown. FIG. 17 shows the results of measuring the loop inductance by changing the hole distance (through hole pitch) and the diameter of the through hole. Here, the value of the loop inductance is a value per 10 mm square.
[0122]
When the loop inductance is 90 pH or less, the power supply capability to the IC chip is improved, and noise and delay are not caused. Therefore, it is desirable that the distance between adjacent conductors in the core substrate be 300 μm or less. Even when a reliability test was performed, no occurrence of a short circuit or the like was observed in the conduction results, and thus there was no problem in electrical connectivity.
In Comparative Example 1, the loop inductance exceeded 100 pH. In Comparative Example 2, those having different distances between the conductor circuits were arranged. As a result, the pH exceeded 90 pH because the effect obtained by the multilayer was offset.
In Reference Example 1, since the distance between the conductors was 350, it is considered that the pH exceeded 90 pH. In Reference Example 2, there was no problem with the loop inductance itself, but a short circuit was caused in the reliability result test. Again, it was difficult to ensure insulation between the conductor layers, and a part of the conductor layers came into contact. Therefore, the result of the reliability test was bad. Considering this, it is more desirable that the distance between the conductor layers is 15 to 300 μm. This range is more desirable in terms of reliability. This is because, within this range, reliability is excellent.
Furthermore, it is more desirable that the distance between the conductor layers is 30 to 250 μm. This is because within this range, the reliability results are stable for a long period of time, and the inductance surely becomes 90 pH or less.
It is more likely that all adjacent conductor layers of the core substrate will have a uniform inductance than that of the surface layer between conductor layers.Therefore, when a multilayer core substrate is used, the conductor layers must be uniform. It is desirable to arrange them.
[0123]
Even if the through-hole pitch is changed, a lattice arrangement or staggered arrangement (a structure in which the ground through-hole and the power supply through-hole are adjacent) rather than a random arrangement (a structure in which the ground through-hole and the power supply through-hole are not adjacent) is used. This can reduce the loop inductance. As a result, noise can be suppressed, malfunctions and delays can be suppressed, and the mutual inductance itself can be reduced.
[0124]
Regardless of the through-hole pitch, the lattice arrangement can reduce the loop inductance as compared to the staggered arrangement. Therefore, it can be said that it is superior in electrical characteristics. 17, the mutual inductance value can be reduced when the ground through-hole 36E and the power supply through-hole 36P are arranged diagonally.
[0125]
The loop inductance was calculated from the simulation by changing the through-hole pitch. The results are shown in FIGS. 18B and 19. Here, the value of the loop inductance is a value per 10 mm square.
Furthermore, a reliability test was performed on the substrate under high-temperature and high-humidity conditions (85 ° C., humidity 85 wt%, 500 hours) at each through-hole pitch in the lattice arrangement and the staggered arrangement, and the presence or absence of cracks in the insulating layer of the through-holes. FIG. 18A shows the results of the resistance measurement in the continuity test.
[0126]
When the loop inductance becomes 75 pH or less, the characteristics of the substrate in an IC chip having a frequency of 3 GHz can be improved. In this case, as shown in FIG. 17, such a result is obtained when the through hole pitch is 600 μm or less. In addition, in consideration of the results of FIG. 18A, it can be said that the electrical characteristics can be appropriately improved and the reliability can be ensured when the thickness is in the range of 60 to 600 μm.
Further, when formed in a lattice arrangement, the through-hole pitch is desirably between 60 and 600 μm. This is because, in such a range, the loop inductance can be reduced to a certain level (75 pH) or less, and reliability can be ensured. Further, if the through-hole pitch is between 75 and 550 μm, reliability can be ensured at the same time as being inside the relevant loop inductance region.
[0127]
In the case of a staggered arrangement, the through-hole pitch is desirably between 60 and 550 μm. Within this range, the loop inductance can be reduced to a certain level (75 pH) or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 500 μm, reliability can be ensured at the same time as being inside the corresponding loop inductance region.
[0128]
When the loop inductance is 60 pH or less, the characteristics of the substrate in an IC chip having a frequency of 5 GHz can be improved. In this case, as shown in FIG. 17, such a result is obtained when the through hole pitch is 550 μm or less. In addition, in consideration of the result of FIG. 18A, it can be said that when the thickness is in the range of 60 to 550 μm, electrical characteristics can be appropriately improved, and reliability can be ensured.
[0129]
When formed in a lattice arrangement, the through hole pitch is desirably between 60 and 550 μm. Within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 500 μm, reliability can be ensured at the same time as being inside the relevant loop inductance region.
[0130]
In the case of a staggered arrangement, the through-hole pitch is desirably between 60 and 425 μm. Within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 500 μm, reliability can be ensured at the same time as being inside the relevant loop inductance region.
[0131]
Further, when the loop inductance becomes 55 pH or less, the characteristics of the substrate can be improved regardless of the frequency of the IC chip. In this case, as shown in FIG. 17, such a result is obtained when the through-hole pitch is 450 μm or less. In addition, in consideration of the result of FIG. 18A, it can be said that when the thickness is in the range of 60 to 450 μm, the electrical characteristics can be appropriately improved, and the reliability can be ensured.
[0132]
When formed in a lattice arrangement, the through hole pitch is desirably between 60 and 450 μm. Within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Further, if the through-hole pitch is between 75 and 425 μm, reliability can be ensured at the same time as being inside the relevant loop inductance region.
[0133]
In the case of a staggered arrangement, the through-hole pitch is desirably between 60 and 400 μm. Within this range, the loop inductance level can be reduced to 60 pH or less, and reliability can be ensured. Furthermore, if the through-hole pitch is between 75 and 350 μm, reliability can be ensured at the same time as being inside the relevant loop inductance region.
[0134]
An IC chip having a frequency of 3.1 GHz is mounted on the boards of the respective examples, comparative examples, and reference examples, and the same amount of power is supplied. FIG. 20 shows the result of simulating the amount of voltage drop at the time of starting. Here, the thickness of the conductor layer was verified. The horizontal axis sets the ratio of the thickness of the power supply layer of the core / the thickness of the interlayer insulating layer, and the vertical axis sets the maximum voltage drop (V).
If the thickness of the conductor is small, peeling occurs at the via connection portion, and the reliability is reduced. However, if the ratio of the thickness of the power supply layer of the core substrate to the thickness of the conductor layer of the interlayer insulating layer exceeds 1.2, the reliability is improved. On the other hand, if the ratio of the thickness of the power supply layer of the core substrate to the thickness of the conductor layer of the interlayer insulating layer exceeds 40, defects in the upper conductor circuit (for example, the occurrence of stress on the upper conductor circuit or the decrease in adhesion due to undulation may be reduced). Cause the reliability to decrease.
If the power supply voltage is 1.0 V and the fluctuation tolerance is ± 10%, the voltage behavior is stable, and the IC chip does not malfunction. In other words, in this case, if the amount of voltage drop is within 0.1 V, malfunction of the IC chip due to the voltage drop will not be caused. If it is 0.09 V or less, the stability will increase. Therefore, the ratio of (thickness of the power supply layer of the core substrate / thickness of the interlayer insulating layer) preferably exceeds 1.2. Further, if the range is 1.2 ≦ (thickness of power supply layer of core substrate / thickness of interlayer insulating layer) ≦ 40, the numerical value tends to decrease, so that the effect is easily obtained. In the range of 40 <(thickness of power supply layer of core substrate / thickness of interlayer insulating layer), the amount of voltage drop increases.
Further, if 5.0 <(thickness of the power supply layer of the core substrate / thickness of the interlayer insulating layer) ≦ 40, the voltage drop amounts are substantially the same, so that it is stable. That is, it can be said that this range is the most desirable ratio range.
[0135]
【The invention's effect】
In the present invention, by arranging the conductor layers on both surfaces of the multilayer core substrate and the inner conductor layer at a uniform distance, the mutual inductance between the conductor layers can be kept constant, and the overall inductance can be reduced. Therefore, by using the conductor layer as a power supply layer, the ability to supply power to the IC chip can be improved. In addition, by using the conductor layer as a ground layer, a signal to an IC chip and noise superimposed on a power supply can be reduced.
[Brief description of the drawings]
FIG. 1 is a process chart showing a method for manufacturing a multilayer printed wiring board according to a first embodiment of the present invention.
FIG. 2 is a process chart showing a method for manufacturing the multilayer printed wiring board of the first embodiment.
FIG. 3 is a process chart showing a method for manufacturing the multilayer printed wiring board of the first embodiment.
FIG. 4 is a process chart showing a method for manufacturing the multilayer printed wiring board of the first embodiment.
FIG. 5 is a process chart showing a method for manufacturing the multilayer printed wiring board of the first embodiment.
FIG. 6 is a process chart showing a method for manufacturing the multilayer printed wiring board of the first embodiment.
FIG. 7 is a process chart showing a method for manufacturing the multilayer printed wiring board of the first embodiment.
FIG. 8 is a sectional view of the multilayer printed wiring board according to the first embodiment.
FIG. 9 is a sectional view showing a state in which an IC chip is mounted on the multilayer printed wiring board according to the first embodiment.
10A is a cross-sectional view of the multilayer printed wiring board taken along line XX in FIG. 8, and FIG. 10B is a cross-sectional view of the multilayer printed wiring board according to a modification of the first embodiment. FIG.
11A is an explanatory diagram showing an enlarged dotted line I portion in FIG. 10A, and FIG. 11B is an enlarged enlarged view of a dotted line II portion in FIG. 11B. (C) is an explanatory diagram of a through-hole pitch and a diameter.
FIG. 12 is a sectional view of a multilayer printed wiring board according to a second embodiment.
FIG. 13 is a sectional view of a multilayer printed wiring board according to a modification of the second embodiment.
FIG. 14 is a sectional view of a multilayer printed wiring board according to a third embodiment.
FIG. 15 is a sectional view of a multilayer printed wiring board according to a fourth embodiment.
FIG. 16 is a table showing the results of a loop inductance and a reliability test under high temperature and high humidity performed by the first embodiment group, the second embodiment group, the third embodiment group, the comparative example, and the reference example group, respectively. is there.
FIG. 17 is a table showing the results of simulating loop inductances for through-hole grid arrangement and staggered arrangement.
FIGS. 18A and 18B are tables showing the results of simulating loop inductances for through hole grid arrangement and staggered arrangement.
FIG. 19 is a graph showing the results of simulating the loop inductance for the lattice arrangement of the through holes and the staggered arrangement.
FIG. 20 is a graph showing the results of simulating the maximum voltage drop (V) with respect to (the ratio of the thickness of the power supply layer of the core / the thickness of the interlayer insulating layer).
FIGS. 21A and 21B are explanatory diagrams showing the arrangement of conductor layers in a multilayer core substrate.
FIG. 22 is a graph showing calculation results of loop inductances for the first example group, the second example group, the third example group, the comparative example, and the reference example group.
FIG. 23
It is sectional drawing of the multilayer printed wiring board which concerns on a prior art.
[Explanation of symbols]
12 Metal layer (metal plate)
14 Resin layer
16P conductor layer
16E conductor layer
18 resin layer
30 substrates
32 copper foil
34 conductor circuit
34P conductor layer
34E conductor layer
36P power supply through hole
36E Ground through hole
40 Resin packed layer
50 interlayer resin insulation layer
58 conductor circuit
60 Via Hole
70 Solder resist layer
71 Opening
76U, 76D solder bump
90 IC chip
94 Daughter Board
98 chip capacitor

Claims (10)

On a multilayer core substrate having a plurality of through holes, at least three or more conductor layers having conductor layers on both surfaces and a conductor layer on the inner layer, an interlayer insulating layer and a conductor layer are formed on both surfaces or one surface, In a multilayer printed wiring board in which electrical connection is made via holes,
A multilayer printed wiring board, wherein a conductor layer on a surface of the multilayer core substrate and a conductor layer on an inner layer are respectively arranged at a uniform distance. On a multilayer core substrate having a plurality of through holes, at least three or more conductor layers having conductor layers on both surfaces and a conductor layer on the inner layer, an interlayer insulating layer and a conductor layer are formed on both surfaces or one surface, In a multilayer printed wiring board in which electrical connection is made via holes,
The multilayer printed wiring board, wherein adjacent conductor layers of the multilayer core substrate are arranged at a uniform distance from each other. The multilayer printed wiring board according to claim 1, wherein adjacent conductor layers of the multilayer core substrate are a sequence of a conductor layer for a power supply layer and a conductor layer for a ground. The multilayer printed wiring board according to claim 1, wherein a thickness of the conductor layer of the multilayer core substrate is larger than a thickness of the conductor layer on the interlayer resin insulating layer. 5. The multilayer printed wiring board according to claim 4, wherein α2 <α1 ≦ 40α2, where α1 is the thickness of the conductor layer of the multilayer core substrate and α2 is the thickness of the conductor layer on the interlayer insulating layer. 3. The multilayer printed wiring board according to claim 1, wherein a distance between conductor layers of the multilayer core substrate is 15 to 300 [mu] m. 3. The multilayer printed wiring board according to claim 1, wherein the conductor layer of the multilayer core substrate has at least two or more power supply conductor layers or ground conductor layers. 4. The through-holes of the multilayer core substrate have two or more ground through-holes and two or more power supply through-holes, each of which is arranged in a lattice or staggered pattern at adjacent positions. The multilayer printed wiring board according to claim 1 or 2, wherein: The multilayer printed wiring board according to claim 8, wherein a distance between the ground through-hole and the power supply through-hole is between 50 and 550 µm. 9. The multilayer printed wiring board according to claim 8, wherein the diameter of the through hole for the grant is 50 to 400 [mu] m, and the diameter of the through hole for the power supply is 50 to 400 [mu] m.

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