JP2004234129A - Storage device identification circuit in semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of easily identifying a type of a connected flash ROM, and easily setting of an address width, a data bus width or the like according to the type of the flash ROM. <P>SOLUTION: This semiconductor integrated circuit has: a plurality of terminals 7 for executing connection to the flash ROM 30; a terminal state decision circuit 13 deciding a terminal state of each of the plurality of terminals 7; a flash ROM decision circuit 9 reading identification information stored in the flash ROM 30 to identify the flash ROM 30; a flash ROM control circuit 4 executing setting necessary for the connection to the flash ROM 30, and imparting a required control command to a write command; a terminal control circuit 6 controlling the address width/data bus width when executing access through the plurality of terminals 7; and a control circuit 8 of an internal address bus width and an internal data bus width for transmitting a signal between the plurality of terminals 7 and each of the circuits. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a storage device identification circuit, and more particularly, to a flash ROM identification circuit used in connection with a semiconductor integrated circuit.
[0002]
[Prior art]
Generally, in a semiconductor integrated circuit, an external storage device is often used for storing a control code, and a flash ROM is often used as the external storage device due to characteristics such as storage capacity, cost advantages, and non-volatility. Can be
[0003]
At the stage of studying the connection system between the semiconductor integrated circuit and the flash ROM, the flash ROM to be connected may be frequently switched, so that the semiconductor integrated circuit flexibly sets various settings required for connection with the flash ROM. It is hoped that it can be performed.
[0004]
In a semiconductor integrated circuit with a built-in microcomputer, a part of the address space of a central processing unit (CPU) is allocated to an externally connected flash ROM, so that the CPU can access the flash ROM.
[0005]
When a semiconductor integrated circuit is connected to a flash ROM, it is necessary to set the storage capacity of the flash ROM, the latency, the specifications of the output waveforms of various control signals, and the like in the semiconductor integrated circuit. The setting required for the connection of the semiconductor integrated circuit to the flash ROM is performed by setting in a register for controlling the flash ROM mounted on the semiconductor integrated circuit by the CPU.
[0006]
As a method of storing the control code in the flash ROM, there are a method of using a flash ROM writer and a method of writing data from the semiconductor integrated circuit to the flash ROM. In the stage of mass production of a final product on which a semiconductor integrated circuit is mounted, the following method is used instead of the above method from the viewpoint of manufacturing cost.
[0007]
A method described below will be described with reference to the drawings.
FIG. 3 is a schematic diagram of a conventional technique in which a semiconductor integrated circuit is connected to a flash ROM.
FIG. 4 is a flowchart in the case where writing is performed from the semiconductor integrated circuit to the flash ROM. Referring to FIG. 4, the operation in the case where writing is performed from the semiconductor integrated circuit to the flash ROM will be described. I do.
[0008]
The control code to be stored in the flash ROM 200 is temporarily written, together with the control code transfer software, into a RAM (Random Access Memory) 102 built in the semiconductor integrated circuit 100 by the data communication means 103 with the outside (step S41). Then, when the CPU 101 starts operating (step S42) and executes the control code transfer software stored in the RAM 102 (step S43), the control code is written into the flash ROM 200.
[0009]
The operation of writing data to the flash ROM 200 by the CPU 101 is performed by executing a predetermined number of instructions for writing predetermined data to a predetermined address of the flash ROM 200. Here, this operation is referred to as executing a write command.
[0010]
However, here, write commands to be given from the semiconductor integrated circuit 100 to the flash ROM 200 may be different depending on the manufacturers and products of various flash ROMs.
[0011]
As an example, the following two write commands for the flash ROM, MBM29LV002C (product name) manufactured by Fujitsu Limited and SST39LF512 (product name) manufactured by Silicon Storage Technology, are shown below. Here, it is described in hexadecimal notation in the order of address / data.
[0012]
Fujitsu Limited MBM29LV002TC
1.0x555 / 0xaa
2.0x2aa / 0x55
3.0x555 / 0xa0
4. Write address / write data
SST39LF512 manufactured by Silicon Storage Technology
1.0x5555 / 0xaa
2.0x2aaa / 0x55
3.0x5555 / 0xa0
4. Write address / write data [0014]
Here, the command setting for controlling the connection with the flash ROM and the write command given to the flash ROM are executed by control code transfer software.
[0015]
[Patent Document 1]
JP 2001-154916 A
[Problems to be solved by the invention]
The control code and the control code transfer software are temporarily written in a RAM (Random Access Memory) 102 built in the semiconductor integrated circuit 100 by the above-described data communication means 103 with the outside, and the control code transfer software is written by the CPU 101. In the method of writing the control code into the flash ROM 200 by executing the control code, when the connected flash ROM 200 is changed, the control code transfer software sets the optimum control register for the connected flash ROM 200, The contents set in the flash ROM control register in step S44 of FIG. 4 are modified by the control code transfer software.) The control code and the control code transfer software are again transmitted by the data communication means 103 to / from the semiconductor integrated circuit. Since it is necessary to write to the RAM102 built in the 100, the operation is complicated, there is a disadvantage of lacking versatility.
[0017]
Further, the CPU 101 does not start operating until the control code and the control code transfer software are transferred to the RAM 102 built in the semiconductor integrated circuit 100 by the data communication means 103 with the outside. There is a disadvantage that the control register cannot be set, and the first access to the flash ROM 200 is delayed.
[0018]
In addition, when the connection of the flash ROM 200 to be connected is repeatedly changed, for example, at the stage of examining a connection system between the semiconductor integrated circuit 100 and the flash ROM 200, the above-described write command is changed to a command corresponding to the connected flash ROM 200. Since it is necessary, the write command is changed to a write command corresponding to the flash ROM 200 to be connected. (That is, the content of the portion where the control code is transferred to the flash ROM in step S45 of FIG. 4 is modified.) )) It is necessary to write the control code transfer software again in the RAM 102 incorporated in the semiconductor integrated circuit 100 as the control code and the control code transfer software in the data communication means 103 with the outside, so that the operation is also complicated. Lacks versatility There was a point.
[0019]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-described conventional problems, and is capable of flexibly executing various settings required for connection to a flash ROM without using control code transfer software. It is intended to provide a device identification circuit.
[0020]
[Means for Solving the Problems]
A storage device identification circuit according to claim 1 of the present invention is a storage device identification circuit for identifying a storage device connected to a semiconductor integrated circuit, wherein the storage device has an identification of the storage device in the storage device. A plurality of terminals for storing information, the terminals being connected to the storage device, and capable of controlling input from the storage device and output to the storage device, and having a pull-up thereof. A plurality of terminals capable of pull-down processing, a terminal state determination circuit for reading terminal states of the plurality of terminals and determining the terminal states; and a storage device from the storage device via the plurality of terminals. The storage device determination circuit that reads the identification information of the storage device and identifies the storage device, the output of the terminal state determination circuit, and the output of the storage device determination circuit are input, and settings necessary for connection with the storage device are input. A storage device control circuit for performing, when accessing the storage device via the plurality of terminals, an address bus width / data bus width terminal control circuit for controlling an address bus width and a data bus width via the terminals; An internal address bus width / internal data bus width control circuit for controlling a bus width of an internal address bus and an internal data bus for transmitting signals between the plurality of terminals and the circuits. It is a feature.
[0021]
A storage device identification circuit according to a second aspect of the present invention is the storage device identification circuit according to the first aspect, wherein the storage device is a flash ROM.
[0022]
The storage device identification circuit according to claim 3 of the present invention is the storage device identification circuit according to claim 1 or 2, wherein the storage device determination circuit transmits identification information of the storage device from the storage device after power-on. Read out and identify the storage device.
[0023]
A storage device identification circuit according to a fourth aspect of the present invention is the storage device identification circuit according to any one of the first to third aspects, wherein the storage device determination circuit determines a manufacturer number of the storage device from the storage device. At least one of the product numbers is read.
[0024]
The storage device identification circuit according to a fifth aspect of the present invention is the storage device identification circuit according to the fourth aspect, wherein the storage device determination circuit has a table, and the read manufacturer number and / or the storage device of the storage device. Alternatively, the storage device is identified based on the information of the product number.
[0025]
A storage device identification circuit according to claim 6 of the present invention is the storage device identification circuit according to claim 5, wherein the table of the storage device determination circuit is a ROM.
[0026]
A storage device identification circuit according to a seventh aspect of the present invention is the storage device identification circuit according to any one of the first to sixth aspects, wherein the terminal state determination circuit determines a terminal state of the plurality of terminals after power-on. Is determined.
[0027]
The storage device identification circuit according to claim 8 of the present invention is the storage device identification circuit according to any one of claims 1 to 7, wherein the storage device control circuit transmits setting information necessary for connection with the storage device. A storage device control register to be held, and a command providing circuit for providing a control command corresponding to the storage device output from the storage device determination circuit to a write command given to the storage device. It is.
[0028]
A storage device identification circuit in a semiconductor integrated circuit according to claim 9 of the present invention is the storage device identification circuit according to claim 8, wherein the storage device control circuit reads a manufacturer number and a product number from the storage device. Based on at least one of the information, the specifications relating to the address bus terminal and the internal address bus required for connection with the storage device are set in the storage device control register.
[0029]
The storage device identification circuit in the semiconductor integrated circuit according to claim 10 of the present invention is the storage device identification circuit according to claim 8, wherein the storage device control circuit determines a terminal state of the plurality of terminals after power-on. Based on the information, the specifications relating to a data bus terminal and an internal data bus required for connection with the storage device are set in the storage device control register.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram for explaining a semiconductor integrated circuit to which a flash ROM is connected according to a first embodiment of the present invention.
FIG. 2 is a flowchart in the case where writing is performed from the semiconductor integrated circuit to the flash ROM in the first embodiment of the present invention.
[0030]
The semiconductor integrated circuit 20 for connecting the flash ROM 30 according to the first embodiment shown in FIG. 1 is a plurality of terminals 7 for connection with the flash ROM 30 and is an input from the flash ROM 30 or a flash. A terminal state determination that controls output to the ROM 30 and reads a plurality of terminals 7 that are terminals capable of pull-up / pull-down processing and terminal states of the plurality of terminals 7 to determine the terminal states. Through the circuit 13, the plurality of terminals 7, an address bus width / data bus width terminal control circuit 6 described later, and the flash ROM control circuit 4, the identification information of the flash ROM 30 stored in the flash ROM 30 is obtained. By reading the information, the type of the flash ROM 30 is identified, and the bus width outside the terminal 7 is changed. A flash ROM having a command table 11 in which a correspondence relationship between an external data bus width, an external address bus width, and a command is set so that the external data bus width can be optimally set by the connected flash ROM 30. The setting necessary for the connection between the determination circuit 9 and the flash ROM 30 is performed in the flash ROM control register 5, and when the CPU 1 executes writing to the flash ROM 30, a write command given to the flash ROM 30 includes a flash ROM By giving a control command corresponding to the flash ROM 30 output from the determination circuit 9 and executing a command for writing write data to a write address as a write command from the CPU 1, the flash ROM 30 of a different type can be used. Also, a flash ROM control circuit 4 having a command providing circuit 12 capable of executing a write process, and an address bus width and data by the terminals when accessing the flash ROM 30 via the plurality of terminals 7 An address bus width / data bus width terminal control circuit 6 for controlling a bus width; the plurality of terminals 7; the flash ROM determination circuit 9; the flash ROM control circuit 4; the terminal state determination circuit 13; An internal address bus for controlling transmission of signals between the data bus width terminal control circuit and an internal address bus width and an internal data bus width control circuit for controlling a bus width of the internal data bus; Be composed.
[0031]
The above-described circuits, the flash ROM determination circuit 9, the flash ROM control circuit 4, the terminal state determination circuit 13, the address bus terminal and data bus terminal control circuit 6, the internal address bus width and the internal data bus width control circuit 8, The internal bus 15 is interconnected by an internal bus 15. The internal bus 15 is composed of an address bus, a data bus, and a control bus such as a read strobe, a write strobe, and a reset signal.
[0032]
Hereinafter, the operation of connecting the flash ROM 30 to the semiconductor integrated circuit according to the first embodiment will be described with reference to the flowchart of FIG.
[0033]
First, after turning on the power (step S1), the terminal state determination circuit 13 determines the state of at least one of the plurality of terminals 7 that is reserved (set) in advance, for example, The determination is made based on the High or Low level (high or low with respect to the threshold voltage) of the terminal (step S2).
[0034]
Next, on the basis of the states of the plurality of terminals 7 determined by the terminal state determination circuit 13 in the above step S2 and the previously reserved terminals determined above, the flash ROM control circuit 4 The bus width of the data terminal and the bus width of the internal data bus, which are the required numbers, are set to the High or Low level (high or low with respect to the threshold voltage) of the corresponding terminal. High level is determined and set in the flash ROM control register 5 in the flash ROM control circuit 4 (step S3).
[0035]
Next, after the above step S3, the first access to the flash ROM 30 is made to the address where the identification information of the connected flash ROM 30 is stored, and based on the address, as the flash ROM identification information, At least one of the manufacturer number and the product number of the flash ROM 30 is read (step S4).
[0036]
After reading the identification information of the flash ROM in step S4, the flash ROM determination circuit 9 determines the type of the connected flash ROM 30 with reference to the command table 11 stored in the circuit 9 ( Step S5).
[0037]
On the basis of the information on the type of the flash ROM 30 determined by the flash ROM determination circuit 9, the flash ROM control circuit 4 determines the storage capacity, latency, and output waveform specifications of various control signals of the connected flash ROM 30. It is set in the flash ROM control register 5 (step S6).
[0038]
Further, based on the information determined by the flash ROM determination circuit 9, the flash ROM control circuit 4 determines the specifications related to the address bus terminal and the internal address bus necessary for accessing the connected flash ROM 30, and the connection. The pull-up / pull-down processing of the address bus terminal of the plurality of terminals 7 which is unnecessary for the connection with the flash ROM 30 thus set is set in the flash ROM control register 5 (step S7).
[0039]
When writing to the flash ROM 30, the CPU 1 only needs to execute a command to write the write data to the write address as a write command. Reference numeral 12 gives a control command corresponding to the flash ROM 30 output from the flash ROM determination circuit 9 to a write command given to the flash ROM 30 so that a write command suitable for the connected flash ROM 30 is obtained. Once generated, it is possible to access the flash ROM 30 (step S8).
[0040]
As described above, in the first embodiment, before the CPU 1 starts the operation, the bus width of the data terminal and the bus width of the internal data bus for performing input / output with the connected flash ROM 30 are determined. Further, settings such as the storage capacity of the connected flash ROM 30, the latency, and the specification of the output waveform of various control signals, etc., and further, an address bus terminal required for accessing the connected flash ROM 30, and The settings relating to the internal address bus and the setting of the pull-up / pull-down processing of the address bus terminal of the plurality of terminals 7 which are not necessary for connection with the connected flash ROM 30 are set in the flash ROM control register 5. CPU 1 writes write data to a write address as a write command. By simply executing the instruction to insert the flash ROM 30, the command giving circuit 12 gives the write command given to the flash ROM 30 a control command corresponding to the flash ROM 30 so that the write command suitable for the connected flash ROM 30 is obtained. It is generated and allows easy access to the flash ROM 30.
[0041]
At this time, the type of the connected flash ROM is identified based on the identification information of the flash ROM, and the setting necessary for the connection is output by the flash ROM determination circuit 9. Therefore, even when the connected flash ROM 30 is changed, There is no need to obtain the specifications required for access to the newly connected flash ROM 30 from the outside by the data communication means and to set the specifications by executing the software, thereby simplifying the processing when changing the flash ROM. Is obtained.
[0042]
Further, the terminal state determination circuit 13 determines the connection state of the reserved terminal among the plurality of terminals 7 connected to the flash ROM 30 with the flash ROM 30, and performs input / output with the flash ROM 30. Since the bus width of the data terminal and the bus width of the internal data bus are determined, even when the flash ROM to be connected is changed, the data bus width required for access to the newly connected flash ROM 30 is changed. The setting can be easily performed without the need to obtain the setting from the outside by the data communication means, and there is an effect that connection of different types of flash ROMs can be easily made.
[0043]
Further, a flash ROM determination circuit 9 for setting necessary for accessing the connected flash ROM 30 in the semiconductor integrated circuit, and a terminal state determination circuit 13 for setting a bus width of a data terminal and a bus width of an internal data bus. Before starting the operation of the CPU, it is possible to make settings necessary for accessing the connected flash ROM in a short time, and to eliminate the delay of the first access to the flash ROM. .
[0044]
Further, when writing to the flash ROM 30 is performed by the CPU, a command corresponding to the flash ROM 30 whose type has been determined is added to a general-purpose write command by the CPU by the command applying circuit 12, so that the flash ROM 30 is written. Since the CPU generates a write command that conforms to the above specifications, the CPU can execute writing to general-purpose write data, and can also execute writing to flash ROMs with different write commands, simplifying the writing process. Can be
[0045]
In this embodiment, the case where a flash ROM which is a rewritable nonvolatile memory is connected has been described as an example. However, in the present invention, instead of the flash ROM, identification information capable of specifying specifications is used. In addition, the present invention can be similarly applied to a case where another storage device such as a RAM or a ROM that requires a unique write command for writing data is connected, and has the same effect as the above embodiment.
[0046]
【The invention's effect】
As described above, the storage device identification circuit in the semiconductor storage device according to the present invention is a storage device identification circuit that identifies a storage device connected to a semiconductor integrated circuit. A plurality of terminals for connecting to the storage device, wherein input terminals from the storage device and outputs to the storage device can be controlled. And a plurality of terminals capable of performing pull-up / pull-down processing, a terminal state determination circuit for reading terminal states of the plurality of terminals, and determining the terminal states, and a plurality of terminals via the plurality of terminals. The storage device determination circuit that reads the identification information of the storage device from the storage device and performs identification of the storage device, the output of the terminal state determination circuit, and the output of the storage device determination circuit are input. A storage device control circuit for performing settings necessary for connection with the storage device, and an address for controlling an address bus width and a data bus width via the terminals when accessing the storage device via the plurality of terminals. A bus width / data bus width terminal control circuit, the plurality of terminals, an internal address bus for controlling transmission of signals between the circuits, and an internal address bus width / internal data bus width for controlling a bus width of the internal data bus And a control circuit, so that it is not necessary for the CPU to perform the setting relating to the connection of the flash ROM and the execution of the write command by the control code transfer software in advance by the CPU, so that complicated processing is not performed. Thus, an effect is obtained that allows connection between the semiconductor integrated circuit and an unspecified storage device.
[Brief description of the drawings]
FIG. 1 is a schematic diagram when a semiconductor integrated circuit and a flash ROM are connected in Embodiment 1 of the present invention.
FIG. 2 is a flowchart in the case where writing is performed from the semiconductor integrated circuit to the flash ROM according to the first embodiment of the present invention;
FIG. 3 is a schematic diagram of a conventional technique when a semiconductor integrated circuit and a flash ROM are connected.
FIG. 4 is a flowchart of a conventional technique for writing data from a semiconductor integrated circuit to a flash ROM.
[Explanation of symbols]
1 CPU
30 Flash ROM
7 Plural terminals 13 Terminal state determination circuit 9 Flash ROM determination circuit 4 Flash ROM control circuit 6 Address bus width and data bus width terminal control circuit 8 Internal address bus width and internal data bus width control circuit 15 Internal bus step S1 Power on Step S2 Step 7 for determining the status of the terminal 7 Step S3 for setting the specifications relating to the data bus terminal and the internal data bus necessary for accessing the connected flash ROM. Step S4: Specifying either the manufacturer number or the product number. Step S5 for reading Step S6 for determining the connected flash ROM Step S6 for setting the storage capacity of the connected flash ROM, the latency, and the specification of the output waveform of various control signals Step S7 Step S8 for setting the address bus terminal and internal address bus necessary for access to the flash ROM 30 and the pull-up / pull-down processing of the address bus terminal which is not necessary for connection to the connected flash ROM Steps to do

Claims (10)

A storage device identification circuit for identifying a storage device connected to a semiconductor integrated circuit,
The storage device stores identification information of the storage device in the storage device,
A plurality of terminals for connecting to the storage device, the plurality of terminals being capable of controlling input from the storage device and output to the storage device, and capable of performing pull-up / pull-down processing thereof; When,
A terminal state determination circuit that reads terminal states of the plurality of terminals and determines the terminal state;
A storage device determination circuit that reads the identification information of the storage device from the storage device through the plurality of terminals and performs identification of the storage device;
An output of the terminal state determination circuit and an output of the storage device determination circuit are input, and a storage device control circuit that performs settings necessary for connection with the storage device,
An address bus width / data bus width terminal control circuit for controlling an address bus width and a data bus width via the terminals when accessing the storage device through the plurality of terminals;
An internal address bus width / internal data bus width control circuit for controlling a bus width of an internal address bus and an internal data bus for transmitting a signal between the plurality of terminals and the respective circuits,
A storage device identification circuit. The storage device identification circuit according to claim 1,
The storage device is a flash ROM,
A storage device identification circuit. 3. The storage device identification circuit according to claim 1, wherein
The storage device determination circuit reads the identification information of the storage device from the storage device after power-on, and performs identification of the storage device.
A storage device identification circuit. The storage device identification circuit according to any one of claims 1 to 3,
The storage device determination circuit reads at least one of a manufacturer number and a product number of the storage device from the storage device,
A storage device identification circuit. The storage device identification circuit according to claim 4,
The storage device determination circuit holds a table, and identifies the storage device based on at least one of the read manufacturer number and product number of the storage device,
A storage device identification circuit. The storage device identification circuit according to claim 5,
The table of the storage device determination circuit is a ROM.
A storage device identification circuit. The storage device identification circuit according to any one of claims 1 to 6,
The terminal state determination circuit determines the terminal states of the plurality of terminals after power-on,
A storage device identification circuit. The storage device identification circuit according to any one of claims 1 to 7,
The storage device control circuit includes a storage device control register that holds setting information necessary for connection with the storage device, and
A write command given to the storage device, a command application circuit for applying a control command corresponding to the storage device output from the storage device determination circuit,
A storage device identification circuit. 9. The storage device identification circuit according to claim 8,
The storage device control circuit relates to an address bus terminal and an internal address bus necessary for connection to the storage device based on at least one of a manufacturer number and a product number read from the storage device. Setting the specifications in the storage device control register,
A storage device identification circuit. The storage device identification circuit according to claim 8, wherein
The storage device control circuit, based on the determination information of the terminal state of the plurality of terminals after power is turned on, the specification of the data bus terminal and the internal data bus required for connection with the storage device, Set in the control register,
A storage device identification circuit.

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