JP2004208216A - Pulse width modulator/amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate a DC offset by reducing a manufacturing cost. <P>SOLUTION: A comparator CMP compares pulse width modulation outputs on both sides, to generate a duty pulse whose signal level is lowered by a pulse train of the same shape as the output. An integration circuit 4 smooths a duty deviation of the duty pulse, being the DC offset, contained in the modulation output, to output a signal on a level proportional to the DC offset. An adder 5 adds the signal on the level proportional to the DC offset to an input signal INO to make an input signal IN to an Lch pulse width modulator/amplifier part 1. For example, when the DC offset on a positive level is included in the pulse width modulation output, a signal on a negative level is outputted from the integration circuit 4. Thereby, since the level of the input signal IN falls, a duty ratio of the pulse width modulation outputs on each side is corrected in a decrease direction. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a pulse width modulation amplifier configured to remove a DC (direct current) offset included in a pulse width modulation output.
[0002]
[Prior art]
The DC offset included in the pulse width modulation output, that is, the unnecessary DC component included in the pulse width modulation output generated by pulse width modulation amplification of an input signal whose signal level does not include a DC component in the time average value thereof, Pulse width modulation amplifiers that have been eliminated are conventionally known.
[0003]
As such a pulse width modulation amplifier, a DC offset included in the pulse width modulation output is detected, and the detection result is fed back to the sawtooth wave generator used to generate the pulse width modulation signal as an error signal, There is one in which the DC level of a sawtooth wave generated by a sawtooth wave generator is changed according to the level of an error signal (for example, see Patent Document 1).
[0004]
[Patent Document 1]
Japanese Patent Publication No. Hei 2-60089 [0005]
[Problems to be solved by the invention]
However, in the conventional pulse width modulation amplifier, when detecting the error signal, the time average of the pulse width modulation output is detected, and the peak-to-peak level of the pulse width modulation output is detected. An error signal is obtained by taking the difference from 1/2 of the level, and a large number of circuits are required just to detect the error signal. Further, when this error signal is fed back to the sawtooth wave generator side, a low-pass filter (LPF), a DC amplifier and an adder are used, so that the manufacturing cost has increased.
[0006]
The present invention has been made in view of this point, and it is an object of the present invention to provide a pulse width modulation amplifier capable of removing a DC offset included in a pulse width modulation output while reducing manufacturing costs. I do.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the pulse width modulation amplifier according to claim 1, further comprising a BTL output circuit, wherein the pulse width modulation amplifier outputs two pulse width modulation amplified signals from the BTL output circuit. A comparing unit that detects the duty of the pulse width modulation amplified signal by comparing the level of the modulated amplified signal; an integrating unit that integrates a comparison result obtained by the comparing unit; Removing means for removing a DC offset included in the pulse width modulation amplified signal.
[0008]
According to another aspect of the present invention, in the pulse width modulation amplifier for outputting a pulse width modulation amplification signal, the level of the pulse width modulation amplification signal is compared with a predetermined value. A comparison means for detecting the duty of the pulse width modulation amplification signal, an integration means for integrating the comparison result by the comparison means, and a DC included in the pulse width modulation amplification signal according to the integration result by the integration means. Removing means for removing the offset.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0010]
FIG. 1 is a block diagram showing an overall configuration of a pulse width modulation amplifier according to one embodiment of the present invention.
[0011]
As shown in the figure, the pulse width modulation amplifier of the present embodiment includes a left channel (Lch) pulse width modulation amplification unit 1 having a BTL (Balanced Transformer Less) output circuit operated by a single power supply VBB. Similarly, a right channel (Rch) pulse width modulation amplifying section 2 having a BTL output circuit that also operates with a single power supply, and a triangular wave of a predetermined frequency are generated. It is mainly constituted by the triangular wave generator 3 to be supplied.
[0012]
The Lch pulse width modulation amplifier 1 compares the level of the amplified input signal IN with the level of the triangular wave supplied from the triangular wave generator 3 with the input signal amplifier 11 that amplifies the input signal IN that is an audio signal. Accordingly, a pulse width modulation (PWM) unit 12 that generates a pulse signal having a duty ratio according to the level of the input signal IN, the field effect transistors PNM1, PPM1, PNM2, PPM2, and the field effect transistors PNM1, PPM1, PNM2 (Metal Oxicide Semiconductor) driver 13 that switches PPM2, PPM2, and the output terminals + OUT, -OUT are short-circuited to apply an excessive current flowing through the field-effect transistors PNM1, PPM1, PNM2, and PPM2 to the resistor R41. The first overcurrent detection (OC) that is detected by detecting the voltage value ) A speaker connected to the circuit 14 through the LC filter described later, while detecting the excessive current flowing through the field effect transistors PNM1, PPM1, PNM2, and PPM2 by detecting the voltage value applied to the resistor R46. When the other signal input terminal of the speaker is grounded while one signal input terminal of the (load R) is connected to one of the output terminals + OUT and -OUT, the above-described resistance is used to prevent the DC current from flowing through the speaker. A second overcurrent detection (OCP) circuit 15 for detecting by detecting a negative voltage applied to R46.
[0013]
The driver 13 and the field-effect transistors PNM1, PPM1, PNM2, PPM2 form a BTL output circuit, and this BTL output circuit operates with a single power supply VBB.
[0014]
The pulse width modulation output from the pulse width modulation unit 12 is supplied to the driver 13, and the driver 13 generates an inverted pulse obtained by inverting the pulse width modulated output, and outputs the pulse width modulated output and its inverted pulse.
[0015]
The first complementary circuit including the P-channel field-effect transistor PPM1 and the N-channel field-effect transistor PNM1 is driven by the pulse width modulation output output from the driver 13, and the inverted pulse of the pulse width modulation output output from the driver 13 Thereby, the second complementary circuit including the P-channel field-effect transistor PPM2 and the N-channel field-effect transistor PNM2 is driven.
[0016]
Then, each output of the first and second complementary circuits is supplied to a first low-pass filter including a coil L1 and a capacitor C1 and a second low-pass filter including a coil L2 and a capacitor C2, as shown in FIG. The high-frequency components are respectively supplied and removed by the first and second low-pass filters, and the load (speaker) R is driven by the outputs of the first and second low-pass filters.
[0017]
Note that the first and second overcurrent detection circuits 14 and 15 are not essential to the present invention, and a description thereof will be omitted.
[0018]
Further, since the Rch pulse width modulation amplifier 2 has the same configuration as the Lch pulse width modulation amplifier 1, the detailed configuration is not shown.
[0019]
FIG. 2 is a diagram showing an example of the configuration of a DC offset removing circuit that removes a DC offset included in the pulse width modulation output from the Lch pulse width modulation amplifier 1, and FIG. 2 shows the first and second DC offset removing circuits. Are also shown.
[0020]
As shown in the figure, the DC offset removal circuit compares the positive (+) side pulse width modulation output and the negative (−) side pulse width modulation output output from the Lch pulse width modulation amplifier 1 with: A comparator CMP that outputs a voltage of a level corresponding to the comparison result, and an integration circuit 4 that integrates an output from the comparator CMP and extracts only a DC component included in the output, for example, a low-pass filter (LPF). And an adder 5 for adding the output signal from the integration circuit 4 and the input signal IN0.
[0021]
The comparator CMP operates at a power supply voltage VDD (for example, 5 V) lower than the power supply voltage VBB of the pulse width modulation amplifier 1. That is, the comparator CMP generates a pulse train having the same shape as the pulse width modulation output and a reduced signal level, that is, a duty pulse, by comparing the pulse width modulation outputs on both sides.
[0022]
The integration circuit 4 smoothes this duty pulse. Here, since the DC offset included in the pulse width modulation output appears as a duty error of the duty pulse, the integration circuit 4 smoothes the duty error. As a result, the integration circuit 4 outputs a signal having a level proportional to the DC offset. The adder 5 adds the signal having a level proportional to the DC offset and the input signal IN0 to obtain an input signal IN to the Lch pulse width modulation amplifier 1.
[0023]
For example, if the pulse width modulation output includes a positive level DC offset, the integration circuit 4 outputs a negative level signal. As a result, the level of the input signal IN decreases, so that the duty ratio of the pulse width modulation output on each side is corrected in a decreasing direction. On the other hand, if the pulse width modulation output includes a negative level DC offset, the operation is the reverse of the above operation.
[0024]
FIG. 3 is a diagram showing an example of a voltage waveform applied to a predetermined terminal in FIG. 2 when the DC offset removing circuit is not operated. FIG. 4 is a diagram showing the DC offset in the state of FIG. FIG. 3 is a diagram showing a voltage waveform applied to a predetermined terminal in FIG. 2 when the removing circuit is operated.
[0025]
As can be seen by comparing FIGS. 3 and 4, by operating the DC offset removing circuit, the duty error of the pulse width modulation output is reduced ((c)), and the DC offset included in the pulse width modulation output is reduced. It is removed ((b)).
[0026]
In this embodiment, a pulse width modulation amplifier having a BTL output circuit has been described as an example. However, the present invention is not limited to this, and the same applies to a normal pulse width modulation amplifier. Can be applied to
[0027]
FIG. 5 is a diagram illustrating an example of a DC offset removal circuit provided in a normal pulse width modulation amplifier. 2 differs from FIG. 2 in that the level of the pulse width modulation output from the Lch pulse width modulation amplifier 1 'is compared with the ground potential by the comparator CMP. As a result, the comparator CMP generates a pulse train having the same shape as the pulse width modulation output from the pulse width modulation amplification section 1 ′ and having a reduced signal level, that is, a duty pulse, as in FIG. are doing. Other configurations and operations are not different from those described in FIG. 2, and thus description thereof is omitted.
[0028]
As described above, in the present embodiment, the DC offset included in the pulse width modulation output is removed only by comparing the pulse width modulation outputs, integrating the comparison result, and adding the integration result to the input signal. Therefore, a DC offset removing circuit can be configured with a small number of components, and thereby, it is possible to remove the DC offset included in the pulse width modulation output while reducing the manufacturing cost.
[0029]
【The invention's effect】
As described above, according to the first or second aspect of the present invention, a simple configuration of comparing the levels of the pulse width modulated amplified signals, integrating the comparison result, and removing the DC offset according to the integration result is provided. Since the DC offset included in the pulse width modulation amplified signal can be removed, the DC offset included in the pulse width modulation output can be removed while reducing the manufacturing cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a pulse width modulation amplifier according to one embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of a configuration of a DC offset removal circuit that removes a DC offset included in a pulse width modulation output from an Lch pulse width modulation amplification unit in FIG.
3 is a diagram illustrating an example of a voltage waveform applied to a predetermined terminal in FIG. 2 when the DC offset removing circuit in FIG. 2 is not operated.
FIG. 4 is a diagram showing a voltage waveform applied to a predetermined terminal of FIG. 2 when the DC offset removing circuit of FIG. 2 is operated in the state of FIG. 3;
FIG. 5 is a diagram illustrating an example of a DC offset removal circuit provided in a normal pulse width modulation amplifier.
[Explanation of symbols]
1 Lch pulse width modulation amplification section, 3 triangular wave generator, 4 integration circuit, 5 adder, 12 pulse modulation (PWM) section, 13 MOS driver, PNM1, PPM1, PNM2, PPM2 field effect transistor, CMP comparator

Claims (2)

A pulse width modulation amplifier including a BTL output circuit and outputting two pulse width modulation amplification signals from the BTL output circuit,
Comparing means for detecting the duty of the pulse width modulated amplified signal by comparing the level of each pulse width modulated amplified signal;
Integrating means for integrating the result of comparison by the comparing means;
A pulse width modulation amplifier, comprising: a removal unit that removes a DC offset included in the pulse width modulation amplification signal in accordance with a result of integration by the integration unit. In a pulse width modulation amplifier that outputs a pulse width modulation amplified signal,
Comparing means for comparing the level of the pulse width modulated amplified signal with a predetermined value to detect the duty of the pulse width modulated amplified signal;
Integrating means for integrating the result of comparison by the comparing means;
A pulse width modulation amplifier, comprising: a removal unit that removes a DC offset included in the pulse width modulation amplification signal in accordance with a result of integration by the integration unit.

Images