JP2004186359A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve yield or reliability of devices by improving characteristics for separating elements. <P>SOLUTION: A method is provided which comprises steps of giving dry etching to a semiconductor substrate 1 using a silicon nitride film 5 as a mask to form a groove 7 for separating an element, injecting nitrogen ions into the groove 7 by ion implantation to form an oxide film 9 so that a semiconductor region 8 containing the nitrogen ions remains at a bottom of the groove 7, depositing an oxide silicon film 13, polishing the surface of the oxide silicon film 13 so that the silicon nitride film 5 is exposed to form an element separation portion, and removing the silicon nitride film 5 to form a p-type well, an n-type well, a complementary MISFET or the like in an element forming region. Thus, the semiconductor region 8 containing nitrogen ions disposed between the element separation portion and the semiconductor substrate 1 can prevent diffusion of impurities (particularly, boron constituting the p-type well) constituting the wells and thus can prevent reduction in the impurities concentration in the vicinity of the element separation portion, thereby ensuring pressure resistance at the element separation portion. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for manufacturing a semiconductor integrated circuit device (semiconductor device), and more particularly to a technology effective when applied to a semiconductor integrated circuit device using element isolation by an SGI (Shallow Groove Isolation) method.
[0002]
[Prior art]
The SGI method is a type of element isolation technology in an LSI manufacturing process, in which an insulating film such as a silicon oxide film is formed inside a groove formed in a semiconductor substrate, and the silicon oxide film outside the groove is removed by polishing or the like. An element isolation is formed, and this is used for isolation between elements. When the SGI is used, there are advantages that the element separation interval can be reduced and the element isolation film thickness can be easily controlled.
[0003]
On the other hand, conventionally, well isolation has been used for the isolation of a complementary MISFET, etc., and an n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on a p-type well, and a p-channel MISFET is formed on the n-type well. Is formed.
[0004]
Well isolation and SGI isolation are used together in order to improve element characteristics such as latch-up resistance.
[0005]
[Problems to be solved by the invention]
The present inventor is engaged in research and development of a semiconductor integrated circuit device, and uses the SGI method for separating elements such as complementary MISFETs.
[0006]
However, as a result of the study by the present inventors, it has been found that the element isolation width is reduced, and that the element isolation characteristics are degraded as the element isolation groove becomes shallower.
[0007]
This is because when the junction between the wells is located at the bottom of the SGI, the impurity (for example, boron) in the p-type well diffuses into the insulating film constituting the SGI, and the impurity concentration on the side wall of the SGI decreases. Is likely to be due to the junctions of the cells entering the p-type well. In particular, boron, which is often used as a p-type impurity, has a smaller atomic weight than an n-type impurity (phosphorus or arsenic) and is easily diffused into an insulating film, so that a junction between wells enters the p-type well.
[0008]
As will be described in detail later, when the junction between the wells enters the p-type well, the source / drain regions of the n-channel MISFET formed on the p-type well come close to the n-type well, and the leakage current decreases. (See FIG. 21).
[0009]
Such a problem becomes conspicuous as the element isolation width decreases and the element isolation groove becomes shallower.
[0010]
For example, the minimum element isolation width (distance between element formation regions) at the 0.13 μm node is 0.8 μm, whereas that at the 0.1 μm node is 0.44 μm. Further, in an SRAM (Static Random Access Memory) having the current minimum cell size, there is an area having an element isolation width of about 0.18 μm.
[0011]
Further, as will be described in detail later, a mask for forming a groove has to be thinned due to a demand for fine processing, and accordingly, the groove for element isolation tends to be shallow. In such a case, it is particularly important to secure element isolation resistance.
[0012]
FIG. 32 shows a simulation result of the impurity concentration near the bottom of the SGI studied by the present inventors. The simulation results when the depth of the SGI is 200 nm, the width is 0.18 μm, and boron is used for the p-type well (PWELL) and phosphorus is used for the n-type well (NWELL) are shown. The impurity concentrations of the p-type well and the n-type well are the same as in the case of the 0.13 μm node (SGI depth: 300 nm). As shown, the PN junction surface (boundary between wells) has entered the p-type well region.
[0013]
As described above, when the width of the SGI is small and the SGI is shallow, the penetration of the PN junction boundary into the p-type well region cannot be ignored, and it becomes difficult to secure the isolation breakdown voltage.
[0014]
To cope with such a phenomenon, p-type impurities diffused into the SGI may be compensated for by increasing the p-type impurity concentration. In this case, however, the diffusion of the impurities toward the surface of the semiconductor substrate causes the junction capacitance and the substrate to be reduced. The effect constant increases. As a result, the performance of the semiconductor element deteriorates, such as an increase in the drive current of the transistor.
[0015]
An object of the present invention is to improve element isolation characteristics.
[0016]
Another object of the present invention is to improve the characteristics of a semiconductor integrated circuit device by improving element isolation characteristics.
[0017]
Another object of the present invention is to improve the yield and reliability of a semiconductor integrated circuit device.
[0018]
Another object of the present invention is to provide an element isolation technology corresponding to miniaturization.
[0019]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0020]
[Means for Solving the Problems]
The following is a brief description of an outline of typical inventions disclosed in the present application.
[0021]
The semiconductor integrated circuit device of the present invention includes: (a) a semiconductor substrate having an element formation region and an element isolation region; (b) a groove formed in the element isolation region of the semiconductor substrate; A first semiconductor region containing nitrogen ions formed on sidewalls and a bottom portion, (d) an insulating film formed on the first semiconductor region, and (e) a first semiconductor region formed on the element formation region of the semiconductor substrate. And a second semiconductor region in contact with the first semiconductor region.
[0022]
Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention is a method of manufacturing a semiconductor integrated circuit device having an element formation region and an element isolation region, and having a semiconductor element on the element formation region. Forming a groove by etching the element isolation region of the semiconductor substrate; (b) implanting nitrogen ions into the inner wall of the groove; and (c) forming an insulating film inside the groove. (D) implanting a p-type impurity into the element formation region of the semiconductor substrate.
[0023]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.
[0024]
(Embodiment 1)
First Embodiment A semiconductor integrated circuit device according to a first embodiment of the present invention will be described according to its manufacturing process. 1 to 20 are main-portion cross-sectional views of a substrate showing a method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention.
[0025]
First, as shown in FIG. 1, a semiconductor substrate 1 made of, for example, p-type single crystal silicon is thermally oxidized to form a thermal oxide film 3 with a thickness of about 10 nm on the surface of the semiconductor substrate 1. Next, as shown in FIG. 2, a silicon nitride film 5 having a thickness of about 100 nm to 140 nm is deposited on the thermal oxide film 3. Next, as shown in FIG. 3, an antireflection film 6a is deposited on the silicon nitride film 5, and a photoresist film (hereinafter simply referred to as "resist film") 6b is formed thereon. This resist film 6b is a resist film for an argon fluoride (ArF) excimer laser (λ = 193 nm). The main component is, for example, a methacrylate resin.
[0026]
Next, as shown in FIG. 4, the resist film 6b is exposed by irradiating an ArF excimer laser, and is further developed to remove the resist film 6b on the element isolation region. Next, the antireflection film 6a, the silicon nitride film 5, and the thermal oxide film 3 are etched using the resist film 6b as a mask. Next, as shown in FIG. 5, the resist film 6b and the antireflection film 6a are removed.
[0027]
Next, as shown in FIG. 6, using the silicon nitride film 5 as a mask, the semiconductor substrate 1 is dry-etched to form trenches 7 for element isolation. The depth of the groove 7 is, for example, about 300 nm to 200 nm.
[0028]
Next, as shown in FIG. 7, nitrogen ions (N ions) were applied from the top of the semiconductor substrate 1 at 10 KeV to 1.0 × 10 ¹⁴ cm ^-2 (Hereafter, 1.0E14cm ^-2 ). As a result, a semiconductor region 8 containing nitrogen ions is formed on the side walls and the bottom of the trench 7. The semiconductor region 8 has a thickness of, for example, about 20 nm, and the thickness is set such that the semiconductor region 8 remains on the inner wall of the groove 7 even after the subsequent step of forming the oxide film 9.
[0029]
At this time, nitrogen ions are also implanted into the surface of the silicon nitride film 5.
[0030]
Next, as shown in FIG. 8, an oxide film (silicon oxide film) 9 having a thickness of about 20 nm is formed on the inner wall of the groove 7 by subjecting the semiconductor substrate 1 to an oxidation treatment. When Si (silicon) is oxidized, volume expansion occurs, so that even if an oxide film 9 of 20 nm is formed, a semiconductor region 8 of about 10 nm remains at the bottom thereof. This oxide film 9 is formed to recover the damage of the dry etching generated on the inner wall of the groove 7 and to round the corner of the groove.
[0031]
In addition, this oxidation step may be performed by using, for example, an ISSG (In-situ Stem Generation) oxidation method. ISSG oxidation is an oxidation method in which hydrogen and oxygen are introduced into a reaction chamber (chamber) to cause an oxidation reaction on the surface of a heated semiconductor substrate. According to this oxidation method, the oxidizing power is larger than that of normal dry oxidation, and the surface of the silicon nitride film 5 is also oxidized.
[0032]
Next, as shown in FIG. 9, a silicon oxide film 13 is deposited on the semiconductor substrate 1 including the inside of the trench 7 by a CVD (Chemical Vapor deposition) method so as to fill the trench 7. The silicon oxide film 13 is made of, for example, ozone teos (O ₃ -TEOS) film and can be formed by a CVD method using ozone and tetraethoxysilane as raw materials. Next, the surface of the silicon oxide film 13 is polished and flattened by using a chemical mechanical polishing (CMP) method until the silicon nitride film 5 is exposed. Thus, the silicon nitride film 5 also functions as a stopper film at the time of CMP. As a result of the CMP, the element isolation including the trench 7, the oxide film 9, and the silicon oxide film 13 is completed.
[0033]
Next, as shown in FIG. 10, the silicon nitride film 5 is removed by, for example, wet etching using hot phosphoric acid.
[0034]
Here, the surface of the silicon oxide film 13 protrudes from the surface of the semiconductor substrate 1 by the thickness of the silicon nitride film 5 as shown in the figure. By the process, the surface of the silicon oxide film 13 gradually recedes (recess phenomenon). Therefore, in consideration of the recession of the silicon oxide film 13, it is desirable to secure the protrusion of the silicon oxide film 13 at about 75 nm to 105 nm at this stage. That is, it is desirable to secure the thickness of the remaining silicon nitride film 5 to about 75 nm to 105 nm after polishing the silicon oxide film 13 by the CMP method.
[0035]
Next, a complementary MISFET is formed in an element formation region (active) defined by element isolation made of the silicon oxide film 13 or the like.
[0036]
First, as shown in FIG. 11, a sacrificial oxide film 15 of about 10 nm is formed by performing a heat treatment on the semiconductor substrate 1. Next, as shown in FIG. 12, after p-type impurities and n-type impurities are ion-implanted through the sacrificial oxide film 15, the impurities are diffused by heat treatment to thereby form the p-type well 17, the n-type well 19, and the NiSO region. 20 are formed. The NiSO region 20 is an n-type semiconductor region, and is formed for fixing the substrate to a predetermined potential, electrically separating the p-type well 17 from the semiconductor substrate 1, and the like.
[0037]
Conditions for implanting the impurities in the p-type well 17, the n-type well 19 and the NiSO region 20 are, for example, as follows. As for the p-type well 17, boron is supplied at an energy of 120 keV to 160 keV to form 5.0E12 cm. ^-2 5.0E11 cm at 55 keV to 30 keV energy ^-2 2.0E13cm with energy of 100keV ~ 60keV ^-2 About to inject. In addition, boron is also used as a punch-through stopper 18p at an energy of 20 keV for 1.0E13 cm. ^-2 It may be injected to a certain degree. Further, with respect to the n-type well 19, phosphorus is supplied at an energy of 450 keV to 370 keV to 3.0E12 cm. ^-2 5.0E11cm at an energy of 160 keV to 100 keV ^-2 2.0E13cm with energy of 240keV ~ 160keV ^-2 About to inject. In addition, arsenic is used as a punch-through stopper 18n at an energy of 100 keV and 1.0E13 cm. ^-2 It may be injected to a certain degree. In addition, for the NiSO region 20, phosphorus is applied at an energy of 1.0 MeV to 800 keV to 5.0E12 cm. ^-2 About to inject.
[0038]
Next, as shown in FIG. 13, impurities for threshold adjustment are implanted into the surfaces of the p-type well 17 and the n-type well 19. The impurity regions for adjusting the threshold are 21a and 21b.
[0039]
Next, as shown in FIG. 14, the sacrificial oxide film 15 is removed, and a gate insulating film 22 is formed on each of the p-type well 17 and the n-type well 19. The gate insulating film 22 is made of, for example, an oxynitride film.
[0040]
Next, as shown in FIG. 15, a low-resistance polycrystalline silicon film 23 doped with impurities is deposited on the gate insulating film 22 by the CVD method, and the polycrystalline silicon film 23 is dry-etched to form the gate electrode G. To form The gate length is, for example, about 65 nm.
[0041]
Next, as shown in FIG. 16, for example, a silicon oxide film is deposited as an insulating film on the semiconductor substrate 1 to a thickness of about 10 nm by a CVD method, and anisotropically etched to form an offset spacer 24 on the side wall of the gate electrode G. .
[0042]
Next, as shown in FIG. 17, n-type impurities are ion-implanted into the p-type wells 17 on both sides of the gate electrode G to form n-type impurities. ⁻ The p-type impurity is ion-implanted into the n-type well 19 to form the p-type semiconductor region 25. ⁻ A type semiconductor region 27 is formed. At this time, n ⁻ A p-type halo layer 26 is formed by implanting a p-type impurity under the p-type semiconductor region 25, ⁻ The n-type halo layer 28 may be formed by implanting an n-type impurity under the type semiconductor region 27.
[0043]
Next, as shown in FIG. 18, for example, a silicon oxide film 29a, a silicon nitride film 29b, and a silicon oxide film 29c are sequentially deposited as an insulating film on the semiconductor substrate 1 by a CVD method, and then anisotropically etched. Then, on the side wall of the gate electrode G, a side wall spacer 29 made of these laminated films is formed.
[0044]
Next, as shown in FIG. 19, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type ⁺ A p-type impurity (for example, boron) is ion-implanted into the n-type well 19 by forming a p-type semiconductor region 31 (source, drain). ⁺ A type semiconductor region 33 (source, drain) is formed.
[0045]
Next, as shown in FIG. 20, for example, a Co (cobalt) film is deposited as a metal film on the semiconductor substrate 1 and is subjected to a heat treatment so that a contact portion between the film and the gate electrode G and the semiconductor substrate 1 is formed. By causing a silicidation reaction, a cobalt silicide film 35 is formed in a self-aligned manner. Next, the unreacted Co film is removed, and heat treatment is further performed.
[0046]
Through the steps so far, an n-channel MISFET Qn and a p-channel MISFET Qp each having a source and a drain having an LDD (Lightly Doped Drain) structure are formed.
[0047]
Thereafter, although not shown, a multilayer wiring layer is formed by repeating formation of an interlayer insulating film, plugs (connection portions), and wiring on the MISFETs Qn and Qp. Further, a protective layer is formed on the uppermost wiring layer, and after dicing, the pad portion of the uppermost wiring exposed from the protective layer is electrically connected to an external terminal such as a mounting board, and the outer periphery thereof is covered with a molten resin or the like. By using and sealing, the semiconductor integrated circuit device is substantially completed.
[0048]
As described above, according to the present embodiment, the semiconductor region 8 containing nitrogen ions is provided at the boundary between the element isolation and the semiconductor substrate 1, so that the impurity constituting the well is prevented from diffusing during the element isolation. can do. In particular, although boron constituting the p-type well is easily diffused into the silicon oxide film, this diffusion can be prevented. Therefore, it is possible to prevent a decrease in the impurity concentration of the p-type well near the element isolation, and it is possible to secure the isolation breakdown voltage.
[0049]
For example, as shown in FIG. 21, when the PN junction surface (boundary between wells) enters the p-type well region and contacts the source and drain regions (31) of the n-channel MISFET Qn on the main surface of the p-type well 17. The source and drain regions of the MISFET and the n-type well are brought into conduction through this PN junction surface, and the leakage current increases. FIG. 21 is a diagram schematically showing a cross section of a main part of a semiconductor integrated circuit device for describing an effect of the present embodiment.
[0050]
In addition, such a problem becomes particularly remarkable when the trench for element isolation becomes shallow. For example, the groove for element isolation becomes shallower for the following reason.
[0051]
For example, when the width of the trench for element isolation becomes finer, that is, when the pattern of the silicon nitride film 5 and its space become finer, high-precision resolution of the resist film 6b serving as a mask when forming this pattern is required. Is done.
[0052]
There are various countermeasures for improving the resolution. For example, shortening the wavelength of the laser at the time of exposure is one of the effective solutions.
[0053]
However, for example, when the KrF excimer laser (λ = 248 nm) is changed to an ArF excimer laser (λ = 193 nm), the KrF excimer laser resist film (main component: polyhydroxystyrene resin) is compared with the ArF excimer laser resist film. The resist film 226 has a low etching resistance of the silicon nitride film thereafter, and is easily damaged when etching the silicon nitride film 5 (see FIG. 22). Therefore, when the silicon nitride film 5 is made thicker, the resist film is deformed or deteriorated at the time of etching, and eventually does not serve as a resist film. FIG. 22 is a diagram schematically showing an etched state of a silicon nitride film when a resist film for an ArF excimer laser is used.
[0054]
Therefore, it is necessary to make the silicon nitride film 5 relatively thin and to etch the silicon nitride film 5 while the damage to the resist film is small.
[0055]
On the other hand, the silicon nitride film 5 serves as a polishing stopper during CMP. Further, as described above, after the silicon nitride film 5 is removed, the surface of the element isolation (silicon oxide film 13) is maintained higher than the semiconductor substrate 1 to reduce the influence of the subsequent recess of the element isolation surface (recess phenomenon). It is preferable that the silicon nitride film 5 remains as thick as possible after the CMP.
[0056]
Further, the formation of the trench for element isolation, that is, the etching of the semiconductor substrate and the CMP also cause the silicon nitride film 5 to decrease in thickness. Therefore, it is necessary to make the trench for element isolation as shallow as possible and to reduce the film thickness of the silicon nitride film 5.
[0057]
Even if the trench for element isolation is made shallow, it is needless to say that it is necessary to secure a depth necessary for isolation between elements. Also, with the miniaturization of devices, the diffusion layers and various films constituting the device tend to be thinner, and even if the trenches for device isolation are made shallower, there is no problem in isolation between devices.
[0058]
As described above, the trench for element isolation tends to be shallow, and as described with reference to FIG. 21, a leak current is likely to occur.
[0059]
However, according to the present embodiment, even if the trench for element isolation becomes shallow, the bias of the PN junction surface due to diffusion of impurities can be prevented, and the leak current can be reduced. Also, the separation withstand voltage can be secured.
[0060]
In the present embodiment, oxide film 9 is formed by ISSG oxidation after nitrogen ions are implanted. However, nitrogen ions may be implanted into the bottom of the oxide film after the oxidation process.
[0061]
(Embodiment 2)
In the first embodiment, nitrogen ions are vertically implanted from above the semiconductor substrate 1. However, nitrogen ions are contained only in the sidewalls of the well-side grooves where diffusion of impurities is to be prevented by oblique ion implantation or the like. The semiconductor region 208 may be formed.
[0062]
Steps other than the nitrogen ion implantation step are the same as those in Embodiment 1, and thus the nitrogen ion implantation step will be described in detail.
[0063]
As described in the first embodiment with reference to FIG. 6, the semiconductor substrate 1 is dry-etched using the silicon nitride film 5 as a mask to form the trench 7 for element isolation.
[0064]
Next, as shown in FIG. 23, nitrogen ions (N ions) are applied from above the semiconductor substrate 1 at 10 KeV to 1.0 × 10 ¹⁴ cm ^-2 (Hereafter, 1.0E14cm ^-2 ).
[0065]
At this time, a semiconductor region 208 containing nitrogen ions is formed on one side wall of the trench 7 and its lower part, and nitrogen ions are not implanted on the other side wall and its lower part because the side wall and its lower part are shadowed by the side wall. The semiconductor region 208 has a thickness of, for example, about 20 nm, and the thickness is set so as to remain on the inner wall of the groove even after the subsequent step of forming the oxide film 9.
[0066]
Thereafter, as described in the first embodiment with reference to FIG. 9, an oxide film 9 and a silicon oxide film 13 are formed in the trench 7, and further, a well, a MISFET, and the like are formed. Here, the p-type well 17 is formed on the side of the semiconductor region 208 containing nitrogen ions.
[0067]
As described above, according to the present embodiment, the semiconductor region 208 containing nitrogen ions is provided at the boundary between the element isolation and the semiconductor substrate 1 in the same manner as in the first embodiment. Diffusion can be prevented. Therefore, it is possible to prevent a decrease in the impurity concentration of the p-type well near the element isolation, and it is possible to secure the isolation breakdown voltage.
[0068]
In addition, even if the trench for element isolation becomes shallow, deviation of the PN junction surface due to diffusion of impurities can be prevented, and leakage current can be reduced. Also, the separation withstand voltage can be secured.
[0069]
Instead of using the oblique ion implantation method, for example, the semiconductor region 208 containing nitrogen ions may be provided by covering the side wall of the groove on the n-type well formation region side with a resist film or the like. In this case, A step of forming a resist film and a step of removing the resist film are required.
[0070]
In the present embodiment, after nitrogen ions are implanted, oxide film 9 is formed by ISSG oxidation or the like. However, nitrogen ions may be implanted into the bottom after the oxidation treatment.
[0071]
(Embodiment 3)
In the first embodiment and the like, the semiconductor region containing nitrogen ions is used as the diffusion preventing layer of the impurity constituting the well. For example, an amorphous layer of SiGe (silicon germanium) is formed, and An impurity trap layer may be provided at the interface to secure the impurity concentration.
[0072]
Steps other than the Ge (germanium) ion implantation step are the same as those in the first embodiment, so the Ge ion implantation step will be described in detail.
[0073]
As described in the first embodiment with reference to FIG. 6, the semiconductor substrate 1 is dry-etched using the silicon nitride film 5 as a mask to form the trench 7 for element isolation.
[0074]
Next, as shown in FIG. 24, by subjecting the semiconductor substrate 1 to ISSG oxidation, an oxide film 9 of about 20 nm is formed on the inner wall of the groove 7.
[0075]
Next, as shown in FIG. 25, Ge ions were injected from the top of the semiconductor substrate 1 at 20 KeV and 5.0E14 cm. ^-2 About to inject. As a result, Ge ions are implanted into the boundary between the oxide film 9 and the semiconductor substrate 1, and an amorphous layer 308 made of SiGe is formed. This SiGe layer contains crystal defects, and impurity ions are easily trapped in such defects.
[0076]
Therefore, even if the impurity (for example, boron) in the p-type well diffuses in the direction of the insulating film constituting the element isolation, the impurity is trapped in the SiGe layer, and a decrease in the impurity concentration can be prevented.
[0077]
At this time, Ge ions are also implanted into the surface of the silicon nitride film 5.
[0078]
Thereafter, as in the first embodiment described with reference to FIGS. 9 to 20, a silicon oxide film 13 is formed in the trench 7, and a well, a MISFET, and the like are formed.
[0079]
Also in this embodiment, the isolation withstand voltage can be ensured, and it is possible to cope with a shallower trench for element isolation.
[0080]
In this embodiment, Ge ions are implanted after performing the ISSG oxidation. However, after the Ge ions are implanted, the oxide film 9 may be formed by an oxidation process so that the SiGe layer remains.
[0081]
(Embodiment 4)
In the third embodiment, an amorphous layer made of SiGe is formed at the boundary between the oxide film 9 and the semiconductor substrate 1, but in this embodiment, this boundary is nitrided.
[0082]
Steps other than the nitriding process are the same as those in the first embodiment, and thus the nitriding process will be described in detail.
[0083]
As described in the first embodiment with reference to FIG. 6, the semiconductor substrate 1 is dry-etched using the silicon nitride film 5 as a mask to form the trench 7 for element isolation.
[0084]
Next, as shown in FIG. 26, an oxide film 9 having a thickness of about 20 nm is formed on the inner wall of the groove 7 by subjecting the semiconductor substrate 1 to an oxidation treatment.
[0085]
Next, as shown in FIG. ₂ By performing O treatment, the boundary between the oxide film 9 and the semiconductor substrate 1 is nitrided. As a result, a nitride layer 408 is formed at this boundary. This nitride layer is considered to be a nitride film or an oxynitride film.
[0086]
Thereafter, as in the first embodiment described with reference to FIGS. 9 to 20, a silicon oxide film 13 is formed in the trench 7, and a well, a MISFET, and the like are formed.
[0087]
As described above, according to the present embodiment, nitride layer 408 is provided at the boundary between element isolation and semiconductor substrate 1 as in the first embodiment, so that diffusion of boron constituting the p-type well can be prevented. Therefore, it is possible to prevent a decrease in the impurity concentration of the p-type well near the element isolation, and it is possible to secure the isolation breakdown voltage.
[0088]
In addition, even if the trench for element isolation becomes shallow, deviation of the PN junction surface due to diffusion of impurities can be prevented, and leakage current can be reduced. Also, the separation withstand voltage can be secured.
[0089]
(Embodiment 5)
In this embodiment mode, a trench is formed after a sidewall film is formed on a side wall of a silicon nitride film serving as a mask when forming a trench for element isolation.
[0090]
Note that detailed description of the same steps as those in Embodiment 1 is omitted.
[0091]
As described with reference to FIG. 5 in the first embodiment, after patterning the silicon nitride film 5 and removing the resist film thereon, as shown in FIG. A side wall film 505 having a thickness of about 10 nm is formed on the side wall of the silicon nitride film 5 by depositing a silicon oxide film by a CVD method and anisotropically etching the silicon oxide film.
[0092]
Next, as shown in FIG. 29, using the silicon nitride film 5 and the sidewall film 505 as a mask, the semiconductor substrate 1 is dry-etched to form a trench 7 for element isolation.
[0093]
Next, as shown in FIG. 30, the sidewall film 505 is removed. As a result, the semiconductor substrate 1 at the upper end portion of the groove 7 (portion a: substrate surface above the side wall of the groove) is exposed.
[0094]
Next, as shown in FIG. 31, nitrogen ions (N ions) are applied from above the semiconductor substrate 1 at 10 KeV and 1.0E14 cm as in the first embodiment. ^-2 About to inject. As a result, a semiconductor region 508 containing nitrogen ions is formed on the side wall and the bottom of the trench 7 to a thickness of about 20 nm. At this time, a semiconductor region 508 containing nitrogen ions is also formed at the upper end (part a) of the groove 7.
[0095]
Next, an oxide film of about 20 nm is formed on the inner wall of the groove 7 by performing ISSG oxidation in the same manner as in the first embodiment. At this time, oxidation is performed so that the semiconductor region 508 remains at the bottom of the oxide film.
[0096]
Thereafter, as in the first embodiment described with reference to FIGS. 9 to 20, a silicon oxide film is formed in the trench, and a well, a MISFET, and the like are formed.
[0097]
As described above, according to the present embodiment, the semiconductor region 508 containing nitrogen ions is provided at the boundary between the element isolation and the semiconductor substrate 1 in the same manner as in the first embodiment. Diffusion can be prevented. Therefore, it is possible to prevent a decrease in the impurity concentration of the p-type well near the element isolation, and it is possible to secure the isolation breakdown voltage.
[0098]
In addition, even if the trench for element isolation becomes shallow, deviation of the PN junction surface due to diffusion of impurities can be prevented, and leakage current can be reduced. Also, the separation withstand voltage can be secured.
[0099]
Further, in the present embodiment, since the upper end portion (a portion) of trench 7 is also covered with semiconductor region 508 containing nitrogen ions, the diffusion of boron in the upper portion of the p-type well can be suppressed, and n-channel MISFET can be suppressed. Of the threshold value can be suppressed. Further, it is possible to prevent the source and the drain of the MISFET (particularly, the boron constituting the source and the drain of the p-channel MISFET) from being diffused during the isolation. As a result, the characteristics of the MISFET can be improved.
[0100]
In this embodiment, an oxide film is formed by ISSG oxidation after nitrogen ions are implanted. However, nitrogen ions may be implanted into the bottom of the oxide film after the oxidation treatment.
[0101]
As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.
[0102]
In particular, in the above-described embodiment, the MISFET has been described as an example of the semiconductor element formed on the well. However, the present invention is not limited to the case where such an element is formed. is there.
[0103]
Further, in the above-described embodiment, boron has been described as an example of the p-type impurity. However, it is considered that similar effects can be obtained when a boron compound such as boron fluoride is used.
[0104]
【The invention's effect】
The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.
[0105]
Since the first semiconductor region containing nitrogen ions is provided on the side wall and the bottom of the groove formed in the element isolation region, diffusion of impurities from the second semiconductor region in contact with the first semiconductor region can be prevented.
[0106]
As a result, element isolation characteristics can be improved. Further, the characteristics of the semiconductor integrated circuit device can be improved. Further, the yield and reliability of the semiconductor integrated circuit device can be improved. Further, it is possible to cope with miniaturization of a semiconductor integrated circuit device.
[Brief description of the drawings]
FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to Embodiment 1 of the present invention;
FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 3 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 6 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 7 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 8 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.
10 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG.
FIG. 11 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 12 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
13 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention; FIG.
FIG. 14 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 15 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 16 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 18 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.
FIG. 19 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention;
FIG. 20 is an essential part cross sectional view of the substrate for illustrating the method for manufacturing the semiconductor integrated circuit device of the first embodiment of the present invention.
FIG. 21 is a diagram schematically illustrating a cross section of a main part of a semiconductor integrated circuit device for describing an effect of the first embodiment of the present invention;
FIG. 22 is a diagram schematically showing an etching state of a silicon nitride film when a resist film for ArF excimer laser is used.
FIG. 23 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the second embodiment of the present invention;
FIG. 24 is an essential part cross sectional view of the substrate for illustrating the method for manufacturing the semiconductor integrated circuit device of the third embodiment of the present invention.
FIG. 25 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the third embodiment of the present invention;
FIG. 26 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fourth embodiment of the present invention;
FIG. 27 is an essential part cross sectional view of the substrate for illustrating the method for manufacturing the semiconductor integrated circuit device of Embodiment 4 of the present invention.
FIG. 28 is an essential part cross sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.
FIG. 29 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention;
FIG. 30 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the fifth embodiment of the present invention.
FIG. 31 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device of the fifth embodiment of the present invention.
FIG. 32 is a cross-sectional view showing a simulation result of the impurity concentration near the bottom of the SGI studied by the present inventors.
[Explanation of symbols]
1 semiconductor substrate
3 Thermal oxide film
5 Silicon nitride film
6a Anti-reflective coating
6b resist film
7 grooves
8 Semiconductor region containing nitrogen ions
9 oxide film
13 Silicon oxide film
15 Sacrificial oxide film
17 p-type well
18n Punch Through Stopper
18p Punch through stopper
19 n-type well
20 NiSO region
22 Gate insulating film
23 Polycrystalline silicon film
24 Offset spacer
25 n ⁻ Semiconductor region
26 p-type halo layer
27p ⁻ Semiconductor region
28 n-type halo layer
29 Sidewall spacer
29a Silicon oxide film
29b Silicon nitride film
29c silicon oxide film
31 n ⁺ Semiconductor region
33 p ⁺ Semiconductor region
35 Cobalt silicide film
208 Semiconductor region containing nitrogen ions
226 resist film
226a Anti-reflective coating
308 Amorphous layer of SiGe
408 nitride layer
505 Sidewall film
508 Semiconductor region containing nitrogen ions
G gate electrode
Qn n-channel type MISFET
Qp p-channel type MISFET

Claims (5)

(A) a semiconductor substrate having an element formation region and an element isolation region;
(B) a groove formed in the element isolation region of the semiconductor substrate;
(C) a first semiconductor region containing nitrogen ions formed on the side wall and the bottom of the trench;
(D) an insulating film formed on the first semiconductor region;
(E) a second semiconductor region formed in the element formation region of the semiconductor substrate and in contact with the first semiconductor region;
A semiconductor integrated circuit device comprising: (A) a silicon substrate having an element formation region and an element isolation region;
(B) a groove formed in the element isolation region of the silicon substrate;
(C) an amorphous silicon germanium layer formed on the side wall and the bottom of the groove;
(D) an insulating film formed on the silicon germanium layer;
(E) a semiconductor region formed in the element formation region of the semiconductor substrate and in contact with the silicon germanium layer;
A semiconductor integrated circuit device comprising: (A) a semiconductor substrate having an element formation region and an element isolation region;
(B) a groove formed in the element isolation region of the semiconductor substrate;
(C) a nitride layer formed on the side wall and the bottom of the groove;
(D) an insulating film formed on the nitride layer;
(E) a semiconductor region formed in the element formation region of the semiconductor substrate and in contact with the nitride layer;
A semiconductor integrated circuit device comprising: (A) a semiconductor substrate having an element formation region and an element isolation region;
(B) a groove formed in the element isolation region of the semiconductor substrate;
(C) a first semiconductor region containing nitrogen ions formed on the surface of the semiconductor substrate on the side wall, bottom portion and upper portion of the groove;
(D) an insulating film formed on the first semiconductor region;
(E) a second semiconductor region formed in the element formation region of the semiconductor substrate and in contact with the first semiconductor region;
A semiconductor integrated circuit device comprising: A method for manufacturing a semiconductor integrated circuit device having an element formation region and an element isolation region, and having a semiconductor element on the element formation region,
(A) forming a groove by etching the element isolation region of the semiconductor substrate;
(B) implanting nitrogen ions into the inner wall of the groove;
(C) forming an insulating film inside the groove;
(D) implanting a p-type impurity into the element formation region of the semiconductor substrate.

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