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JP2004146656A - Multilayer wiring board and its manufacturing method - Google Patents

Multilayer wiring board and its manufacturing method Download PDF

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Publication number
JP2004146656A
JP2004146656A JP2002310979A JP2002310979A JP2004146656A JP 2004146656 A JP2004146656 A JP 2004146656A JP 2002310979 A JP2002310979 A JP 2002310979A JP 2002310979 A JP2002310979 A JP 2002310979A JP 2004146656 A JP2004146656 A JP 2004146656A
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JP
Japan
Prior art keywords
wiring board
multilayer wiring
mounting portion
mount
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002310979A
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Japanese (ja)
Inventor
Koichi Morishita
森下 広一
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Denso Corp
Original Assignee
Denso Corp
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Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2002310979A priority Critical patent/JP2004146656A/en
Publication of JP2004146656A publication Critical patent/JP2004146656A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To improve the connection reliability of a surface mounted component with a simple and inexpensive constitution. <P>SOLUTION: On a mount surface (top surface) of a multilayer wiring board 11, a mount part 15 having many lands 15a is provided and a CSP type surface mounted component 12 is soldered with a joint 13. On the surface of an opposite surface (reverse surface) from the mount 15, a cut recessed part 16 corresponding to the mount part 15 is formed. The mount 15 decreases in thickness and then decreases in rigidity, so that stress operating on the solder joint 13 in temperature cycles can be absorbed. When the multilayer wiring board 11 is manufactured, sheet type base materials made of thermoplastic resin constituting respective insulating layers 14 are pressed into integration, while heated in a stacked state, and at this time, cut parts constituting the cut recessed part 16 are previously formed in a plurality of base materials positioned on the reverse surface side. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は、層間に導体パターンを有する多層の絶縁層を備えて構成されると共に、表面に表面実装部品がはんだ接合される実装部を備える多層配線基板及びその製造方法に関する。
【0002】
【従来の技術】
例えば各種の小型電子機器に組込まれる実装基板においては、多層配線基板に、小型、高密度の表面実装部品、例えばBGA(Ball Grid Array )タイプや、CSP(Chip Size Package )タイプといった狭ピッチで且つ多端子の電子部品を実装する構成が採用されている。また、前記多層配線基板は、例えばエポキシ樹脂などの熱硬化性樹脂を主体とした多層の絶縁層を有すると共に、表面や層間に導体パターンを有して構成され、その表面に形成されたランドに、前記表面実装部品のはんだバンプが接合(はんだ付け)されるようになっている。
【0003】
【発明が解決しようとする課題】
ところが、このような実装基板にあっては、多層配線基板と電子部品との熱膨張係数の差などに起因して、温度変化によって反り変形などの変形挙動が発生する事情がある。一例をあげると、図4に誇大的に示すように、多層配線基板1の表面(上面)に、電子部品(ICチップ)2がはんだ接合部(はんだバンプ)3によりはんだ接合されている場合、高温時において、(a)に示すように、多層配線基板1に上方に凸状となるような反り変形が生じ、低温時において、(b)に示すように、多層配線基板1に下方に凸状となるような反り変形が生ずる。
【0004】
このため、はんだ接合部3部分、特に最外周に位置するはんだ接合部3に大きな応力が作用し、いわゆる熱疲労クラックオープンが発生する虞があった。即ち、図5に拡大して示すように、クラックCは、はんだ接合部3の多層配線基板1のランド1aとの界面や、電子部品2のパッケージの電極2aとの界面に発生しやすく、ひいては剥離に至るなど、接続信頼性が低下する不具合があった。
【0005】
特に、車載環境、例えばカーナビやエンジン制御用のECU、カーエアコン、車載通信機、カーオーディオなどに使用されるような場合には、一年を通じた温度サイクルは、例えば−30℃〜85℃もの広い温度範囲となり、熱衝撃ストレスが製品寿命に大きな影響を与えるものとなっている。
【0006】
そこで、その対策として、従来では、上記したような電子部品2の下面側(多層配線基板1との隙間部分)にアンダーフィル(封止樹脂)を流し込んで硬化させることで、はんだ接合部3の歪みを抑制して製品寿命を延ばす方法や、電子部品2のインターポーザの剛性を下げることで歪みを緩和して製品寿命を延ばす方法があった。しかしながら、これらの対策では、電子部品2を実装するにあたっての余分な工程や材料が必要となってコストアップを招く、あるいは、電子部品2そのものが高価となる問題点があった。
【0007】
本発明は上記事情に鑑みてなされたもので、その目的は、表面実装部品の接続信頼性の向上を図ることができ、しかも簡単で安価な構成で済ませることができる多層配線基板及びその製造方法を提供するにある。
【0008】
【課題を解決するための手段】
上記目的を達成するために、本発明の多層配線基板は、表面実装部品がはんだ接合される実装部とは反対面側の該実装部に対応した位置に、一部の絶縁層を切欠いた切欠凹部を設けたところに特徴を有する(請求項1の発明)。これによれば、切欠凹部を設けたことにより、基板のうちの表面実装部品の実装部部分の厚みが他の部分よりも薄くなり、その部分だけ剛性が下がることになる。このため、多層配線基板と電子部品との熱膨張係数差に起因してはんだ接合部に作用する応力を、その剛性の低い部分の変形により吸収することができる。
【0009】
この結果、表面実装部品の接続信頼性の向上を図ることができて製品寿命を長くすることができ、しかも切欠凹部を設けるという簡単で安価な構成で済ませることができるものである。尚、はんだ接合部の歪みを吸収する観点からは、実装部における基板の厚みは、より薄い方が望ましいが、あまりに薄くし過ぎると、今度は部品の自重による自重反りが発生し、はんだ接合部のいわゆる初期的オープンに至る虞が生ずる。従って、実装部の基板の厚み(言い換えれば切欠凹部の深さ)は、基板の弾性率(材質)、表面実装部品の重量、実装面積等を考慮して、初期的なオープンが起こらない範囲で極力薄くするように設定することが望ましい。
【0010】
ところで、上記した多層配線基板を製造する方法としては、多層の絶縁層の積層後に、実装部とは反対面側に切欠凹部をくり抜き形成する(いわゆるザグリ)ことも可能であるが、導体パターンを形成した結晶転移型の熱可塑性樹脂からなるシート状の基材を、複数枚積層した状態で、加熱しながら積層方向に加圧することにより全体を一体化するようにした製造方法にあっては、基材のうち実装部とは反対面側を構成する1枚以上の基材に、該実装部に対応した位置に予め切欠部を形成しておくことにより、切欠凹部を有した多層配線基板を製造することが可能となる(請求項2の発明)。これによれば、多層配線基板の形成と同時に切欠凹部も形成されるようになり、切欠凹部の形成をより簡単に済ませることができる。
【0011】
【発明の実施の形態】
以下、本発明の一実施例について、図1ないし図3を参照しながら説明する。図1は、本実施例に係る多層配線基板11の表面の実装面(図で上面)に、例えばCSPタイプの表面実装部品12を実装した様子を模式的に示している。前記表面実装部品12は、矩形状のパッケージ12aの下面に多数個の電極(図示せず)をアレイ状に有し、それら各電極に、はんだバンプ(実装によりはんだ接合部13となる)を設けて構成されている。
【0012】
これに対し、前記多層配線基板11は、樹脂材料からなる多数の絶縁層14を積層して構成されており、図示はしないが、それら絶縁層14間には、例えば銅箔からなる導体パターンが形成されていると共に、要所には層間の導体パターンを電気的に接続する層間接続部が設けられている。このとき、多層配線基板11の実装面(上面)に導体パターンが設けられるのであるが、図2(a)にも示すように、その実装面の中央部が、前記表面実装部品12が実装される矩形状の実装部15とされ、その実装部15に位置して、前記表面実装部品12のはんだバンプに対応した多数個のランド15aが形成されている。
【0013】
そして、この多層配線基板11の前記実装部15とは反対面側つまり図で下面側には、該実装部15に対応した位置(真下の位置)に、矩形状の切欠凹部16が形成されている。この場合、切欠凹部16は、一部の絶縁層14図では下面側3層分の絶縁層14を四角く切欠いた(くり抜いた)形態に形成されている。これにて、実装部15は他の部分と比べて薄肉状とされるのである。尚、実際には、絶縁層14の層数は十数層〜数十層にもなるが、ここでは便宜上6層で図示している。
【0014】
ここで、上記した多層配線基板11の製造方法について、図2及び図3も参照して簡単に述べる。まず、図2(a)に示すように、各絶縁層14を構成する結晶転移型の熱可塑性樹脂からなるシート(フィルム)状の基材17が製作される。この基材17は、例えばポリエーテルエーテルケトン(PEEK)樹脂35〜65重量%と、ポリエーテルイミド(PEI)樹脂35〜65重量%とを含んだ材質からなり、多層配線基板11の大きさに対応した矩形状をなし、厚みが25〜75ミクロンのフィルム状とされている。この樹脂材料は、図3に示すように、例えば200℃付近では軟質となるが、それより低い温度でも高い温度でも硬質となる(さらに高い温度(約400℃)では溶解する)性状を呈し、また、高温から温度低下する際には、200℃付近でも硬質を保つものとなっている。
【0015】
このとき、基材17のうち下面側の絶縁層14を構成する複数枚(図では3枚)の基材17には、多層配線基板11の切欠凹部16となる矩形状の切欠部(開口部)17aが予め形成されている。また、詳しく図示はしないが、この基材17の表面には、銅箔が貼付けられており、エッチングにて導体パターンが形成される。このとき、最表面の絶縁層14を構成する基材17については、実装部15のランド15aが形成されることになる。さらに、図示はしないが、基材17のうちの要所には、層間接続部を構成するためのビアホールが形成されると共にそのビアホール内に導電ペーストが充填される。
【0016】
次に、これら基材17が、図2(a)に示すように積層され、真空加圧プレス機により、200〜350℃に加熱されながら、0.1〜10Mpaの圧力で加圧される。この場合、上記材質の基材17は、図3に示すような温度に対する弾性率変化を生ずるので、この熱プレスの工程により、各基材17が熱により一旦軟化した状態で加圧されることによって相互に融着し、その後結晶化(硬化)して一体化するようになり、多層の絶縁層14が形成されるのである。
【0017】
また、導体パターンが絶縁層14間に埋込まれた形態となると共に、ビアホール内の導電ペーストが硬化して層間接続部が形成され、以て、図1及び図2(b)に示すような多層配線基板11が形成されるのである。そしてこのとき、下面側の複数の絶縁層14を構成する基材17に予め形成された切欠部17aにより、実装部15に対応した矩形状の切欠凹部16が形成されるようになる。
【0018】
この後、多層配線基板11に対する表面実装部品12の実装が行われる。この実装は、多層配線基板11の実装面のランド15aにはんだペーストを印刷により塗布し、各ランド15a上に各はんだバンプが載置されるように表面実装部品12を位置合せ状態で搭載(仮接合)し、リフロー炉を通してリフロー加熱することにより行われる。これにて、図1及び図2(b)に示すように、表面実装部品12が、はんだ接合部13により実装部15上にはんだ付けされるようになるのである。尚、このリフロー加熱の工程では、多層配線基板11は、300℃程度に加熱されるが、図3に示すように、この温度では各絶縁層14が軟化することはなく、結晶状態が保たれる。
【0019】
さて、上記構成においては、多層配線基板11の実装部15の真下部分に切欠凹部16が設けられていることにより、実装部15部分の厚みが他の部分よりも薄くなり、その部分だけ剛性が下がることになる。このため、多層配線基板11と表面実装部品12との熱膨張係数差に起因してはんだ接合部13に作用する応力を、その薄肉部分の変形により吸収することができ、はんだ接合部13の歪を低減することができる。
【0020】
ちなみに、本発明者は、BGAタイプの部品を多層配線基板に実装し、−30度〜105度の熱衝撃加速試験を実施したところ、その実験データから、熱疲労クラックオープン(累積故障率B10)に至るサイクル数と、はんだ接合部の歪値との間には、以下の関係があることが判明した。
【0021】
Y=41.7×10
ただし、Y:サイクル数の伸び(サイクル)
X:はんだ接合部の歪値の低減量(%)
この結果から、はんだ接合部13の歪値を低減することにより、製品寿命を大幅に向上させることができることが明らかとなった。
【0022】
尚、はんだ接合部13の歪みを吸収する観点からは、実装部15における基板の厚みは、より薄い方が望ましいが、あまりに薄くし過ぎると、今度は部品12の自重による自重反りが発生し、はんだ接合部13のいわゆる初期的オープンに至る虞が生ずる。従って、実装部15の基板の厚み(言い換えれば切欠凹部16の深さ)は、基板11の弾性率(材質)、表面実装部品12の重量、実装面積等を考慮して、初期的なオープンが起こらない範囲で極力薄くするように設定することが望ましい。
【0023】
このように本実施例の多層配線基板11によれば、例えば車載用に用いられて大きな温度サイクルを受けても、はんだ接合部13がその影響を受けにくくなり、クラックが発生するといったことを抑制でき、表面実装部品12の接続信頼性の向上を図ることができて製品寿命を長くすることができる。しかも、多層配線基板11のうち実装部15に対応した部分に切欠凹部16を設けるという、簡単で安価な構成で済ませることができるものである。
【0024】
また、本実施例の多層配線基板11の製造方法によれば、導体パターンを形成した結晶転移型の熱可塑性樹脂からなるシート状の基材17を、複数枚積層した状態で、熱プレスにより全体を一体化して多層配線基板11を製造する方法にあって、基材17のうち実装部15とは反対面側を構成する1枚以上の基材17に、該実装部15に対応した位置に予め切欠部17aを形成しておくようにしたので、上記のような優れた多層配線基板11を容易に製造することができると共に、多層配線基板11の形成と同時に切欠凹部16も形成されるようになり、切欠凹部16の形成をより簡単に済ませることができるといった利点を得ることができる。
【0025】
尚、上記実施例では、予め切欠部17aを形成した基材17を用いて多層配線基板11に切欠凹部16を形成するようにしたが、多層配線基板を構成した後に切欠凹部をくり抜き形成する(いわゆるザグリ)ようにしても良い。また、上記実施例では、多層配線基板の製造方法として、結晶転移型の熱可塑性樹脂からなるシート状の基材を複数枚積層した状態で、熱プレスにより全体を一体化する方法を採用したが、ガラスエポキシ樹脂などを用いて製造された多層配線基板にあっても、切欠凹部を設ける構成とすることにより、同様の効果を得ることができる。
【0026】
その他、本発明は上記した実施例に限定されるものではなく、例えば表面実装部品としてはCSPタイプのものに限らず、BGAタイプ、QFPタイプ、MCMタイプなど各種パッケージの表面実装部品全般に本発明を適用することができ、また、多層配線基板の用途としても、車載用に限らず、広い用途に用いることができるなど、要旨を逸脱しない範囲内で適宜変更して実施し得る。
【図面の簡単な説明】
【図1】本発明の一実施例を示すもので、多層配線基板に表面実装部品を実装した様子を示す縦断正面図(図2(b)のA−A線に沿う縦断面図)
【図2】多層配線基板の製造方法を説明するための斜視図
【図3】基材の温度変化と弾性率との関係を示す図
【図4】従来例を示すもので、多層配線基板の反り変形の様子を誇大的に示す図
【図5】はんだ接合部にクラックが生じた様子を示す拡大縦断面図
【符号の説明】
図面中、11は多層配線基板、12は表面実装部品、13ははんだ接合部、14は絶縁層、15は実装部、15aはランド、16は切欠凹部、17は基材、17aは切欠部を示す。
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multi-layer wiring board including a multi-layer insulating layer having a conductor pattern between layers and having a mounting portion on a surface of which a surface mounting component is soldered, and a method for manufacturing the same.
[0002]
[Prior art]
For example, in a mounting board to be incorporated in various small electronic devices, a multilayer wiring board is provided with a small and high-density surface mounting component, for example, a narrow pitch such as a BGA (Ball Grid Array) type or a CSP (Chip Size Package) type. A configuration for mounting a multi-terminal electronic component is employed. Further, the multilayer wiring board has a multilayer insulating layer mainly composed of a thermosetting resin such as an epoxy resin, for example, and has a conductor pattern between surfaces and layers, and has a land formed on the surface. The solder bumps of the surface mount component are joined (soldered).
[0003]
[Problems to be solved by the invention]
However, in such a mounting board, there is a situation that a deformation behavior such as a warp deformation occurs due to a temperature change due to a difference in thermal expansion coefficient between the multilayer wiring board and the electronic component. As an example, when an electronic component (IC chip) 2 is solder-bonded to the surface (upper surface) of the multilayer wiring board 1 by a solder joint (solder bump) 3 as shown exaggeratedly in FIG. At a high temperature, the multilayer wiring board 1 is warped so as to be upwardly convex as shown in FIG. 3A, and at a low temperature, as shown in FIG. Warp deformation occurs.
[0004]
For this reason, a large stress acts on the solder joint portion 3, particularly the solder joint portion 3 located at the outermost periphery, and there is a possibility that so-called thermal fatigue crack open may occur. That is, as shown in an enlarged manner in FIG. 5, cracks C tend to occur at the interface of the solder joint 3 with the land 1a of the multilayer wiring board 1 and at the interface with the electrode 2a of the package of the electronic component 2, and as a result, There was a problem that connection reliability was lowered, such as peeling.
[0005]
In particular, when used in an in-vehicle environment, such as an ECU for car navigation or engine control, a car air conditioner, an in-vehicle communication device, or a car audio, the temperature cycle throughout the year is, for example, -30 ° C to 85 ° C. The temperature range is wide, and thermal shock stress has a significant effect on product life.
[0006]
Therefore, as a countermeasure, an underfill (sealing resin) is poured into the lower surface side of the electronic component 2 (a gap portion with the multilayer wiring board 1) and hardened, so that the solder joint 3 is formed. There are a method of extending the product life by suppressing the distortion, and a method of extending the product life by reducing the distortion by reducing the rigidity of the interposer of the electronic component 2. However, these countermeasures have a problem that extra steps and materials are required for mounting the electronic component 2 to increase the cost, or the electronic component 2 itself becomes expensive.
[0007]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multilayer wiring board capable of improving the connection reliability of surface-mounted components and having a simple and inexpensive configuration, and a method of manufacturing the same. To provide.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, a multilayer wiring board according to the present invention has a notch in which a part of an insulating layer is cut out at a position corresponding to the mounting portion on a surface opposite to a mounting portion to which a surface mount component is soldered. The present invention is characterized in that a concave portion is provided (the invention of claim 1). According to this, the provision of the cutout concave portion makes the thickness of the mounting portion of the surface mount component of the substrate thinner than other portions, and the rigidity is reduced only at that portion. Therefore, the stress acting on the solder joint due to the difference in the thermal expansion coefficient between the multilayer wiring board and the electronic component can be absorbed by the deformation of the low rigidity portion.
[0009]
As a result, the connection reliability of the surface mount component can be improved, the product life can be prolonged, and a simple and inexpensive configuration in which a cutout recess is provided can be achieved. In addition, from the viewpoint of absorbing the distortion of the solder joint, it is desirable that the thickness of the board in the mounting part is thinner. Is likely to result in a so-called initial opening. Therefore, the thickness of the board in the mounting portion (in other words, the depth of the notch recess) is set within a range in which initial opening does not occur in consideration of the elastic modulus (material) of the board, the weight of the surface mount component, the mounting area, and the like. It is desirable to set as thin as possible.
[0010]
By the way, as a method of manufacturing the above-mentioned multilayer wiring board, after laminating the multilayer insulating layers, it is possible to cut out and form a cutout recess (so-called counterbore) on the side opposite to the mounting portion. In a manufacturing method in which a sheet-shaped substrate made of a formed crystal transition type thermoplastic resin is laminated, a plurality of sheets are laminated, and the whole is integrated by pressing in the laminating direction while heating. By forming a notch in advance at a position corresponding to the mounting part on at least one base material constituting the side opposite to the mounting part of the base, a multilayer wiring board having a notch concave part is formed. It can be manufactured (the invention of claim 2). According to this, the notch recess is formed at the same time as the formation of the multilayer wiring board, and the formation of the notch recess can be completed more easily.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 schematically shows a state where, for example, a CSP type surface mounting component 12 is mounted on a mounting surface (upper surface in the figure) of a surface of a multilayer wiring board 11 according to the present embodiment. The surface mount component 12 has a large number of electrodes (not shown) in an array on the lower surface of a rectangular package 12a, and a solder bump (which becomes a solder joint 13 by mounting) is provided on each of these electrodes. It is configured.
[0012]
On the other hand, the multilayer wiring board 11 is formed by laminating a large number of insulating layers 14 made of a resin material. Although not shown, a conductor pattern made of, for example, copper foil is provided between the insulating layers 14. In addition to being formed, an interlayer connection portion for electrically connecting the conductive patterns between the layers is provided at a key point. At this time, the conductor pattern is provided on the mounting surface (upper surface) of the multilayer wiring board 11, and as shown in FIG. 2A, the center of the mounting surface is mounted with the surface mounting component 12. A plurality of lands 15 a corresponding to the solder bumps of the surface-mounted component 12 are formed at the mounting portion 15.
[0013]
On the opposite side of the multilayer wiring board 11 from the mounting portion 15, that is, on the lower surface side in the figure, a rectangular cutout recess 16 is formed at a position corresponding to the mounting portion 15 (a position directly below). I have. In this case, the cutout recess 16 is formed in a form in which the insulating layer 14 corresponding to the lower three layers in the lower part of the insulating layer 14 in FIG. Thus, the mounting portion 15 is made thinner than the other portions. In practice, the number of the insulating layers 14 may be as many as ten to several tens, but here, six layers are shown for convenience.
[0014]
Here, a method of manufacturing the above-described multilayer wiring board 11 will be briefly described with reference to FIGS. First, as shown in FIG. 2A, a sheet (film) -like base material 17 made of a crystal transition type thermoplastic resin constituting each insulating layer 14 is manufactured. The base material 17 is made of a material containing, for example, 35 to 65% by weight of a polyetheretherketone (PEEK) resin and 35 to 65% by weight of a polyetherimide (PEI) resin. It has a corresponding rectangular shape and a film thickness of 25 to 75 microns. As shown in FIG. 3, this resin material becomes soft at, for example, around 200 ° C., but becomes hard at lower and higher temperatures (dissolves at a higher temperature (about 400 ° C.)). Further, when the temperature is lowered from a high temperature, the hardness is maintained even at around 200 ° C.
[0015]
At this time, a plurality of (three in the figure) base materials 17 constituting the lower insulating layer 14 of the base material 17 are provided with rectangular cutouts (opening portions) serving as cutout recesses 16 of the multilayer wiring board 11. ) 17a are formed in advance. Although not shown in detail, a copper foil is stuck on the surface of the base material 17, and a conductor pattern is formed by etching. At this time, the lands 15a of the mounting portion 15 are formed on the base material 17 constituting the outermost insulating layer 14. Further, although not shown, via holes for forming interlayer connection portions are formed at important points of the base material 17, and the via holes are filled with a conductive paste.
[0016]
Next, these base materials 17 are laminated as shown in FIG. 2A, and are pressed by a vacuum press at a pressure of 0.1 to 10 MPa while being heated to 200 to 350 ° C. In this case, since the base material 17 made of the above-described material undergoes a change in elastic modulus with respect to temperature as shown in FIG. 3, it is necessary to press each base material 17 in a state in which each base material 17 has been once softened by heat. Are fused to each other, and then crystallized (hardened) to be integrated, thereby forming a multilayer insulating layer 14.
[0017]
In addition, the conductive pattern is embedded between the insulating layers 14, and the conductive paste in the via hole is cured to form an interlayer connection portion. Thus, as shown in FIG. 1 and FIG. Thus, the multilayer wiring board 11 is formed. At this time, the cutout portion 17 a formed in advance on the base material 17 constituting the plurality of insulating layers 14 on the lower surface forms a rectangular cutout concave portion 16 corresponding to the mounting portion 15.
[0018]
Thereafter, mounting of the surface mount component 12 on the multilayer wiring board 11 is performed. In this mounting, a solder paste is applied to the lands 15a on the mounting surface of the multilayer wiring board 11 by printing, and the surface mount components 12 are mounted in an aligned state so that the solder bumps are mounted on the lands 15a (temporarily). Bonding) and reflow heating through a reflow furnace. As a result, as shown in FIGS. 1 and 2B, the surface mount component 12 is soldered onto the mounting portion 15 by the solder joint portion 13. In this reflow heating step, the multilayer wiring board 11 is heated to about 300 ° C., but as shown in FIG. 3, at this temperature, the insulating layers 14 do not soften and the crystalline state is maintained. It is.
[0019]
Now, in the above configuration, the notch 16 is provided directly below the mounting portion 15 of the multilayer wiring board 11, so that the thickness of the mounting portion 15 is thinner than other portions, and only that portion has rigidity. Will go down. For this reason, the stress acting on the solder joint 13 due to the difference in the thermal expansion coefficient between the multilayer wiring board 11 and the surface mount component 12 can be absorbed by the deformation of the thin portion, and the distortion of the solder joint 13 can be reduced. Can be reduced.
[0020]
By the way, the present inventor mounted a BGA type component on a multilayer wiring board and performed a thermal shock acceleration test at -30 to 105 degrees. From the experimental data, the thermal fatigue crack open (cumulative failure rate B10) It has been found that the following relationship exists between the number of cycles leading to and the strain value of the solder joint.
[0021]
Y = 41.7 × 10 3 X
Where Y is the number of cycles (cycle)
X: Reduction amount of strain value of solder joint (%)
From this result, it has been clarified that the product life can be significantly improved by reducing the strain value of the solder joint 13.
[0022]
In addition, from the viewpoint of absorbing the distortion of the solder joint 13, it is desirable that the thickness of the substrate in the mounting portion 15 is thinner. However, if the thickness is too thin, the self-weight warpage due to the own weight of the component 12 occurs. There is a possibility that the solder joint 13 may be so-called initially opened. Therefore, the thickness of the substrate of the mounting portion 15 (in other words, the depth of the notch 16) is determined in consideration of the elastic modulus (material) of the substrate 11, the weight of the surface mount component 12, the mounting area, and the like. It is desirable to set as thin as possible within the range that does not occur.
[0023]
As described above, according to the multilayer wiring board 11 of the present embodiment, even if the multilayer wiring board 11 is used for a vehicle and undergoes a large temperature cycle, the solder joint portion 13 is hardly affected by the temperature cycle, and the occurrence of cracks is suppressed. As a result, the connection reliability of the surface mount component 12 can be improved, and the product life can be extended. In addition, a simple and inexpensive configuration in which the notch recess 16 is provided in a portion of the multilayer wiring board 11 corresponding to the mounting portion 15 can be achieved.
[0024]
Further, according to the method of manufacturing the multilayer wiring board 11 of the present embodiment, a plurality of sheet-like base materials 17 made of a crystal transition type thermoplastic resin having a conductor pattern formed thereon are laminated by a hot press. In a method of manufacturing the multilayer wiring board 11 by integrating the above-mentioned components into one or more base materials 17 constituting the opposite side of the base material 17 from the mounting portion 15 at a position corresponding to the mounting portion 15. Since the notch 17a is formed in advance, the excellent multilayer wiring board 11 as described above can be easily manufactured, and the notch recess 16 is formed simultaneously with the formation of the multilayer wiring board 11. Therefore, there is an advantage that the formation of the cutout recess 16 can be more easily completed.
[0025]
In the above-described embodiment, the cutout recess 16 is formed in the multilayer wiring board 11 using the base material 17 in which the cutout 17a has been formed in advance. However, after the multilayer wiring board is formed, the cutout recess is cut out ( (So-called counterbore). Further, in the above embodiment, as a method of manufacturing a multilayer wiring board, a method in which a plurality of sheet-shaped substrates made of a crystal transition type thermoplastic resin are laminated, and the whole is integrated by a hot press, is employed. Even in a multilayer wiring board manufactured using a glass epoxy resin or the like, a similar effect can be obtained by providing a cutout recess.
[0026]
In addition, the present invention is not limited to the above-described embodiments. For example, the present invention is not limited to CSP type surface mount components, but is applicable to various surface mount components of various packages such as BGA type, QFP type, and MCM type. In addition, the application of the multilayer wiring board is not limited to the on-vehicle use, but can be used for a wide range of uses.
[Brief description of the drawings]
FIG. 1 shows an embodiment of the present invention, and is a longitudinal sectional front view showing a state where surface-mounted components are mounted on a multilayer wiring board (longitudinal sectional view along line AA in FIG. 2 (b)).
FIG. 2 is a perspective view for explaining a method of manufacturing a multilayer wiring board; FIG. 3 is a view showing a relationship between a temperature change of a substrate and an elastic modulus; FIG. 4 is a view showing a conventional example; Figure showing exaggerated warpage deformation. FIG. 5 is an enlarged vertical sectional view showing a state in which a crack has occurred in a solder joint.
In the drawing, 11 is a multilayer wiring board, 12 is a surface mount component, 13 is a solder joint, 14 is an insulating layer, 15 is a mounting portion, 15a is a land, 16 is a cutout recess, 17 is a base material, and 17a is a cutout portion. Show.

Claims (2)

層間に導体パターンを有する多層の絶縁層を備えて構成されると共に、表面に表面実装部品がはんだ接合される実装部を備える多層配線基板において、
前記実装部とは反対面側の該実装部に対応した位置に、一部の絶縁層を切欠いた切欠凹部を設けたことを特徴とする多層配線基板。
In a multilayer wiring board comprising a multilayer insulating layer having a conductor pattern between layers and having a mounting portion on the surface of which a surface mount component is soldered,
A multilayer wiring board, characterized in that a cutout recessed by cutting out a part of an insulating layer is provided at a position corresponding to the mounting portion on the side opposite to the mounting portion.
層間に導体パターンを有する多層の絶縁層を備えて構成されると共に、表面に表面実装部品がはんだ接合される実装部を備える多層配線基板を製造するための方法であって、
導体パターンを形成した結晶転移型の熱可塑性樹脂からなるシート状の基材を、複数枚積層した状態で、加熱しながら積層方向に加圧することにより全体を一体化するようになっていると共に、
前記基材のうち前記実装部とは反対面側を構成する1枚以上の基材に、該実装部に対応した位置に予め切欠部を形成しておくことを特徴とする多層配線基板の製造方法。
A method for manufacturing a multilayer wiring board comprising a multilayer insulating layer having a conductor pattern between layers and having a mounting portion on the surface of which a surface mounting component is soldered,
A sheet-shaped substrate made of a crystal transition type thermoplastic resin having a conductive pattern formed thereon, in a state where a plurality of sheets are laminated, and the whole is integrated by pressing in the laminating direction while heating,
Manufacturing a multilayer wiring board, wherein a notch is formed in advance at a position corresponding to the mounting portion on at least one base material constituting a surface opposite to the mounting portion of the base material. Method.
JP2002310979A 2002-10-25 2002-10-25 Multilayer wiring board and its manufacturing method Pending JP2004146656A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094419A (en) * 2007-10-12 2009-04-30 Fujitsu Ltd Circuit substrate and semiconductor device
JP2013105840A (en) * 2011-11-11 2013-05-30 Shinko Electric Ind Co Ltd Semiconductor package, method for manufacturing the same, and semiconductor device
JP2013175567A (en) * 2012-02-24 2013-09-05 Mitsubishi Electric Corp Printed wiring board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094419A (en) * 2007-10-12 2009-04-30 Fujitsu Ltd Circuit substrate and semiconductor device
JP2013105840A (en) * 2011-11-11 2013-05-30 Shinko Electric Ind Co Ltd Semiconductor package, method for manufacturing the same, and semiconductor device
JP2013175567A (en) * 2012-02-24 2013-09-05 Mitsubishi Electric Corp Printed wiring board

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