JP2004030897A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an erroneous writing occurs when the threshold voltage of a memory cell becomes equal to or less than a prescribed voltage after an erasing. <P>SOLUTION: A first sense latch circuit S/L1 is connected to bit lines BLE and BLO through transistors QNH3 and QNL1 and a second sense latch circuit S/L2 is connected to the lines through transistors QNH4 and QNL2. After erasing the data in a memory cell, data are read for excessive erasing detection and the read data are latched to the circuit S/L1. The presence and/or the absence of an excessively erased cell is detected from the latched data. When an excessively erased cell exists, a soft writing is conducted so that the threshold voltage is converged into a prescribed range. <P>COPYRIGHT: (C)2004,JPO

Description

【００３８】
図６乃至図８はそれぞれデータの読み出し、書き込み、消去の動作を示す波形図である。本実施例では読み出しと書き込みにおいて、ＢＬＥを選択、ＢＬＯを非選択としている。
【００３９】
ここで、図４に示すメモリセルＭＣ４を選択する場合について説明する。
【００４０】
先ず、図６を参照して読み出し動作について説明する。選択されたビット線ＢＬＥは信号ＰｅｒＥ　に応じて動作されるプリチャージ回路１２により１．５Ｖに充電され、その後フローティングとされる。この後、非選択ワード線ＷＬ２〜８と選択ゲートＳＧＳ、ＳＧＤは電源電圧Ｖｃｃとされる。選択ワード線は０Ｖである。選択されたメモリセルのデータが“０”であるとき、ビット線は０Ｖに放電され、さもなければビット線は１．５Ｖのままである。
【００４１】
ビット線ＢＬＥの電圧は、信号ＢＬＳＨＦＥによりオンとされるトランジスタＱＮＨ３、信号ＳＢＬ１によってオンとされるトランジスタＱＮＬ１を介して第１のセンスラッチ回路Ｓ／Ｌ１に読み込まれる。したがって、ノードＮ１の電位ははデータが“０”であればローレベル“Ｌ”、データが“１”又は“２”であればハイレベル“Ｈ”となる。
【００４２】
この後、選択されたワード線はＶＧ１（＝１．８Ｖ）とされる。選択されたメモリセルのデータが“１”であれば０Ｖに放電され、“２”であれば１．５Ｖのままとなる。データが“０”であればビット線はすでに０Ｖである。ビット線ＢＬＥの電圧は、トランジスタＱＮＨ３及び信号ＳＢＬ２によってオンとされるトランジスタＱＮＬ２を介して第２のセンスラッチ回路Ｓ／Ｌ２に読み込まれる。したがって、ノードＮ２はデータが“０”又は“１”であれば“Ｌ”、“２”であれば“Ｈ”となる（表１）。これら第１、第２のセンスラッチ回路Ｓ／Ｌ１、Ｓ／Ｌ２にラッチされたデータは、カラムデコーダ１０の動作に応じてシリアルにＩＯ線に読み出される。
【００４３】
次に、図７を参照して書き込み動作について説明する。電源投入時、チップが正常動作するために十分な電圧に達するとパワーオン信号Ｐｏｎが“Ｈ”となる。この信号を利用して３値のセンスアンプ兼ラッチ回路４のラッチデータＮ１，Ｎ２はともに“Ｌ”とされる。書き込みデータを入力するためのコマンドが供給されると、このコマンド信号を用いて、ラッチデータＮ１，Ｎ２はともに反転し“Ｈ”となる。
【００４４】
選択されたビット線ＢＬＥは書き込みデータ“０”〜“２”に応じてそれぞれ電源電圧Ｖｃｃ、ＶＤ３−Ｖｔ（＝１Ｖ）、０Ｖとされる。非選択のビット線ＢＬＯには、プリチャージ回路１２を介してデータを変更しないための電圧Ｖｃｃが印加される。この後、選択ゲートＳＧＤは電源電圧Ｖｃｃに、ＳＧＳは０Ｖに、選択ワード線ＷＬ１はＶＰＰ（＝２０Ｖ）に、ＷＬ２は０Ｖに、その他の非選択ワード線ＷＬ３〜ＷＬ８はＶＭ１０（＝１０Ｖ）にそれぞれ設定される。なお、ここで、センスアンプ兼ラッチ回路４からビット線に出力される電圧のうち、０Ｖが書き込み電圧、電源電圧Ｖｃｃが非書き込み電圧に相当する。
【００４５】
ビット線に０Ｖ又は１Ｖが印加された選択メモリセルでは、ゲート・チャネル間電圧が高いため、トンネル電流が流れてメモリセルの閾値電圧が上昇する。ビット線が０Ｖである方が１Ｖである方よりトンネル電流が多く流れるため、閾値電圧はより高くなる。電源電圧Ｖｃｃが印加された選択メモリセルはゲート・チャネル間電圧が低いためトンネル電流は流れず、データ“０”を保持する。
【００４６】
次に、図８を参照して消去動作について説明する。消去コマンドが入力されると、メモリセルアレイ２のウェルにはＶＰＰ（＝２０Ｖ）が印加される。選択されたメモリセルのゲートは０Ｖとされるため、トンネル電流が書き込み時とは反対方向に流れ、メモリセルの閾値電圧は降下する。一方、非選択のメモリセル及び選択トランジスタのゲートはフローティングとされるため、メモリセルアレイ２のウェルとともにＶＰＰ近傍まで上昇する。このため、トンネル電流は流れず、閾値電圧の変動はない。
【００４７】
上記のように、書き込み及び読み出しは３値のセンスアンプ兼ラッチ回路４が共有する２カラムのうちの一方のみ（例えばＢＬＥのみ）に接続される。消去動作では、ＢＬＥとＢＬＯの２カラムが同時に選択され、ブロック単位で消去される。
【００４８】
＜消去ベリファイリード＞
次に、消去後、メモリセルの閾値が所定の電圧以下に消去されているかを調べる消去ベリファイリードが行われる。
【００４９】
図９は、消去ベリファイリード動作を示すタイミングチャートである。ブロック単位で消去が行われる場合、１ブロック内のメモリセル（例えばワード線ＷＬ１〜ＷＬ８で選択されるメモリセル）に対して、奇数ページと偶数ページの２回に分けてベリファイリードが行われる。
【００５０】
先ず、偶数ページ（例えば図４のビット線ＢＬＥに接続されたメモリセル）についてベリファイリードを行い、読み出したデータを第１のセンスラッチ回路Ｓ／Ｌ１に保持する。次に、奇数ページ（例えば図４のビット線ＢＬＯに接続されたメモリセル）についてベリファイリードを行い、読み出したデータを第２のセンスラッチ回路Ｓ／Ｌ２に保持する。
【００５１】
すなわち、先ず、図９に示すように、ビット線ＢＬＥを１．５Ｖにプリチャージする。この後、時刻ｔ１において、選択ゲートＳＧＳ、ＳＧＤを電源電圧Ｖｃｃ、ワード線ＷＬ１〜ＷＬ８を０Ｖにすると、メモリセルが十分消去されている場合、全メモリセルがオンとなるためビット線の電位は放電されるため、ビット線の電位は０Ｖとなる。また、消去不十分の場合、オフ状態のメモリセルが存在するため、ビット線の電位は放電されず１．５Ｖに保持される。
【００５２】
時刻ｔ２に信号ＢＬＳＨＦＥが１．５Ｖとなり、トランジスタＱＮＨ３がオンすると、ビット線の電位が３値のセンスアンプ兼ラッチ回路４内に転送される。その後、信号ＳＢＬ１が“Ｈ”になると、トランジスタＱＮＬ１がオンし、データがノードＮ１に転送され、第１のセンスラッチ回路Ｓ／Ｌ１によりセンスされる。このように偶数ページのデータは第１のセンスラッチ回路Ｓ／Ｌ１に保持される。偶数ページの読み出し中は、ビット線間カップリングノイズを低減するため、ビット線ＢＬＯは０Ｖに保持される。
【００５３】
続いて奇数ページ（例えば図４のビット線ＢＬＯに接続されるメモリセル）についてベリファイリードが行われる。先ず、時刻ｔ３において、ビット線ＢＬＯが１．５Ｖにプリチャージされる。この後、時刻ｔ４において、選択ゲートＳＧＳ、ＳＧＤが電源電圧Ｖｃｃ、ワード線ＷＬ１〜ＷＬ８が０Ｖとされると、メモリセルが十分消去されている場合、ビット線は０Ｖとなり、消去不十分の場合、１．５Ｖを保つ。時刻ｔ５において、信号ＢＬＳＨＦＯが１．５Ｖになり、トランジスタＱＮＨ４がオンすると、ビット線ＢＬＯの電位が３値のセンスアンプ兼ラッチ回路４内に転送される。その後、信号ＳＢＬ２が“Ｈ”となり、トランジスタＱＮＬ２がオンすると、データがノードＮ２に転送され、第２のセンスラッチ回路Ｓ／Ｌ２によりセンスされる。このように奇数ページのデータは第２のセンスラッチ回路Ｓ／Ｌ２に保持される。奇数ページの読み出し中は、ビット線間カップリングノイズを低減するために、ビット線ＢＬＥは０Ｖに保持される。
【００５４】
本発明では、消去状態の閾値分布を０Ｖ以下であり、かつ−３Ｖ以上であるように制御する。閾値電圧に下限（−３Ｖ）を設ける理由は、書き込み時に、選択した制御ゲートの隣に位置し、ゲートが０Ｖにバイアスされたメモリセルをオフさせ、誤書き込みを防止するためである。
【００５５】
図１０は、一連の消去ベリファイリード動作を示している。上述したように、選択したブロック内の、全てのメモリセルが十分に消去された後（ＳＴ１〜３）、メモリセルの閾値電圧が所定の電圧以上か調べる過消去検知リードを行う（ＳＴ４）。この結果、閾値電圧が−３Ｖよりも小さい過消去状態のメモリセルがある場合、閾値電圧を−３Ｖよりも高くする、ソフト書き込みを行う（ＳＴ５、ＳＴ６）。
【００５６】
以下で、過消去検知リード、及びソフト書き込みについて説明する。
【００５７】
＜過消去検知リード＞
図１１に示すように、過消去検知リード動作は、先ず、ビット線ＢＬＥにセンスアンプ兼ラッチ回路４を接続し、ワード線ＷＬ８で選択されるメモリセルからワード線ＷＬ７、ＷＬ６、…、ＷＬ１で選択されるメモリセルまで順次過消去検知リードを行う（ＳＴ１１〜ＳＴ１８）。続いて、ビット線ＢＬＯにセンスアンプ兼ラッチ回路４を接続し、ワード線ＷＬ８で選択されるメモリセルからＷＬ７、ＷＬ６、…、ＷＬ１で選択されるメモリセルまで順次過消去検知リードを行う（ＳＴ１９〜ＳＴ２６）。
【００５８】
図１２は、ビット線ＢＬＥにセンスアンプ兼ラッチ回路４を接続し、ワード線ＷＬ８で選択されるメモリセルの過消去検知リード動作を示している。先ず、時刻ｔｃｓ１　において、選択ビット線ＢＬＥを０Ｖにする。過消去検知リード中、非選択ビット線ＢＬＯは電圧Ｖｂｌ（例えばＶｃｃ）に保持され、ビット線間カップリングノイズを除去する。時刻ｔｃｓ２　において、選択したワード線ＷＬ８を０Ｖ、非選択ワード線を電圧Ｖｒｅａｄ、選択ゲートＳＧＳ、ＳＧＤを電圧Ｖｒｅａｄとする。電圧Ｖｒｅａｄは例えば４．５Ｖであるが、Ｖｒｅａｄ＝Ｖｃｃとしてもよい。ソース線は電圧Ｖｓ（例えばＶｃｃ）とする。
【００５９】
以下では電圧ＶｓがＶｃｃの場合を例に説明する。選択ゲートの電圧を上げると、選択したメモリセルＭＣ８の閾値電圧に従って、ビット線の電位が設定される。すなわち、電源電圧Ｖｃｃを３Ｖとすると、ＭＣ８の（バックゲートバイアスが−３Ｖ時の）閾値電圧が−３Ｖ以下に過剰消去されている場合、ビット線は３Ｖになる。
【００６０】
一方、バックゲートバイアスが−３Ｖ時の閾値電圧が例えば−２．５Ｖの場合、ビット線は２．５Ｖになる。ここでは、ビット線の電圧がセンスノードＮ４に転送されるように信号ＢＬＳＨＦＥは例えば５Ｖにすればよい。この間、キャパシタとしてのトランジスタＱＮＨ５に印加される電圧Ｖｓｅｎ　は例えばＶｃｃ／３である。電圧Ｖｓｅｎ　は、書き込み、消去、の間は所望の電圧、例えば０Ｖ又はＶｃｃに固定すればよい。
【００６１】
その後、時刻ｔｃｓ３　において、電圧Ｖｓｅｎ　がＶｃｃ／３、例えば１Ｖから０Ｖになる。この間、信号ＢＬＳＨＦＥは電圧Ｖｃｐ、例えば２Ｖである。メモリセルが過消去されている場合、トランジスタＱＮＨ３はオフするためノードＮ４はフローティング状態となる。この場合、キャパシタを構成するトランジスタＱＮＨ５の容量は、ノードＮ４に寄生する他の容量よりも十分大きいため、ノードＮ４の電位は３Ｖから２Ｖとなる。
【００６２】
一方、メモリセルが過消去されていない場合、ノードＮ４の電位は１．５Ｖから０．５Ｖになる。信号ＢＬＳＨＦＥの電位を２Ｖとしているため、ノードＮ４の電位は０．５Ｖより低くならない。
【００６３】
時刻ｔｃｓ４　において、信号ＳＢＬ１がハイレベルとなると、ノードＮ４の電位がトランジスタＱＮＬ１を通ってノードＮ１に転送され、時刻ｔｃｓ５　に第１のセンスラッチ回路Ｓ／Ｌ１によりセンスされ、時刻ｔｃｓ６　にラッチされる。過消去したセルがあるか否かはノードＮ１、Ｎ３の電位をＩＯ線に読み出しても良い。あるいは一括検知用トランジスタＱＮＬ７を用いて検知してもよい。すなわち、このトランジスタＱＮＬ７がオンするか否かにより、過消去状態のセルがあるか否かを検出できる。トランジスタＱＮＬ７は各カラムに並列接続されている。まず、配線ＩＤＥＴ１を例えば電源電圧Ｖｃｃにプリチャージし、その後、フローティングとする。この状態で１カラムでも過消去のセルがあると、そのカラムのノードＮ１が“Ｈ”になるため、配線ＩＤＥＴ１は０Ｖに放電され、過消去が検知される。
【００６４】
この後、図１１で示すように、ビット線ＢＬＥ、ワード線ＷＬ７〜ＷＬ１により選択されるメモリセルに対して過消去検知リードが行われる。その後、ビット線ＢＬＯに接続されるメモリセルに対して過消去検知リードが行われる。
【００６５】
図１３は、ビット線ＢＬＯとワード線ＷＬ８により選択されるメモリセルの過消去検知リード動作を示している。この場合、ビット線ＢＬＯから読み出されたデータはトランジスタＱＮＨ４、ＱＮＬ１を介して第１のセンスラッチ回路Ｓ／Ｌ１にラッチされる。この他の動作は、図１２と同様であるため説明は省略する。
【００６６】
上記過消去検知リードにより過消去状態のメモリセルが検知された場合、そのメモリセルに対してソフト書き込みが行われる。
【００６７】
図１４は、ソフト書き込みの動作を示している。ソフト書き込みでは全ビット線が０Ｖに接地され、ワード線ＷＬ１、ＷＬ２…ＷＬ８が電圧Ｖｓｐｇｍ、例えば６Ｖに昇圧される。過消去されたメモリセルは、例えばトンネル酸化膜の厚さが薄いため書き込み易いので、閾値電圧が例えば−５Ｖから−２Ｖになるが、過消去されていないメモリセルは、比較的書き込みにくいため、消去された閾値電圧を保持する。
【００６８】
ソフト書き込み後、図１０に示すように、再度過消去検知リードをしてもよい（ＳＴ４〜ＳＴ５）。また、１回のソフト書き込みで十分に閾値が変化する場合は、図１５のようにソフト書き込み後、過消去検知リードをせずに一連の消去動作を終了してもよい。図１５において、図１０と同一部分には同一符号を付し説明は省略する。
【００６９】
上記実施の形態によれば、データを消去した後、過消去検知リードを行い、過消去状態のセルが検出された場合、ソフト書き込みを行っている。したがって、メモリセルの閾値電圧を所定の例えば−３Ｖから−１Ｖの範囲内に収めることができ、誤書き込みを防止できる。
【００７０】
図１６は、本発明の第２の実施の形態を示すものであり、過消去検知リードの他の例を示している。この場合、先ず、ビット線ＢＬＥをセンスアンプ兼ラッチ回路４に接続し、ワード線ＷＬ８で選択されるメモリセルに対して過消去検知リードを行い（ＳＴ３１）、次に、ビット線ＢＬＯをセンスアンプ兼ラッチ回路４に接続して、ワード線ＷＬ８により選択されるメモリセルに対して過消去検知リードを行う（ＳＴ３２）。この後、ビット線ＢＬＥとワード線ＷＬ７で選択されるメモリセルに対して過消去検知リードを行う（ＳＴ３３）というように、ビット線を交互に選択するとともに、ワード線を交互に選択して過消去検知リードを行ってもよい。
【００７１】
図１７は、本発明の第３の実施の形態を示すものであり、過消去検知リード、及びソフト書き込み動作の他の例を示すものである。
【００７２】
この実施の形態は各ページ毎に過消去検知リード、及びソフト書き込みを行うものである。先ず、ビット線ＢＬＥとワード線ＷＬ８とで選択されるメモリセルについて過消去検知リードを行い、この読み出しデータを第１のセンスラッチ回路Ｓ／Ｌ１にラッチする（ＳＴ４１）。この後、ビット線ＢＬＯとワード線ＷＬ８とで選択されるメモリセルについて過消去検知リードを行い、この読み出しデータを第２のセンスラッチ回路Ｓ／Ｌ２にラッチする（ＳＴ４２）。続いて、これらラッチされたデータより過消去状態のセルがあるか否かが判別され（ＳＴ４３）、過消去状態のセルが有る場合は、ワード線ＷＬ８に接続されたメモリセルに対してソフト書き込みが行われる（ＳＴ４４）。このソフト書き込みでは、ワード線ＷＬ８のみを電圧Ｖｓｐｇｍ、ワード線ＷＬ１、ＷＬ２、…ＷＬ７を０Ｖ、あるいは電源電圧Ｖｃｃとすればよい。
【００７３】
このようにして、ワード線ＷＬ８に対する過消去回復動作を行った後、ワード線ＷＬ７、ＷＬ６…ＷＬ１と順次過消去回復動作を行ってもよい。
【００７４】
また、ビット線ＢＬＯに接続されたメモリセルから読み出したデータを第２のセンスラッチ回路Ｓ／Ｌ２にラッチする場合、図１３に示すタイミングチャートにおいて、信号ＳＢＬ１、ＳＥＮＰ１、ＳＥＮＮ１、ＬＡＴＰ１、ＬＡＴＮ１を活性化する代わりに、ＳＢＬ２、ＳＥＮＰ２、ＳＥＮＮ２、ＬＡＴＰ２、ＬＡＴＮ２を活性化すればよい。第１、第２のセンスラッチ回路Ｓ／Ｌ１、Ｓ／Ｌ２にデータをラッチした状態において、一括検知用のトランジスタＱＮＬ７、ＱＮＬ８を用いることにより、過消去セルを一括検知できる。この際、第１のセンスラッチ回路Ｓ／Ｌ１と第２のセンスラッチ回路Ｓ／Ｌ２のデータを同時に検知する場合には、配線ＩＤＥＴ２をＩＤＥＴ１と同一の信号にしてもよい。
【００７５】
図１８は、本発明の第４の実施の形態を示すものであり、過消去検知リード、及びソフト書き込み動作の他の例を示すものである。図１９は、この実施の形態に適用される回路を示している。
【００７６】
図１９は、図１とほぼ同一の構成であるため、異なる部分についてのみ説明する。すなわち、図１９において、電圧Ｖ_ＳＥが供給される端子とノードＮ４の相互間にはＮＭＯＳトランジスタＱＮ２１、ＱＮ２２が直列接続されている。前記トランジスタＱＮ２１のゲートは前記トランジスタＱＰ３のゲートに接続され、トランジスタＱＮ２２のゲートには信号ｎＶＲＦＹ１が供給されている。
【００７７】
この実施の形態の場合、先ず、ビット線ＢＬＥとワード線ＷＬ８で選択されるメモリセルの過消去検知リードを行い、読み出したデータを第１のセンスラッチ回路Ｓ／Ｌ１にラッチする（ＳＴ５１）。この動作のタイミングチャートは図１２と同様である。その結果、過消去されている場合には、ノードＮ１が“Ｈ”、ノードＮ３が“Ｌ”とされる。過消去されてない場合には、ノードＮ３が“Ｈ”となる。
【００７８】
次に、ビット線ＢＬＯとワード線ＷＬ８で選択されるメモリセルの過消去検知リードを行い、読み出したデータを第１のセンスラッチ回路Ｓ／Ｌ１にラッチする（ＳＴ５２）。
【００７９】
図２０は、この動作のタイミングチャートである。図２０において、図１３と異なるのは、時刻ｔＣＡ３　において、信号ｎＶＥＲＩＦＹ　を０Ｖとし、トランジスタＱｐ２を活性化することである。こうして先に第１のセンスラッチ回路Ｓ／Ｌ１にラッチされているデータが過消去であると、ノードＮ３が“Ｌ”であるため、トランジスタＱＰ３がオンとなり、ビット線ＢＬＯとワード線ＷＬ８により選択されるメモリセルは過消去されていないことが読み出された場合であっても、ノードＮ４は電源電圧Ｖｃｃに充電される。
【００８０】
一方、第１のセンスラッチ回路Ｓ／Ｌにラッチされているデータが過消去でない場合は、ノードＮ３が“Ｈ”であるため、トランジスタＱＰ３がオンすることなく、ビット線ＢＬＯとワード線ＷＬ８で選択されるメモリセルから読み出したデータはそのままノードＮ４に保持される。その後、時刻ｔＣＡ５　において、トランジスタＱＮＬ１がオンとなると、ノードＮ４の電位が第１のセンスラッチ回路Ｓ／Ｌ１にラッチされる。
【００８１】
その後、ビット線ＢＬＥとワード線ＷＬ７で選択されるメモリセルの過消去検知リードを行い、第１のセンスラッチ回路Ｓ／Ｌ１にラッチする（ＳＴ５３）。
【００８２】
図２１は、このタイミングチャートを示している。図２１において、図１２と異なるのは、時間ｔＣＢ３　に信号ｎＶＥＲＩＦＹ　を０Ｖとし、トランジスタＱｐ２を活性化することである。ここで、図２０の場合と同様に、先に第１のセンスラッチ回路Ｓ／Ｌ１にラッチされているデータが過消去であるときのみ、ノードＮ３の電位が“Ｌ”であるため、ノードＮ４は電源電圧Ｖｃｃに充電される。その後、トランジスタＱＮＬ１がオンすると、ノードＮ４の電位が第１のセンスラッチ回路Ｓ／Ｌ１にラッチされる。
【００８３】
この後、ビット線ＢＬＯとワード線ＷＬ７で選択されるメモリセルの過消去検知リードからビット線ＢＬＯとワード線ＷＬ１で選択されるメモリセルの過消去検知リードまでを順次行い、第１のセンスラッチ回路Ｓ／Ｌ１にラッチする（ＳＴ５４〜ＳＴ６６）。
【００８４】
以上のように、過消去検知リードを行った結果、ビット線ＢＬＥ、又はビット線ＢＬＯとＷＬ１からＷＬ８で選択されるメモリセルのうち、１個でも過消去状態のメモリセルがあると、第１のセンスラッチ回路Ｓ／Ｌ１のノードＮ１は“Ｈ”となる。
【００８５】
続いて、第１のセンスラッチ回路Ｓ／Ｌ１にラッチされたデータに基づいて、過消去状態のメモリセルがあるか否かが判別され（ＳＴ６７）、過消去状態のメモリセルが有る場合はソフト書き込みが行われる（ＳＴ６８）。ラッチ状態の検知は、前述したように一括検知用のトランジスタＱＮＬ７を用いればよい。
【００８６】
図２２は、図１８に示すソフト書き込みのタイミングチャートを示している。先ず、ビット線ＢＬＥ、ＢＬＯの電位は、０Ｖに設定される。この後、時刻ｔｓｐｇ１において、信号ｎＶＲＦＹ１が“Ｈ”になることにより、第１のセンスラッチ回路Ｓ／Ｌ１にラッチされたデータに従って、ビット線ＢＬＥ、ＢＬＯの電位が設定される。つまり、過消去セルがある場合、ビット線の電位は０Ｖのままである。過消去セルがない場合、電圧Ｖ_ＳＥを電源電圧ＶｃｃあるいはＶｃｃよりも高電位とするとビット線の電位はＶ_ＳＥからＶｃｃあるいはＶｃｃ−Ｖｔｈ（ＶｔｈはＶ_ＳＥとビット線間に接続されたトランジスタの閾値電圧）に設定される。時刻ｔｓｐｇ２において、ワード線の電位がＶｓｐｇｍ（例えば８Ｖ）となると、過消去セルはチャネルの電位が０Ｖ、制御ゲートの電位がＶｓｐｇｍであるため、閾値電圧が例えば−２Ｖ程度に書き込まれる。一方、過消去セルがない場合、チャネルの電位がＶｃｃであるため、トンネル酸化膜に印加される電圧が緩和され、書き込みは行われない。
【００８７】
上記第４の実施の形態によれば、２つのビット線に接続された１６個のメモリセルに対して、続けて過消去検出リードを行って第１のセンスラッチ回路Ｓ／Ｌ１にデータをラッチし、この後、１回だけ過消去状態のメモリセルがあるか否かを検知している。このため、過消去セルを高速に検知できる。
【００８８】
尚、図１８の動作において、最初の過消去検知リードで、図２１に示すように時刻ｔＣＢ３　に信号ｎＶＥＲＩＦＹ　を“Ｌ”としてトランジスタＱｐ２を活性化してもよい。但し、この場合、ノードＮ４に読み出されたデータの破壊を防止するため、予め第１のセンスラッチ回路Ｓ／Ｌ１のノードＮ１を“Ｌ”、ノードＮ３を“Ｈ”に設定しておく必要がある。
【００８９】
上記各実施の形態において、測定できるメモリセルの閾値電圧の範囲は、バックゲートバイアス効果を含めて閾値電圧が−Ｖｓ（Ｖｓは過消去検知リード時のソース線電位）以上である。例えばＶｓが３．３Ｖとすると、メモリセルの閾値電圧が−３．３Ｖ以下の場合、ビット線の電位は３．３Ｖとなる。したがって、電圧Ｖｓを電源電圧よりも高い、例えば６Ｖとすれば、電源電圧よりも高い絶対値の閾値電圧を読むことができる。但し、この場合、選択するメモリセルと直列接続されたメモリセルのゲートの電圧Ｖｒｅａｄは、例えば７Ｖであるのが望ましい。このように、電圧を設定することにより、閾値電圧分だけ降下することなくソース電位、例えば６Ｖを転送できる。
【００９０】
さらに、ソース線の電位Ｖｓを電源電圧Ｖｃｃとし、電源電圧Ｖｃｃを高くすれば、低い閾値電圧も読み出すことができる。例えば、チップ試験時にＶｃｃを高くすれば、低い閾値電圧も読み出すことができる。
【００９１】
また、過消去検知リード、ソフト書き込み後に、ソフト書き込みしたメモリセルが書き込まれ過ぎていないかを調べてもよい。図２３は、ソフト書き込み後のベリファイ動作を示しており、図１０と同一部分には同一符号を付す。
【００９２】
図２３において、過消去検知リードにより過消去を検知されたメモリセルに対してソフト書き込みを行う（ＳＴ４〜ＳＴ７）。ソフト書き込み終了後、消去ベリファイリードを行い、閾値電圧が高くなり過ぎていないかどうかを検知する（ＳＴ７〜ＳＴ３）。この結果、ソフト書き込みにより閾値電圧が高くなり過ぎている場合には、再び消去を行う（ＳＴ１）。消去ベリファイリードをパスしたメモリセルはその後、過消去検知リードを行う（ＳＴ４）。
【００９３】
図２３のように動作させれば、消去状態の閾値電圧を、所望の上限値と下限値の間に設定することができる。
【００９４】
上記実施例ではビット線電位をノードＮ４に転送した後、電圧Ｖｓｅｎ　を変化させることによりノードＮ４の電位を変化させる。例えばメモリセルの閾値電圧が−２．５Ｖ以下であると、ビット線の電位は２．５Ｖ以上になる。図１２の時刻ｔｃｓ２　に、電圧Ｖｓｅｎ　を１Ｖから０Ｖとすることにより、メモリセルの閾値電圧が−２．５Ｖ以下であるとノードＮ４の電位は１．５Ｖ以上になり、センス時にノードＮ１は“Ｈ”になる。時刻ｔｃｓ２　における電圧Ｖｓｅｎ　の電位変化を変えることにより、センスアンプで検知するメモリセルの閾値レベルを変えることができる。例えば時刻ｔｃｓ２　に電圧Ｖｓｅｎ　を０．５Ｖから０Ｖに変化させた場合、メモリセルの閾値電圧が−２Ｖ以下であると、ノードＮ４の電位は１．５Ｖ以上になり、センス時にノードＮｌは“Ｈ”になる。あるいは、時刻ｔｃｓ２　に電圧Ｖｓｅｎ　を全く変化させない場合、メモリセルの閾値が−１．５Ｖ以下であるとノードＮ４の電位は１．５Ｖ以上になり、センス時にノードＮ１は“Ｈ”になる。このように、電圧Ｖｓｅｎ　をチップ内部あるいはチップ外部から変え得るようにすれば、負の閾値電圧を測定することができる。
【００９５】
また、読み出し時に電圧Ｖｓｅｎ　を変化させないで読むこともできる。図２４にこの場合のタイミングチャートを示す。図２４は、図４に示すビット線ＢＬＥに接続され、ワード線ＷＬ８で選択されるメモリセルの過消去検知リードを示している。センスアンプの回路構成は図１である。
【００９６】
先ず、時刻ｔｃｔ１　に選択ビット線ＢＬＥを０Ｖにする。過消去検知リード中、非選択ビット線ＢＬＯは電圧Ｖｂｌ（例えばＶｃｃ）を保つことにより、ビット線間のカップリングノイズを除去する。時刻ｔｃｔ２　に選択したワード線ＷＬ８を０Ｖ，非ワード線を電圧Ｖｒｅａｄ、選択ゲートＳＧＳ，ＳＧＤを電圧Ｖｒｅａｄにする。電圧Ｖｒｅａｄは例えば電源電圧Ｖｃｃに限らず４．５Ｖとしてもよいし、Ｖｒｅａｄ＝Ｖｃｃとしてもよい。また、メモリセルの閾値電圧が負であるため、電圧Ｖｒｅａｄを例えば２Ｖ程度まで低くしても大きな読み出し電流を得ることができる。ソース線を電圧Ｖｓ　（例えばＶｃｃ）にする。
【００９７】
ここでは、電圧Ｖｓ　がＶｃｃの場合を例に取って説明する。選択ゲートの電圧を上げると、選択したメモリセルＭＣ４の閾値電圧に従って、ビット線にビット線の電位が設定される。電源電圧Ｖｃｃを３Ｖとすると、（バックバイアス−３Ｖ時の）閾値電圧が例えば−１．５Ｖの場合、ビット線は１．５Ｖになる。読み出し時電圧Ｖｓｅｎ　は０Ｖである。また、時刻ｔｃｔ１　からｔｃｔ３　の間、ＣＡＰＲＳＴが“Ｌ”であり、ノードＮ４はＶｃｃにプリチャージされる。
【００９８】
その後、時刻ｔｃｔ３　においてＣＡＰＲＳＴが“Ｈ”になると、ノードＮ４はＶｃｃでフローティングになる。信号ＢＬＳＨＦＥはＶｃｌａｍｐ　（例えば２Ｖ）にする。過消去の場合、ビット線電位は１Ｖよりも大きいため、トランジスタＱＮＨ３はオフし、ノードＮ４はＶｃｃを保つ。
【００９９】
一方、過消去でない場合、トランジスタＱＮＨ３はオンし、ノードＮ４はＶｃｃから例えば１Ｖになる。このようにトランジスタＱＮＨ３のゲートをクランプすることにより、ノードＮ４はＶｃｃまたは１Ｖ以下になり、センス動作時に大きな電位振幅を得ることができる。
【０１００】
時刻ｔｃｔ４　にノードＮ４の電位がノードＮｌに転送され、時刻ｔｃｔ５　にセンスされ、時刻ｔｃｔ６　にラッチされる。過消去したセルがあるか否かはノードＮｌ、Ｎ３の電位をＩＯ線に読み出して検知したり、あるいは一括検知用トランジスタＱＮＬ７を用いて検知してもよい。この場合、各カラムのトランジスタＱＮＬ７は並列接続されている。まず、ＩＤＥＴを例えばＶｃｃにプリチャージしてフローティングにする。その後、１カラムでも過消去のセルがあると、そのノードＮ１が“Ｈ”になるため、ＩＤＥＴは０Ｖに放電され、過消去が検知される。
【０１０１】
上記実施例では例えばメモリセルの閾値電圧が−１Ｖ以下であるとセンスノードＮ４は電源電圧Ｖｃｃになる。選択ワード線の電位を変えることにより、センスアンプで検知するメモリセルの閾値レベルを変えることができる。例えば図２４でワード線ＷＬ８の電位を０．５Ｖにすると、メモリセルの閾値電圧が−０．５Ｖ以下であるとノードＮ４の電位はＶｃｃになり、センス時にノードＮｌは“Ｈ”になる。このように、選択ワード線の電位をチップ内部あるいはチップ外部から変え得るようにすれば、負の閾値電圧を測定することができる。
【０１０２】
上記実施例では過消去検知のために負の閾値電圧を測定する回路について説明したが、本発明の負の閾値電圧測定法はこれに限定されない。つまり、過消去検知のみならずメモリセルのエンデュランス試験等で負の閾値電圧を測定する場合にも本発明は有効である。
【０１０３】
尚、本発明は、ＮＡＮＤ型ＥＥＰＲＯＭに限定されるものではなく、ＮＯＲ型、ＡＮＤ型（Ａ．Ｎｏｚｏｅ　：　ＩＳＳＣＣ，　Ｄｉｇｅｓｔ　ｏｆ　Ｔｅｃｈｎｉｃａｌ　Ｐａｐｅｒｓ，１９９５）、ＤＩＮＯＲ型（Ｓ．Ｋｏｂａｙａｓｈｉ　：　ＩＳＳＣＣ，　Ｄｉｇｅｓｔ　ｏｆ　Ｔｅｃｈｎｉｃａｌ　Ｐａｐｅｒｓ，１９９５）、Ｖｉｒｔｕａｌ　ＧｒｏｕｎｄＡｒｒａｙ型（Ｌｅｅ，　ｅｔ　ａｌ．　：　Ｓｙｍｐｏｓｉｕｍ　ｏｎ　ＶＬＳＩ　Ｃｉｒｃｕｉｔｓ，　Ｄｉｇｅｓｔ　ｏｆ　Ｔｅｃｈｎｉｃａｌ　Ｐａｐｅｒｓ，１９９４）　等のいかなるメモリセルアレイにも適用可能である。
【０１０４】
さらに、本発明は、フラッシュメモリに限らず、マスクＲＯＭ、ＥＰＲＯＭ等などにも適用可能である。
【０１０５】
また、センスラッチ回路としては、３値のセンスアンプ兼ラッチ回路を用いたがこれに限定されるものではなく、３値以外のセンスアンプ兼ラッチ回路を用いることも可能である。
【０１０６】
その他、本発明の要旨を変えない範囲において、種々変形実施可能なことは勿論である。
【０１０７】
【発明の効果】
以上、詳述したようにこの発明によれば、メモリセルのデータを消去した後、過消去状態のセルの有無を検知し、過消去状態のセルが検知された場合、ソフト書き込みを行うことが可能となる。したがって、消去後のメモリセルの閾値電圧が所定の電圧以下に低下しないように制御できるため、誤書き込みを防止できる。
【図面の簡単な説明】
【図１】本発明のセンスアンプ兼ラッチ回路を示す回路図。
【図２】本発明のＮＡＮＤ型ＥＥＰＲＯＭセルの構成を示すものであり、同図（ａ）は平面図、同図（ｂ）は等価回路図。
【図３】図３（ａ）は図２（ａ）の３ａ−３ａ線に沿った断面図、図３（ｂ）は図２（ａ）の３ｂ−３ｂ線に沿った断面図。
【図４】本発明のＮＡＮＤ型ＥＥＰＲＯＭのメモリセルアレイを示す回路構成図。
【図５】本発明の半導体記憶装置の構成を示すブロック図。
【図６】本発明のデータ読み出し動作を説明するために示すタイミングチャート。
【図７】本発明のデータ書き込み動作を説明するために示すタイミングチャート。
【図８】本発明の消去動作を説明するために示すタイミングチャート。
【図９】本発明の消去ベリファイ読み出し動作を説明するために示すタイミングチャート。
【図１０】本発明の消去動作を説明する図。
【図１１】本発明の過消去検知リードを説明する図。
【図１２】メモリセルの過消去検知リードを説明するために示すタイミングチャート。
【図１３】メモリセルの過消去検知リードを説明するために示すタイミングチャート。
【図１４】ソフト書き込みを説明するために示すタイミングチャート。
【図１５】本発明の消去動作を説明する図。
【図１６】本発明の第２の実施の形態を示すものであり、過消去検知リードを説明する図。
【図１７】本発明の第３の実施の形態を示すものであり、過消去検知リードおよびソフト書き込みを説明する図。
【図１８】本発明の第４の実施の形態を示すものであり、過消去検知リードおよびソフト書き込みの動作を説明する図。
【図１９】本発明の第４の実施の形態を示す回路図。
【図２０】ビット線ＢＬＯとワード線ＷＬ８で選択されるメモリセルの過消去検知リードを説明するために示すタイミングチャート。
【図２１】ビット線ＢＬＥとワード線ＷＬ７で選択されるメモリセルの過消去検知リードを説明するために示すタイミングチャート。
【図２２】ソフト書き込みの他の例を示すタイミングチャート。
【図２３】消去動作の他の例を説明する図。
【図２４】この発明の変形例を示すタイミングチャート。
【符号の説明】
２…メモリセルアレイ、３…ローデコーダ、４…センスアンプ兼ラッチ回路、１０…カラムデコーダ、１１…制御部、１２…プリチャージ回路、ＢＬＥ、ＢＬＯ…ビット線、ＷＬ１〜ＷＬ８…ワード線、Ｓ／Ｌ１、Ｓ／Ｌ２…第１、第２のセンスラッチ回路、Ｉ１〜Ｉ４…インバータ回路、ＭＣ１〜ＭＣ４…メモリセル。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electrically rewritable semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device such as an EEPROM (Electrically Erasable Programmable ROM).
[0002]
[Prior art]
In recent years, a NAND cell type EEPROM has been developed as one of electrically rewritable nonvolatile semiconductor memory devices. In this NAND cell type EEPROM, the sources and drains of a plurality of memory cells are connected in series between adjacent ones, and this is connected as a unit to a bit line. Each memory cell has a floating structure as a charge storage layer. It has an n-channel MOSFET structure in which a gate and a control gate are stacked.
[0003]
FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The operation of the NAND type EEPROM is as follows.
[0004]
As a highly reliable writing method for preventing erroneous writing, local self boost has been proposed (for example, see Non-Patent Document 1). In this writing method, data writing is performed sequentially from the memory cell farther from the bit line. 0 V or power supply voltage Vcc is applied to the bit line according to data. That is, when writing data "0", 0 V is applied to the bit line, and when writing data "1", the power supply voltage Vcc is applied to the bit line.
[0005]
The select gate connected to the bit line is at the power supply voltage Vcc, and the select gate connected to the source line is at 0V. A boosted write voltage Vpgm (= about 20 V) is applied to the control gate of the selected memory cell, and the control gates on both sides of the selected control gate are set to 0V. An intermediate potential Vpass (= about 10 V) is applied to the control gates of the other unselected memory cells. Each memory cell before writing is collectively erased in block units, and the threshold voltage is negative.
[0006]
For example, when writing data to the memory cell MC1 in FIG. 4, the word line WL7 is set to the write voltage Vpgm, WL6 and WL8 are set to 0V, and WL1, WL2... WL5 are set to the intermediate potential Vpass. When writing data "0", the memory cell MC2 having WL6 as a gate electrode has an erased state, so the threshold value is negative, and 0 V of the bit line potential is transferred to the channel of MC1. As a result, since the channel potential of MC1 is 0 V, a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are injected from the substrate into the floating gate by the tunnel current, and the threshold voltage moves in the positive direction.
[0007]
When data "1" is written to the memory cell MC1, the bit line BLE is at Vcc (for example, 3.3 V). If the threshold voltage of the memory cell MC3 is, for example, -1 V, MC3 is turned off and the memory cell MC1 is turned off. The channel will be floating. The floating channel has a capacity of about 8 V due to capacitive coupling with the control gate, and maintains the "1" state because electron injection does not occur.
[0008]
Data is erased almost simultaneously in block units. That is, all control gates and select gates of the block to be erased are set to 0 V, and a boosted potential VppE (about 20 V) is applied to the p-type well and the n-type substrate. VppE is also applied to the control gate and select gate of the block that is not erased. As a result, in the memory cell of the block to be erased, electrons of the floating gate are emitted to the well, and the threshold voltage moves in the negative direction. In the erasing operation, an erasing pulse of about 2 ms is applied, and memory cells that are easy to erase and memory cells that are difficult to erase are erased by the same erase pulse. Therefore, the threshold distribution of the memory cell in the erased state ("1" state) is distributed in a range from about -1V to about -5V.
[0009]
In the data read operation, the bit line is precharged and then floated, the control gate of the selected memory cell is set to 0 V, the control gates of the other memory cells and the selection gate are set to the power supply voltage Vcc (for example, 3 V), the source line Is set to 0V. In this state, data is read by detecting the potential of the bit line to determine whether a current flows through the selected memory cell. That is, when the data written in the memory cell is “0” (threshold Vth of the memory cell> 0), the memory cell is off, and the bit line maintains the precharge potential. On the other hand, when the data written in the memory cell is “1” (threshold Vth <0 of the memory cell), the memory cell is turned on and the bit line drops by ΔV from the precharge potential. By detecting these bit line potentials with a sense amplifier, data in a memory cell is read.
[0010]
[Non-patent document 1]
IEEE Journal of Solid-State Circuits. Vol. 31, No. 11, November 1996 pp. 1575-1582
[0011]
[Problems to be solved by the invention]
By the way, consider the case where data "1" is written to the memory cell MC1 at the time of data writing. For example, when writing data to the memory cell MC1 shown in FIG. 4, the gate of the memory cell MC3 is set to 0V. When the threshold voltage of MC3 is, for example, -5V, MC3 is not turned off when the word lines WL1 to WL5, WL7 are, for example, the power supply voltage Vcc, WL6 is 0V, and the bit line BLE is Vcc. Therefore, when boosting the word line WL7 from 0 V to the voltage Vpgm, the channel of MC1 to which data "1" is written does not reliably become floating. For this reason, the channel of the memory cell MC1 is not boosted to 8V, but is boosted only to, for example, 5V. In this case, since the channel of the memory cell MC1 is 5 V and the gate is 20 V, there is a problem that electrons are injected and erroneous writing is performed.
[0012]
That is, conventionally, when erasing data, only the upper limit value is controlled so that the threshold voltage becomes 0 V or less, for example. However, the threshold voltage of each memory cell after erasing is, for example, -1 V to -5 V In some cases, erroneous writing may occur during data writing.
[0013]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object of the present invention is to control erroneous writing by controlling a threshold voltage of a memory cell after erasing so as not to drop below a predetermined voltage. It is intended to provide a semiconductor memory device that can be prevented.
[0014]
[Means for Solving the Problems]
According to the semiconductor memory device of one embodiment of the present invention, a memory cell unit including a NAND memory cell in which a plurality of memory cells are connected in series, an erasing unit for erasing data in the memory cell, and the erasing unit After erasing, an over-erase detecting means for checking whether the memory cell is excessively erased, a first signal line connected to one end of the NAND-type memory cell, and a first signal line connected to the other end of the NAND-type memory cell A second signal line connected to the first signal line, and read means for reading a threshold voltage of the memory cell, wherein the read means connects the first signal line and a first node to each other. A first switch to be connected, a sense amplifier for detecting a potential of the first node, and a capacitor having one end connected to the first node and the other end connected to the second node, Potential applied to the second node is to the sense amplifier is changed at the time of sensing the potential of said first node.
[0015]
According to the semiconductor memory device of another aspect of the present invention, the first signal line connected to one end of the memory cell, the second signal line connected to the other end of the memory cell, Reading means connected to a signal line for reading a threshold voltage of the memory cell, the reading means comprising: a first switch connecting the first signal line to a first node; A sense amplifier for detecting the potential of the node; and a capacitor having one end connected to the first node and the other end connected to the second node, wherein the potential applied to the second node is It is changed when the sense amplifier senses the potential of the first node.
[0016]
According to the semiconductor memory device of another aspect of the present invention, the first signal line connected to one end of the memory cell, the MOS transistor having one end connected to the first signal line, and the other of the MOS transistor A detection node connected to one end, a capacitor having one end connected to the detection node and the other end connected to a second signal line, and a sense amplifier for detecting a potential of the detection node; The potential of the first signal line is taken into the detection node via a transistor, the potential of the second signal line is changed, and then the potential of the detection node is detected by the sense amplifier.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
Conventionally, the erase state is controlled so as to be, for example, 0 V or less. However, the control is not performed so that the threshold voltage does not fall below a predetermined voltage. In the present invention, during the erase operation, the threshold distribution in the erased state is controlled so as to be 0 V or less and a predetermined voltage, for example, −3 V or more. By controlling the erase voltage to be equal to or higher than the predetermined voltage, erroneous writing at the time of writing can be prevented.
[0019]
Hereinafter, the present invention will be described using a multi-value NAND cell type EEPROM as an example. The erase operation is the same in the case of a multi-level memory cell and a case of a binary memory cell.
[0020]
FIGS. 2A and 2B are a plan view and an equivalent circuit diagram of one NAND cell part of the memory cell array. FIG. 3A is a sectional view taken along line 3a-3a shown in FIG. 2A, and FIG. 3B is a sectional view taken along line 3b-3b shown in FIG.
[0021]
A memory cell array including a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11a surrounded by an element isolation oxide film 12a. In this embodiment, one NAND cell includes eight memory cells M1 to M8 connected in series. In each memory cell, the floating gate 14 (141, 142... 148) is formed on the substrate 11a with the gate insulating film 13 interposed. Adjacent ones of the n-type diffusion layers 19 as sources and drains of these memory cells are connected in series.
[0022]
A first select gate 149, 169 and a second select gate 1410, 1610 are provided on the drain side and the source side of the NAND cell. The first select gates 149, 169 and the second select gates 1410, 1610 are formed simultaneously with the floating gate 14 (141... 148) and the control gate 16 (161... 168) of the memory cell. Note that the first and second select gates 149 and 169 and the second select gates 1410 and 1610 are electrically connected to each other at a desired portion (not shown) between the first and second layers. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which a bit line 18 is provided. The control gates 161, 162... 168 (CG1, CG2... CG8) of the NAND cells are word lines, and the selection gates 149, 169 and 1410, 1610 (SG1, SG2) are arranged in the row direction, respectively. Is done.
[0023]
FIG. 4 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The source line SL is connected to a reference potential wiring made of aluminum (Al), polysilicon (poly-Si), or the like via a contact (not shown), for example, at one place for every 64 bit lines. This reference potential wiring is connected to a peripheral circuit.
[0024]
The control gate and the first and second select gates of the memory cell are arranged in the row direction. Usually, a set of memory cells connected to one control gate is called one page, and is sandwiched between a pair of select gates on the drain side (first select gate) and the source side (second select gate). A set of pages is called one NAND block or simply one block. One page is composed of, for example, 256 bytes (256 × 8) memory cells. Data is written to memory cells of one page almost simultaneously. One block is composed of, for example, 2048 bytes (2048 × 8) memory cells. Memory cells for one block are erased almost simultaneously.
[0025]
FIG. 5 is a block diagram showing a configuration of a semiconductor memory device to which the present invention is applied. This semiconductor memory device 1 includes a memory cell array 2, a row decoder 3, a sense amplifier / latch circuit 4, a word line / bit line control signal generation circuit 5, a well voltage control circuit 6, an address buffer 7, an IO buffer 8, and a command buffer 9. , A column decoder 10, a control unit 11, a precharge circuit 12, and the like.
[0026]
As shown in FIG. 4, the memory cell array 2 includes a plurality of memory cells arranged in a matrix selected by word lines and bit lines. The address buffer 7 generates a column address signal and a row address signal according to an input address or a command supplied from the command buffer 9. The row decoder 3 selects a word line according to a row address signal supplied from an address buffer 7 and applies a predetermined voltage to a memory cell. The column decoder 10 selects the sense amplifier / latch circuit 4 in accordance with the column address signal supplied from the address buffer 7, and connects to the bit line. The sense amplifier / latch circuit 4 senses a voltage on a bit line according to the read data when reading data from a memory cell, and applies a voltage according to the write data when writing data to the memory cell. Is applied. The word line / bit line control signal generation circuit 5 supplies control signals to word lines and bit lines. When writing data to a memory cell, the precharge circuit 12 supplies a voltage that does not change the data of the memory cell to a bit line that is not connected to the sense amplifier / latch circuit 4. The IO buffer 8 exchanges input data to be written into a memory cell and output data to be read from the memory cell with the outside of the semiconductor memory device 1. The command buffer 9 generates commands such as writing and reading. The well voltage control circuit 6 applies a predetermined voltage to the well of the memory cell. The control unit 11 is connected to the command buffer 9, the well voltage control circuit 6, a voltage generation circuit (not shown), and controls operations such as writing, reading, erasing, and verifying of the semiconductor memory device. Controls the sequence of detection read and software write.
[0027]
FIG. 1 shows a connection relationship among a column decoder 10, a sense amplifier / latch circuit 4, a precharge circuit 12, a bit line, and an IO line of the semiconductor memory device shown in FIG. In this embodiment, a case of a semiconductor memory device using ternary NAND flash memory cells will be described.
[0028]
The ternary sense amplifier / latch circuit 4 is selectively connected to the two bit lines BLE and BLO by, for example, N-channel MOS transistors (hereinafter referred to as NMOS transistors) QNH3 and QNH4 with high breakdown voltage. Signals BLSHFE and BLSHFO are supplied to the gates of these NMOS transistors QNH3 and QNH4, respectively. A precharge circuit 12 is connected to each of the bit lines BLE and BLO.
[0029]
The precharge circuit 12 connected to the bit line BLE includes, for example, a high-breakdown-voltage NMOS transistor QNH1. One end of the current path of the NMOS transistor QNH1 is connected to the bit line BLE, the other end is supplied with the voltage VBLE, and the gate is supplied with the signal PreE.
[0030]
Further, the precharge circuit 12 connected to the bit line BLO is constituted by, for example, a high breakdown voltage NMOS transistor QNH2. One end of the current path of the NMOS transistor QNH2 is connected to the bit line BLO, the other end is supplied with the voltage VBLO, and the gate is supplied with the signal PreO.
[0031]
The ternary sense amplifier / latch circuit 4 includes a sense amplifier / latch circuit (hereinafter, referred to as a first sense latch circuit) S / L1 composed of inverter circuits I1 and I2, and inverter circuits I3 and I4. And a sense amplifier / latch circuit (hereinafter, referred to as a second sense latch circuit) S / L2. The inverter circuit I1 is a clocked inverter operated according to the signals SENN1 and SENP1, and the inverter circuit I2 is a clocked inverter operated according to the signals LATN1 and LATP1. Further, the inverter circuit I3 is a clocked inverter that operates according to the signals SENN2 and SENP2, and the inverter circuit I4 is a clocked inverter that operates according to the signals LATN2 and LATP2.
[0032]
In the ternary sense amplifier / latch circuit 4, one end of a current path of a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) QP1 is supplied with a power supply voltage Vcc, and the other end is connected to a current path of the transistor QNH3. Have been. PMOS transistors QP2 and QP3 are connected in series between the other end of the current path of the PMOS transistor QP1 and a terminal to which the power supply voltage Vcc is supplied. The signal nVERFY is supplied to the gate of the transistor QP2. Further, one end of a current path of the NMOS transistor QNL1 is connected to a connection node N4 between the transistors QP1 and QP2. The signal SBL1 is supplied to the gate of the transistor QNL1, and the other end of the current path of the transistor QNL1 is connected to the input terminal of the inverter circuit I1 and the output terminal of the inverter circuit I2. The output terminal of the inverter circuit I1 and the input terminal of the inverter circuit I2 are connected to the gate of the transistor QP3.
[0033]
On the other hand, the voltage Vsen is supplied to one end of the current path of the NMOS transistor QNH5 forming the capacitor, and the other end is connected to the current path of the transistor QNH4. The other end of the current path of the NMOS transistor QNH5 is connected to one end of the current path of the NMOS transistor QNL2. The signal SBL2 is supplied to the gate of the transistor QNL2. The other end of the current path of the transistor QNL2 is connected to the input terminal of the inverter circuit I3 and the output terminal of the inverter circuit I4. The output terminal of the inverter circuit I3 and the input terminal of the inverter circuit I4 are connected to each other.
[0034]
The gate of an NMOS transistor QNL7 is connected to the other end of the current path of the transistor QNL1. Wiring IDET1 is connected to one end of the current path of transistor QNL7, and the other end is grounded. The input terminal of the inverter circuit I4 is connected to the gate of an NMOS transistor QNL8. Wiring IDET2 is connected to one end of the current path of transistor QNL8, and the other end is grounded.
[0035]
Further, the ternary sense amplifier / latch circuit 4 is connected to the IO line by the column decoder 10. In the column decoder 10, the address signals YAj, YBj, YCj are supplied to a NAND circuit G1. The output terminal of the NAND circuit G1 is connected to the gates of the NMOS transistors QNL3, QNL4, QNL5, and QNL6 via the inverter circuit I5. One end of the current path of the transistor QNL3 is connected to the output terminal of the inverter circuit I2, and one end of the current path of the transistor QNL4 is connected to the input terminal of the inverter circuit I2. One end of the current path of the transistor QNL5 is connected to the output terminal of the inverter circuit I4, and one end of the current path of the transistor QNL6 is connected to the input terminal of the inverter circuit I4. The other ends of the current paths of the transistors QNL3, QNL4, QNL5, and QNL6 are connected to IO lines DL1, nDL1, DLi + 1, and nDLi + 1, respectively.
[0036]
Table 1 shows the relationship between the ternary data "0" to "2" of the memory cell, the threshold voltage thereof, and the latch data N1 and N2 of the ternary sense amplifier / latch circuit 4.
[0037]
[Table 1]

[0038]
FIGS. 6 to 8 are waveform diagrams showing data reading, writing, and erasing operations, respectively. In this embodiment, in reading and writing, BLE is selected and BLO is not selected.
[0039]
Here, a case where the memory cell MC4 shown in FIG. 4 is selected will be described.
[0040]
First, the read operation will be described with reference to FIG. The selected bit line BLE is charged to 1.5 V by the precharge circuit 12 operated in response to the signal PerE, and then floats. Thereafter, the unselected word lines WL2 to WL8 and the selection gates SGS and SGD are set to the power supply voltage Vcc. The selected word line is at 0V. When the data of the selected memory cell is "0", the bit line is discharged to 0V, otherwise the bit line remains at 1.5V.
[0041]
The voltage of the bit line BLE is read into the first sense latch circuit S / L1 via the transistor QNH3 which is turned on by the signal BSHFE and the transistor QNL1 which is turned on by the signal SBL1. Therefore, the potential of the node N1 becomes low level "L" when the data is "0", and becomes high level "H" when the data is "1" or "2".
[0042]
Thereafter, the selected word line is set to VG1 (= 1.8 V). If the data of the selected memory cell is "1", it is discharged to 0V, and if it is "2", it remains at 1.5V. If the data is "0", the bit line is already at 0V. The voltage of the bit line BLE is read into the second sense latch circuit S / L2 via the transistor QNH3 and the transistor QNL2 which is turned on by the signal SBL2. Therefore, the node N2 becomes "L" when the data is "0" or "1", and becomes "H" when the data is "2" (Table 1). The data latched by the first and second sense latch circuits S / L1 and S / L2 are serially read out to the IO line according to the operation of the column decoder 10.
[0043]
Next, the write operation will be described with reference to FIG. At power-on, when the voltage reaches a voltage sufficient for normal operation of the chip, the power-on signal Pon becomes “H”. Using this signal, the latch data N1 and N2 of the ternary sense amplifier / latch circuit 4 are both set to "L". When a command for inputting write data is supplied, the latch data N1 and N2 are both inverted to "H" using this command signal.
[0044]
The selected bit line BLE is set to the power supply voltage Vcc, VD3-Vt (= 1 V), and 0 V according to the write data "0" to "2", respectively. A voltage Vcc for not changing data is applied to the unselected bit lines BLO via the precharge circuit 12. Thereafter, the selection gate SGD is set to the power supply voltage Vcc, the SGS is set to 0 V, the selected word line WL1 is set to VPP (= 20 V), WL2 is set to 0 V, and the other unselected word lines WL3 to WL8 are set to VM10 (= 10 V). Each is set. Here, of the voltages output from the sense amplifier and latch circuit 4 to the bit lines, 0 V corresponds to the write voltage, and the power supply voltage Vcc corresponds to the non-write voltage.
[0045]
In the selected memory cell in which 0 V or 1 V is applied to the bit line, since the gate-channel voltage is high, a tunnel current flows and the threshold voltage of the memory cell increases. Since the tunnel current flows more when the bit line is at 0 V than when it is at 1 V, the threshold voltage is higher. The selected memory cell to which the power supply voltage Vcc is applied has a low gate-channel voltage, so that no tunnel current flows and data "0" is retained.
[0046]
Next, an erasing operation will be described with reference to FIG. When an erase command is input, VPP (= 20 V) is applied to the well of the memory cell array 2. Since the gate of the selected memory cell is set to 0 V, a tunnel current flows in the direction opposite to that during writing, and the threshold voltage of the memory cell drops. On the other hand, since the gates of the unselected memory cells and the selection transistors are floating, they rise to near VPP together with the wells of the memory cell array 2. Therefore, no tunnel current flows and there is no change in the threshold voltage.
[0047]
As described above, writing and reading are connected to only one of the two columns shared by the ternary sense amplifier / latch circuit 4 (for example, only BLE). In the erase operation, two columns, BLE and BLO, are simultaneously selected and erased in block units.
[0048]
<Erase verify read>
Next, after erasing, an erase verify read is performed to check whether the threshold of the memory cell has been erased below a predetermined voltage.
[0049]
FIG. 9 is a timing chart showing the erase verify read operation. When erasing is performed in units of blocks, verify reading is performed on memory cells in one block (for example, memory cells selected by word lines WL1 to WL8) in two steps: odd pages and even pages.
[0050]
First, verify reading is performed on an even page (for example, a memory cell connected to the bit line BLE in FIG. 4), and the read data is held in the first sense latch circuit S / L1. Next, verify reading is performed for an odd page (for example, a memory cell connected to the bit line BLO in FIG. 4), and the read data is held in the second sense latch circuit S / L2.
[0051]
That is, first, as shown in FIG. 9, the bit line BLE is precharged to 1.5V. Thereafter, at time t1, when the select gates SGS and SGD are set to the power supply voltage Vcc and the word lines WL1 to WL8 are set to 0 V, if all the memory cells are sufficiently erased, the potential of the bit line becomes Since the bit line is discharged, the potential of the bit line becomes 0V. In addition, in the case of insufficient erasing, the potential of the bit line is maintained at 1.5 V without being discharged because there is a memory cell in an off state.
[0052]
When the signal BLSHFE becomes 1.5 V at time t2 and the transistor QNH3 turns on, the potential of the bit line is transferred to the ternary sense amplifier / latch circuit 4. Thereafter, when the signal SBL1 becomes “H”, the transistor QNL1 turns on, data is transferred to the node N1, and sensed by the first sense latch circuit S / L1. Thus, the data of the even page is held in the first sense latch circuit S / L1. During reading of the even-numbered page, the bit line BLO is kept at 0 V to reduce coupling noise between bit lines.
[0053]
Subsequently, verify reading is performed on odd pages (for example, memory cells connected to the bit line BLO in FIG. 4). First, at time t3, the bit line BLO is precharged to 1.5V. Thereafter, at time t4, when the select gates SGS and SGD are set to the power supply voltage Vcc and the word lines WL1 to WL8 are set to 0V, the bit line becomes 0V when the memory cell is sufficiently erased, and when the erase is insufficient. , 1.5V. At time t5, when the signal BLSHFO becomes 1.5 V and the transistor QNH4 turns on, the potential of the bit line BLO is transferred to the ternary sense amplifier / latch circuit 4. Thereafter, when the signal SBL2 becomes “H” and the transistor QNL2 turns on, data is transferred to the node N2 and sensed by the second sense latch circuit S / L2. Thus, the data of the odd page is held in the second sense latch circuit S / L2. During the reading of the odd page, the bit line BLE is kept at 0 V in order to reduce the coupling noise between bit lines.
[0054]
In the present invention, the threshold distribution in the erased state is controlled so as to be 0 V or less and -3 V or more. The reason why the lower limit (−3 V) is provided for the threshold voltage is to turn off a memory cell which is located next to the selected control gate and whose gate is biased to 0 V at the time of writing to prevent erroneous writing.
[0055]
FIG. 10 shows a series of erase verify read operations. As described above, after all the memory cells in the selected block are sufficiently erased (ST1 to ST3), an over-erase detection read is performed to check whether the threshold voltage of the memory cells is equal to or higher than a predetermined voltage (ST4). As a result, if there is a memory cell in an over-erased state whose threshold voltage is lower than -3 V, soft writing is performed to increase the threshold voltage to -3 V (ST5, ST6).
[0056]
Hereinafter, the over-erase detection read and the soft write will be described.
[0057]
<Over-erase detection lead>
As shown in FIG. 11, in the over-erase detection read operation, first, the sense amplifier / latch circuit 4 is connected to the bit line BLE, and the memory cell selected by the word line WL8 is connected to the word lines WL7, WL6,. Over-erase detection read is sequentially performed up to the selected memory cell (ST11 to ST18). Subsequently, the sense amplifier / latch circuit 4 is connected to the bit line BLO, and over-erase detection reading is sequentially performed from the memory cell selected by the word line WL8 to the memory cell selected by WL7, WL6,..., WL1 (ST19). To ST26).
[0058]
FIG. 12 shows an over-erase detection read operation of the memory cell selected by the word line WL8 with the sense amplifier / latch circuit 4 connected to the bit line BLE. First, at time tcs1, the selected bit line BLE is set to 0V. During the over-erase detection read, the non-selected bit line BLO is kept at the voltage Vbl (for example, Vcc) to remove coupling noise between bit lines. At time tcs2, the selected word line WL8 is set to 0 V, the unselected word lines are set to the voltage Vread, and the selection gates SGS and SGD are set to the voltage Vread. The voltage Vread is, for example, 4.5 V, but may be Vread = Vcc. The source line is set at a voltage Vs (for example, Vcc).
[0059]
Hereinafter, a case where the voltage Vs is Vcc will be described as an example. When the voltage of the selection gate is increased, the potential of the bit line is set according to the threshold voltage of the selected memory cell MC8. That is, assuming that the power supply voltage Vcc is 3 V, when the threshold voltage of the MC 8 (when the back gate bias is -3 V) is excessively erased to -3 V or less, the bit line becomes 3 V.
[0060]
On the other hand, when the threshold voltage when the back gate bias is −3 V is, for example, −2.5 V, the bit line becomes 2.5 V. Here, the signal BSHFE may be set to, for example, 5 V so that the voltage of the bit line is transferred to the sense node N4. During this time, the voltage Vsen applied to the transistor QNH5 as a capacitor is, for example, Vcc / 3. The voltage Vsen may be fixed to a desired voltage, for example, 0 V or Vcc during writing and erasing.
[0061]
Thereafter, at time tcs3, the voltage Vsen becomes Vcc / 3, for example, from 1V to 0V. During this time, the signal BLSHFE is at the voltage Vcp, for example, 2V. When the memory cell is over-erased, the transistor QNH3 is turned off and the node N4 is in a floating state. In this case, since the capacitance of the transistor QNH5 forming the capacitor is sufficiently larger than the other parasitic capacitance of the node N4, the potential of the node N4 changes from 3V to 2V.
[0062]
On the other hand, when the memory cell is not over-erased, the potential of the node N4 changes from 1.5V to 0.5V. Since the potential of the signal BLSHFE is 2 V, the potential of the node N4 does not become lower than 0.5 V.
[0063]
At time tcs4, when the signal SBL1 goes high, the potential of the node N4 is transferred to the node N1 through the transistor QNL1, sensed by the first sense latch circuit S / L1 at time tcs5, and latched at time tcs6. . To determine whether or not there is an overerased cell, the potentials of the nodes N1 and N3 may be read out to the IO line. Alternatively, the detection may be performed using the collective detection transistor QNL7. That is, whether or not there is a cell in an overerased state can be detected based on whether or not the transistor QNL7 is turned on. The transistor QNL7 is connected in parallel to each column. First, the wiring IDET1 is precharged to, for example, the power supply voltage Vcc, and then is made floating. In this state, if there is an over-erased cell in at least one column, the node N1 in that column becomes "H", so that the wiring IDET1 is discharged to 0 V and over-erased is detected.
[0064]
Thereafter, as shown in FIG. 11, an over-erase detection read is performed on the memory cell selected by the bit line BLE and the word lines WL7 to WL1. Thereafter, an over-erase detection read is performed on the memory cells connected to the bit line BLO.
[0065]
FIG. 13 shows an over-erase detection read operation of a memory cell selected by the bit line BLO and the word line WL8. In this case, data read from the bit line BLO is latched by the first sense latch circuit S / L1 via the transistors QNH4 and QNL1. The other operations are the same as those in FIG.
[0066]
When a memory cell in an over-erased state is detected by the over-erased detection lead, soft writing is performed on the memory cell.
[0067]
FIG. 14 shows the operation of soft writing. In the soft write, all the bit lines are grounded to 0V, and the word lines WL1, WL2 ... WL8 are boosted to a voltage Vspgm, for example, 6V. The over-erased memory cell has a threshold voltage of, for example, −5 V to −2 V because the tunnel oxide film has a small thickness, for example, so that writing is easy. However, the memory cell that has not been over-erased is relatively difficult to write. Hold the erased threshold voltage.
[0068]
After the soft write, as shown in FIG. 10, the over-erase detection read may be performed again (ST4 to ST5). When the threshold value is sufficiently changed by one soft write, a series of erase operations may be ended without performing over-erase detection read after the soft write as shown in FIG. 15, the same parts as those in FIG. 10 are denoted by the same reference numerals, and the description will be omitted.
[0069]
According to the above-described embodiment, after erasing data, an over-erasure detection read is performed, and when an over-erased cell is detected, soft writing is performed. Therefore, the threshold voltage of the memory cell can be kept within a predetermined range of, for example, -3 V to -1 V, and erroneous writing can be prevented.
[0070]
FIG. 16 shows the second embodiment of the present invention, and shows another example of the over-erase detection lead. In this case, first, the bit line BLE is connected to the sense amplifier / latch circuit 4, an over-erase detection read is performed on the memory cell selected by the word line WL8 (ST31), and then the bit line BLO is connected to the sense amplifier. The over-erase detection read is performed on the memory cell selected by the word line WL8 by connecting to the latch circuit 4 (ST32). Thereafter, the bit lines are alternately selected and the word lines are alternately selected, as in the over-erase detection read for the memory cell selected by the bit line BLE and the word line WL7 (ST33). An erase detection read may be performed.
[0071]
FIG. 17 shows the third embodiment of the present invention, and shows another example of the over-erase detection read and the soft write operation.
[0072]
In this embodiment, over-erase detection read and software write are performed for each page. First, an over-erase detection read is performed on the memory cell selected by the bit line BLE and the word line WL8, and the read data is latched in the first sense latch circuit S / L1 (ST41). Thereafter, an over-erase detection read is performed on the memory cell selected by the bit line BLO and the word line WL8, and the read data is latched in the second sense latch circuit S / L2 (ST42). Subsequently, it is determined from the latched data whether or not there is a cell in an over-erased state (ST43). If there is a cell in an over-erased state, soft writing is performed on a memory cell connected to the word line WL8. Is performed (ST44). In this soft write, only the word line WL8 may be set to the voltage Vspgm, and the word lines WL1, WL2,..., WL7 may be set to 0V or the power supply voltage Vcc.
[0073]
In this manner, after performing the over-erase recovery operation on the word line WL8, the over-erase recovery operation may be sequentially performed on the word lines WL7, WL6,.
[0074]
When data read from a memory cell connected to the bit line BLO is latched by the second sense latch circuit S / L2, the signals SBL1, SENP1, SENN1, LATP1, LATN1 are activated in the timing chart shown in FIG. Instead of activating, SBL2, SENP2, SENN2, LATP2, and LATN2 may be activated. When data is latched in the first and second sense latch circuits S / L1 and S / L2, over-erased cells can be collectively detected by using the transistors QNL7 and QNL8 for collective detection. At this time, when data of the first sense latch circuit S / L1 and data of the second sense latch circuit S / L2 are simultaneously detected, the signal of the wiring IDET2 may be the same as that of the IDET1.
[0075]
FIG. 18 shows the fourth embodiment of the present invention, and shows another example of the over-erase detection read and the soft write operation. FIG. 19 shows a circuit applied to this embodiment.
[0076]
FIG. 19 has almost the same configuration as that of FIG. 1, and only different parts will be described. That is, in FIG. _SE NMOS transistors QN21 and QN22 are connected in series between the terminal to which is supplied and the node N4. The gate of the transistor QN21 is connected to the gate of the transistor QP3, and the signal nVRFY1 is supplied to the gate of the transistor QN22.
[0077]
In the case of this embodiment, first, an over-erase detection read of the memory cell selected by the bit line BLE and the word line WL8 is performed, and the read data is latched in the first sense latch circuit S / L1 (ST51). The timing chart of this operation is the same as that of FIG. As a result, when over-erased, the node N1 is set to "H" and the node N3 is set to "L". If it has not been over-erased, the node N3 becomes "H".
[0078]
Next, an over-erase detection read of the memory cell selected by the bit line BLO and the word line WL8 is performed, and the read data is latched in the first sense latch circuit S / L1 (ST52).
[0079]
FIG. 20 is a timing chart of this operation. 20 differs from FIG. 13 in that signal nVERIFY is set to 0 V at time tCA3 to activate transistor Qp2. If the data previously latched in the first sense latch circuit S / L1 is overerased, the transistor QP3 is turned on because the node N3 is at "L", and is selected by the bit line BLO and the word line WL8. Even if it is read that the memory cell to be erased is not overerased, node N4 is charged to power supply voltage Vcc.
[0080]
On the other hand, when the data latched in the first sense latch circuit S / L is not overerased, the node N3 is at "H", so that the transistor QP3 is not turned on and the bit line BLO and the word line WL8 are not turned on. Data read from the selected memory cell is held at the node N4 as it is. Thereafter, at time tCA5, when transistor QNL1 is turned on, the potential of node N4 is latched by first sense latch circuit S / L1.
[0081]
After that, an over-erase detection read of the memory cell selected by the bit line BLE and the word line WL7 is performed and latched by the first sense latch circuit S / L1 (ST53).
[0082]
FIG. 21 shows this timing chart. 21 differs from FIG. 12 in that the signal nVERIFY is set to 0 V at time tCB3 to activate the transistor Qp2. Here, as in the case of FIG. 20, the potential of the node N3 is "L" only when the data previously latched in the first sense latch circuit S / L1 is over-erased. Are charged to the power supply voltage Vcc. Thereafter, when the transistor QNL1 turns on, the potential of the node N4 is latched by the first sense latch circuit S / L1.
[0083]
Thereafter, from the over-erase detection read of the memory cell selected by the bit line BLO and the word line WL7 to the over-erase detection read of the memory cell selected by the bit line BLO and the word line WL1, the first sense latch is performed. It is latched in the circuit S / L1 (ST54 to ST66).
[0084]
As described above, as a result of performing the over-erase detection read, if at least one of the memory cells selected by the bit line BLE or the bit lines BLO and WL1 to WL8 is in the over-erased state, the first Of the sense latch circuit S / L1 at "H".
[0085]
Subsequently, based on the data latched in the first sense latch circuit S / L1, it is determined whether or not there is a memory cell in an over-erased state (ST67). Writing is performed (ST68). As described above, the detection of the latch state may use the transistor QNL7 for batch detection.
[0086]
FIG. 22 shows a timing chart of the soft writing shown in FIG. First, the potentials of the bit lines BLE and BLO are set to 0V. Thereafter, at time tspg1, the signal nVRFY1 changes to "H", whereby the potentials of the bit lines BLE and BLO are set according to the data latched in the first sense latch circuit S / L1. That is, when there is an overerased cell, the potential of the bit line remains at 0V. If there is no over-erased cell, the voltage V _SE Is set to a potential higher than the power supply voltage Vcc or Vcc, the potential of the bit line becomes Vcc. _SE From Vcc or Vcc-Vth (Vth is V _SE And the threshold voltage of the transistor connected between the bit lines. At time tspg2, when the potential of the word line becomes Vspgm (for example, 8 V), the threshold voltage is written to about -2 V, for example, since the over-erased cell has a channel potential of 0 V and a control gate potential of Vspgm. On the other hand, when there is no over-erased cell, the voltage applied to the tunnel oxide film is relaxed because the channel potential is Vcc, and writing is not performed.
[0087]
According to the fourth embodiment, over-erase detection read is continuously performed on 16 memory cells connected to two bit lines, and data is latched in the first sense latch circuit S / L1. Thereafter, it is detected whether or not there is a memory cell in an over-erased state only once. Therefore, over-erased cells can be detected at high speed.
[0088]
In the operation shown in FIG. 18, the transistor np2 may be activated by setting the signal nVERIFY to "L" at time tCB3 in the first over-erase detection lead as shown in FIG. However, in this case, in order to prevent destruction of data read to the node N4, it is necessary to set the node N1 of the first sense latch circuit S / L1 to "L" and the node N3 to "H" in advance. There is.
[0089]
In each of the above embodiments, the range of the measurable threshold voltage of the memory cell including the back gate bias effect is equal to or higher than -Vs (Vs is the source line potential at the time of over-erase detection read). For example, when Vs is 3.3 V, when the threshold voltage of the memory cell is −3.3 V or less, the potential of the bit line becomes 3.3 V. Therefore, if the voltage Vs is higher than the power supply voltage, for example, 6 V, a threshold voltage having an absolute value higher than the power supply voltage can be read. However, in this case, it is desirable that the voltage Vread of the gate of the memory cell connected in series with the selected memory cell is, for example, 7V. By setting the voltage in this manner, the source potential, for example, 6 V can be transferred without dropping by the threshold voltage.
[0090]
Furthermore, if the potential Vs of the source line is set to the power supply voltage Vcc and the power supply voltage Vcc is increased, a low threshold voltage can be read. For example, if Vcc is increased during a chip test, a low threshold voltage can be read.
[0091]
After the over-erase detection read and the software writing, it may be checked whether or not the memory cell to which the software writing has been performed is excessively written. FIG. 23 shows a verifying operation after soft writing, and the same parts as those in FIG. 10 are denoted by the same reference numerals.
[0092]
In FIG. 23, software writing is performed on a memory cell in which over-erasure has been detected by the over-erasure detection lead (ST4 to ST7). After the completion of the soft write, an erase verify read is performed to detect whether the threshold voltage has become too high (ST7 to ST3). As a result, if the threshold voltage has become too high due to the soft writing, erasing is performed again (ST1). After that, the memory cells that have passed the erase verify read perform an over-erase detection read (ST4).
[0093]
By operating as shown in FIG. 23, the threshold voltage in the erased state can be set between the desired upper limit and lower limit.
[0094]
In the above embodiment, after the bit line potential is transferred to the node N4, the potential of the node N4 is changed by changing the voltage Vsen. For example, if the threshold voltage of the memory cell is -2.5 V or less, the potential of the bit line becomes 2.5 V or more. At time tcs2 in FIG. 12, the voltage Vsen is changed from 1 V to 0 V, so that when the threshold voltage of the memory cell is -2.5 V or less, the potential of the node N4 becomes 1.5 V or more. H ”. By changing the potential change of the voltage Vsen at the time tcs2, the threshold level of the memory cell detected by the sense amplifier can be changed. For example, when the voltage Vsen is changed from 0.5 V to 0 V at time tcs2, if the threshold voltage of the memory cell is −2 V or less, the potential of the node N4 becomes 1.5 V or more, and the node N1 is set to “H” at the time of sensing. "become. Alternatively, in the case where the voltage Vsen is not changed at all at the time tcs2, the potential of the node N4 becomes 1.5 V or more if the threshold value of the memory cell is -1.5 V or less, and the node N1 becomes "H" at the time of sensing. As described above, if the voltage Vsen can be changed from inside or outside the chip, a negative threshold voltage can be measured.
[0095]
Further, at the time of reading, reading can be performed without changing the voltage Vsen. FIG. 24 shows a timing chart in this case. FIG. 24 shows an over-erase detection lead of the memory cell connected to the bit line BLE shown in FIG. 4 and selected by the word line WL8. FIG. 1 shows a circuit configuration of the sense amplifier.
[0096]
First, the selected bit line BLE is set to 0 V at time tct1. During the over-erase detection read, the unselected bit line BLO keeps the voltage Vbl (for example, Vcc) to remove coupling noise between the bit lines. At time tct2, the selected word line WL8 is set at 0 V, the non-word lines are set at voltage Vread, and the selection gates SGS and SGD are set at voltage Vread. The voltage Vread is not limited to the power supply voltage Vcc, for example, and may be 4.5 V, or Vread = Vcc. Further, since the threshold voltage of the memory cell is negative, a large read current can be obtained even when the voltage Vread is reduced to, for example, about 2V. The source line is set to the voltage Vs (for example, Vcc).
[0097]
Here, the case where the voltage Vs is Vcc will be described as an example. When the voltage of the selection gate is increased, the potential of the bit line is set to the bit line according to the threshold voltage of the selected memory cell MC4. Assuming that the power supply voltage Vcc is 3 V, if the threshold voltage (at the time of back bias of -3 V) is, for example, -1.5 V, the bit line becomes 1.5 V. The read voltage Vsen is 0V. From time tct1 to tct3, CAPRST is at "L", and node N4 is precharged to Vcc.
[0098]
Thereafter, when CAPRST changes to "H" at time tct3, node N4 floats at Vcc. The signal BLSHFE is set to Vclamp (for example, 2 V). In the case of over-erasing, since the bit line potential is higher than 1 V, the transistor QNH3 turns off and the node N4 maintains Vcc.
[0099]
On the other hand, if it is not over-erasing, the transistor QNH3 is turned on, and the node N4 changes from Vcc to, for example, 1V. By clamping the gate of transistor QNH3 in this manner, node N4 becomes Vcc or 1 V or less, and a large potential amplitude can be obtained during the sensing operation.
[0100]
At time tct4, the potential of node N4 is transferred to node Nl, sensed at time tct5, and latched at time tct6. Whether or not there is an overerased cell may be detected by reading the potentials of the nodes N1 and N3 onto the IO line, or may be detected by using the collective detection transistor QNL7. In this case, the transistors QNL7 of each column are connected in parallel. First, the IDET is precharged to, for example, Vcc to make it floating. Thereafter, if there is an over-erased cell in at least one column, the node N1 becomes "H", so that IDET is discharged to 0 V and over-erased is detected.
[0101]
In the above embodiment, for example, when the threshold voltage of the memory cell is -1 V or less, the sense node N4 becomes the power supply voltage Vcc. By changing the potential of the selected word line, the threshold level of the memory cell detected by the sense amplifier can be changed. For example, assuming that the potential of the word line WL8 is 0.5 V in FIG. 24, if the threshold voltage of the memory cell is -0.5 V or less, the potential of the node N4 becomes Vcc, and the node N1 becomes "H" at the time of sensing. In this way, if the potential of the selected word line can be changed from inside the chip or outside the chip, a negative threshold voltage can be measured.
[0102]
In the above embodiment, a circuit for measuring a negative threshold voltage for detecting over-erasure has been described. However, the method for measuring a negative threshold voltage of the present invention is not limited to this. That is, the present invention is effective not only in detecting over-erase but also in measuring a negative threshold voltage in an endurance test or the like of a memory cell.
[0103]
Note that the present invention is not limited to a NAND type EEPROM, but includes a NOR type, an AND type (A. Nozoe: ISSCC, Digest of Technical Papers, 1995), and a DINOR type (S. Kobayashi: ISSCC, Digestive physics). , 1995), and Virtual Ground Array type (Lee, et al .: Symposium on VLSI Circuits, Digest of Technical Papers, 1994).
[0104]
Further, the present invention is not limited to a flash memory, but can be applied to a mask ROM, an EPROM, and the like.
[0105]
Further, as the sense latch circuit, a ternary sense amplifier / latch circuit is used. However, the present invention is not limited to this, and a sense amplifier / latch circuit other than ternary values can be used.
[0106]
Of course, various modifications can be made without departing from the scope of the present invention.
[0107]
【The invention's effect】
As described above in detail, according to the present invention, after erasing data in a memory cell, the presence or absence of an over-erased cell is detected, and if an over-erased cell is detected, soft writing can be performed. It becomes possible. Therefore, control can be performed so that the threshold voltage of the memory cell after erasing does not drop below a predetermined voltage, so that erroneous writing can be prevented.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a sense amplifier and latch circuit of the present invention.
2A and 2B show a configuration of a NAND type EEPROM cell of the present invention, wherein FIG. 2A is a plan view and FIG. 2B is an equivalent circuit diagram.
3A is a cross-sectional view taken along line 3a-3a in FIG. 2A, and FIG. 3B is a cross-sectional view taken along line 3b-3b in FIG. 2A.
FIG. 4 is a circuit diagram showing a memory cell array of a NAND type EEPROM of the present invention.
FIG. 5 is a block diagram showing a configuration of a semiconductor memory device of the present invention.
FIG. 6 is a timing chart illustrating a data read operation of the present invention.
FIG. 7 is a timing chart shown to explain a data write operation of the present invention.
FIG. 8 is a timing chart shown to explain an erase operation of the present invention.
FIG. 9 is a timing chart shown to explain an erase verify read operation of the present invention.
FIG. 10 is a diagram illustrating an erase operation of the present invention.
FIG. 11 is a diagram illustrating an over-erase detection lead according to the present invention.
FIG. 12 is a timing chart for explaining over-erase detection read of a memory cell;
FIG. 13 is a timing chart for explaining over-erase detection read of a memory cell;
FIG. 14 is a timing chart illustrating software writing.
FIG. 15 is a diagram illustrating an erase operation of the present invention.
FIG. 16 is a view showing the second embodiment of the present invention and illustrating an overerased detection lead.
FIG. 17 illustrates the third embodiment of the present invention, and illustrates an over-erase detection lead and soft writing.
FIG. 18 shows the fourth embodiment of the present invention, and is a diagram for explaining the operation of over-erasure detection read and soft write.
FIG. 19 is a circuit diagram showing a fourth embodiment of the present invention.
FIG. 20 is a timing chart shown to explain over-erase detection read of a memory cell selected by a bit line BLO and a word line WL8.
FIG. 21 is a timing chart shown to explain over-erase detection read of a memory cell selected by a bit line BLE and a word line WL7.
FIG. 22 is a timing chart showing another example of software writing.
FIG. 23 illustrates another example of an erasing operation.
FIG. 24 is a timing chart showing a modification of the present invention.
[Explanation of symbols]
2 memory cell array, 3 row decoder, 4 sense amplifier / latch circuit, 10 column decoder, 11 control unit, 12 precharge circuit, BLE, BLO bit line, WL1 to WL8 word line, S / L1, S / L2: first and second sense latch circuits, I1 to I4, inverter circuits, MC1 to MC4, memory cells.

Claims (7)

A memory cell portion including a NAND memory cell in which a plurality of memory cells are connected in series,
Erasing means for erasing data in the memory cell;
After erasing by the erasing means, an over-erase detecting means for checking whether the memory cell is excessively erased,
A first signal line connected to one end of the NAND type memory cell;
A second signal line connected to the other end of the NAND memory cell;
Reading means connected to the first signal line and reading a threshold voltage of the memory cell;
With
The reading means,
A first switch connecting the first signal line and a first node;
A sense amplifier for detecting a potential of the first node;
A capacitor having one end connected to the first node and the other end connected to the second node;
The semiconductor memory device according to claim 1, wherein the potential applied to the second node is changed when the sense amplifier senses the potential of the first node. 2. The semiconductor memory device according to claim 1, further comprising soft writing means for performing weak writing on a memory cell which has been excessively erased. 3. The transistor according to claim 1, further comprising a transistor having a gate connected to an output terminal of the sense amplifier and outputting a signal when a memory cell excessively erased by the sense amplifier is detected. 13. The semiconductor memory device according to claim 1. A first signal line connected to one end of the memory cell;
A second signal line connected to the other end of the memory cell;
Reading means connected to the first signal line and reading a threshold voltage of the memory cell,
The reading means,
A first switch connecting the first signal line and a first node;
A sense amplifier for detecting a potential of the first node;
A capacitor having one end connected to the first node and the other end connected to the second node;
The semiconductor memory device according to claim 1, wherein the potential applied to the second node is changed when the sense amplifier senses the potential of the first node. 5. The semiconductor memory device according to claim 4, wherein a potential of said second signal line is set to a potential higher than a potential of said first signal line during a read operation. A first signal line connected to one end of the memory cell;
A MOS transistor having one end connected to the first signal line;
A detection node connected to the other end of the MOS transistor;
A capacitor having one end connected to the detection node and the other end connected to a second signal line;
A sense amplifier for detecting the potential of the detection node;
With
Fetching the potential of the first signal line into the detection node via the MOS transistor, thereafter changing the potential of the second signal line, and further detecting the potential of the detection node with the sense amplifier. A semiconductor memory device characterized by the above-mentioned. The other end of the memory cell is connected to a third signal line, a reference potential is applied to the third signal line, the first signal line is charged via the memory cell, and the first signal line is charged via the MOS transistor. 7. The semiconductor memory device according to claim 6, wherein said signal line potential is taken into said detection node.

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