JP2004013799A - Clock switching system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem on the waste consumption of an electric current in a PLL when the supply of a CPU clock to an UART is kept without switching the PLL to a standby state, in the software stop mode of a CPU. <P>SOLUTION: This system comprises a clock switching circuit 6 for switching the frequency of the clock supplied to a UART 7 between the software stop mode state and the usual operating state of a CPU core part 2. A REF clock is supplied to the UART 7 in the software stop mode of the CPU core part 2, and a CPU clock is supplied in the usual operating state. Whereby the UART 7 can be operated even in the standby state of the PLL 3, and the CPU core part can be recovered from the software stop mode by an interruption signal of the UART 7. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock switching system used for a microcomputer or the like and for switching a clock frequency.
[0002]
[Prior art]
FIG. 5 is a block diagram showing a conventional clock switching system. In the figure, reference numeral 8 denotes a system LSI incorporating a CPU, a PLL, and the like. The CPU core unit 9 is a core unit of the CPU, and is a basic unit for interpreting and executing instructions in the system LSI 8. The PLL 10 converts the frequency of the clock signal REFCLK input from outside the system LSI 8 into, for example, a clock signal CPUCLK having a double or triple frequency and outputs the same to the CPU core unit 9.
[0003]
When the CPU core unit 9 enters the software STOP mode, the PLL control circuit 11 sets the PLLON to the L level by the H-level signal SWSTOPRQ, thereby bringing the PLL 10 into a standby state. Further, the PLL 10 is set to the operating state by setting PLLON = H level by an interrupt signal CPUINT to the CPU core unit 9 output from the interrupt control circuit 12. The interrupt control circuit 12 ORs the interrupt signal EXTINT input from outside the system LSI 8 and the interrupt signal UARTINT input from the UART 13, and outputs an interrupt signal CPUINT to the CPU core unit 9.
[0004]
The UART 13 is operated by a clock signal REFCLK input from outside the system LSI 8 and a clock signal CPUCLK output from the PLL 10. TXD is a data output to the outside of the system LSI 8, and RXD is a data input from the outside of the system LSI 8. When the data input is completed, the UART 13 outputs an interrupt signal UARTINT to the interrupt control circuit 12, and the CPU core unit 9 is returned from the software STOP mode to the normal operation state.
[0005]
Next, the operation of the conventional system will be described. First, when the CPU core unit 9 shifts to the software STOP mode, the CPU enters the software STOP mode by setting the SWSTOPRQ signal = H. In the software STOP mode, there is no need to supply CPUCLK to the CPU core unit 9, so that the PLL 10 is set to the standby mode by the PLLON signal from the PLL control circuit 11. To return from the software STOP mode to the normal operation, the CPU is set to the normal operation state by the CPUINT signal input to the CPU core unit 9.
[0006]
When the CPU core unit 9 is in the normal state, the CPU 10 needs the CPUCLK, so that the PLL 10 is brought into the operating state by the PLLON signal from the PLL control circuit 11. The UART 13 re-times the CPU bus from the CPU core unit 9 with CPUCLK, performs internal register control, and operates an internal state machine with CPUCLK. Further, a baud rate used in TXD and RXD is internally generated by REFCLK from outside the system LSI 8.
[0007]
The CPU core unit 9 returns from the software STOP mode as an EXINT signal input to the interrupt control circuit 12 from the outside of the system LSI 8 or an interrupt signal UARTINT in the UART 13 due to reception of RXD data from the outside of the system LSI 8. Either.
[0008]
FIG. 6 shows a timing chart when the CPU core unit 9 returns from the software STOP mode by the EXINT signal. FIG. 6 shows REFCLK, EXTINT, UARTINT, CPUINT, SWSTOPRQ, the state of the CPU core unit, the state of PLLON, the PLL, the CPUCLK, TXD, and RXD.
[0009]
First, as shown in FIG. 6, when the CPU core unit 9 enters the software STOP mode, the PLL 10 enters a standby state, and the CPUCLK stops. As shown in FIG. 6, an EXINT interrupt from the outside of the system LSI 8 causes the CPU core unit 9 to return from the software STOP mode, the PLL 10 to operate, and the CPU core unit 9 to operate.
[0010]
FIG. 7 is a timing chart when the CPU core unit 9 returns from the software STOP mode by UARTINT. FIG. 7 shows REFCLK, EXTINT, UARTINT, CPUINT, SWSTOPRQ, the state of the CPU core, PLLON, the state of PLL, CPUCLK, TXD, and RXD, similarly to FIG. First, as shown in FIG. 7, when the CPU core 9 enters the software STOP mode, the PLL 10 enters a standby state, and the CPUCLK stops. In addition, the reception data from the RXD outside the system LSI 8 is input to the UART 13, but since the CPUCLK is stopped, the UART 13 does not operate the internal state machine and cannot generate the UARTINT. Cannot return from STOP mode.
[0011]
[Problems to be solved by the invention]
Conventionally, in order to solve the above problem, the PLL is not kept in the standby state and the CPUCLK is kept supplied, but this method has a problem that the current consumption of the PLL unit is wasted.
[0012]
SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described conventional problems, and an object of the present invention is to provide a clock switching system capable of operating a UART and returning from a software STOP mode even when a PLL is in a standby mode. .
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a CPU, a PLL that converts an external clock into a CPU clock of a predetermined frequency and supplies the CPU to the CPU, and a PLL control circuit that controls the PLL to a standby state or an operation state. And a UART that outputs data to the outside or receives data from the outside and outputs an interrupt signal, and the CPU is brought out of the software stop mode by an interrupt signal from the outside or an interrupt signal due to data reception from the UART. In a system for returning to the normal operation state, the system further comprises means for switching a frequency of a clock supplied to the UART between a case where the CPU is in the software stop mode state and a case where the CPU is in the normal operation state.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings. First, according to the present invention, when the CPU core unit is in the software STOP mode, the clock supply to the UART is switched to REFCLK supplied from outside the system LSI by hardware automatically or by software designation, instead of CPUCLK of PLL output. As a result, the UART operates even when the PLL is in the standby mode. As a result, the CPU core unit can be returned from the software STOP mode by an interrupt signal due to input of received data from the RXD of the UART.
[0015]
(1st Embodiment)
FIG. 1 is a block diagram showing a first embodiment of the clock switching system of the present invention. In FIG. 1, a system LSI 1 is a system LSI incorporating a CPU, a PLL, and the like. The CPU core unit 2 is a core unit of the CPU, and indicates a basic part for interpreting and executing instructions in the system LSI 1. The PLL 3 converts the frequency of the clock signal REFCLK input from outside the system LSI 1 into, for example, a clock signal CPUCLK having a double or triple frequency, and outputs the clock signal to the CPU core unit 2.
[0016]
When the CPU core unit 2 enters the software STOP mode, the PLL control circuit 4 outputs an H-level signal STOPREQ. This signal is re-synchronized with a clock signal RTCCLK input from outside the system LSI 1 to generate a signal PLLON. This is a circuit for setting the PLL 3 to the standby state by setting the PLL ON = L level. Also, the PLL 3 is set to the operating state by setting PLLON = H level by an interrupt signal CPUINT from the interrupt control circuit 5 to the CPU core unit 2. Further, the PLLON is retimed, and a switching timing signal PLLON2 is output to the clock switching circuit 6.
[0017]
The interrupt control circuit 5 ORs the interrupt signal EXTINT input from outside the system LSI 1 and the interrupt signal UARTINT input from the UART 7, and outputs an interrupt signal CPUINT to the CPU core unit 2. The clock switching circuit 6 automatically switches the clock SELCLK to be output to the UART 7 by hardware, outputs REFCLK to SELCLK when the PLLON signal input from the PLL control circuit 4 is at L level, and outputs REFCLK to SELCLK when it is at H level. Outputs CPUCLK as SELCLK.
[0018]
The UART 7 is operated by a clock signal REFCLK input from outside the system LSI 1 and a clock signal SELCLK output from the clock switching circuit 6, and generates an interrupt signal by outputting data to the outside or receiving data from the outside. . TXD shown in FIG. 1 is a data output to the outside of the system LSI1, and RXD is a data input to the outside of the system LSI1. When the data input is completed, the UART 7 outputs an interrupt signal UARTINT to the interrupt control circuit 5, and returns the CPU core unit 2 from the software STOP mode.
[0019]
Next, the operation of this embodiment will be described with reference to FIGS. FIG. 2 is a timing chart showing the operation of the present embodiment. FIG. 2 shows the timings of REFCLK, RTCCLK, EXTINT, UARTINT, CPUINT, SWSTOPRQ, CPU core state, PLLON, PLL state, PLLON2, CPUCLK, SELCLK, TXD, and RXD.
[0020]
First, when the CPU core unit 2 is operating, the UART 7 is supplied with REFCLK as a baud rate generation clock, and SELCLK for register control and state machine with CPUCLK. When the CPU core unit 2 enters the software STOP mode, SWSTOPRQ = H as shown in FIG.
[0021]
When SWSTOPRQ = H, the PLL control circuit 4 sets PLLON2 = L (internal signal = L) as shown in FIG. 2, and a signal PLLON = re-timed this internal signal with RTCCLK which is a clock clock from the outside of the system LSI1. L (see FIG. 2). The PLL3 immediately goes into the standby mode when PLLON = L, and stops supplying the CPUCLK as shown in FIG.
[0022]
The clock switching circuit 6 switches the SEL clock from CPUCLK to REFCLK at time T1 from PLLON2 = L to PLLON = L as shown in FIG. Thus, even in the software STOP mode state, the UART 7 is supplied with REFCLK as a baud rate generation clock and REFCLK for register control and state machine use. Accordingly, since the register control clock is not CPUCLK, register control cannot be performed. However, the state machine can be operated by REFCLK, and can be operated by data received by the RXD signal from outside the system LSI 1.
[0023]
In this case, since the CPU is in the software STOP mode state, the CPU core unit 2 cannot control the register to the UART 7 by the CPU bus, and there is no particular problem even if the register unit does not operate. Here, as shown in FIG. 2, when data received from the outside of the system LSI 1 by the RXD signal is input to the UART 7 during the software STOP mode, the UART 7 outputs an interrupt signal UARTINT to the interrupt control circuit 5 (see FIG. 2). ). The interrupt control circuit 5 outputs the UARTINT signal to the CPU core unit 2 and the PLL control circuit 4 as a CPUINT signal.
[0024]
When CPUINT is input, the CPU core unit 2 returns to the normal operation state from the software STOP mode as shown in FIG. 2, and when UARTINT is input at the same time, the PLL control circuit 4 causes the PLLON = 4 as shown in FIG. H, a signal PLLON2 = H is output by retiming the PLLON with RTCCLK, which is a clock clock from outside the system LSI1. As soon as PLL3 becomes H, the PLL 3 is brought into the operating state, and starts supplying the CPUCLK as shown in FIG.
[0025]
As shown in FIG. 2, the clock switching circuit 6 switches the SEL clock from REFCLK to CPUCLK at a time T2 from PLLON = H to PLLON2 = H. By the above operation, the state is returned from the software STOP mode state to the normal operation state. The return operation from the software STOP mode state by the EXINT signal which is an interrupt from the outside of the system LSI 1 is performed by the interrupt control circuit 5 because EXINT is output to the CPUINT as it is, regardless of SELCLK supplied to the UART7. The CPU core unit 2 returns from the software STOP mode state.
[0026]
(Second embodiment)
FIG. 3 is a block diagram showing a second embodiment of the present invention. In FIG. 3, a system LSI 14 is a system LSI including a CPU, a PLL, and the like. The CPU core unit 15 is a core unit of the CPU, and indicates a basic part for interpreting and executing instructions in the system LSI 14. The PLL 16 converts the frequency of the clock signal REFCLK input from outside the system LSI 14 into, for example, a clock signal CPUCLK having a double or triple frequency, and outputs the clock signal to the CPU core unit 15.
[0027]
When the CPU core unit 15 enters the software STOP mode, the PLL control circuit 17 outputs an H-level signal STOPREQ. The PLL control circuit 17 generates a signal PLLON in which this signal is resynchronized with a clock signal RTCCLK input from outside the system LSI 14. Then, the PLL 16 is brought into a standby state by setting PLLON = L level. Further, the PLL 16 is set to the operating state by setting PLLON = H level by an interrupt signal CPUINT from the interrupt control circuit 18 to the CPU core unit 15.
[0028]
The interrupt control circuit 18 ORs the interrupt signal EXTINT input from outside the system LSI 14 and the interrupt signal UARTINT input from the UART 20, and outputs an interrupt signal CPUINT to the CPU core unit 15. The register switching circuit 19 switches between outputting the clock SELCLK to be output to the UART 20 and outputting REFCLK to SELCLK or outputting CPUCLK to SELCLK by software using the CPU bus output from the CPU core unit 15.
[0029]
The UART 20 is operated by a clock signal REFCLK input from outside the system LSI 14 and a clock signal SELCLK output from the register switching circuit 19, and outputs an external data or receives external data to generate an interrupt signal. TXD shown in FIG. 3 is a data output to the outside of the system LSI 14, and RXD is a data input to the outside of the system LSI 14. When the data input is completed, the UART 20 outputs an interrupt signal UARTINT to the interrupt control circuit 18, and returns the CPU core unit 15 from the software STOP mode.
[0030]
Next, the operation of this embodiment will be described with reference to FIGS. FIG. 4 is a timing chart showing the operation of the present embodiment. FIG. 4 shows the timings of REFCLK, RTCCLK, EXTINT, UARTINT, CPUINT, SWSTOPRQ, CPU core state, PLLON, PLL state, CPUCLK, SELCLK, TXD, and RXD.
[0031]
First, when the CPU core unit 15 is in the operating state as shown in FIG. 4, the UART 20 is supplied with REFCLK as a baud rate generation clock and SELCLK for register control and SELCLK for a state machine. Here, as shown in FIG. 4, at timing T3 before the CPU core unit 15 enters the software STOP mode, the CPU core unit 15 controls the register switching circuit 19 via the CPU bus to switch SELCLK from CPUCLK to REFCLK. .
[0032]
When the CPU core unit 15 enters the software STOP mode as shown in FIG. 4, it sets SWSTOPRQ = H. When SWSTOPRQ = H, the PLL control circuit 17 sets PLLON = L (internal signal = L) as shown in FIG. The PLL 16 immediately enters the standby mode when PLLON = L, and stops supplying the CPUCLK as shown in FIG.
[0033]
At this time, since the clock switching has already been performed under the control of the CPU bus of the CPU core unit 15, REFCLK is supplied to the UART 20 as a baud rate generation clock and REFCLK for register control and state machine use even in the software STOP mode state. Therefore, since the register control clock is not CPUCLK, register control cannot be performed, but the state machine can operate with REFCLK and can operate with received data by an RXD signal from outside the system LSI 14.
[0034]
Further, since the state is the software STOP mode, there is no control of the register from the CPU core unit 15 to the UART 20 by the CPU bus, and there is no particular problem even if the register unit does not operate. Here, when data received by the RXD signal from outside the system LSI 14 is input to the UART 20 during the software STOP mode, the UART 20 outputs an interrupt signal UARTINT to the interrupt control circuit 18 as shown in FIG. The interrupt control circuit 18 outputs the UARTINT signal as a CPUINT signal to the PLL control circuit 17 and the CPU core unit 15, respectively.
[0035]
When CPUINT is input, the CPU core unit 15 returns from the software STOP mode to the normal operation state as shown in FIG. 4, and when UARTINT is input, the PLL control circuit 17 sets PLLON = H. As soon as PLLON = H, the PLL 16 is brought into the operating state, and starts supplying the CPUCLK as shown in FIG. Further, after the CPU core unit 15 returns from the software STOP mode state to the normal operation state, the CPU core unit 15 controls the register switching circuit 19 via the CPU bus at timing T4 shown in FIG. 4 to switch SELCLK from REFCLK to CPUCLK. I do. As a result, the UART 20 is in a state where register control from the CPU core unit 15 is possible.
[0036]
By the above operation, the state is returned from the software STOP mode state to the normal operation state. The return operation from the software STOP mode state by the EXINT signal which is an interrupt from the outside of the system LSI 14 is performed by the interrupt control circuit 18 because EXINT is output to the CPUINT as it is, regardless of SELCLK supplied to the UART 20. The core unit 15 returns from the software STOP mode state.
[0037]
【The invention's effect】
As described above, according to the present invention, the clock generated from the PLL is switched to another clock while the PLL is in a standby state by hardware automatically or by software control using a macro such as UART which requires two clocks. Since a macro such as a UART can be operated, the macro such as the UART can be operated even during the standby of the PLL, and the CPU can be returned from the software STOP mode by an interrupt signal of the macro such as the UART. Further, conventionally, it was necessary to put the PLL into an operating state in order to operate a macro such as a UART. However, in the present invention, since the PLL can be placed in a standby state, the operating current of the PLL can be reduced, and power consumption can be reduced. Can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a clock switching system of the present invention.
FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1;
FIG. 3 is a block diagram showing a second embodiment of the present invention.
FIG. 4 is a timing chart for explaining the operation of the embodiment of FIG. 3;
FIG. 5 is a block diagram showing a conventional clock switching system.
FIG. 6 is a timing chart for explaining the operation of the conventional system of FIG. 5 when returning from the software STOP mode by an EXINT signal.
FIG. 7 is a timing chart for explaining an operation when returning from the software STOP mode by UARTINT of the conventional system of FIG. 5;
[Explanation of symbols]
1,14 System LSI
2,15 CPU core unit 3,16 PLL
4, 17 PLL control circuit 5, 18 Interrupt control circuit 6 Clock switching circuit 7, 20 UART
19 Register switching circuit

Claims (7)

A CPU, a PLL that converts an external clock into a CPU clock having a predetermined frequency and supplies the CPU clock to the CPU, a PLL control circuit that controls the PLL to a standby state or an operation state, and outputs data to the outside or data from the outside. And a UART for receiving an interrupt signal from the UART and returning the CPU to a normal operation state from a software stop mode by an external interrupt signal or an interrupt signal due to data reception from the UART. A clock switching system comprising: means for switching a frequency of a clock supplied to the UART depending on whether the device is in a software stop mode state or a normal operation state. The switching means switches a frequency of a clock supplied to the UART immediately before the CPU enters the software stop mode, and a clock supplied to the UART immediately after the CPU returns to the normal operation state from the software stop mode. 2. The clock switching system according to claim 1, wherein the frequency is returned to the original clock frequency. When the CPU is in the software stop mode, the clock supplied to the UART is set to a low-speed clock, and the CPU is returned from the software stop mode by an interrupt signal due to external data reception of the UART. The clock switching system according to claim 1, wherein The clock switching system according to claim 1, wherein the PLL is in an operating state while the CPU is operating, and is in a standby state while the CPU is in a software stop mode. 5. The PLL according to claim 1, wherein the PLL is controlled to a standby state by a stop mode signal from the CPU, and the CPU is controlled to an operation state after returning from the software stop mode by an interrupt signal. Clock switching system. The switching means switches a frequency of a clock supplied to the UART during a signal change time between a signal corresponding to a stop mode signal from the CPU and a signal obtained by retiming the signal with an external clock. The clock switching system according to claim 1, wherein: 8. The clock switching system according to claim 1, wherein the switching unit switches to the high-speed CPU clock during the operation of the CPU, and to the low-speed reference clock while the CPU is in the software stop mode. .

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