JP2004005994A - Data-eproducing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform display or a control operation of which the timing is, in correspondence with timing of an audio output signal, while effectively using recording capacity, such that only main data are stored in a buffer RAM 6. <P>SOLUTION: Main data are extracted by decoding data read from a disc using a signal processing unit 4, and write and read are controlled for a buffer RAM 6 by a RAM controller 5, thereby the main data are sent to a igital/analog converter 7 at a constant rate and output via LPF 8. A system controller 10 obtains the delay amount between the write-in and read-out based on the data amount stored in the buffer RAM 6, and makes time or control data of sub-code data from the unit 4 to be delayed, only by the delay amount and makes the data to be displayed on a display unit 11, or makes the LPF 8 to perform switching control. <P>COPYRIGHT: (C)2004,JPO

Description

【００３５】
ただし、この場合、計算後のデータには誤差が発生し、ＣＤの経過時間等の表示では時間が戻ったりすることもある。このような場合には、計算値が誤差分によって減ることのないようプログラムで対応することにより、不自然な感じを防ぐことができる。
【００３６】
また、アドレス差ΔＡを、数字により、あるいは視覚的な量の表現により、表示部１１に表示することにより、機器の使用者にバッファ用ＲＡＭ６のメモリ残量やメモリ記憶データ量等を知らせることができ、動作状態の確認等に有用である。ここで上記視覚的な量を表現するような表示とは、例えばバッファ用ＲＡＭ６を想起させる容器を表現する固定表示エレメントと、この固定表示エレメントに囲まれる位置に配置されＲＡＭ６に記憶されている再生可能なデータ量を逐一表現する可変表示エレメントとにより実現できる。
【００３７】
以上の説明からも明らかなように、本発明の実施の形態によれば、メモリ（ＲＡＭ６）にはメインデータを蓄えるだけでよく、メモリ容量が有効に使用でき、なおかつ書込データの情報で読出メインデータをコントロールしたりできる。また、サブコードＱデータによる絶対時間Ｔ_ＱＡＢＳや曲内経過時間（ラップタイム）Ｔ_ＱＬＡＰ等から上記バッファ用ＲＡＭ６での遅延量の時間Ｔｄを減算するだけで、実際に再生されるメインデータに対してタイミングの一致した時間情報（Ｔ_ＡＢＳ　やＴ_ＬＡＰ　等）を得ることができ、適切な表示を行わせることができ、バッファ用ＲＡＭ６内の再生可能なデータ量を表示して装置の動作状態を知らせることもできる。また、ディエンファシス切換等の再生データの制御を正しいタイミングで行わせることができる。さらに、ポーズ、Ａ−Ｂリピート等の特別な動作を行わせるときも、違和感のない自然な操作や表示が行える。
【００３８】
すなわち、本発明に係るデータ再生装置の実施の形態によれば、メインデータに補助データが付加された記録データを記録媒体から読み出して上記メインデータを分離し、バッファ用メモリに対して書込／読出を制御する際に、このバッファ用メモリに記憶されている再生可能なデータの量に応じた書込、読出間の遅延量と上記記録媒体から読み出された上記補助データから得られる時間関連情報とに基づき、上記バッファ用メモリから読み出されているメインデータの時間関連情報を算出しているため、上記バッファ用メモリにはメインデータのみを蓄えればよく記憶容量の有効利用率が高まり、該バッファ用メモリから読み出されて実際に再生されているメインデータに対してタイミングの一致した時間関連情報が得られる。
【００３９】
また、本発明に係るデータ再生装置の実施の形態によれば、上記補助データから得られるディエンファシス切換等の制御情報信号を、上記バッファ用メモリに記憶されている再生可能なデータの量に応じた書込、読出間の遅延量の時間だけ遅延させて、ディエンファシス切換等の制御を行わせているため、上記バッファ用メモリから読み出されているメインデータに対する制御が正しいタイミングで行われる。
【００４０】
なお、本発明は上記実施例のみに限定されるものではなく、例えば、記録媒体としては、光ディスクの他にも、光磁気ディスク、磁気ディスク、磁気テープ等が使用でき、フォーマットもいわゆるＣＤフォーマットに限定されない。また、ＰＣＭオーディオデータ以外に、ビデオデータや、圧縮処理されたデータ等も、上記メインデータとして使用できる。さらに、補助データは上記サブコードデータに限定されず、また誤り訂正処理を行わないようなフォーマットにも適用できる。ハードウェア構成も図示の例に限定されないことは勿論である。
【００４１】
【発明の効果】
以上の説明からも明らかなように、本発明に係るデータ再生装置によれば、メインデータと補助データとからなる記録データが記録された記録媒体から上記記録データを再生する再生手段と、上記再生手段にて再生された記録データから上記メインデータと上記補助データとを分離する分離手段と、上記分離されたメインデータを一旦記憶する記憶手段と、上記記憶手段に対して上記メインデータを第１の転送レートで間欠的に書き込み、上記記憶手段に記憶された上記メインデータを上記第１の転送レートより遅い第２の転送レートで連続的に読み出し制御する記憶制御手段と、上記記憶手段に記憶されている変動するメインデータの記憶量と上記記憶手段から読み出されるメインデータの転送レートとに基づいて、上記記憶手段に記憶されているメインデータの書き込みから読み出しまでの遅延量を算出する演算手段と、上記分離手段にて分離された補助データに基づいて、上記記憶手段から読み出されるメインデータに対応した時間情報の表示を行う表示手段と、上記演算手段にて演算された変動する遅延量に基づいて上記表示手段の時間表示を制御する制御手段とを有しているため、上記記憶手段にはメインデータのみを蓄えればよく記憶容量の有効利用率が高まり、また該記憶手段から読み出されたメインデータについてはタイミングの一致した時間情報を得て表示することができる。
【図面の簡単な説明】
【図１】本発明に係るデータ再生装置の一実施例の全体の概略構成を示すブロック図である。
【図２】上記実施例中の信号処理部の具体例を示すブロック回路図である。
【図３】上記実施例中のＲＡＭコントローラの具体例及びその周辺を示すブロック回路図である。
【図４】上記実施例中のバッファ用ＲＡＭのメモリ空間上での書込アドレス及び読出アドレスの移動を説明するための図である。
【図５】上記図３中のアドレス生成回路の内部構成の一例を示すブロック図である。
【符号の説明】
１　光ディスク、　２　光ピックアップ、　４　信号処理部、　５　ＲＡＭコントローラ、　６　バッファ用ＲＡＭ、　９　サーボ制御回路、　１０　システムコントローラ、　１１　表示部、　１２　キー入力部、　１３　書込アドレスカウンタ、　１４　有効書込アドレスカウンタ、　１５　読出アドレスカウンタ、　１６　減算器、　２１　ＥＦＭ復調回路、　２３　ＰＬＬ・タイミング発生回路、　２４　サブコードＱ処理回路、　２５　誤り訂正処理回路、　２６　デコード処理用ＲＡＭ、　２７　読出／書込制御回路、　２９　タイミング発生回路、　３１，３３，３５　レジスタ、　３６　データ比較器[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data reproducing apparatus that stores data read from a recording medium in a memory, reads the data from the memory at a constant rate, and reproduces the data.
[0002]
[Prior art]
Generally, in a tape recorder or a disc player for recording and / or reproducing a digital audio signal, a digital video signal, and the like, the recording digital signal includes digital audio data, digital video data, and the like that have been subjected to error correction coding processing and interleaving processing. Many data have main data and auxiliary data such as address information and control information. For example, in the format of a so-called compact disc (CD), stereo left and right two-channel audio signals are each sampled at 44.1 kHz and quantized by 16 bits to obtain an audio PCM signal, which is obtained by CIRC (Cross Interleaved Reed-Solomon code). Encoding processing is performed as main data. This main data includes auxiliary data including information such as identification information indicating whether the song is a song or between songs, a song number (track number), an elapsed time (lap time) in the song, an absolute time (absolute time), and emphasis control. The subcode data is added to form recording data, and the recording data is modulated by an EFM (8-14 modulation) method to form a recording signal.
[0003]
When a compact disc (CD) having such a format is reproduced by an ordinary reproducing apparatus, a clock component is generally detected (clock reproduced) from a EFM signal read from the disc using a PLL (phase locked loop) configuration. The reproduced clock fetches binary data, and demodulates the EFM signal. The data after the EFM demodulation is usually subjected to decoding (decoding) processing including error correction and deinterleaving based on the CIRC using a RAM for decoding processing to be converted into a digital audio signal (PCM signal). Data is written to the decode processing RAM in synchronization with the reproduction clock of the PLL system, and data is read in synchronization with a clock from a reference oscillator such as a crystal oscillator. The digital audio PCM signal obtained by the decoding process becomes an analog audio signal via a D / A converter and a low-pass filter (LPF).
[0004]
By the way, in a data reproducing apparatus, particularly an apparatus having an optical pickup such as the above-mentioned CD player, a servo system such as a focus servo and a tracking servo of the optical pickup is disengaged due to mechanical disturbance such as shock or vibration to the device. In some cases, normal data reproduction cannot be performed. In this case, it is not possible to cope with the error correction as described above, and the reproduction may be temporarily interrupted.
[0005]
In view of this, the applicant of the present application has disclosed in Japanese Patent Application Laid-Open No. H10-15095 such that the reproduced data is stored in a relatively large-capacity buffer RAM and read at a constant rate, and the buffer RAM always has a predetermined amount of data. By storing the above reproduction data, even if normal data cannot be obtained from a medium such as a disk due to a reading error or the like, the data stored in the buffer RAM is read to reproduce a reproduction signal such as sound cutoff. A system that compensates for the interruption of the system is proposed.
[0006]
As such a system, for example, in the case of a compact disk reproducing apparatus as described above, data is read out from a disk at high speed in a burst (intermittent) manner and sequentially written into the buffer RAM, and data is continuously read from the RAM. When reading data at a constant rate and writing data to the buffer RAM, it is necessary to control the write address and store adjacent data in the RAM in a continuous state. Specifically, for example, the disk is rotated at a rotation speed of about twice or three times to four times the standard, and the data read from the disk is divided into sub-coding frames (sub-code blocks, 13.3 msec during standard reproduction). (Length) in the buffer RAM.
[0007]
[Patent Document 1]
Japanese Patent No. 2973539 (JP-A-04-330670)
[0008]
[Problems to be solved by the invention]
By the way, in a data reproducing apparatus using such a buffer RAM, for example, a CD player, between data read from a disk and a signal (music or the like) read from the buffer RAM and currently reproduced. Has a time difference at least corresponding to the data stored in the buffer RAM. The decoded main data (PCM data) itself includes auxiliary information such as the subcode data, that is, information such as a song number (track number), an absolute time, a time in a song (lap time), and de-emphasis. Etc. are not left.
[0009]
Therefore, if the display of the music number and the time of the reproduced music or the control of the de-emphasis using the subcode data read from the disc is performed, a deviation from the music actually reproduced occurs due to the time difference. Therefore, unnatural display, unnatural de-emphasis switching, or the like is performed.
[0010]
Here, not only the main data but also auxiliary data (subcode data and the like) may be stored in the buffer RAM as it is, but the storage capacity of the main data is reduced by that amount, and the write / read processing and configuration are also reduced. It is complicated and not preferable.
[0011]
SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has been described in a data reproducing apparatus which controls writing / reading of main data read and reproduced from a medium such as a disk to / from a buffer memory. To provide a data reproducing apparatus capable of displaying time information and the like having an accurate correspondence with main data read from a memory for use and performing control such as de-emphasis switching at a correct timing. And
[0012]
[Means for Solving the Problems]
A data reproducing apparatus according to the present invention includes: a reproducing unit that reproduces the recording data from a recording medium on which recording data including main data and auxiliary data is recorded; and a main unit that reproduces the main data from the recording data reproduced by the reproducing unit. Separating means for separating the main data from the auxiliary data, storing means for temporarily storing the separated main data, and writing the main data to the storing means intermittently at a first transfer rate; Storage control means for continuously reading and controlling the main data stored in the memory at a second transfer rate lower than the first transfer rate; and a storage amount of the variable main data stored in the storage means. Based on the transfer rate of the main data read from the storage means, the main data stored in the storage means is written and read. Calculating means for calculating an amount of delay until then, display means for displaying time information corresponding to main data read from the storage means based on the auxiliary data separated by the separating means, and the calculating means The above-mentioned problem is solved by having a control means for controlling the time display of the display means based on the fluctuating delay amount calculated in.
[0013]
In this case, a buffer memory is used as the storage means, and the control means obtains a delay amount between writing and reading according to the amount of reproducible data stored in the buffer memory. In this case, the control information signal obtained from the auxiliary data is delayed by the amount of the delay amount to control the main data read from the buffer memory.
[0014]
In this case, the buffer memory has a ring-shaped address memory space, and the delay amount (time difference) is determined according to the address difference from the write address to the read address. The auxiliary data is, for example, subcode Q data in a so-called CD format. The subcode Q data includes absolute time (absolute time) information from the head position of the disc, elapsed time (lap time) information for each song, Time-related information such as number (track number) information and index number information, and control information such as emphasis information are included. When displaying such time information or number information or performing control such as de-emphasis switching, the obtained information of the subcode Q data is displayed after being delayed by the time of the delay amount in the buffer memory. That is, it is made to perform control. Here, the time information such as the absolute time or the elapsed time in the music (lap time) is obtained by subtracting the delay time from the value of each time information obtained from the auxiliary data (subcode Q data). Can be.
[0015]
In addition, the amount of reproducible data stored in the buffer memory is displayed, and the time-related information is calculated in consideration of the delay amount even during special reproduction such as pause or AB repeat. Is preferred.
[0016]
Time-related information at the same timing as the main data read from the buffer memory and actually reproduced is obtained, and control such as de-emphasis switching is performed.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of an apparatus in which a data reproducing apparatus according to the present invention is applied to a so-called compact disc (CD) player. That is, on the optical disk 1, so-called CD-format recording data is recorded. The so-called CD format will be briefly described. Upper and lower 8 bits of PCM digital audio data of 16 bits per word are separated into symbols which are error correction coding units. (Reed-Solomon code), an error correction parity is added, and an interleave process is performed. The main data of a total of 32 symbols of 24 symbols of the CIRC-encoded audio data and 8 symbols of parity constitutes one recording unit (frame), to which a so-called sub-code, which is 8-bit auxiliary data, is added. The frame is modulated by an 8-14 modulation method and a frame synchronization pattern is added, so that one frame is recorded on the optical disc 1 as an EFM signal of 588 channel bits. The sub-code is one block (sub-coding frame) of 98 frames, and carries auxiliary information for eight channels P to W. The Q channel of this subcode includes auxiliary data such as a song number, an index number, an elapsed time in the song, and an absolute time.
[0018]
In FIG. 1, the optical disc 1 is rotated by a drive motor 13 at a speed higher than a standard speed (linear speed) (for example, twice as fast), and a signal is read out intermittently or burst by an optical pickup 2 to preamplify. The signal is amplified at 3 and sent to the signal processing unit 4 as a so-called RF signal. This RF signal is a signal modulated by the above-described EFM method, and is subjected to processing such as EFM demodulation, deinterleaving, error correction, interpolation, and decoding of a subcode in the signal processing unit 4, and its main data ( The audio PCM data) output is stored in the buffer RAM 6 via the RAM controller 5. The data transfer rate up to this point is higher (eg, twice as high) than the standard reproduction rate in accordance with the high-speed disk rotation drive. However, the reading of data from the optical disk 1 is performed intermittently or in a so-called burst manner, and even if the instantaneous data transfer rate is higher than the standard, the average rate including the read pause period is almost the same as the standard reproduction. Rate. In this way, the data sent and stored intermittently or burstwise to the buffer RAM 6 is continuously read out by the RAM controller 5 at the standard reproduction rate, and the D / A converter 7 and the LPF (low-pass filter) are used. ) 8 to be extracted as an analog audio output signal.
[0019]
The servo control circuit 9 performs control operations such as focus servo, tracking servo, spindle motor servo, and thread (head movement) servo. That is, focus control of the optical system of the optical pickup 2 is performed by the focus servo so that the focus error signal becomes 0, and tracking control of the optical system of the optical pickup 2 is performed by the tracking servo so that the tracking signal becomes 0. Further, the rotation of the spindle motor 13 is controlled by the spindle motor servo so that the optical disc 1 is driven to rotate at a predetermined linear velocity (for example, twice the standard linear velocity). Further, the sled servo controls the movement of the optical pickup 2 to a target track position of the optical disk 1 specified by the system controller 10. The servo control circuit 9 that performs such various control operations sends information indicating the operation state of each unit controlled by the servo control circuit 9 to the system controller 10.
[0020]
The system controller 10 includes a CPU (Central Processing Unit) such as a microprocessor for controlling the operation of each unit, a ROM (Read Only Memory) in which a control program executed by the CPU is stored in advance, and various types of data. A so-called microcontroller having a RAM (random access memory) that is read and temporarily stored, and an I / O (input / output) circuit for transmitting and receiving various signals between the CPU and the outside. It is a computer (microcomputer) system. The system controller 10 is connected to a display unit 11 for displaying an operation state of each unit, a key input operation unit 12 for instructing various operations, and the like. As the display unit 11, for example, an LCD (liquid crystal display), an LED (light emitting diode) display, an FL display, a plasma display, or the like is used. The key input operation unit 12 is provided with various operation keys such as a play button, a stop button, and a fast forward button. The system controller 10 sends and receives signals to and from the signal processing unit 4 and the RAM controller 5, and controls the operations of the signal processing unit 4 and the RAM controller 5.
[0021]
Here, for example, when a cause occurs that the servo system is disturbed due to disturbance or the like and the reproduction signal is interrupted, that is, specifically, for example, a) when the focus is out of focus, b) the subcode Q data is discontinuous. In the case where the error occurs, c) when the PLL system becomes unstable for a certain period of time or more, d) when the interpolation processing is performed (the interpolation flag is set), the system controller 10 monitors it, and the like. The writing to the buffer RAM 6 is interrupted. Then, after returning the servo system, for example, an address immediately before the interruption of the reproduction signal is accessed, and writing is restarted from the address position. As a result, as long as the data stored in the buffer RAM 6 does not become empty, continuous reproduction output can be obtained. Also, when the data stored in the buffer RAM 6 becomes full, the writing to the RAM 6 is temporarily interrupted, and a pause operation or the like is started.
[0022]
By the way, the RF signal input to the signal processing unit 4 is synchronized with a so-called PLL clock including the rotation unevenness of the optical disc 1, while the main data output to the RAM controller 5 is used as a reference clock. For example, since it is synchronized with a so-called crystal clock, jitter exists between the two. For this reason, if the timing at which the writing to the buffer RAM 6 is started is made dependent on the absolute time obtained by decoding the so-called subcode Q data in the signal processing unit 4, a connection error such as data loss or duplication occurs. I do. For this reason, a data comparison block is provided in the RAM controller 5 so that the data of the last few samples of the data written in the buffer RAM 6 and the data sent from the signal processing unit 4 to the RAM 6 via the RAM controller 5 are stored. And the data from the signal processing unit 4 is written to the buffer RAM 6 when the data match.
[0023]
That is, FIG. 2 shows a specific example of the signal processing unit 4, and FIG. 3 shows a specific example of the RAM controller 5. 2, the RF signal from the preamplifier 3 is sent to an EFM demodulation circuit 21, a synchronization detection circuit 22, and a PLL / timing generation circuit 23, respectively. The EFM demodulation circuit 21 demodulates the RF signal modulated by the EFM method, and sends the main data signal to the data bus DB and the subcode data signal to the subcode Q processing circuit 24. The synchronization detection circuit 22 detects the sub-coding frame synchronization signal and sends it to the PLL / timing generation circuit 23. The PLL / timing generation circuit 23 detects the channel bit clock (EFM clock) component of the RF signal, locks the PLL, and divides the channel bit clock by using the sub-coding frame synchronization signal. , A word clock, a bit clock of data after EFM demodulation, and the like, and send a write clock WCK to the read / write control circuit 27. Further, a sub-coding frame synchronization signal or the like is output from the PLL / timing generation circuit 23 and is used for, for example, a spindle servo. Subcode Q data and the like are serially output from the subcode Q processing circuit 24 and are used as current position information of the optical pickup 2 on the optical disk 1.
[0024]
The main data (audio data and parity data for error detection and correction) sent from the EFM demodulation circuit 21 to the data bus DB is written from the PLL / timing generation circuit 23 including a jitter component due to uneven rotation of the optical disc 1 or the like. The data is written to the decoding RAM 26 by the read / write control circuit 27 in synchronization with the write clock WCK. After that, while the read / write to / from the decoding RAM 26 is controlled by the read / write control circuit 27, error detection / correction processing and deinterleave processing by the error correction processing circuit 25 are performed based on the CIRC. . The decoding RAM 26 has such a capacity that a predetermined margin (for example, ± 24 frames) can be obtained for absorbing the jitter, in addition to the capacity required for the CIRC decoding (for example, about 108 frames). For example, a 32 kbit RAM is used. The decoded main data (PCM data) is read from the decoding RAM 26 by the read / write control circuit 27 in synchronization with a read clock RCK from a timing generation circuit 29 having a reference oscillator such as a crystal oscillator. And sent to the interface circuit 28. The interface circuit 28 outputs the decoded main data and various clocks such as a bit clock BCK, a word clock WDCK, and an LR (for switching between left and right stereo channel words) clock LRCK. The RAM controller 5 and the system controller 10 etc. Here, the write / read operation is performed intermittently at a speed higher than the standard, for example, twice as fast.
[0025]
Next, in FIG. 3, input data from (the interface circuit 28 of) the signal processing circuit 4 is sent to the register 31 and stored as 16-bit PCM data per sample, and the system controller 10 permits data writing. In this case, the data is written to the buffer RAM 6 via the data selector 32 in accordance with the write address output from the address generation circuit 34. At this time, data writing is performed intermittently at a speed higher than the standard. Data is read from the buffer RAM 6 via the data selector 32 into the register 33 in accordance with the read address output from the address generation circuit 34, and is read out at a constant reproduction rate according to the sampling frequency (for example, 44.1 kHz). The signal is continuously output from the D / A converter 33 and sent to the D / A converter 7.
[0026]
Here, when the writing to the buffer RAM 6 as described above is temporarily interrupted and then resumed, that is, when the data connection is performed, the address at the time when the data was last written into the buffer RAM 6 is determined by the address generation circuit 34. The data is output from the buffer RAM 6 to the register 35 via the data selector 32. This data is compared with the data input from the signal processing unit 4 to the register 31 by the data comparator 36, and when they match, a match output is issued to determine the timing of data connection. That is, the input data from the signal processing unit 4 after the coincidence output is obtained may be written into the buffer RAM 6.
[0027]
Next, FIG. 4 schematically shows a write / read operation for the buffer RAM 6 in a memory space, and FIG. 5 shows an example of an internal configuration of the address generation circuit 34. 4 and 5, when the write enable signal W-EN from the system controller 10 of FIG. 1 is sent to the write address counter 13, the write address counter 13 operates and the write address counter 13 becomes higher than the standard. Generate a write address WA which proceeds at a high speed (increments). The data is written to the buffer RAM 6 by the write address WA. Further, the system controller 10 or the like confirms a skip in sound by checking subcode information or the like, and sends a state good signal SOK to the valid write address latch 14 if there is no problem. Effective write address latch 14 latches write address WA from write address counter 13 in response to this signal SOK, and outputs it as effective write address VWA. The stored data up to the address VWA is reproducible data with no sound skip or the like, and can be sent to the D / A converter 7.
[0028]
Further, the read address counter 15 operates in response to the read enable signal R-EN from the system controller 10, generates a read address RA that advances at a standard speed, and sequentially reads the data written in the buffer RAM 6. Since the step speed (write speed) of the write address WA is higher than the speed (read speed) of the step operation (increment) of the read address RA, the address WA becomes the address RA in the loop memory space. In this case, the step operation of the write address WA is stopped, and the writing is resumed when the read address RA advances and the remaining amount of data falls below a predetermined amount (step of the write address WA). Resuming operation). The remaining data amount at this time indicates the amount of data that can be actually reproduced from the effective write address VWA to the read address RA. The subtracter 16 obtains an address difference ΔA obtained by subtracting the address RA from the address VWA.
[0029]
Here, the time between the data read from the buffer RAM 6 and sent to the D / A converter 7 and the time information of the subcode obtained by the subcode Q processing circuit 24 or the like and held by the system controller 10 is stored. The time difference is obtained by adding the delay amount in the decoding RAM 26 and the delay amount in the buffer RAM 6. The delay amount in the decoding RAM 26 is about tens of msec even if the jitter correction amount described above is included. In the following description, only the amount of delay in the buffer RAM 6 is taken into consideration.
[0030]
Therefore, the time difference Td between the actual reproduced data and the time information of the subcode is obtained by dividing the data amount Dm according to the address difference ΔA (= VWA−RA) by the data read rate Dr. Assuming that the number of bits of the storage unit (word) for one address of the buffer RAM 6 is n, the time difference Td is Td = Dm / Dr = (n × ΔA) / Dr.
[0031]
From the above, the system controller 10 delays all the subcode information received from the subcode Q processing circuit 24 or the like of the signal processing unit 4 by the time difference Td, and performs control operations such as actual time display and deemphasis switching. Should be performed. That is, the display unit 11 displays the absolute time T _ABS And the elapsed time (lap time) T in the song _LAP Is displayed, the absolute time T obtained from the subcode Q information is used. _QABS And time T in the song _QLAP The values obtained by subtracting the time differences Td from the above may be displayed. Also, when switching control such as de-emphasis is performed, the contents can be made to match the contents of the reproduced audio signal by switching with a delay of the time differences Td. The same applies to the display of the song number (track number) and the index number.
[0032]
Further, even in a special reproduction state such as a pause (pause) or a repeat between A and B, by performing control while taking the time difference Td into consideration, an unnaturalness occurs between display of the apparatus, audio output, and key operation. You can avoid giving a feeling.
[0033]
For the address difference ΔA, it is not necessary to obtain all bits of the address bit number (for example, 20 bits), and it may be possible to use several higher-order bits depending on required accuracy. Here, as a specific example of the buffer RAM 6, the bit number n of one word is 4 bits and the bit number of the address is 20 bits (A ₀ ~ A ₁₉ ), A memory having a storage capacity of 4 Mbits is used. ₁₆ ~ A ₁₉ ) Alone, the accuracy can be distinguished in 0.25 Mbit units. Assuming that the data read rate Dr is about 1.4 Mbit / sec, a 20-bit address (A ₀ ~ A ₁₉ ) Upper 4 bits (A ₁₆ ~ A ₁₉ ), And the amount of time conversion [sec. Table 1 is shown in Table 1 below.
[0034]
[Table 1]

[0035]
However, in this case, an error occurs in the calculated data, and the time may be returned in the display of the elapsed time of the CD or the like. In such a case, an unnatural feeling can be prevented by using a program so that the calculated value is not reduced by the error.
[0036]
In addition, the address difference ΔA is displayed on the display unit 11 by a number or a visual expression so that the user of the device can be notified of the remaining amount of memory in the buffer RAM 6 and the amount of data stored in the memory. It is useful for checking the operation state. Here, the display that expresses the visual amount is, for example, a fixed display element that expresses a container reminiscent of the buffer RAM 6 and a reproduction stored in the RAM 6 that is arranged at a position surrounded by the fixed display element. It can be realized by a variable display element that expresses a possible data amount one by one.
[0037]
As is clear from the above description, according to the embodiment of the present invention, it is only necessary to store the main data in the memory (RAM 6), the memory capacity can be used effectively, and the read operation is performed based on the information of the write data. And control the main data. Also, the absolute time T based on the subcode Q data _QABS And elapsed time in the song (lap time) T _QLAP By subtracting the time Td of the amount of delay in the buffer RAM 6 from the above, the time information (T _ABS And T _LAP ) Can be obtained, an appropriate display can be performed, and the amount of reproducible data in the buffer RAM 6 can be displayed to inform the operating state of the apparatus. In addition, it is possible to control reproduction data such as de-emphasis switching at a correct timing. Furthermore, even when performing a special operation such as a pause or AB repeat, a natural operation and display without discomfort can be performed.
[0038]
That is, according to the embodiment of the data reproducing apparatus of the present invention, the recording data in which the auxiliary data is added to the main data is read out from the recording medium to separate the main data, and the main data is written / written to / from the buffer memory. When reading is controlled, a delay time between writing and reading in accordance with the amount of reproducible data stored in the buffer memory and a time relation obtained from the auxiliary data read from the recording medium. Since the time-related information of the main data read from the buffer memory is calculated based on the information, only the main data needs to be stored in the buffer memory, and the effective utilization rate of the storage capacity increases. Thus, time-related information at the same timing as the main data read from the buffer memory and actually reproduced can be obtained.
[0039]
Further, according to the embodiment of the data reproducing apparatus according to the present invention, the control information signal such as de-emphasis switching obtained from the auxiliary data is changed according to the amount of reproducible data stored in the buffer memory. Since control such as de-emphasis switching is performed with a delay of the amount of delay between writing and reading, control of main data read from the buffer memory is performed at a correct timing.
[0040]
The present invention is not limited to only the above-described embodiment. For example, as a recording medium, in addition to an optical disk, a magneto-optical disk, a magnetic disk, a magnetic tape, or the like can be used. Not limited. In addition to the PCM audio data, video data, compressed data, and the like can also be used as the main data. Further, the auxiliary data is not limited to the above subcode data, and can be applied to a format in which error correction processing is not performed. Of course, the hardware configuration is not limited to the illustrated example.
[0041]
【The invention's effect】
As is apparent from the above description, according to the data reproducing apparatus of the present invention, a reproducing means for reproducing the recorded data from a recording medium on which recorded data composed of main data and auxiliary data is recorded; Separating means for separating the main data and the auxiliary data from the recorded data reproduced by the means, storage means for temporarily storing the separated main data, and first storing the main data in the storage means. Storage control means for intermittently writing at a transfer rate of the storage means for continuously reading out the main data stored at the storage means at a second transfer rate lower than the first transfer rate; Based on the storage amount of the fluctuating main data and the transfer rate of the main data read from the storage unit, the storage unit stores the main data. Calculating means for calculating an amount of delay from writing to reading of the main data, and displaying time information corresponding to the main data read from the storage means, based on the auxiliary data separated by the separating means. Display means, and control means for controlling the time display of the display means based on the variable delay amount calculated by the calculation means, so that only the main data can be stored in the storage means. The effective utilization rate of the storage capacity is often increased, and the main data read from the storage means can be displayed by obtaining time information at the same timing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall schematic configuration of an embodiment of a data reproducing apparatus according to the present invention.
FIG. 2 is a block circuit diagram showing a specific example of a signal processing unit in the embodiment.
FIG. 3 is a block circuit diagram showing a specific example of a RAM controller in the embodiment and its periphery.
FIG. 4 is a diagram for explaining movement of a write address and a read address in a memory space of a buffer RAM in the embodiment.
FIG. 5 is a block diagram showing an example of an internal configuration of an address generation circuit in FIG. 3;
[Explanation of symbols]
Reference Signs List 1 optical disk, 2 optical pickup, 4 signal processing unit, 5 RAM controller, 6 buffer RAM, 9 servo control circuit, 10 system controller, 11 display unit, 12 key input unit, 13 write address counter, 14 effective write address Counter, 15 read address counter, 16 subtractor, 21 EFM demodulation circuit, 23 PLL / timing generation circuit, 24 subcode Q processing circuit, 25 error correction processing circuit, 26 decoding processing RAM, 27 read / write control circuit, 29 timing generation circuit, 31, 33, 35 register, 36 data comparator

Claims (1)

Reproducing means for reproducing the recording data from a recording medium on which recording data composed of main data and auxiliary data is recorded;
Separating means for separating the main data and the auxiliary data from the recording data reproduced by the reproducing means,
Storage means for temporarily storing the separated main data,
The main data is intermittently written to the storage means at a first transfer rate, and the main data stored in the storage means is continuously read at a second transfer rate lower than the first transfer rate. Storage control means for controlling;
The amount of delay from writing to reading of the main data stored in the storage means, based on the amount of fluctuating main data stored in the storage means and the transfer rate of the main data read from the storage means. Calculating means for calculating
Display means for displaying time information corresponding to the main data read from the storage means, based on the auxiliary data separated by the separation means,
Control means for controlling the time display of said display means based on the variable delay amount calculated by said calculation means.

Images