JP2004095028A - Memory test circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a memory test circuit capable of changing test contents by adding necessary minimum external terminals for a test and a circuit. <P>SOLUTION: This memory test circuit is provided with: signal generating circuits for respectively generating a CS signal, an address signal, a data signal and an R/W signal of a memory to be tested; and a test setting control circuit for generating the control data of these signal generating circuits. The signal generating circuits and the test setting control circuit have shift registers, and control data and test data are serially inputted to these shift registers from external terminals. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test circuit for a memory, and more particularly to a test circuit for a memory of a semiconductor integrated circuit in which a memory and a logic unit are mounted on one semiconductor chip.
[0002]
[Prior art]
In recent years, various LSIs have been proposed in which a memory is mounted in a logic unit such as an ASIC or a microprocessor. In this type of LSI, the normal operation of the memory is controlled by a signal from the logic unit. For example, when a read command is issued from the logic unit, the memory outputs data at a selected address to the logic unit. Similarly, the memory outputs the data at the selected address to the logic unit. In this type of LSI, since it is not practical to perform a memory test via a complicated logic unit, various dedicated test circuits for testing the memory have been proposed.
[0003]
FIG. 10 is a diagram showing a configuration of a test circuit of a conventional memory (for example, see Patent Document 1). In FIG. 10, reference numeral 211 denotes a memory circuit to be tested, which has a plurality of data input terminals DI and a plurality of data output terminals DO. 212 is an internal logic circuit having an external input terminal NI, and 213 and 214 are selectors, respectively, which switch the input terminals A and B according to a switching control signal from a test mode terminal TEST.
[0004]
Next, the operation will be described. When writing normal data, the selectors 213 and 214 both select the input terminal A according to the switching control signal from the test mode terminal TEST. Normal data is input from the external input terminal NI, and is written from the data input terminal DI to the memory circuit 211 via the internal logic circuit 212 and the selector 213. Further, when reading normal data, the data is output from the data output terminal DO of the memory circuit 211 to the external output terminal OUT via the internal logic circuit 212 and the selector 214.
[0005]
When writing test data, each of the selectors 213 and 214 selects the input terminal B according to the switching control signal from the test mode terminal TEST. The test data is input from the test input terminal TI, and is written from the data input terminal DI to the memory circuit 211 via the selector 213. When reading test data, the test data is output from the data output terminal DO of the memory circuit 211 to the external output terminal OUT via the selector 214.
[0006]
Such a conventional memory test circuit can control the selectors 213 and 214 when testing the memory, thereby performing the memory test of the memory circuit 211 alone without passing through the internal logic circuit 212. it can.
[0007]
As a conventional technique of another memory test circuit, there is a technique known as a built-in self test circuit (BIST circuit). Whereas the test circuit of the memory described above performs all of the generation of test patterns and analysis of output data by an external tester, the BIST circuit includes a test pattern generator and a test result analyzer. Therefore, only the judgment result of the test is output to the external tester. Therefore, the BIST circuit has an advantage that the number of test terminals required for the LSI is small.
[0008]
However, a general BIST circuit has a sequencer inside the memory test circuit, and the sequencer controls the test contents, so that the test contents are fixed, and it is impossible to change the test contents after designing the LSI. .
[0009]
In view of this, a programmable BIST circuit has been considered as a method that allows the test contents to be changed even after the LSI is designed. FIG. 11 is a configuration diagram of a generally conceivable programmable BIST circuit. The RAM test instruction memory 102 receives and stores program data 101 expressing an algorithm for generating test contents from an external input terminal. The RAM test control circuit 103 is set to the test mode when the test mode setting signal TEST has a predetermined logic, operates in synchronization with the RAM test clock CLK, applies the address designation signal 106 to the RAM test instruction memory 102, The program data 107 is sequentially read from the test instruction memory 102.
[0010]
The test pattern generator 110 sequentially generates test pattern data 111 corresponding to the program data according to the control signal 108 output from the RAM test control circuit 103. The test pattern data 111 is switched by the selector 114 to a signal 115 during normal operation, and is selected as input data to the memory under test 116.
[0011]
In such a programmable BIST circuit, an arbitrary RAM test can be executed by changing program data held in the RAM test instruction memory. Further, in order to avoid an increase in area due to the RAM test instruction memory, a method has been proposed in which a scan path register inside an LSI is used instead of the RAM test instruction memory (for example, see Patent Document 2).
[0012]
[Patent Document 1]
JP-A-2002-42493 (FIG. 5)
[Patent Document 2]
JP 2001-297598 A (FIG. 1)
[0013]
[Problems to be solved by the invention]
In a method in which a selector is switched and controlled to test a memory circuit without passing through an internal logic circuit, test terminals are required by the number of data input terminals and data output terminals. Therefore, when the bit width of data input and data output is large, or when a plurality of memories are built in, a large number of test terminals are required, which is not practical.
[0014]
A general BIST circuit has a sequencer inside the circuit, and the sequencer controls the test content, so that the test content is fixed, and it is impossible to change the test content after designing the LSI. On the other hand, in the BIST strike circuit as shown in FIG. 11, an increase in area due to the incorporation of the RAM test instruction memory inside the LSI and the test of the RAM test instruction memory itself are also problems. In the BIST circuit proposed in Patent Document 2, although the area is not increased by adding a RAM test instruction memory, a signal for extracting a program from a scan path register in an LSI used as a substitute for the RAM test instruction memory is used. Problems such as an increase in area due to lines or the like and deterioration in wiring properties at the time of layout occur. In addition, since these test circuits generate test patterns from programs, RAM test control circuits and test pattern generators require circuits for decoding programs, generating control signals for RAM, and the like, which increases the circuit scale. There is a disadvantage that.
[0015]
The present invention has been made to solve the above-described problems, and has as its object to realize a memory test circuit in which test contents can be changed by adding a necessary minimum number of test external terminals and circuits. I do.
[0016]
[Means for Solving the Problems]
A test circuit for a memory according to the present invention includes, in a test circuit built in a semiconductor integrated circuit together with a memory, a test signal generation circuit for generating a test signal for the memory, and a control circuit for controlling the test signal generation circuit. A test setting mode and a test execution mode are switched according to a first control signal input from the outside, and initial data of the test signal and the test signal generation are input to the test signal generation circuit in the test setting mode. Control data for controlling the circuit and control data for the control circuit are configured to be serially input from the same terminal.
[0017]
According to the present invention, a test setting mode and a test execution mode are switched according to a first control signal input from the outside, and in the test setting mode, initial data of a test signal and the test signal input to the test signal generation circuit. Since the control data for controlling the test signal generation circuit and the control data for the control circuit are configured to be serially input from the same terminal, the test contents of the memory can be controlled by a small number of external terminals. Can be changed.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in more detail based on embodiments of the present invention with reference to the drawings.
[0019]
FIG. 1 shows the configuration of an LSI including a memory test circuit according to an embodiment of the present invention. An LSI to which the memory test circuit of the present invention is applied includes a plurality of RAMs 91 to 9m and a test circuit 500.
[0020]
The output 6 of the test circuit 500 is a data signal, an address signal, a chip select (CS) signal, and a read / write (R / W) signal, which are input signals to each of the RAMs 91 to 9m at the time of the test. The data signal, the address signal, the CS signal, and the R / W signal are connected to one of the inputs of the selector 4 as the input signal 7 to each of the RAMs 91 to 9m during the normal operation. .
[0021]
The selector 4 switches between the signals 6 and 7 according to the test switching signal 1 input from an external terminal, and the output signal 8 is input to each of the RAMs 91 to 9m. The RAM selected by the CS signal reads or writes data depending on the value of the R / W signal.
[0022]
The output of each of the RAMs 91 to 9m is also input to the test circuit 500, and the output data of the RAM selected by the selector 550 is output from the LSI to the outside as the output data signal 2.
[0023]
The test circuit 500 includes a selector 4, a CS signal generation circuit 510 for generating a RAM CS signal, an address signal generation circuit 520 for generating a RAM address signal, and a data signal generation circuit 530 for generating write data to the RAM. An R / W signal generation circuit 540 for generating an R / W signal to the RAM, a selector 550 for selecting an output signal from the selected RAM by a CS signal, a CS signal, an address signal, and a data signal of the RAM. And a test setting control circuit 560 for controlling the value of Test control signals 31 to 34 are input to the test setting control circuit 560 from control terminals of the LSI.
[0024]
Output signals from the CS signal generation circuit 510, the address signal generation circuit 520, the data signal generation circuit 530, and the R / W signal generation circuit 540, which are test signal generation circuits of the present invention, are selected as test signals 6 to each RAM. 4 is output.
[0025]
The address signal generation circuit 520 includes an Inc / Dec circuit 521 for incrementing / decrementing (Inc / Dec) the address signal to the RAM, and an Inc / Dec control circuit 522 for controlling the same (selecting Inc or Dec).
[0026]
The data signal generating circuit 530 includes an inverting / non-inverting circuit 531 for inverting / non-inverting write data to the RAM.
[0027]
The CS signal generation circuit 510, the address signal generation circuit 520, the data signal generation circuit 530, and the test setting control circuit 560 include a shift register (SR). The Inc / Dec control circuit 522 includes a register (R). A test control signal 31 serving as data for setting a value is input to these SR and R. The initial value 0 is set to the flip-flops constituting these SR and R by receiving a test reset signal 12 input from an external terminal in advance.
[0028]
FIG. 5 shows a configuration example of the test setting control circuit 560. The test setting control circuit 560 selects the SR of the CS signal generation circuit 510, the SR of the address signal generation circuit 520, the SR of the data signal generation circuit 530, and the R of the Inc / Dec control circuit 522. The operation of the address signal generation circuit 520, the data signal generation circuit 530, and the operation of the R / W signal generation circuit 540 are controlled.
[0029]
In FIG. 5, signals 570-5 to 570-8 are the SR of the CS signal generation circuit 510, the SR of the address signal generation circuit 520, the R of the Inc / Dec control circuit 522, and the signal of the data signal generation circuit 530, respectively. This is an SR selection signal. The selection signals 570-5 to 570-8 are generated by decoding the value of each flip-flop (F / F) constituting the SR with a decoder. The selection signals 570-5 to 570-8 become active when the test control signal 34 is set to 0 and the test control signal 32 is set to 1. This SR value is set by setting the test control signal 34 to 0, the test control signal 33 to 1, and the test control signal 31 as a serial input to the clock 11 input from an external terminal common to other logic units of the LSI. This is performed by latching the value synchronously. Signals 570-1 to 570-4 are control signals for CS signal generation circuit 510, address signal generation circuit 520, data signal generation circuit 530, and R / W signal generation circuit 540, respectively. The control signals 570-1 to 570-4 become valid when the test control signal 34 is set to 1.
[0030]
FIG. 6 shows a configuration example of the CS signal generation circuit 510. This figure shows a case where there are four RAMs. The CS signal generation circuit 510 generates a CS signal based on the value of F / F constituting the SR of the CS signal generation circuit 510. To set the SR value, after setting the SR value of the test setting control circuit 560, the test control signal 34 is set to 0, the test control signal 32 is set to 1 to activate the selection signal 570-5, and the test control signal 31 is set to This is performed by latching a value in synchronization with the clock 11 as a serial input. The CS signal 6-510 output from the CS signal generation circuit 510 is output by setting the test control signal 34 to 1 and activating the control signal 570-1.
[0031]
FIG. 7 shows a configuration example of the address signal generation circuit 520. This figure shows a case where the address line is 4 bits wide. The address signal generation circuit 520 generates an address signal based on the SR value of the address signal generation circuit 520. The setting of the SR value as the initial address value is performed by setting the SR value of the test setting control circuit 560, setting the test control signal 34 to 0, setting the test control signal 32 to 1, and activating the selection signal 570-6. This is performed by latching a value in synchronization with the clock 11 using the test control signal 31 as a serial input. The SR of the address signal generation circuit 520 connects each F / F constituting the SR to a shift register only during a period when the selection signal 570-6 for setting an initial address is active, and an address output from the Inc / Dec 521 at the time of test execution. A selector for writing a signal to each of these flip-flops in parallel is provided.
[0032]
The Inc / Dec control circuit 522 generates an Inc / Dec control signal based on the value of the register (R) of the Inc / Dec control circuit 522, and the Inc / Dec circuit 521 switches between Inc and Dec based on this value. To set the value of R, after setting the value of SR of the test setting control circuit 560, the test control signal 34 is set to 0, the test control signal 32 is set to 1, the selection signal 570-7 is activated, and the test control signal 31 is set to This is performed by latching a value in synchronization with the clock 11 as an input.
[0033]
As the address signal 6-520 output from the address signal generation circuit 520, the value of each flip-flop of SR is output. The address signal 6-520 is input to the Inc / Dec circuit 521, and the Inc / Dec circuit 521 Inc / Dec outputs the address signal 6-520. When the test control signal 34 is set to 1 and the test control signal 33 is set to 1 and the control signal 570-2 is activated, the output of the Inc / Dec circuit 521 is connected in parallel to each flip-flop of the SR of the address signal generation circuit 520. (Inc / Dec of the address signal is performed). When the control signal 570-2 is not active, the value of SR (address signal) of the address signal generation circuit 520 does not change.
[0034]
FIG. 8 shows a configuration example of the data signal generation circuit 530. This figure shows a case where the data line has a 4-bit width. The data signal generation circuit 530 generates a data signal serving as write data to the RAM based on the value of each F / F of SR of the data signal generation circuit 530. After setting the SR value of the test setting control circuit 560, the test control signal 34 is set to 0, the test control signal 32 is set to 1 and the selection signal 570-8 is activated, and the test control signal 31 is set. This is performed by latching a value in synchronization with the clock 11 as a serial input.
[0035]
The inversion / non-inversion circuit 531 receives the value of each F / F of SR of the data signal generation circuit 530 as input, sets the test control signal 34 and the test control signal 32 to 1, and the control signal 570-3 becomes active. When the control signal 570-3 is not active, data that is not inverted is output. The data signal 6-530 output from the data signal generation circuit 530 is the output of the inversion / non-inversion circuit 531.
[0036]
FIG. 9 shows a configuration example of the R / W signal generation circuit 540. This figure shows a case where there are four RAMs. The R / W signal generation circuit 540 outputs based on the output 6-510 of the CS signal generation circuit 510. The R / W signal 6-540 output from the R / W signal generation circuit 540 becomes 1 (write) by setting the test control signal 34 to 1 and the test control signal 31 to 1 to activate the control signal 570-4. When the control signal 570-4 is not active, 0 (read) is output.
[0037]
Next, the operation of this embodiment will be described. The operation of the test circuit 500 is divided into two, “test setting” and “test execution”. Switching between “test setting” and “test execution” is performed by a test control signal 34.
[0038]
First, the operation of “test setting” will be described. The operation of "test setting" is to select a RAM to be tested (determination of a CS value), determine a test start address value, select an address value Inc or Dec, and determine a write data value. It is. The CS signal, the address signal, the selection of the address Inc or Dec, and the data signal correspond to the SR (shift register) of the CS signal generation circuit 510, the address signal generation circuit 520, the Inc / Dec control circuit 522, and the data signal generation circuit 530. ) Or R (register) value, setting these SR or R values is an operation in “test setting”.
[0039]
The flow of "test setting" is shown below. 1. The test control signal 34 is set to 0. 2. The test control signal 33 is set to 1, the SR value of the test control circuit 560 is set as the serial input of the test control signal 31, and the SR or R to be set (here, the CS signal generation circuit 510, the address signal generation circuit 520, and the data SR of the signal generation circuit 530 and R) of the Inc / Dec control circuit 522 are selected. 3. Set the test control signal 32 to 1; The value of SR or R selected in is set as the test control signal 31 as a serial input. 4. 1. until all SR or R values are set And 3. repeat.
[0040]
Next, the operation of “test execution” will be described. The operation of "test execution" is to read and write (R / W) data to and from the RAM. What can be controlled by "test execution" is the presence / absence of address Inc (Dec), R / W, and the presence / absence of data inversion.
[0041]
When the test control signal 33 is set to 1, Inc (Dec) of the SR value of the address generation circuit 520 is performed, and when the test control signal 33 is set to 0, the Inc (Dec) is not performed. The selection of Inc or Dec is set to R of the Inc / Dec control circuit 522 at the time of “test setting”. When the test control signal 32 is set to 1, writing to the RAM is performed, and when set to 0, reading is performed. When the test control signal 31 is set to 1, the value of SR of the data signal generation circuit 530 is inverted, and when it is set to 0, it is not performed.
[0042]
FIG. 2 shows a summary of the operation of the test circuit by the combination of the test control signals. An example of the operation according to the operation content shown in FIG. 2 will be described below.
[0043]
First, an example of the operation of “test setting” is shown in FIG. By setting the test control signal 34 to “0”, “test setting” is set. At time 0, the SR of the test setting control circuit 560 selects (CS) the SR of the CS signal generation circuit. Here, when the test control signal 32 is set to 1, the value of the test control signal 31 is serially input to the SR of the CS signal generation circuit 510 and the value is set (RAM 91 is selected).
[0044]
At time 1, when the test control signal 33 is set to 1, the value of the test control signal 31 is input to the SR of the test setting control circuit 560 by serial input, and the value is set (Inc / Dec). At time 2, when the test control signal 32 is set to 1, the value of the test control signal 31 is input to R of the Inc / Dec control circuit 522 and the value is set (Dec is selected).
[0045]
Similarly, the values 1, 0, and 1 of the test control signal 31 at the rise of the clock 11 at times 5, 6, and 7 are input to SR of the data signal generation circuit 530, and 5 (hexadecimal) is set. In the SR of the signal generation circuit 520, the values 1, 1, and 0 of the test control signal 31 at the rise of the clock 11 at times 10, 11, and 12 are input, and 6 (hexadecimal) is set. This completes the setting.
[0046]
Next, an example of the operation of “test execution” is shown in FIG. By setting the test control signal 34 to "1", "test execution" is performed, and the values set in the respective SRs are output as CS, data and address signals of the RAM. At time 15, when the test control signal 32 is set to 1, the RAM R / W signal becomes 1 (W). At time 17, when the test control signal 31 is set to 1, the value of the data signal of the RAM becomes an inverted value A (hexadecimal). When the test control signal 33 is set to 1 at times 18 to 24, the RAM address is decremented.
[0047]
As described above, in the test circuit of the present invention, the test start address and the data to be written to the RAM can be freely set, and the timing of read / write, data inversion, and address increment (decrement) can be freely controlled. can do.
[0048]
Although the description has been given based on the embodiment, the test circuit of the memory of the present invention is not limited to the configuration of the above-described embodiment, and may have various changes from the configuration of the above-described embodiment. , Within the scope of the present invention. For example, in the embodiment, the number of memories to be tested and the bit width of the data signal are all four, but these numbers can be easily changed to any number.
[0049]
【The invention's effect】
The first effect is that the test contents of the RAM can be changed with a small number of external terminals. The reason is that serial input is used when externally supplying data necessary for the test, and that the addressing and R / W timing can be controlled from an external terminal.
[0050]
A second effect is that a RAM test circuit can be configured with a small amount of hardware. The reason is that there is no sequencer or ROM code etc. inside the circuit to operate and determine the test content, and the test content is reduced by the minimum necessary shift registers and a small amount of logic inside the circuit, and a small number of external terminals. This is because the configuration is operable.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an LSI incorporating a memory test circuit according to an embodiment of the present invention.
FIG. 2 is a diagram summarizing the operation of a test circuit of a memory based on a combination of test control signals according to an embodiment of the present invention.
FIG. 3 is a timing chart showing an operation example of “test setting” of the test circuit of the memory according to the embodiment of the present invention;
FIG. 4 is a timing chart showing an operation example of “test operation setting” of the test circuit of the memory according to the embodiment of the present invention;
FIG. 5 is a diagram showing a configuration example of a test setting control circuit of the test circuit of the memory according to the embodiment of the present invention;
FIG. 6 is a diagram illustrating a configuration example of a CS signal generation circuit of the test circuit of the memory according to the embodiment of the present invention;
FIG. 7 is a diagram showing a configuration example of an address signal generation circuit of the test circuit of the memory according to the embodiment of the present invention;
FIG. 8 is a diagram showing a configuration example of a data signal generation circuit of the test circuit of the memory according to the embodiment of the present invention;
FIG. 9 is a diagram showing a configuration example of an R / W signal generation circuit test setting control circuit of the test circuit of the memory according to the embodiment of the present invention;
FIG. 10 is a diagram showing a configuration of a memory test circuit according to a first conventional technique.
FIG. 11 is a diagram showing a configuration of a memory test circuit according to a second conventional technique.
[Explanation of symbols]
1 Test switching signal 2 Output data signal 31, 32, 33, 34 Test control signal 4 Selector 500 Test circuit 510 CS signal generation circuit 520 Address signal generation circuit 530 Data signal generation circuit 540 R / W signal generation circuit 550 Selector 560 Test setting Control circuit

Claims (5)

A test circuit built in a semiconductor integrated circuit together with a memory, comprising: a test signal generation circuit for generating a test signal for the memory; and a control circuit for controlling the test signal generation circuit. A test setting mode and a test execution mode are switched according to a control signal, and initial data of a test signal and control data for controlling the test signal generating circuit, which are input to the test signal generating circuit in the test setting mode, And a control circuit for serially inputting control data to the control circuit from the same terminal. 2. The memory test circuit according to claim 1, wherein said test signal generation circuit comprises a chip select signal generation circuit, an address signal generation circuit, a data signal generation circuit, and a read / write signal generation circuit. 2. The method according to claim 1, wherein an address increment, a decrement control, a read / write control, and a data inversion presence / absence control are respectively performed according to second, third, and fourth control signals input from outside. Or the test circuit of the memory according to 2. 4. The memory test circuit according to claim 1, further comprising a selector for selecting output data of the selected memory and outputting the selected output data to the outside as output data. 5. The memory test circuit according to claim 1, wherein said read / write signal generation circuit generates a read / write signal based on an output signal of said chip select signal generation circuit.

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