JP2004094930A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of reducing time until an intended process is executed when a predetermined event occurs. <P>SOLUTION: This semiconductor integrated circuit has: first function blocks (1, 2); an event detection circuit (4) for detecting occurrence of an event for which an exceptional process should be requested to the first function blocks and for requesting the exceptional process to the corresponding first function blocks; second function blocks (7, 8, 9, 10) for generating an event for which the exceptional process should be requested to the first function blocks; and selection control means (131, 132) for making the frequency of a first system clock signal (ϕB) fed to the first function blocks and the event detection circuit variable and selectable and for forcibly bringing the selection state of the frequency into a predetermined state based on the detection of a predetermined event by the detection circuit (4). Each selection control means has a clock control circuit (13). <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a plurality of functional blocks operated in synchronization with a clock signal, and particularly to a technique which is particularly effective when used in a single-chip microcomputer requiring low power consumption.
[0002]
[Prior art]
As described in P607 to P632 of the “H8 / 3048 Series Hardware Manual” issued by Hitachi, Ltd. in March 1994, each functional block of the single-chip microcomputer transmits the system clock signal φ. Act as a reference. The system clock signal φ is connected to an external clock input to an external clock input terminal (EXTAL) provided in a single-chip microcomputer or to an oscillation terminal (EXTAL, XTAL) provided in a microcomputer. It is generated from the original oscillation generated by a vibrator such as a quartz or ceramic. An example in which a unique clock signal is supplied to each functional block in a microcomputer is described in JP-A-3-286213. Japanese Patent Application Laid-Open No. Hei 5-81447 discloses a technique in which a microcomputer including a CPU (central processing unit) and its peripheral circuits is provided with a clock signal frequency divider and clock selection means in each peripheral circuit. ing. Japanese Patent Application Laid-Open No. 3-58207 discloses a technique in which the output of an oscillation circuit is divided by a divider circuit, and one of the divided clock signals is selected to be used as a system clock signal.
[0003]
[Problems to be solved by the invention]
The inventor has made the following study on the system clock signal of a semiconductor integrated circuit such as a single-chip microcomputer.
[0004]
The system clock signal φ can be selected to have the same frequency as the original oscillation or a so-called gear function, that is, a frequency obtained by dividing the original oscillation. Such a system clock signal is commonly supplied to a CPU (Central Processing Unit) and its peripheral circuits. In the gear function, it is desirable to switch the frequency of the system clock signal in accordance with the content to be processed by the CPU from the viewpoint of reducing the power consumption of the single-chip microcomputer. Further, when it is considered that a signal obtained by steadily dividing the original oscillation by two is selected as the system clock signal, the oscillation frequency of the original oscillation is set to 予 め in advance, and the system clock signal is used as the system clock signal. Compared with the case of the same frequency, the operating frequency of the original oscillator is twice that of the former oscillator, and the current consumption of the original oscillator is twice that of the latter.
[0005]
On the other hand, if the frequency of the system clock signal is switched during operation in accordance with the content to be processed by the CPU, the following problem occurs. For example, when the system clock φ is used as a reference clock of the serial communication interface (SCI), if the frequency division ratio of the system clock signal is reduced to が, the transmission / reception bit rate or baud rate of the SCI is reduced to ２. In particular, communication becomes impossible in the case of start-stop synchronous communication. Therefore, when switching the frequency of the system clock signal, the setting of the bit rate or baud rate of the SCI must be changed to correspond to the system clock signal after the switching. Therefore, such switching of the system clock signal frequency must be performed while the operation of the SCI is stopped.
[0006]
Similarly, if a system clock signal is used as a clock source in a general timer, if the frequency of the system clock signal is halved, the cycle is doubled. Otherwise, the absolute timekeeping time will be different. Similar resetting processing must be performed for most peripheral circuits or peripheral functions other than the SCI and the timer, and the software load required for such resetting is not negligible.
[0007]
Further, the situation is the same when the frequency of the system clock signal is increased by changing the frequency division ratio of the system clock signal from 1/2 to 1/1. In particular, the change to high speed is when high-speed processing occurs as processing for the CPU. In such a case, if the setting change is performed for most of the peripheral functions, there is a large waste of time, It becomes impossible to cope with situations that require high-speed processing.
[0008]
On the other hand, in the above-mentioned Japanese Patent Application Laid-Open No. 3-286213, in which a specific clock signal is supplied to each functional block of the microcomputer, the frequency division ratio of the clock signal supplied to each functional block can be set independently. . Therefore, a change in the frequency division ratio of the clock signal for one functional block does not affect the other functional blocks, and the burden on software is reduced.
[0009]
However, when an independent clock signal is supplied to each functional block, the total length of the clock wiring, in other words, the capacity is inevitably increased. The current consumption is expressed as the sum of the product of the capacitance (C), voltage (V), and frequency (f) of the signal line, that is, ΣC · V · f. Will increase in proportion to. The clock signal is a signal having the highest frequency (f) inside the microcomputer, and such current consumption cannot be ignored. At least, it is not a good idea to reduce power consumption.
[0010]
Also, when each functional block is operating at an arbitrary frequency division ratio, it is not clear at which interface the rising transition point of one clock signal is in which phase of the other clock signal. This makes it difficult to secure the setup time and hold time of the device, and inevitably results in an asynchronous interface. In such an asynchronous interface, the logical design is complicated, and the logical scale required for such an interface is also increased.
[0011]
Further, if the clock signal is switched exclusively by software, a predetermined event such as a reset or a predetermined interrupt request is generated, and when high-speed processing of the CPU is required, such an event is recognized as an interrupt. After executing interrupt exception processing and switching the frequency division ratio of the system clock signal in the interrupt processing routine, desired processing is performed. In this case, the time from when the event occurs to when the desired processing is performed becomes long, which is not convenient.
[0012]
An object of the present invention is to provide a semiconductor integrated circuit that can achieve low power consumption for a system clock signal.
[0013]
Another object of the present invention is to provide a semiconductor integrated circuit capable of changing the operation speed of a built-in functional block such as a CPU while reducing the load on software.
[0014]
Still another object of the present invention is to provide a semiconductor integrated circuit that can reduce the time required for performing a desired process when a predetermined event occurs.
[0015]
Another object of the present invention is to provide a semiconductor integrated circuit capable of facilitating an interface between functional blocks having different frequencies of supplied system clock signals.
[0016]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0017]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0018]
[1] A second clock for commonly supplying a second system clock signal (φS) having a constant frequency formed based on an output from an oscillator (12) to a plurality of functional blocks in a semiconductor integrated circuit A division ratio can be selected for the signal line (L2) and the output from the oscillator (12), and a first system clock signal (φB) whose frequency is equal to or lower than the second system clock signal is used. A clock control circuit (13) to be formed, and a first clock signal line (L1) for supplying a first system clock signal formed by the clock control circuit (13) to a predetermined functional block. .
[0019]
[2] The functional block to which the first system clock signal is supplied via the first clock signal wiring is a bus master (1, 2). In a data processor such as a microcomputer, a CPU operating as a bus master frequently starts a bus cycle for fetching instructions and data. This is because in order to reduce the power consumption of the semiconductor integrated circuit, it is advisable to supply a system clock signal having a variable division ratio to the bus masters.
[0020]
[3] The functional block to which the second system clock signal is supplied via the second clock signal wiring is a bus slave (7, 8, 9, 10). Even if the frequency of the system clock signal of the bus master is changed, the bit rate or baud rate of the serial communication interface and the clock cycle of the timer are kept constant, so that setting of these peripheral function blocks does not need to be changed. It is.
[0021]
According to the above-described means, the second system clock signal (also referred to as a peripheral clock signal) supplied to a functional block such as a peripheral circuit or a bus slave is supplied to a functional block such as a bus master independently of the second system clock signal. By making the frequency division ratio of the system clock signal (also referred to as a bus master clock signal) variable, the frequency division ratio of the bus master clock signal is increased in accordance with the operation state of the CPU or the like, thereby reducing power consumption. Can be realized.
[0022]
Also, since the peripheral clock signal can be fixed, even if the bus master clock signal is changed, the bit rate or baud rate of the serial communication interface, the cycle of the timer, and the like are kept constant. It is not necessary to change the settings of those peripheral function blocks by changing the frequency of the signal.
[0023]
Using a clock signal such as the peripheral clock signal as a clock signal common to a plurality of functional blocks reduces the wiring capacity of the clock wiring and reduces power consumption compared to supplying an independent clock signal to each functional block. Is made smaller.
[0024]
[4] The clock control circuit (13) can include a register means (132) in which information for selecting the frequency division ratio of the first clock signal (φB) can be set by the bus master. . This is because the division ratio can be arbitrarily selected by a bus master such as a CPU.
[0025]
[5] a first internal data bus (IDB) to which a functional block which is supplied with a first system clock signal (φB) via the first clock signal wiring and operates as a bus master is connected; A second system clock signal (φS) is supplied via the clock signal wiring, and the data bus is separated from a second internal data bus (PDB) to which a functional block operating as a bus slave is connected. When the bus slave connected to the second internal data bus is accessed by the bus master connected to the first internal data bus, the first internal data bus is connected to the second internal data bus in response to the access. A bus controller (3) connected to the bus is provided. The second internal data bus holds the state of the connected functional block when all outputs of the connected functional block are in a high impedance state, and when the connected functional block is read or written, the bus is accordingly connected. Hold circuits (HD1, HD2) that allow the state to change are provided. By connecting a function block that frequently starts a bus cycle, such as a bus master such as a CPU, to a data bus different from a bus slave, the load on a frequently accessed data bus is reduced. For a data bus that is relatively infrequently used for access, the data in the data bus is held by a hold circuit, thereby reducing the number of times of charging and discharging on the data bus to achieve low power consumption. As described above, since the peripheral function block operates less frequently than the bus master, the peripheral function block operates only when a predetermined signal is input, and the operation can be prohibited if necessary. The power consumption of the semiconductor integrated circuit is further reduced. At this time, the operation can be resumed immediately after the operation is permitted by holding the internal state in the peripheral function block in the operation prohibited state.
[0026]
[6] The functional block to which the first system clock signal (φB) is supplied is a no-overlap which forms a first no-overlap two-phase clock signal (φ1B, φ2B) from the first system clock signal. A functional block that includes a generating circuit and to which a second system clock signal (φS) is supplied includes a no-over (NO) signal that forms a second no-overlap two-phase clock signal (φ1S, φ2S) from the second system clock signal. The first no-overlap two-phase clock signal (φ1B, φ2B) is partially matched in phase with the second no-overlap two-phase clock signal (φ1S, φ2S) (for example, Functional blocks to which the second system clock signal is supplied (for example, the rising timing of φ1S and φ2B in FIG. 23) (for example, FIG. A functional block (a slave) is supplied with a first system clock signal in synchronization with the timing (for example, the rise of φ1S in state 3 in FIG. 23) of the second no-overlap two-phase clock signal. For example, the signal to be supplied to the bus master in FIG. 19) is changed. According to this interface specification, a period of one cycle or more of the second system clock signal (φS) between the output of data and the input and latch of the data between functional blocks having different system clock signals. Can be secured. This facilitates the interface between the functional blocks having different frequencies of the system clock signal, in other words, the timing design for the interface is facilitated. As described above, the bus master clock signal is always equal to or later than the peripheral clock signal, and the interface signal between the bus master and the peripheral function block is synchronized with, for example, a common transition point between the bus master clock signal and the peripheral clock signal. , The interface between the bus master and the peripheral function block can be made an easy synchronous interface. As a result, the logic scale of the semiconductor integrated circuit is reduced, which contributes to a reduction in manufacturing cost and a reduction in power consumption.
[0027]
[7] The functional block to which the first system clock signal (φB) is supplied is a no-over that forms a first no-overlap two-phase clock signal (φ1B, φ2B) from the first system clock signal. A functional block provided with a lap generation circuit and supplied with a second system clock signal (φS) forms a second non-overlapping two-phase clock signal (φ1S, φ2S) from the second system clock signal. A no overlap generation circuit (700) is provided. The low-level period of the first phase clock signal (eg, φ1B in FIG. 20) of the first no-overlapping two-phase clock signal is the first phase of the second no-overlapping two-phase clock signal. The low-level period of the clock signal (eg, φ1S in FIG. 20) is the same as the low-level period of the clock signal (eg, φ2B in FIG. 20) of the second phase of the first no overlap two-phase clock signal. The high-level period of the second-phase clock signal (eg, φ2S in FIG. 20) of the two-phase no-overlap two-phase clock signal. Regardless of whether the output and the input of each functional block are synchronized with either the first phase or the second phase clock signal, data is output between functional blocks having different system clock signals and then input. Until latching, a period of one cycle or more of the second system clock signal (φS) can be secured. This facilitates the interface between the functional blocks having different frequencies of the system clock signal, in other words, the timing design for the interface is facilitated.
[0028]
[8] An output circuit (for example, IOP60, IOP61 in FIGS. 26 and 27) for selectively outputting the first system clock signal (φB) and the second system clock signal (φS) to the outside, and the output circuit A logic circuit (1300, 1301, 1307) for forcing the clock input wiring (1310, 1311) of the output circuit to a predetermined level when an output from the circuit is in a non-selected state is provided. When external output of the system clock signal is not required, charging and discharging of the clock input wiring is suppressed, which contributes to low power consumption.
[0029]
[9] A semiconductor integrated circuit according to another aspect of the present invention, in which generation of an internal clock signal or the like is individually suppressed for each functional block, according to the present invention, is performed based on a system clock signal formed based on an output from an oscillator (12). φS) to form a plurality of phases of internal clock signals (φ1S, φ2S) synchronized with the system clock signal, and a plurality of functional blocks (7, 8, 9, 10) operating according to the formed internal clock signals. And register means (133) for rewritably holding information for inhibiting the formation of an internal clock signal in units of the functional block, wherein the functional block forms the internal clock signal based on correspondence information from the register means. Internal clock signal is stopped at a constant state when the internal clock signal is Comprises control means (700). The change of the internal clock signal is stopped in the unused built-in functional block, and the power consumption due to the charge / discharge current due to the useless change of the clock signal is suppressed. Holding the internal state while the internal clock signal is stopped saves the trouble of setting the internal circuit again when the operation restart is selected.
[0030]
[10] The functional block further forms internal timing signals (φ1-PWM, φ2-PWM) from the multi-phase internal clock signals (φ1S, φ2S) by selecting its own operation, A second internal clock control means (710) for stopping the change of the internal timing signal to a constant state by maintaining the internal state by deselecting the operation of (1). In a non-selected state of operation, power consumption in a circuit receiving internal timing signals (φ1-PWM, φ2-PWM) is suppressed. Holding the internal state when the change of the internal timing signal is stopped in the operation non-selection state saves the trouble of resetting the internal circuit when the operation is restarted.
[0031]
[11] The internal timing signal is a no-overlapping two-phase timing signal (φ1-PWM, φ2-PWM), and a circuit operated in response to the timing signal transmits the first-phase timing signal. A dynamic circuit (23) that receives and dynamically operates, and a static circuit (21) that is serially connected to the dynamic circuit and that operates statically by receiving a second-phase timing signal. . By supplying the timing signal of the phase with the large duty ratio to the dynamic circuit and the timing signal of the phase with the small duty ratio to the static circuit, the two-phase timing signals (φ1-PWM, φ2-PWM) having no overlap are provided. Even if the information holding time due to the output load capacitance of the dynamic circuit is finite, the period during which the information is to be held by the dynamic circuit can be shortened, and the range in which the frequency of the system clock signal can be reduced can be widened. Further, the physical scale of the circuit can be reduced as compared with the case where both are configured by static latch circuits.
[0032]
[12] A semiconductor integrated circuit according to another aspect of the present invention, in which the frequency of a system clock signal is forcibly changed based on event detection, includes one or more first functional blocks (1, 2). An event detection circuit (4) that detects the occurrence of an internal or external event that requires exceptional processing to the first functional block and outputs a signal requesting exceptional processing to the corresponding first functional block (4) ), One or more second function blocks (7, 8, 9, 10) for generating an event that requires exceptional processing for the first function block, and the first function block and the event The frequency of the first system clock signal (φB) supplied to the detection circuit can be variably selected, and the frequency can be selected based on the detection of a predetermined event by the event detection circuit (4). Having a selection control means for forcing the state to a predetermined state (131, 132), the. When a predetermined event occurs, even if the set system clock signal frequency is low, the selection control means can force the selection state of the system clock signal frequency to a predetermined state, for example, the highest frequency selection state. The time required for performing a desired process when a predetermined event occurs is shortened.
[0033]
[13] The selecting means includes a first register means (132) for rewritably holding control information for frequency selection, and a first system clock signal in accordance with the control information held by the first register means. A selector (131) for selecting a frequency, wherein the first register means instructs the selection of the specific frequency (φOSC) in the first state (= "0") and sets a predetermined event by the event detection circuit. The first storage area (MSME) forced to the first state based on the detection of the first state and the frequency selection made significant in the second state (MSME = "1") in the first storage area And a second storage area (CKS1, CKS0) for storing information for storing the information. When a predetermined event occurs, the first storage area (MSME) may be forced to the first state (= "0"), so that the process of forcing the system clock signal to a specific frequency is simplified.
[0034]
[14] The first functional block is a central processing unit (1), and the central processing unit, to which the signal for requesting the exceptional processing is given from the event detection circuit, executes the first processing when returning from the exceptional processing. One storage area can be set to the second state (MSME = "1"). Accordingly, after performing the requested exceptional processing, the central processing unit may return to the second storage area (CKS1, CKS2) even if the processing should be returned to the processing at the time of the request or the next processing. Does not need to be saved and restored.
[0035]
[15] The first functional block is a data transfer controller (2), and the data transfer controller to which the signal for requesting the exceptional processing is given from the event detection circuit instructs termination of the exceptional processing. A signal (1325) is output, and the logic means can set the first storage area to the second state (MSME = "1") according to the active state of the signal indicating the end. This does not impose a burden on the central processing unit or software to restore the system clock signal.
[0036]
[16] The second functional block (7, 8, 9, 10) forms an internal clock signal (φ1S, φ2S) from a second system clock signal (φS) supplied to the second function block, and A second register means (133), which is operated thereby and rewritably holds information for inhibiting the formation of the internal clock signal in units of second functional blocks, is provided. On the basis of the detection (for example, reset), the second register means is initialized to a state in which the formation of the internal clock signal is prohibited. This is to reduce power consumption in an initial state when a predetermined event such as a reset occurs.
[0037]
[17] The invention according to another aspect of using control information paired with a vector such as an interrupt vector in order to forcibly change the frequency of a system clock signal provides a central processing unit (1) and a central processing unit. An event detection circuit (4) for outputting a signal for requesting exceptional processing, a peripheral circuit (7, 8, 9, 10) of the central processing unit, and the central processing unit and the event detection circuit. First register means (132) for instructing the frequency of the first system clock signal (φB) to be selectable, and the internal circuit unit for each of the above-mentioned peripheral circuits operated in response to the second system clock signal (φS). A second register means (133) for rewritably holding information for inhibiting the formation of a clock signal, wherein the central processing unit performs an exceptional process from the event detection circuit; When requested, control information to be set in the first and second register means is obtained from an area (addresses 0, 4, 8, and 12 in FIG. 30) paired with a vector corresponding to the request. . This is because the low power consumption setting can be finely performed according to the type of the event.
[0038]
[18] When the central processing unit (1) receives a request for exceptional processing from the event detection circuit (4), the central processing unit (1) stores, in the first and second register means, an area paired with a vector corresponding to the request. Before setting the acquired control information, the values of the first and second register means are saved to return from the exceptional processing. This is to deal with the case where it is necessary to return to the state immediately before the occurrence of the event after the end of the requested exceptional processing.
[0039]
[19] Another aspect of the invention in which a prescaler clock signal of a low frequency division ratio that can be generated by a prescaler is not supplied from the prescaler but is generated individually by a frequency divider in a functional block is an oscillator (12). A semiconductor integrated circuit comprising: a clock control circuit (13) for forming a system clock signal based on the output of the clock control circuit; and a plurality of functional blocks operated in response to the system clock signal from the clock control circuit. A frequency divider (720) that divides a system clock signal for each functional block for a functional block requiring a clock signal (φS / 2 in FIG. 6) having a relatively small frequency division ratio separately from the signal (φS). Is provided in common for a plurality of functional blocks that require clock signals (φ / 8, φ / 16) having a relatively large frequency division ratio. It constituted by providing a prescaler (14) for generating and supplying said clock signal. This is because, when a clock signal with a low frequency division ratio is also supplied directly to a plurality of functional blocks, power consumption in the clock signal transmission system increases due to the low frequency division ratio.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
<< Functional Blocks of Single-Chip Microcomputer >> FIG. 1 is a block diagram of a single-chip microcomputer as one embodiment of a semiconductor integrated circuit according to the present invention. This single-chip microcomputer includes a central processing unit (CPU) 1, a data transfer controller (DTC) 2, a bus controller (BSC) 3, an interrupt controller 4, a read only memory (ROM) 5, a random access memory ( RAM) 6, timer 7, watchdog timer (WDT) 8, serial communication interface (SCI) 9, analog / digital (A / D) converter 10, first to eleventh input / output ports IOP1 to IOP11, clock oscillator ( CPG) 12, a clock control circuit 13, and a prescaler 14 are provided with functional blocks (also referred to as circuit modules). These functional blocks are not particularly limited, but may be made of single crystal silicon by a known CMOS semiconductor integrated circuit manufacturing technique. One It is formed on a semiconductor substrate. The timer includes, for example, a PWM (Pulse Width Modulation) timer, and when the timer 7 particularly indicates a PWM timer, it is referred to as a PWM timer 7 for convenience.
[0041]
The single-chip microcomputer has a plurality of external terminals. Of the external terminals, a power supply terminal is supplied with a ground level (Vss), a power supply voltage level (Vcc), an analog ground level (AVss), and an analog power supply voltage level (AVcc). The external terminals are provided with dedicated control terminals in addition to the power supply terminals. These terminals include a reset (RES), a standby (STBY), a mode control (MD0 to MD2), and a clock input (EXTAL, XTAL). And non-maskable interrupt (NMI) terminals.
[0042]
<< Internal Bus Configuration of Single-Chip Microcomputer >> The above-described functional blocks shown in FIG. 1 are interconnected by an internal bus. The internal bus includes a control bus including a read signal, a write signal, and a bus size signal in addition to the address bus and the data bus. IAB and PAB exist on the internal address bus. IDB and PDB exist as internal data buses. These IAB, PAB, IDB, and PDB buses are interfaced with each other by a bus controller 3.
[0043]
The internal data bus IDB and the internal address bus IAB are used when either the CPU 1 or the DTC 2 that can operate as a bus master selectively has a bus right. Which bus right is given depends on the control of the bus controller 3. The bus controller 3 includes a function block selection circuit MS that decodes information output to the internal address bus IAB to determine which function block has been selected. The function block selection circuit MS identifies a function block to be selected by the address signal, and activates a module selection signal (not shown) corresponding to the identified function block. According to the information decoded by the function block selection circuit MS, it is determined (selected) whether the connection between the IAB and the PAB and the connection between the IDB and the PDB are performed or not. That is, if the access target at that time is a circuit module coupled to the internal buses IAB and IDB, the bus controller 3 does not connect the internal buses PAB and PDB to IAB and IDB. On the other hand, when the access target is a circuit module connected to the internal buses PAB and PDB, the bus controller 3 connects the internal buses PAB and PDB to IAB and IDB. In this specification, a bus master means a module that can output (form) an address to a bus and can also input and output data. A bus slave is an output (form) of an address to a bus. Is impossible, and means a module capable of inputting an address, inputting / outputting data, or outputting data.
[0044]
The internal buses IAB and IDB are connected to the CPU 1, the DTC 2, the ROM 5, the RAM 6, and the bus controller 3. Further, the internal address bus IAB is connected to input / output ports IOP1 to IOP3 to enable connection to an external address bus (not shown), and the internal data bus IDB is connected to input / output ports to enable connection to an external data bus (not shown). Connected to ports IOP4 and IOP5. The internal buses PAB and PDB are connected to the bus controller 3, timer 7, watchdog timer 8, SCI 9, A / D converter 10, interrupt controller 4, and input / output ports IOP1 to IOP11. The bus controller 3 controls the bus interface when the internal buses PAB and PDB are used for external access via the input / output ports IOP1 to IOP11.
[0045]
In making the internal bus into two systems of IAB and IDB and PAB and PDB, it is considered that a circuit module with a high frequency of use with bus access shares a bus with a relatively small load. In the bus access by the CPU 1, the number of instruction fetches is increased as compared with the number of data accesses. In order to improve the processing performance of the CPU 1, instructions must be fetched in accordance with the contents to be processed, and the frequency of instruction fetches per unit time is increased. In consideration of this point, in the present embodiment, the CPU 1 and DTC 2 operated as the bus master module and the RAM 6 and the ROM 5 storing programs and the like, which are working areas of the CPU 1, are cut off from other circuit modules to relatively load. Are connected to small internal buses IAB and IDB.
[0046]
In the bus access by the CPU 1, the number of instruction fetches is increased compared to the number of data accesses. In order to improve the processing performance of the CPU 1, instructions must be fetched in accordance with the contents to be processed, and the frequency of instruction fetches per unit time is increased. Most of the instructions of the CPU 1 are stored in the built-in ROM 5 or an external memory (not shown). Therefore, even when the program memory is an external memory, the internal buses IAB and IDB may be used via the input / output ports IOP1 to IOP5, and a large number of circuit modules unrelated to instruction fetch are connected, so that the load is relatively increased. It is not necessary to use the internal buses PAB and PDB.
[0047]
The internal buses PAB, PDB are adapted to retain the previous value on that bus when it is not in use. For example, a static latch circuit is connected to each signal line of the internal bus PDB, and when the internal bus PDB is not used, the output terminal of the circuit module to which the output terminal is connected is set to a high output impedance state. , The previous value is held by the static latch circuit. If a CMOS circuit is used, the current consumption of these PDBs can be reduced to almost zero because the signal state does not change in this case. As shown in FIG. 1, PABs and PDBs have many objects to be connected and have large wiring capacitances. Therefore, by reducing the frequency of signal changes occurring in these, in other words, the PABs and PDBs are relatively infrequently used. The connection of the circuit module can contribute to lower power consumption. That is, the bus modules IAB and IDB having relatively small loads are shared by the circuit modules frequently used with the bus access.
[0048]
<< Clock Supply System of Single-Chip Microcomputer >> The single-chip microcomputer of this embodiment is operated in synchronization with a system clock signal generated by the clock oscillator 12 and the clock control circuit 13. Each functional block is operated by a two-phase clock signal that is formed based on such a system clock signal and has no overlap with each other. According to this embodiment, the system clock signal is roughly classified into φB and φS. For convenience, the system clock signals φS and φB are also simply referred to as the system clock signal φ. Similarly, no-overlapping two-phase clock signals φ1S and φ2S formed based on φS and no-overlapping two-phase clock signals φ1B and φ2B formed based on φB are collectively referred to simply. They may be written as φ1 and φ2. The clock signal output from the clock oscillator 12 is shown as φOSC.
[0049]
The system clock signal φB is supplied as a bus master clock to, for example, the CPU 1, the DTC 2, the bus controller 3, the interrupt controller 4, and the input / output ports IOP1 to IOP5 for an external bus interface. A clock signal line for supplying the system clock signal φB to each circuit module is illustrated as L1. The clock signal φB is formed by dividing the frequency of the clock signal φOSC in the clock control circuit 13. In the present embodiment, this frequency division ratio can be selected. If the frequency division ratio of clock signal φB is increased, the operating frequency of the portion of the circuit module receiving system clock signal φB is reduced in proportion to this, and the current consumption is reduced. Such parts are in principle always active. For example, the interrupt controller 4 must constantly monitor the occurrence of an interrupt request. If an interrupt request occurs, the interrupt controller 4 must generate a predetermined state transition or request the CPU 1 or DTC 2 to perform processing. That is because Therefore, in such a circuit portion, the fact that the operating frequency can be controlled by the clock signal φB realizes a reduction in power consumption in the entire single-chip microcomputer as required.
[0050]
The other system clock signal φS is supplied as a peripheral clock to, for example, the timer 7, the watchdog timer 8, the SCI 9, the A / D converter 10, and the input / output ports IOP1 to IOP11. A clock signal line for supplying the system clock signal φS to each circuit module is illustrated as L2.
[0051]
As is clear from FIG. 1, the clock signal is supplied to each functional block except the ROM 5 and the RAM 6, and the overall clock signal wiring length is considerably lengthened. As shown in FIG. 1, the functional block to which the clock signal φB is supplied and the functional block to which the clock signal φS is supplied are each partially localized. This makes it possible to reduce the total wiring length for the clock signal. At least, the entire wiring length can be reduced as compared with a case where independent clock signals are supplied to all the functional blocks. By suppressing the total wiring length of the clock signal, a parasitic capacitance component on the wiring can be suppressed. Since the clock signal has a high frequency of signal change, power consumption can be suppressed by suppressing the capacitance of the clock signal wiring (by shortening the wiring length).
[0052]
The frequency of the system clock signal φB can be changed depending on the setting of the dividing ratio by software, for example, as described later. On the other hand, the frequency of the system clock signal φS is fixed. Further, the clock control circuit 13 supplies a clock control signal to the DTC 2, the timer 7, the watchdog timer 8, the SCI 9, and the A / D converter 10. The clock control signal permits / stops the operation of the clock signal (change of the clock signal) in the functional block. Such clock control is described in, for example, Japanese Patent Application Laid-Open No. Sho 60-195631. However, in this example, the operation of the functional block during the period in which the operation of the clock is stopped is not considered. According to the study of the present inventors, the internal state should be maintained while the clock of the functional block is stopped. Such a functional block operates in synchronization with a no-overlapping two-phase clock signal φ1, φ2 formed based on a system clock signal φS, and details thereof are shown in FIGS. ), A sequential circuit synchronized with φ1 is constituted by a dynamic circuit, and a sequential circuit synchronized with φ2 is constituted by a static circuit.
[0053]
<< Module Stop in Single-Chip Microcomputer >> The details of the contents of the module stop in the single-chip microcomputer will be described later, but are roughly as follows. The clock control circuit 13 sends a DTC 2, a timer 7, a watchdog timer 8, an SCI 9, and an A / D converter 10 to a clock stop signal, that is, a module stop signal (in FIG. 1, a module stop signal is given by MSTP, respectively). (Shown generically). Such a module stop signal MSTP is provided from the clock control circuit 13 to each functional block as a unique signal. In the case of an SCI including a plurality of channels, a module stop signal MSTP can be assigned to each channel. Such a clock stop in units of functional blocks is described in "H8 / 3048 Series Hardware Manual", P607 to P632, published by Hitachi, Ltd. in March 1994, and Japanese Patent Application Laid-Open No. 60-195631. When the watchdog timer 8 functions as a watchdog timer, the module stop signal is invalidated. This is to prevent the watchdog timer 8 from being stopped by mistake due to the function of monitoring the system. The details will be described later. According to the "H8 / 3048 Series Hardware Manual" P607 to P632 issued by Hitachi, Ltd. in March 1994, when the clock is stopped, the functional blocks are reset and the internal registers need to be reset. , And is. For example, in the start-stop synchronous SCI, the operation cannot be performed immediately by outputting a preamble for one frame when the operation is resumed. In the PWM timer 7, clock selection, duty setting, and the like are required. On the other hand, in the present embodiment, when the clock is stopped, the function block holds the internal state.
[0054]
<< Adoption of Clock Synchronous Internal Memory >> FIG. 2 is a block diagram showing a modification of the single-chip microcomputer of FIG. The single-chip microcomputer shown in FIG. 2 has a circuit type in which the ROM 5 and the RAM 6 are operated in synchronization with a clock signal with respect to FIG. 1, and for example, a clock signal φB similar to that supplied to the CPU 1 is supplied to them. Is done. By operating the built-in memories ROM5 and RAM6 in synchronization with the clocks of the bus masters CPU1 and DTC2, a high-speed operation can be performed. As the RAM 6 operated in synchronization with the clock, a clocked static RAM or the like can be given. Examples of the ROM 5 operated in synchronization with the clock include a mask ROM, an EEPROM, and a flash memory.
[0055]
<< Internal Circuit of Each Functional Block >> FIG. 3A shows a typical block example of a logic circuit constituting each functional block. Each of the logic circuits is basically composed of a combinational circuit 20, a sequential circuit 21 having its output as an input and operating in synchronization with the clock signal φ2, a combinational circuit 22 having an output of the sequential circuit 21 as an input, and a combinational circuit. A circuit represented by a sequential circuit 23 operated in synchronization with the clock signal φ1 with the output of the input 22 as an input is included as a basic unit. Further, if necessary, a signal may be transmitted from the sequential circuit 23 to the combinational circuit 20 in a cyclic manner. Although not shown, an external input signal is input to any of the circuits, and an external output signal is output from any of the circuits.
[0056]
FIG. 3B shows an example in which the representative sequential circuits 21 and 23 are constituted by CMOS dynamic circuits. For example, the sequential circuit 21 is configured by a series circuit of a CMOS clocked inverter 210 and a CMOS inverter 211, and the sequential circuit 23 is configured by a series circuit of a CMOS clocked inverter 230 and a CMOS inverter 231. In the sequential circuit 21, the clocked inverter 210 is enabled to output by the high level of the clock signal φ2, and in the sequential circuit 23, the clocked inverter 230 is enabled to output by the high level of the clock signal φ1. The P-channel type MOS transistor 212 is turned on by a signal SIG which is set to a low level during operation standby, forcing the input of the inverter 211 to a power supply voltage, and setting the inside to a state where the previous value is held. As the signal SIG, a signal similar to the oscillator stop signal 135 described with reference to FIG. 9 can be used.
[0057]
In the circuit form shown in FIG. 3B, information transmission is dynamically performed by charging and discharging the output load capacity of the clocked inverters 210 and 230. By using a two-phase no-overlap clock signal (a no-overlap clock signal is also referred to as a non-overlap clock signal) φ1 and φ2 and a dynamic circuit, the number of transistors can be reduced, and the physical characteristics of the semiconductor integrated circuit can be reduced. The scale can be reduced. However, in this case, data is held by the electric charge stored in the load capacitor, and therefore, data can be held only for a finite time due to the presence of a leakage current from the load capacitor. For example, if the leakage current is constant, the data can be expressed as V-it / C in a state where the high level is maintained. C is the capacity, V is the power supply voltage, i is the leakage current, and t is the elapsed time. As the time elapses, the voltage at the output terminal decreases. If the threshold voltage of a CMOS circuit to which such a voltage is input is Vth, data can be held only for a time equal to or less than C (V-Vth) / i. Therefore, it is necessary to update the data within this time. In other words, the switching frequency of a switching element such as the clocked inverters 210 and 230 cannot be reduced to i / C (V-Vth) or less. As a result, when the internal operation is stopped, such as when the clock is stopped, the switching frequency cannot be sufficiently increased, and the data cannot be held.
[0058]
In order to retain data even in such a clock stopped state, it is conceivable to use a static circuit instead of a dynamic circuit for each of the sequential circuits 21 and 23. The static circuit increases the number of transistors and increases the physical scale of the semiconductor integrated circuit as compared with the dynamic circuit. As the number of transistors increases, the number of wirings increases, and the current consumption increases in proportion to the number of wirings and the number of transistors.
[0059]
FIG. 3C shows an example of a CMOS dynamic circuit used in the single-chip microcomputer of this embodiment. In the figure, the sequential circuit 23 synchronized with the clock signal φ1 is composed of a dynamic circuit, and the sequential circuit 21 synchronized with the clock signal φ2 is composed of a static circuit. In the static circuit, a clocked inverter 213 is added to the inverter 211 in an anti-parallel connection, and the output operation can be performed in a phase opposite to that of the clocked inverter 210. Note that the output stage inverter 231 in the sequential circuit 23 is added to match the logical polarity and may be deleted as necessary. According to the example of FIG. 3C, when the clock is stopped and when the operation is on standby, the clock signal φ1 is at the high level and φ2 is at the low level, and the sequential circuit 21 latches the input data immediately before it, and The state of the sequential circuit 23 is controlled to a state where the previous value is held. The operation standby state means a state in which the clock is not stopped, but the operation is stopped while maintaining the previous state when a predetermined event has not occurred. As the predetermined event, for example, in the case of the PWM timer 7, read / write by a bus master such as the CPU 1, generation of a count-up clock described later, and the like are included.
[0060]
In FIG. 3C, the dynamic circuit forming the sequential circuit 23 is formed of six MOS transistors, and similarly, in FIG. 3C, the static circuit forming the sequential circuit 21 is formed of ten MOS transistors. In FIG. 3B, the dynamic circuit forming the sequential circuit 23 is constituted by six MOS transistors, and similarly, in FIG. 3B, the dynamic circuit forming the sequential circuit 21 is constituted by seven MOS transistors. . If all circuits are static circuits, each of the sequential circuits 21 and 23 is composed of ten MOS transistors. Therefore, comparing this portion, it can be seen that, of the 16 transistors in the configuration of FIG. 3C, 13 transistors if all are dynamic circuits and 20 transistors if all are static circuits. The configuration of ()) requires about 1.23 times the number of transistors as compared to the case where both circuits are dynamic circuits and about 0.8 times the number of transistors as compared to the case where both circuits are static circuits.
[0061]
In addition, as shown in FIG. 3C, static circuits and dynamic circuits are alternately arranged as sequential circuits, and the duty ratios of the no-overlap two-phase clock signals φ1 and φ2 (in this specification, the duty ratio = High level period / 1 cycle) from 50%, and the one with the larger duty ratio is used as the clock signal of the dynamic circuit. In other words, the high output impedance period of the clocked inverter 230 included in the dynamic circuit is set shorter than the high output impedance period of the clocked inverter 210 included in the static circuit. Thereby, for example, the range in which the frequency of system clock signal φB can be reduced can be expanded. For example, a clock signal φ1B having a duty ratio larger than 50% shown in FIG. 20 is used as the clock φ1 of the dynamic circuit, and a clock signal φ2B having a duty ratio smaller than 50% is used as the clock φ2 of the static circuit.
[0062]
<< Prescaler Clock >> In addition to the system clock signal, a so-called prescaler clock signal may be supplied to a predetermined functional block. That is, when the frequency divider divides the system clock signal as needed, the clock signal having various division ratios is formed intensively when the prescaler is used, as compared with the case where the frequency divider is arranged in each functional block. Since the clock having the necessary division ratio is distributed to the necessary functional blocks, the frequency divider of each functional block can be shared, and the logic scale of the entire chip can be reduced.
[0063]
However, according to the study of the present inventors, the prescaler clock signal has a long clock wiring length and a large wiring capacity due to the property commonly used by each functional block. Further, the prescaler clock having a low frequency division ratio has a high signal change frequency. For this reason, current consumption also increases. In the present embodiment taking this into consideration, a clock signal having a relatively high frequency corresponding to a prescaler clock signal having a low frequency division ratio is not shared by the function blocks with respect to the function blocks, and each of the function blocks performs individual frequency division. It is made to generate individually using a circuit.
[0064]
FIG. 4 is a block diagram showing an example of the prescaler 14. The figure typically shows the configuration of the lower four digits, and the latch circuits constituting each digit are illustrated as 140 to 143. The circuit configuration is typically the same as the configuration of the latch circuit 140 shown in detail. Is the same. The latch circuit 140 mainly includes a static latch composed of two-input NOR gates 1401 and 1402, and a clocked inverter 1403 whose output is controlled by a terminal CS is disposed at an output stage thereof. Are provided with two-input AND gates 1404 and 1405 that perform an opening / closing function according to the logical value of the terminal CM. The input terminal T is coupled to one input terminal of a two-input type exclusive OR gate 1406, and the output of the clocked inverter 1403 is fed back to the other input terminal. The output of the exclusive OR gate 1406 is supplied to the AND gate 1404, and the output of the exclusive OR gate 1406 is supplied to the AND gate 1405 after being inverted by the inverter 1407. The logical value "1" is supplied to the input terminal T of the lowermost latch circuit 140, and the lower count-up clocks φ / 4UP, φ / 8UP, φ / 16UP,. They are connected in cascade.
[0065]
The latch circuits 140, 141, 142, 143,... Of each digit update the data held when the terminal CM is at the logical value "1" (high level in this embodiment, although not particularly limited). If the terminal T has a logical value “0” (not particularly limited, but in this embodiment, a low level), the data is held. If the terminal T has a logical value “1”, the data is inverted. That is, the terminal CM and the terminal CS are not simultaneously set to the logical value 1. In other words, φ1 and φ2 are no-overlap two-phase clock signals. The clocked inverter 1403 is enabled to output when the terminal CS is at a high level, and is brought into a high output impedance state when the terminal CS is at a low level. At the logical value “1” of the terminal CM, the other input of the AND gates 1404 and 1405 is reflected on the output of the AND gates 1404 and 1405, and the latch data is updated. At this time, if the terminal T is at a low level, the data that has been latched up to that point is held as it is, and if the terminal T is at a high level, the data that has been latched is inverted. At the low level of the terminal CM, the outputs of 1404 and 1405 are both forced to the low level, and the static latch composed of the two NOR gates 1401 and 1402 statically holds the previous state.
[0066]
The no-overlap two-phase clock signals φ1 and φ2 are generated from the clock signal φOSC. As shown in FIG. 4, the generation circuit 144 mainly includes a pair of AND gates 1443 and 1444 whose one output is fed back to the other input via delay circuits 1441 and 1442, and generates the clock signals φ1 and φ2. An OR gate 1445 for output control for forcing φ1 to a high level when stopped, and an AND gate 1446 for output control for forcing φ2 to a low level are provided. The AND gate 1444 takes a logical product of the inverted signal of the feedback signal via the φOSC and the delay circuit 1441. An AND gate 1443 takes a logical product of the inverted signal of the feedback signal via the delay circuit 1442 and φOSC. The AND gate 1446 ANDs the inverted signal of the prescaler module stop signal MSTPPSC and the output of the AND gate 1444. Although the details of the prescaler module stop signal MSTPPSC will be described later, the output of the clock signals φ1 and φ2 is permitted by the logical value “0”, and the output of the clock signals φ1 and φ2 is prohibited by the logical value “1”. In a state where the output of the clock signals φ1 and φ2 is prohibited, φ1 is fixed at a high level and φ2 is fixed at a low level. Therefore, at this time, changes in various prescaler clock signals are also suppressed.
[0067]
The prescaler 14 shown in FIG. 4 counts up the clock signal φOSC. For example, a prescaler as described in "H8 / 3003 Hardware Manual" p555 published by Hitachi, Ltd. in March 1993 sequentially generates frequency-divided clocks φ / 2, φ / 4, φ / 8. are doing. The prescaler 14 of this embodiment also generates count-up clocks φ / 2UP, φ / 4UP, φ / 8UP... For each digit. The count-up signal (carry signal) at the digit is obtained as a logical product signal of all the carry signals lower than the digit and the output of the latch circuit at the digit.
[0068]
In this embodiment, a clock signal (prescaler clock signal) generated by the prescaler 14 is supplied to predetermined functional blocks, for example, the timer 7, the SCI 9, the A / D converter 10, and the like. In this case, the prescaler clock signal supplied to such a functional block is a prescaler clock signal having a frequency division ratio of φ / 8 or more. Clock signals having a relatively small frequency division ratio (high frequency) such as φ / 2, φ / 4, φ / 2UP, φ / 4UP, etc. are not output from the prescaler 14 to external function blocks. When a clock signal having a low frequency division ratio is collectively supplied from the prescaler 14 to each functional block, charging and discharging are performed at high speed in synchronization with a high frequency on a considerably long clock wiring, so that power consumption increases. Furthermore, each functional block does not always use such a high-frequency clock signal separately from the system clock signal φS, and it is greatly expected that such power consumption will be wasted. Therefore, a clock signal having a relatively high frequency such as φ / 2 uses the system clock signal φS by dividing the frequency inside the functional block. Thus, power consumption can be reduced.
[0069]
5A to 5I show operation timing charts of the prescaler 14. The prescaler clock signal is changed at a timing synchronized with the clock signal φ1. The count-up clock of each digit is set to the logical value "1" when the latch circuit output of the lower digit of the digit becomes the logical value "1" of all the bits, and the digit is changed in synchronization with the subsequent φ1. . That is, a count-up clock to the upper digit is generated once in one cycle of the output Q of each digit. For example, φ / 8 and φ / 16UP are signals having the same cycle, and the high-level period of φ / 16UP matches the high-level period of the clock signal φ / 2.
[0070]
<< Module Stop >> FIG. 6 is a block diagram of the PWM timer 7. The PWM timer 7 includes a no overlap generation circuit 700, a clock control circuit 710, a frequency divider 720, a read / write control circuit 730, a counter clock control circuit 740, an output control 750, a bus interface 760, a control register (TCR) 771, a counter (TCNT) 772, duty register (DTR) 773, and comparator (CMP) 774.
[0071]
The no-overlap generation circuit 700 receives the clock signal φS, and generates a clock signal φ1S having the same phase as φS and a clock signal φ2S having the opposite phase to the clock signal φ1S. . As shown in FIG. 7A, an example of the no overlap generation circuit 700 includes a pair of AND gates 703 and 704 in which one output is fed back to the other input via delay circuits 701 and 702. An output control OR gate 705 for forcing the clock signal φ1S to a high level when the clock signals φ1S and φ2S are to be stopped, and an output control AND gate 706 for forcing the clock signal φ2S to a low level are provided. Become. The AND gate 704 calculates the logical product of the clock signal φS and the inverted signal of the feedback signal via the delay circuit 701. The AND gate 703 calculates the logical product of the clock signal φS and the inverted signal of the feedback signal via the delay circuit 702. The AND gate 706 ANDs the inverted signal of the timer module stop signal MSTPPWM supplied to one input and the output of the AND gate 704. The details of the timer module stop signal MSTPPWM will be described later, but the output of the clock signals φ1S and φ2S is permitted by the logical value “0”, and the output of the clock signals φ1S and φ2S is prohibited by the logical value “1”. That is, when the timer module stop signal MSTPPWM is at the logical value "1", the signal φ1S is fixed at a high level and the signal φ2S is fixed at a low level. As described above, the timer module stop signal MSTPPWM is a control signal for stopping the clock signals φ1S and φ2S with a predetermined logical value when it is not necessary to operate the PWM timer 7.
[0072]
The clock signals φ1S and φ2S generated by the no overlap generation circuit 700 are supplied only to the frequency divider 720, the clock control circuit 710, and the counter clock control circuit 740.
[0073]
Frequency divider 720 receives clock signals φ1S and φ2S and generates clock signal φS / 2. This logical configuration can be realized with the lowest logical configuration in the prescaler 14 described with reference to FIG. The clock signal φS / 2 having a relatively small frequency division ratio with respect to the clock signal φS is generated by a frequency divider in a functional block. This is a consideration for reducing power consumption as described in the prescaler item.
[0074]
The counter clock control circuit 740 inputs φ / 16UP, φ / 64UP, and φ / 256UP as prescaler clocks, and also inputs the clock signal φS / 2 generated by the frequency divider 720. A desired input clock signal is selected from these input clock signals, and the selected input clock signal is used for counting up. That is, the input clock signal to be selected is specified by the CK1 and CK0 bits of the control register (TCR) 771, and the input clock signal is selected by the counter clock control circuit 740 according to this specification, and the selected clock is selected. The count-up clock signal 741 is generated in synchronization with the signal cycle. The generation of the count-up clock signal 741 is permitted when the OE (output enable) bit in the control register (TCR) is "1", and is prohibited when it is "0". The counter (TCNT) 772 performs a count-up operation in synchronization with the count-up clock signal 741.
[0075]
The clock control circuit 710 controls the clock signals φ1S and φ2S and the PWM timer selection signal MSPWM # generated by the address signal output from the CPU 1 (the symbol # indicates that the signal attached thereto is a low enable signal, that is, a signal of negative logic. ), And the count-up clock signal 741 output from the counter clock control circuit 740, and the clock signals φ1-PWM and φ2-PWM are converted to the TCR 771, TCNT 772, CMP 774, DTR 773, bus interface 760, output control circuit 750. The clock signals φ1-PWM and φ2-PWM become valid when the CPU 1 reads / writes the PWM timer 7 or when a count-up clock signal is generated. In other cases, φ1-PWM is fixed at a high level and φ2-PWM is fixed at a low level.
[0076]
The read / write control circuit 730 receives the internal address, read signal RD, write signal WR, and PWM timer selection signal MSPWM # output from the CPU 1 via the bus controller 3 to control each register and the bus interface. , And controls the input and output of data between each register and, for example, the CPU 1.
[0077]
The output control circuit 750 receives the compare match signal 780 output from the CMP 774, the overflow signal 781 output from the TCNT 772, and the OE bit from the TCR 771, and outputs a PWM signal. When the OE bit is set to the logical value “1”, the PWM signal is output to the outside from a predetermined terminal that is also used as an input / output port. The PWM signal outputs a logical value "1" at the time of a compare match (the compare match signal 780 has the logical value "1"), and outputs a logical value "0" at the time of overflow (the overflow signal 781 has the logical value "1"). Is output.
[0078]
The bus interface 760 inputs and outputs information between the internal data bus PDB and the module data bus inside the PWM timer 7 under the control of the read / write control circuit 730.
[0079]
The TCR 771 has an OE bit and CK1 to CK0, and data is input / output under the control of the read / write control circuit 730. When the OE bit is set to "1", the PWM timer 7 operates. As described above, the CK1 to CK0 bits are bits for selecting the count clock cycle. The TCNT 772 inputs and outputs data under the control of the read / write control circuit 730. Further, the count-up operation is performed by the count clock signal 741 output from the counter clock control circuit 740. When an overflow occurs due to the count-up operation, the TCNT 772 activates the overflow signal 781. The DTR 773 inputs and outputs data according to the control of the read / write control circuit 730. The CMP 774 receives and compares the outputs of the TCNT 772 and the DTR 773, and activates the compare match signal 780 when the results match.
[0080]
FIG. 7B illustrates an example of the clock control circuit 710. The clock control circuit 710 includes two OR circuits 711 and 712 and one AND circuit 713. The inverted signal of the timer selection signal MSPWM # and the count-up clock signal 741 are input to the OR circuit 711. An inverted signal of the output of the OR circuit 711 and the clock signal φ1S are input to the OR circuit 712, and this output is used as the clock signal φ1-PWM. The output of the OR circuit 711 and the clock signal φ2S are input to the AND circuit 713, and this output is used as the clock signal φ2-PWM. The clock signals φ1-PWM and φ2-PWM become valid when the CPU 1 activates the timer selection signal MSPWM # to read / write the PWM timer 7, or when the count-up clock signal 741 is generated. . In other cases, the clock signal φ1-PWM is fixed at a high level and the clock signal φ2-PWM is fixed at a low level. That is, only when a predetermined event (read / write of the CPU 1 and generation of a count-up clock signal) occurs, the clocks φ1-PWM and φ2-PWM to be supplied to the respective units change clocks. Therefore, a circuit which receives and operates in synchronization with the clock signals φ1-PWM and φ2-PWM, that is, functional blocks other than the no overlap generation circuit 700, the clock control circuit 710, the frequency divider 720, and the counter clock control circuit 740 Is operated only when the predetermined event occurs. In other states, the change in the signal is suppressed, and the current consumption is suppressed.
[0081]
As described above, the no-overlap generating circuit 700 is configured as shown in FIG. 7A, and φ1S is fixed at a high level and φ2S is fixed at a low level by the high level of the module stop signal MSTPPWM. As is clear from FIG. 7B, in the module stop state in the no overlap generation circuit 700, the clock signals φ1-PWM and φ2-PWM are also fixed to predetermined levels, respectively. As described above, when the PWM timer 7 is not used at all, the change of the internal clock signals φ1S, φ2S, φ1-PWM, φ2-PWM is suppressed by the module stop signal MSTPPWM. By suppressing changes in the internal clock signals φ1-PWM and φ2-PWM until a predetermined event occurs, low power consumption can be achieved.
[0082]
The above-described configuration for selectively suppressing the change of the internal clock signal by the no overlap generation circuit 700 and the clock control circuit 710 is similarly applied to other circuit modules, for example, WDT8, SCI9, and A / D10. The same applies to the supply of a prescaler clock signal with a high frequency division ratio and the generation of a clock with a low frequency division ratio by an internal divider.
[0083]
FIG. 7C shows an example of a no overlap generation circuit employed in the WDT 8. An AND circuit 707 is added to the no overlap generation circuit 700 shown in FIG. One input of the AND circuit 707 is supplied with a module stop signal MSTPWDT assigned to the WDT 8, and the other input is supplied with an inverted signal of a WDTM bit designating a watchdog timer mode. The WDT 8 is also made available as an interval timer, and when it is used as a watchdog timer, the WDTM bit is set to a logical value "1". A WDTM bit is provided in a predetermined register, and this bit is set to a logical value “1” by, for example, the CPU 1 to designate the watchdog timer mode, in other words, once the watchdog timer mode is designated, the module The instruction to stop the module by the stop signal MSTPWDT is ignored. As a result, it is possible to prevent a situation in which the system monitoring function using the WDT 8 is erroneously released, thereby contributing to an improvement in the reliability of the system.
[0084]
FIG. 8 shows an operation timing chart of the PWM timer of FIG. The CPU 1 writes the TCR 771 of the PWM timer 7 from the state S3. Such a write operation requires three states. First, in state S3, the module selection signal MSPWM # is set to low level. When the module selection signal MSPWM # goes low, the output of the OR circuit 711 shown in FIG. 7B goes high, and the clock signals φ1-PWM and φ2-PWM are synchronized with φ1S and φ2S. To start changing. Note that MSPWM # is synchronized with φ1S. The OE bit is set to "1" in the third state of the write operation (start timing of state S5). Further, CK1 to CK0 are set, and for example, the clock signal φS / 2 is selected by the set CK1 to CK0.
[0085]
With the OE bit set to “1”, the clock signal φS / 2 generated by the frequency divider 720 is used as a count-up clock signal 741, and during a period when the count-up clock signal is at a high level, the clock signal φ1- PWM and φ2-PWM are changed in accordance with the clock signals φ1S and φ2S, and the PWM timer 7 performs a count-up operation. During the period from state S6 to state S12, the periods of φ1-PWM and φ2-PWM are halved compared to the case where clock signals φ1S and φ2S are used as they are. Accordingly, the operation frequency of the circuit blocks other than the no-overlap generation circuit 700, the clock control circuit 710, the frequency divider 720, and the counter clock control circuit 740 is also reduced to 、, and the current consumption of such portions is also reduced to １ ／. be able to. For example, if the ratio of the logical scale of such a part to the logical scale of the no overlap generation circuit 700, the clock control circuit 710, the frequency divider 720, and the counter clock control circuit 740 is 8: 2, the PWM timer 7 can also be reduced to 6/10. If φ / 16UP is selected as the count-up clock, this is equal to the frequency of φS / 8, so that the current consumption of the portion is reduced to 1/8, and the current consumption of the entire PWM timer 7 can be reduced to 3/10. .
[0086]
When the OE bit is cleared to “0” by the write operation of the CPU 1 in the state S13 to the state S15, the output of the OR circuit 711 is set to a low level, whereby φ1-PWM is at a high level and φ2-PWM is at a high level. Fixed to low level. During the timer operation of the PWM timer 7 (state S3 to state S5, state S7, state S9, state S11, state S13 to state S15), the pulse widths of φ1-PWM and φ2-PWM are equivalent, and the operation is suspended. , DC1-φPWM is at a high level and φ2-PWM is at a low level. The internal state is maintained in the suspended state of this operation. That is, the sequential circuits in the circuit blocks other than the no-overlap generation circuit 700, the clock control circuit 710, the frequency divider 720, and the counter clock control circuit 740 of the PWM timer 7 are the sequential circuits as shown in FIG. Is used, the clock signal φ2 is used as the clock signal φ2-PWM, and the clock signal φ1 is used as the clock signal φ1-PWM.
[0087]
Similarly, in the module stop mode, the module stop signal MSTPPWM is activated, and stops when φ1S is at a high level and φ2S is at a low level, and further stopped when φ1-PWM is at a high level and φ2-PWM is at a low level. I do. In this state, the state of the PWM timer 7 itself is maintained as described above. For example, the contents of TCR771 and the contents of DTR773 and TCNT772 are retained. It is not necessary to reset the TCR 771 after releasing the module stop. In the module stop state, the CPU 1 cannot perform read / write. Since φ1S and φ2S are stopped, the signal change of the entire PWM timer 7 is suppressed, and the current consumption during that period is substantially zero. The output of the AND circuit is connected to the supply line of the timer module stop signal MSTPPWM shown in FIG. 7A, and the timer module stop signal MSTPWM and the timer module selection signal MSPWM # are supplied to the AND circuit. By doing so, even if the module stop state is set, the PWM timer 7 is made readable / writable by the CPU 1.
[0088]
<< Clock Control Circuit >> FIG. 9 is a block diagram of the clock oscillator 12 and the clock control circuit 13 of the single-chip microcomputer shown in FIG. The clock control circuit 13 includes a frequency divider 130, a selector 131, a clock control register 132, a module stop control register 133, and a standby control circuit 134. The module stop control registers 133 are provided for a predetermined number of bits corresponding to selectable function blocks. That is, bits corresponding to selectable function blocks are provided in the module stop control register 133. A crystal oscillator is connected to the oscillator 12 via EXTAL and XTAL terminals, or an external clock is supplied from the EXTAL terminal. When a crystal oscillator is used, it can be considered that an oscillation circuit is configured by the crystal oscillator and the circuit 12. Although not particularly limited, the oscillation circuit 12 generates the clock signal φOSC having the same frequency as the natural frequency of the crystal resonator or the frequency of the external clock. The oscillator 12 is supplied with an oscillator stop signal 135 from the standby control circuit 134, and the oscillator 12 is stopped by the oscillator stop signal 135 being activated in the standby state, and the clock signal φOSC is fixed at a high level, for example, and its change is made. Is stopped. Note that the oscillator 12 may include a duty correction circuit. Further, the oscillator 12 may incorporate a frequency divider and output a clock signal obtained by dividing the frequency of the crystal oscillator or the external clock by 2 as φOSC. These are described in, for example, "H8 / 3003" issued by Hitachi, Ltd. in March 1993.
Hardware Manual ", pages 553 to 560.
[0089]
The frequency divider 130 receives the clock signal φOSC and, for example, sequentially divides the frequency by two to generate clock signals φOSC / 2, φOSC / 4, and φOSC / 8. Selector 131 receives clock signals φOSC, φOSC / 2, φOSC / 4, and φOSC / 8 and outputs a clock signal selected by MSME bit, CKS1, and CKS0 bits of clock control register 132 as system clock signal φB. Then, it is supplied to the CPU 1 and the like in the single-chip microcomputer. Alternatively, count-up clocks φOSC / 4UP, φOSC / 8UP, and φOSC / 16UP may be input instead of φOSC / 2, φOSC / 4, and φOSC / 8. When changing the selection content by the selector 131, the phase of the clock signal is not particularly matched before and after the change. For example, by changing in synchronization with the rising of the clock signal φS (φ1S when generated inside the selector 131), the minimum pulse width at the transition becomes equal to or greater than the pulse width of the clock signal φS (φOSC). When the clock signal is stopped in the low power consumption state, φOSC is set to the high level, and the clock signals φB and φS are set to the high level. FIG. 10A shows an example of a clock signal selection mode based on the logical values of the MSME bit, the CKS1 bit, and the CKS0 bit. CKS1 and CKS0 are significant when MSME = "1", and when MSME = "0", φS = φOSC regardless of CKS1 and CKS0.
[0090]
FIG. 10B shows an embodiment of the selector controlled by the MSME bit, CKS1 bit, and CKS0 bit. In the figure, an AG 101 is an AND gate (logical product circuit) that receives a CKS 1 bit, a CKS 0 bit, and an MSME bit and outputs “1” when these bits are “1”. An AG 102 is a CKS 0 bit. The AND gate receives the inverted signal, the CKS1 bit and the MSME bit, and outputs “1” when CKS0 = “0”, CKS1 = “1”, and MSME = “1”. AG103 is the inverted signal of the CKS1 bit. , CKS0 bit and MSME bit, and outputs “1” when CKS1 = "0", CKS0 = "1", and MSME = "1". The AG 104 is an AND gate that receives the inverted signal of the CKS0 bit and the inverted signal of the CKS1 and outputs “1” when CKS0 = “0” and CKS1 = “0”. The NG101 is the output of the AG104 and the MSME. An OR gate (logical sum circuit) that receives a bit inversion signal and outputs “1” when the output of the AG 104 is “1” or MSME = “0”. Therefore, the OR gate NG101 outputs “1” when the MSME bit is “0” or when both the CKS0 bit and the CKS1 bit are “0”.
[0091]
AG105 is an AND gate receiving the output of the OR gate NG101 and the clock signal φOSC, AG106 is an AND gate receiving the output of the AND gate AG103 and the divided clock signal φOSC / 2, and the AG107 is the AND gate. The AND gate receives the output of the AND gate AG102 and the divided clock signal φOSC / 4, and the AG 108 receives the output of the AND gate AG101 and the divided clock signal φOSC / 8. Outputs of these AND gates AG105 to AG108 are supplied to an OR gate NG102, and the OR gate NG102 outputs the system clock signal φB. By configuring the selector in this manner, the OR gate NG 102 outputs a system clock signal φB having a frequency according to the combination of each bit shown in FIG.
[0092]
The clock control register 132 and the module stop control register 133 are connected to the internal data bus PDB, and are readable / writable by the CPU 1. The clock control register 132 outputs the MSME bit, CKS1, and CKS0 bits to the selector 131, and outputs the SSBY bit to the standby control circuit 134. The module stop control register 133 supplies a module stop signal MSTP to each functional block. The standby control circuit 134 is formed of, for example, a flip-flop. When the CPU 1 executes a sleep command (the sleep command execution signal is in an active state) in a state where the SSBY bit of the control register 132 is a logical value “1”, the flip-flop is used. Is set to the set state. By the set state of the flip-flop, the oscillator stop signal 135 is activated, the oscillation operation of the oscillator 12 is stopped, and the single-chip microcomputer enters the standby state. When an external interrupt request or reset occurs in the standby state, for example, under the control of the interrupt controller 4, the standby release signal 136 is activated, and the flip-flop is reset. By this reset state, the oscillator stop signal 135 becomes inactive, the oscillation operation of the oscillator 12 is restarted, and the standby state is released. It is preferable to provide an oscillation stabilization time at the time of releasing the standby state, but the detailed procedure and configuration of the release are not directly related to the present invention, and therefore, detailed description thereof is omitted. When the CPU 1 executes the sleep command, the operation clock inside the CPU 1 is stopped. When the CPU 1 executes the sleep command while the SSBY bit is set to the logical value “0”, the oscillation operation of the clock oscillator 12 is not stopped. The state in which the CPU 1 executes the sleep command and is set in the CPU 1 (the sleep state of the CPU 1) can be released by interruption or reset.
[0093]
FIGS. 11A and 11B show examples of the register configuration of the module stop control register 133 for controlling the module stop mode and the register configuration of the clock control register 132 for controlling the medium speed mode. FIGS. 12A to 12C, FIGS. 13A and 13B, and FIGS. 14A to 14C show details of each bit of these registers.
[0094]
The module stop control register 133 is an 8-bit register readable / writable by the CPU 1 and has bits MSTP7 to MSTP3. MSTP7 is a data transfer controller (DTC) 2, MSTP6 is a timer 7, and MSTP5 is a watchdog timer (WDT). 8, MSTP4 corresponds to the serial communication interface (SCI) 9, and MSTP3 corresponds to the A / D converter 10. As shown in FIGS. 12A to 12C and FIGS. 13A and 13B, the module stop state can be specified separately for each functional block. The module stop signal MSTPPWM for the PWM timer 7 is activated by setting the bit MSTP6 to a logical value "1". The logical value "1" set in the bit MSTP5 is effective when not in the watchdog timer mode substantially as described with reference to FIG. 7C. Although the initial values of these bits after power-on or after reset are not particularly limited, they are logical value "1", and after reset, the module is in the stop state. The current consumption immediately after the start of the operation is reduced. For example, the current consumption is reduced according to the ratio of the logical scale of the function block in the module stop state to the function block in the operation state. For example, if the ratio is 4: 6, the current consumption can be reduced to 6/10.
[0095]
The prescaler 14 sets the timer 7, the WDT 8, the SCI 9, and the A / D converter 10 to which the prescaler clock signal is supplied, all in the module stop state, that is, all the MSTP6 to MSTP3 bits are set to "1". In addition, when the WDT 8 is not in the watchdog timer mode, the prescaler module stop signal MSTPPSC is activated and is stopped. According to FIG. 9, the module stop signal MSTPPSC for the prescaler 14 is formed by an AND circuit 137 which takes the logical AND of the module stop signals corresponding to the bits MSTP6 to MSTP3 and the inverted signal of the watchdog timer mode signal WDTM. Note that bits 2 to 0 of the module stop control register 133 are reserved bits, and when read, "0" is read, and writing is invalidated.
[0096]
The clock control register 132 has four bits of SSBY, MSME, CKS1, and CKS0 as shown in FIG. As shown in FIG. 14A, the SSBY bit controls the transition to the standby state. When the CPU 1 executes the sleep command while the SSBY bit is set to the logical value “1”, the oscillation operation of the clock oscillator 12 is stopped, the single-chip microcomputer shifts to the standby state, and the SSBY bit is set to the logical value. When the CPU 1 executes the sleep command in a state where the CPU 1 is cleared to “0”, the clock signal inside the CPU 1 is stopped and the CPU 1 transits to a so-called sleep state. In such a standby state, the entire single-chip microcomputer stops, but in the sleep state, only the CPU 1 stops.
[0097]
As shown in FIGS. 14B and 14C, the bit MSME is a medium speed mode enable bit, and only when this bit is set to the logical value “1”, The specification of the clock signal by the bits CKS1 and CKS0 becomes valid. When such bits MSME, CKS1, and CKS0 are supplied to the selector, the system clock signal φB of the microcomputer is selected from φOSC, φOSC / 2, φOSC / 4, and φOSC / 8. Note that the time of one cycle of the system clock signal φB is called one state. A state in which a clock other than the clock signal φOSC is selected as the clock signal φB is called a medium speed mode. Bits 6 to 3 are reserved bits, and when read, "0" is read and writing is invalid.
[0098]
FIG. 15 shows a schematic operation flowchart focusing on the system clock signal in the single-chip microcomputer of this embodiment. Immediately after the reset, the single-chip microcomputer enters the module stop state, and the bus master such as the CPU 1 starts operating in the high-speed mode (φB = φOSC). Then, it is determined whether the mode is the medium speed mode (ST1). If high speed operation is not required, a desired value is written to the clock control register, and the mode transits to the medium speed mode (ST2). For a function block requiring an operation, a desired value is written to the module stop control register to release the module stop state for the required function block (ST3). After that, each function block is set (ST4). For example, this is performed by initially writing a desired value to a control register or the like of each functional block. Then, desired processing is performed by the CPU 1 (ST5). At that time, if high-speed processing is not required, it is determined whether or not the clock signal φB should be changed to enable transition to the medium-speed mode (ST6). The clock control register is set according to the result (ST7). It is determined whether there is no need to operate a specific function block or whether there is a change in a circuit module (function block) to be operated to cope with a new operation of the specific function block. (ST8) If it should be changed, a desired value is written to the module stop control register to change the module stop state (ST9). Then, it is determined whether or not the microcomputer should be set to the standby state (ST10). If the operation of the entire microcomputer needs to be interrupted, the SSBY bit is set to "1" and a sleep command is executed (ST11). (ST12). When an external interrupt occurs, the operation returns from the standby state and resumes the operation (ST13). Since the internal state of the module is maintained in the standby state as described above, it is not necessary to set each functional block, for example, write to the control register of each functional block, after the standby state is released. The setting of the register in each of the above steps is performed by a program. For example, the CPU 1 executes an instruction to specify a register and write data to the register, thereby setting the register.
[0099]
<< Switching of φB Associated with Interrupt Request and the Like >> According to the study of the present inventors, if the clock is switched by software to reduce the power consumption, a predetermined event, for example, an interrupt to CPU1 occurs and CPU1 is interrupted. When high-speed processing is required, such an event is recognized as an interrupt, an interrupt exception process is performed, and a desired process is performed after switching the frequency division ratio of the system clock in the interrupt processing routine. It will be. In this case, the operation speed from the occurrence of the event to the desired processing cannot be increased, and the response time to the interrupt becomes longer, which is inconvenient. In this embodiment, when a predetermined event such as an interrupt request or a transfer request occurs, the control bit MSME is automatically cleared to the logical value “0”, and the CPU 1 and the DTC 2 are reset to the highest frequency φOSC of the clock signal φB. It is possible to make a transition to a high-speed mode for performing a synchronous operation. Upon return from the interrupt exception handling, bit MSME is set to logical value "1". When the bit MSME is set to the logical value “1” by software, the operation mode is set according to the set control bits CKS0 and CKS1. When a DTC activation request (DTC transfer request) is generated, similarly, the control bit MSME is automatically cleared to the logical value “0”, and the CPU 1 and the DTC 2 transition to the high-speed mode. When the DTC data transfer is completed, the MSME bit is automatically set to the logical value “1”, and the operation mode is set according to the set control bits CKS0 and CKS1. If the DTC 2 has an external transfer request terminal, the same can be applied to a case where an external transfer request is made.
[0100]
FIG. 16 shows a schematic block diagram of the MSME bit. The MSME bit mainly includes a set / reset type flip-flop 1320, for example. A data input terminal D of the flip-flop 1320 is connected to a predetermined signal line of the internal data bus PDB, and a clock input terminal C is an output of the AND circuit 1321, that is, a signal indicating a bus right of the CPU 1, a write signal, and an address decode signal. AND signal with The address decode signal is a signal obtained by decoding the contents of the address bus IAB, and is a signal indicating that the address of the clock control register 132 has been given. The output terminal Q is supplied to the selector 131 of the clock control circuit 13 and output to the data bus via the clocked buffer 1322. The clocked buffer 1322 is enabled to output by a high-level output of a two-input AND circuit 1323 that receives the decode signal and the read signal, and is in a high output impedance state in other states. To the reset input terminal R, a logical sum signal of the reset signal, the DTC transfer request signal, and the CPU interrupt signal is given from the logical sum circuit 1324. DTC transfer end signal 1325 is applied to set input terminal S. DTC transfer end signal 1325 is output from DTC2, and DTC2 is activated, for example, when data transfer ends. As the reset signal, an external reset signal RES or an output signal of the watchdog timer WDT8 is used. The DTC transfer request signal is supplied from the interrupt controller 4, and the CPU interrupt signal is also supplied from the interrupt controller 4.
[0101]
The CPU interrupt signal and the DTC transfer request signal are used as event occurrence signals. When the DTC 2 has an input terminal for an external transfer request other than the DTC transfer request from the interrupt controller 4, the logical sum signal of the external transfer request signal and the transfer request signal from the interrupt controller is a DTC transfer request. The signal is supplied to the OR circuit 1324 as a signal. It should be noted that, even if an interrupt request having a level lower than the mask level of the CPU 1 occurs with reference to the mask information of the CPU 1, the event is not recognized as an event. The interrupt mask is described in, for example, “H8 / 3003 Hardware Manual”, pages 89 to 115, issued by Hitachi, Ltd. in March 1993.
[0102]
FIG. 17 shows an example of the operation timing when an interrupt request occurs. When the bit CKS1 is cleared to “0”, the bit CKS0 is set to “1”, and the bit MSME is set to “1”, the operation at φB = φOSC / 2 (the state of the medium speed mode) )), When an interrupt request signal is generated in the state S5, the MSME bit is cleared to "0", φB = φOSC, and the CPU 1 and the DTC 2 are set to the high-speed mode. When the CPU 1 performs the interrupt exception processing and ends the processing to be processed in the high-speed mode, the CPU 1 sets the MSME bit to “1” by software according to the operation program. For example, in state S15, the MSME bit is set to "1", and φB = φOSC / 2. Thereafter, the CPU 1 executes a return instruction and transitions to the original processing.
[0103]
FIG. 18 shows an example of operation timing when a DTC activation request occurs. As in the case of FIG. 17, first, the CPU 1 operates in the medium speed mode (bit CKS1 is cleared to “0”, bit CKS0 is set to “1”, and bit MSME is set to “1”. φOSC / 2). At this time, when a DTC transfer request which is a DTC activation factor occurs, the bit MSME is cleared to “0”, φB = φOSC, and the CPU 1 and the DTC 2 are operated. When the DTC is activated, for example, the interrupt factor that has caused the activation is cleared, and data transfer is performed. When the necessary data transfer is completed, the DTC transfer end signal 1325 from the DTC 2 is activated, whereby the MSME bit is set to “1”, and the operation speed of the functional block such as the CPU 1 is returned to the original speed.
[0104]
<< Interface Signal >> FIG. 19 schematically shows an example of an interface between the bus master and the bus slave. FIG. 2 representatively shows interface signals I / F1 and I / F2. FIG. 20 shows an example timing of the bus master clock and the bus slave clock. According to the present embodiment, the bus masters are the CPU 1 and the DTC 2 that are operated in synchronization with the clock signal φB, and the bus slaves are functional blocks such as WDT8 and SCI9 that are operated in synchronization with the clock signal φS.
[0105]
The clock signal φB is always longer or equal in cycle to the clock signal φS according to the selection state of the selector 131, and the falling edge of the clock signal φB is synchronized with the rising edge of φS. φ1S and φ2S are no-overlapping two-phase clock signals generated from φS, and φ1B and φ2B are no-overlapping two-phase clock signals generated from φB. In FIG. 20, the duty of the clock signal φB is set to 50% or more. The clock signal φB can be formed, for example, by the logical sum of a signal obtained by dividing the frequency of the clock signal φOSC corresponding to the clock signal φS by 2 at a duty of 50% and a signal obtained by dividing the frequency by 4. Alternatively, the count-up signal φOSC / 8UP may be inverted. In particular, in the example of FIG. 20, the low level period of the clock signal φ1B matches the low level period of the clock signal φ1S, and the high level period of the clock signal φ2B matches the high level period of the clock signal φ2S. In other words, the low-level pulse width of the clock signal φ1B is equal to that of the clock signal φ1S, and the high-level pulse width of the clock signal φ2B is equal to that of φ2S.
[0106]
In the example of FIG. 19, the output signal of the bus master is output in synchronization with the change of the clock signal φ1B to the high level, and the input signal to the bus master is synchronized with the change of the clock signal 2B from the high level to the low level. Latched. The input signal to the bus slave is latched in synchronization with the change of the clock signal φ2S from the high level to the low level, and the output signal of the bus slave is output in synchronization with the change of the clock signal φ1S to the high level. . Referring to FIG. 20, the bus master outputs in synchronization with the high level periods of clock signals φB and φ1B, and the bus slave outputs in synchronization with the high level periods of φS and φ1S. The bus master inputs the clock signal φB while the clock signal φB is at the low level and φ2B is at the high level (the latch is performed in synchronization with the change of the clock signal φ2B from the high level to the low level). The bus slave inputs during a period when φS is at a low level and φ2S is at a high level (latch is performed in synchronization with the change of the clock signal φ2S from a high level to a low level). For example, in FIG. 20, the interface signal I / F1 is an interface signal from the bus master to the bus slave. The interface signal I / F1 is output from the bus master in synchronization with the change of φ1B of the state S9 to the high level, and latched by the bus slave in synchronization with the change of the φ2S of the state S9 from the high level to the low level. The interface signal I / F2 is an interface signal from the bus slave to the bus master. The interface signal I / F2 is output from the bus slave in synchronization with the change of φ1S of the state S3 to the high level, and latched by the bus master in synchronization with the change of φ2B of the state S4 from the high level to the low level. Therefore, a period of one or more states of the clock signal φS can be always ensured from the start of signal output to the capture. Thereby, the timing design can be made similar to the case where the medium speed mode is not considered, that is, the case where φB = φOSC.
[0107]
FIGS. 21 and 22 show the case where the synchronous clock signal for input / output control is reversed from those in FIGS. In the example of FIG. 21, the output of the bus master is synchronized with the change of the clock signal φ2B to the high level, and the input to the bus master is latched in synchronization with the change of the clock signal 1B from the high level to the low level. The input to the bus slave is latched in synchronization with the change of the clock signal φ1S from the high level to the low level, and the output of the bus slave is synchronized with the change in the clock signal φ2S to the high level. Referring to FIG. 22, the output of the bus master is performed in synchronization with the low level of the clock signal φB and the high level of φ2B, and the output of the bus slave is performed in synchronization with the low level of φS and the high level of φ2S. The input of the bus master is performed during the period when the clock signals φB and φ1B are at the high level (the latch is performed in synchronization with the change of the clock signal φ1B from the high level to the low level). This is performed during the level period (the latch is performed in synchronization with the change of the clock signal φ1S from the high level to the low level). For example, in FIG. 22, the interface signal I / F1 is an interface signal from the bus master to the bus slave. The interface signal I / F1 is output from the bus master in synchronization with the change of φ2B of the state S4 to the high level, and latched by the bus slave in synchronization with the change of φ1S of the state S5 from the high level to the low level. The interface signal I / F2 is an interface signal from the bus slave to the bus master. The interface signal I / F2 is output from the bus slave in synchronization with the change of φ2S of the state S7 to the high level, and latched by the bus master in synchronization with the change of φ1B of the state S12 from the high level to the low level. Therefore, a period of one or more states of the clock signal φS can be always ensured from the start of signal output to the capture. Thereby, the timing design can be made similar to the case where the medium speed mode is not considered, that is, the case where φB = φOSC.
[0108]
As shown in FIGS. 20 and 22, the operating clocks (φ1B, φ2B) of the bus master have a lower frequency than the operating clocks (φ1S, φ2S) of the bus slave, so that the interface signal from the bus master to the bus slave must be provided. The bus slave can recognize the same state as the output state of the bus master. Therefore, the interface signal can have an arbitrary pulse width for each state of the bus master. A bus access signal such as a read signal or a write signal, an interrupt factor clear signal, or the like can be assigned to such an interface signal.
[0109]
As shown in FIGS. 20 and 22, since the operating clock of the bus slave has a higher frequency than the operating clock of the bus master, the interface signal from the bus slave to the bus master is recognized by the bus master after the output of the bus slave. (The state of the bus slave) cannot be fixed. Therefore, these interface signals are preferably so-called handshake signals. An interrupt request signal signal, a DTC activation request signal, or the like can be assigned to such an interface signal. For example, once the factor flag is set to "1" and becomes active, the interrupt request signal is held. When the CPU recognizes the interrupt request signal and clears the interrupt factor flag to "0", the interrupt request signal is made inactive. Also, these interface signals are not recognized in one state. When used in only one state period, edge detection is performed on the input side. Note that if the output period at that time is set to a period longer than the longest period of the selectable system clock signal φB, that is, the period of the clock signal φOSC / 8 or more, no handshake is required.
[0110]
The request signal between the bus masters or between the bus slaves can be at any timing.
[0111]
FIG. 23 shows another operation timing of the bus master clock and the bus slave clock. Unlike FIG. 20 and FIG. 22, the clock signal φB has a duty of 50% even in the middle speed mode. The period of the clock signal φB is always equal to or longer than that of the clock signal φS, and the rising edge of the clock signal φB is synchronized with the rising edge of the clock signal φS. The input / output timing of the interface signal between the functional blocks is the same as in FIG. 19, and is as follows in detail. That is, the output of the bus master (bus slave) is permitted in synchronism with the high-level period of φB and φ1B (the high-level period of φS and φ1S) (change of the output signal is permitted). Regarding signal input, the bus master (bus slave) is allowed to input during a period when φB is at a low level and φ2B is at a high level (a period when φS is at a low level and φ2S is at a high level). The input latch timing of the bus master is synchronized with the change of the clock signal φ2B from high level to low level, and the input latch timing of the bus slave is synchronized with the change of the clock signal φ2S from high level to low level. For example, in the figure, an interface signal I / F1 is an interface signal from a bus master to a bus slave. The interface signal I / F1 is output from the bus master in synchronization with φ1B in the state S9, and latched by the bus slave in synchronization with the change of φ2S from the high level to the low level in the state S9. The interface signal I / F2 is an interface signal from the bus slave to the bus master. The interface signal I / F2 is output from the bus slave in synchronization with φ1S of the state S3, and latched by the bus master in synchronization with the change of φ2B from the high level to the low level in the state S4. Therefore, a period of one state or more of the clock signal φS can always be ensured from the start of signal output to capture. Thereby, the timing design can be made similar to the case where the middle speed mode is not considered, that is, the case where φB = φOSC.
[0112]
The point to be noted in the timing of FIG. 23 is that the rising of the clock signal φ2B matches the rising timing of the clock signal φ1S, and at this point, the phases of the clock signals φ2B and φ1S partially match. At the timing when the phases match, a signal is output from the bus slave to the bus master.
[0113]
At this time, if the interface control timing using the clock signal of FIG. 23 is reversed as shown in FIG. 21, the time from the start of signal output to the capture may not be ensured depending on the phase of φB and φS. In some cases, signals cannot be transmitted correctly. For example, when the bus slave outputs a signal in synchronization with the rise of φ2S in state S6 in FIG. 23, the bus master is allowed to latch input data in synchronization with the fall of φ1B in state S7, and Only a half cycle of the clock signal φS can be secured until the input latch of the signal. This is not a problem when there is only one signal, but in the case of a bus having a plurality of signals, among a plurality of signals, an old signal is transmitted and a new signal is transmitted. In some cases, such data may be mixed, and when these combinations make sense, the data may become meaningless data or cause a malfunction.
[0114]
When the clock signal waveform as shown in FIG. 23 is used in the interface specification as shown in FIG. 19, as shown in FIG. 23, the operating clock of the bus master is lower in frequency than the operating clock of the bus slave. Therefore, the interface signal to the bus slave is always recognized by the bus slave in the same state as the output of the bus master. Therefore, the interface signal can have an arbitrary pulse width for each state. A bus access signal such as a read signal or a write signal, an interrupt factor clear signal, or the like can be assigned to such an interface signal.
[0115]
Since the operating clock of the bus slave has a higher frequency than the operating clock of the bus master, the interface signal from the bus slave to the bus master in FIG. 23 is recognized by the bus master after the output of the bus slave (state of the bus slave). Cannot be constant. Therefore, these interface signals are preferably so-called handshake signals. An interrupt request signal signal, a DTC activation request signal, or the like can be assigned to such an interface signal. Note that if the output period at that time is set to a period longer than the longest period of the selectable system clock signal φB, that is, the period of the clock signal φOSC / 8 or more, no handshake is required.
[0116]
Here, the clock signal waveforms of FIGS. 20 and 22 will be further described. As is clear from FIGS. 20 and 22, the high-level period of φ2B is included in the low-level period of φ1S. Therefore, at least a spare time for one state of φS can be secured from the output of the bus slave synchronized with the rise of φ1S to the input signal latch operation of the bus master synchronized with the fall of φ2B. The high-level period of φ2S is included in the low-level period of φ1B. Accordingly, at least a margin of one state of φS can be secured from the output of the bus master synchronized with the rise of φ1B to the input signal latch operation of the bus slave synchronized with the fall of φ2S. These facts hold for both the interface specifications of FIGS. 19 and 21. On the other hand, as shown in FIG. 23, clock signals φ1S, φ2S, φ1B, φ2B, etc. are used in which the phase of the rising change of the clock signal φ2B to the high level coincides with the phase of the rising change of the clock signal φ1S. In this case, only in the bus interface specification (for example, the interface specification in FIG. 19) in which the timing of the phase coincidence is used as the signal output timing from the bus slave to the bus master, the signal φS is set to 1 from the signal output to the input latch of the signal. The extra time for the state can be secured.
[0117]
<< Example of Actual Bus Interface Timing >> FIGS. 24 and 25 show examples of actual bus interface timing. The timings in the figures are based on the use of the clock signals shown in FIGS. 20 and 22. As described above, the interface specifications can be used in exactly the same manner in FIGS. 19 and 21. This is an example in which one of the optimum interface specifications is adopted according to the above. In each figure, an address (via PAB), a functional block signal (MS #), a read signal RD #, and a write signal WR # are provided from a bus master. In FIG. 24, the read operation of the bus master is performed from the state S5. That is, from state S5 to state S16, the address bus and the function block selection signal (MS #) become valid. The read signal RD # becomes active (low level) in synchronization with φ2B in the first state (states S5 to S8) of the bus master. The bus slave detects the transition of the read signal RD # to the active state, and activates the register read signal and the bus interface latch signal inside the bus slave. For example, in FIG. 6, a register 771 or a timer counter 772 is specified by a register read signal, and data is transferred from the specified register or counter to the bus interface 760 via the module data bus and latched. A control signal in the bus slave such as a register read signal is included in, for example, an output control signal of the read / write control circuit 730 in FIG. Then, in synchronization with the next φ2S in state S9, the latched data is output to the data bus. After the read signal RD # is deactivated, the data bus is set to the high impedance state in synchronization with the change of φ1S in the state following the state S16. Read signal RD # is deactivated in synchronization with the rise of φ2B in the third state (states S13 to S16) of the bus master. The bus master latches the contents of the data bus in synchronization with the falling of the clock signal φ2B.
[0118]
In FIG. 25, the write operation of the bus master is performed from the state S5. From state S5 to state S16, the address bus and the function block selection signal (MS #) become valid. Write data is output to the data bus in synchronization with the rise of φ2B in the first state (states S5 to S8) of the bus master. The write signal WR # becomes active (low level) in synchronization with the rise of φ1B in the second state (states S9 to S12) of the bus master. The bus slave detects the transition of the write signal WR # to the active state, and activates the bus interface latch signal and the register write signal. The write data is latched by the bus interface, and the data is transferred from the bus interface to a designated register or a timer counter via the module data bus and written. Such a signal is included in, for example, a control signal output from the read / write control circuit 730 in FIG. The write signal is deactivated in synchronization with the rise of φ2B in the third state (states S13 to S16) of the bus master.
[0119]
<< External Output of Clock Signal φ >> As shown in FIG. 26, the single-chip microcomputer can externally output system clock signals φS and φB. That is, there are a case where the system clock signal φS is used as a reference clock of another semiconductor integrated circuit device and a case where a control signal synchronized with an external bus is generated based on the system clock signal φB. In the present invention, the system clock signal φS can be output to generate a reference clock for another semiconductor integrated circuit device or the like, and the system clock signal φB can be output to generate a control signal synchronized with an external bus. Output terminals TφS and TφB for that purpose are provided independently of each other at a predetermined input / output port IOP. For example, the output of the clock signal φS is assigned to the input / output port IOP60, and the output of the clock signal φB is assigned to the input / output port IOP61. The input / output ports IOP60 and IOP61 are also used for other input / output functions, and are included in the input / output port IOP6 shown in FIG.
[0120]
At this time, the clock signals φS and φB are generated by the clock control circuit 13 and output to the outside via the above-described input / output ports IOP60 and IOP61. The clock signals φS and φB are substantially the highest-speed signals in the semiconductor integrated circuit. Wirings 1310 and 1311 between the clock control circuit 13 and the input / output ports IOP60 and IOP61 extend between the functional blocks and have a relatively large capacitance component. Therefore, when such a clock signal is externally output, current consumption increases due to its relatively large capacitance component and high clock frequency.
[0121]
Since the external output of φS or φB is a necessary operation, it is inevitable to consume current. However, a single-chip microcomputer or the like often does not need to output a clock to the outside. Stopping the clock output is effective in reducing power consumption, coupling noise, and unnecessary radiation, as described in Japanese Patent Application No. 60-184207, for example. To cope with this, in the present embodiment, when the clock signal φS or φB is not output to the outside, the signal between the clock control circuit 13 and the input / output ports IOP60 and IOP61 is set to, for example, the level of the logical value “0”. It is fixed so that no signal change occurs on the clock lines 1310 and 1311 to reduce current consumption. For example, as schematically shown in FIG. 26, a serial circuit of an AND circuit 1300 and a clock driver 1302 is provided for external output of the clock signal φS generated by the clock control circuit 13, and the output of the clock driver 1302 is Connected to input / output port IOP60 via clock wiring. Similarly, a serial circuit of an AND circuit 1301 and a clock driver 1303 is provided for external output of the clock signal φB generated by the clock control circuit 13, and the output of the clock driver 1303 is supplied to the input / output port IOP61 via the clock wiring. Connected. The output of the input / output ports IOP60 and IOP61 is permitted using the corresponding bits DDR60 and DDR61 of the data direction register (not shown) of the corresponding input / output port IOP6. When the bits DDR60 and DDR61 are set to the logical value "1", the IOP60 and IOP61 are in an output enabled state. This can be controlled independently for φS and φB. At this time, the inverted signal of the output permission bit DDR60 is supplied to the other input of the AND circuit 1300, and the inverted signal of the output permission bit DDR61 is supplied to the other input of the AND circuit 1301. Therefore, when the output of the clock signals φS and φB is not permitted to the IOPs 60 and 61, the outputs of the AND circuits 1300 and 1301 are fixed to the low level. Thus, when the clock signals φS and φB are not output to the outside, power consumption in the clock wiring after the clock drivers 1302 and 1303 can be reduced, and further, coupling noise and unnecessary radiation (generation of undesired radio waves) can be reduced. can do.
[0122]
FIG. 27 shows a modification in which either the clock signal φS or φB can be selectively externally output. At this time, the clock control register 132 is provided with PHIS bits shown in FIGS. 28 (A) and (B). As shown in FIG. 28B, when the PHIS bit is a logical value "1", the clock signal φS is instructed to be outputted to the outside, and when the logical value is "0", the clock signal φB is instructed to be outputted to the outside. Is done. The selection of a clock signal to be output is performed by a selector including AND circuits 1304 and 1305 and an OR circuit 1306. The external output of the clock signal selected by this selector is enabled by the output enable bit DDR60 for the input / output port IOP60. The output enable bit is inverted and supplied to the AND circuit 1307 as in the case of FIG. The output clock signal of the selector is supplied from the AND circuit 1307 and the clock driver 1308 to the input / output port IOP61 via the clock wiring only when the output of the clock signal is permitted by the output permission bit DDR60. When the output of the clock signal to the external terminal Tφ is prohibited, the output of the AND circuit 1307 is fixed to the logical value “0” as described above, and as a result, the power consumption of the clock wiring after the clock driver 1308 is reduced. Etc. can be realized.
[0123]
<< Multi-division of Internal Bus >> FIG. 29 shows another example of division of the internal bus of the single-chip microcomputer. FIG. 29 is a block diagram focusing on the internal bus of a single-chip microcomputer. The buffer BUF is a buffer circuit included in the input / output ports IOP1 to IOP5 and interfaced with an external address bus and an external data bus.
[0124]
Internal address bus PAB and internal data bus PDB shown in FIG. 1 are divided into internal address bus PAB1 and internal data bus PDB1 and internal address bus PAB2 and internal data bus PDB2 in FIG. 29, respectively. And I / O ports IOP1 to IOP6, WDT8, and a static latch circuit HD1 are coupled to PDB1. Connected.
[0125]
The internal buses PAB1 and PAB2 and the internal buses PDB1 and PDB2 have the same wiring length, that is, the same wiring capacity, and the total wiring capacity is smaller than the wiring capacity of the internal buses PAB and PDB in the case of FIG. The allocation of the divided internal buses and the circuit modules is determined in accordance with the actual layout of the circuit blocks so that the size of the internal bus does not increase. Logically, there is no restriction on which of the divided buses the input / output port IOP, timer 7, WDT 8, SCI 9, and A / D converter 10 should be connected to.
[0126]
According to the module select determination included in the bus controller 3, one of PAB1 and PDB1 and one of PAB2 and PDB2 is set to an active state. When the ROM 5 or the RAM 6 is accessed, both PAB1 and PDB1 and PAB2 and PDB2 are deactivated. In the inactive state, the internal address buses PAB1 and PAB2 retain the previous value. When the outputs of the bus controller 3 and the functional blocks such as the WDT 8 are set to high impedance, the previous values of the internal data buses PDB1 and PDB2 are held by the static latch circuits HD1 and HD2. Each of the static latch circuits HD1 and HD2 is provided with, for example, two inverter circuits connected in anti-parallel to each signal line, and is configured to hold the state of PDB1 and PDB2. In the case of outputting, it has a relatively small driving ability so that driving of the bus by such output data can be prioritized. That is, the output currents of the inverter circuits constituting the static latch circuits HD1 and HD2 are larger than the leakage currents of the PDB1 and PDB2 and sufficiently smaller than the output currents of the functional blocks. Note that the number of divisions of the internal buses PDB and PAB in FIG. 1 can be three or more. If the number of the internal address buses PAB is small, the internal address buses PAB may be shared and only the internal data bus PDB may be divided.
[0127]
<< Vectorization of Low Power Consumption Information >> As means for forcibly increasing the frequency of the clock signal φB in order to speed up processing for an interrupt request or the like, a clock control register described in FIG. 9A and FIG. In addition to using the 132 MSME bits, low power consumption information may be fetched as a vector at the start of interrupt processing (including exception processing such as reset). In a part of the address space of the CPU 1, a plurality of vectors each corresponding to an interrupt are written in advance. When an interrupt request is generated, the CPU 1 fetches a vector corresponding to the interrupt and performs a process according to the information on the interrupt held in the fetched vector. That is, when an interrupt request occurs, the CPU 1 outputs an address indicating a vector corresponding to the interrupt, and fetches information on the interrupt from a vector area indicated by the address. In this embodiment, this information includes a start address of a program (handler program) to be executed by the interrupt and low power consumption information. In response to the interrupt request, the start address is set in a program counter (not shown) in the CPU 1 for executing the handler program, and the low power consumption information is stored in the module stop signal as described later. It is set in the control register 133 and the clock control register 132. Further, after the processing for the interrupt request is completed, the contents of the status register and the address to be returned are stored in the stack pointer in the CPU 1 when responding to the interrupt request, as described later, in order to return to the original program. The data is written to an address area (stack area) in the address space of the CPU 1 designated by (not shown). As will be understood from the following description, in this embodiment, in addition to the contents of the status register and the return address, the contents of the module stop control register 133 and the clock control register 132 are designated by the stack pointer. It is written (stacked) to the stack area. For example, the interrupt vector has control information for setting the medium speed mode and setting the module stop as low power consumption information together with the start address of the handler to be executed by the interrupt. In this case, the initial value of the clock control register 132 can be determined by the low power consumption information of the reset vector, and it is preferable to set this to the medium speed mode. By doing so, the low power consumption state after the reset can be set immediately, so that the load on the software can be reduced, and the current consumption can be reduced, for example, starting from the medium speed mode is possible.
[0128]
FIGS. 30A to 30C show an example of a vector array designating a low power consumption state and a stack in that case. According to this example, the low power consumption information has 8 bits as shown in FIG. That is, the low power consumption information includes 6 bits (bits 7 and 2 of the low power consumption information) corresponding to bits 7 and 2 (MSTP7 and MSTP2) of the module stop control register 133, and bit 0 and bit 0 of the clock control register 132. 2 (bits 1 and 0 of low power consumption information) corresponding to 1 (CKS0, CKS1). In the vector shown in FIG. 30A, the start address is 24 bits if the address space is 16 MB. As shown in FIG. 30C, in the stack area, in addition to the return address and the low power consumption information used in the return destination, a 16-bit storage area for the status register that holds the internal state of the CPU 1 Is included. The status register includes a condition code indicating the result of the operation, an interrupt mask bit, and the like. In the following description, bits 7 to 2 (MSTP7 to MSTP2) of the module stop control register 133 and bits 0 and 1 (CKS0, CKS1) of the clock control register 132 are combined with a low power consumption state control register. Name.
[0129]
FIG. 31 shows the operation timing at the time of exception processing and at the time of return. Although not particularly limited, the ROM 5 and the RAM 6 can be read / written in one state. Instructions and vectors are arranged in the ROM 5, and the stack area is arranged in the RAM 6. At the time of exception processing, the value of the program counter (PC) at that time and the information of the low power consumption state control registers (CK0 and CK1 of the clock control register 132 and MSTP2 to MSTP7 of the module stop control register 133) and the status register (not shown) Is saved in the stack area (states S1 to S5). That is, the dedicated read signal RD-LPCR # is activated to read the contents of the low power consumption state control register (states S2 to S4), and the write signal WR # is also activated. Is written to the stack area. Following the operation of the stack, the contents of the low power consumption state control register and the PC are read from the ROM 5 as a vector (S6 to S9). The low power consumption state control register read from the ROM 5 is not taken in by the CPU, but is written into the low power consumption state control register (S6 to S8). The dedicated write signal WR-LPCR # for this is activated. As a result, the contents of the low power consumption control register are changed from the state S7, and the setting of the medium speed mode and the setting of the module stop are changed. The start address as a vector is taken into a program counter (not shown) inside the CPU, and the CPU 1 starts executing the instruction from the start address (S11 to S13).
[0130]
At the time of return, the contents of the status register, the low power consumption state control register, and the PC are read from the stack area in the RAM 6 (S14 to S18). The contents of the low power consumption state control register read from the stack area are not taken in by the CPU 1 but written into the low power consumption state control register. The return address is taken into the CPU 1, and the CPU 1 starts executing the instruction from the address. The status register is stored inside the CPU 1. From S16, the contents of the low power consumption control register are restored. The setting of the medium speed mode and the setting of the module stop are restored, and the state becomes the same as the state before S6. If the medium speed mode is set before S6 and after S16, and the high speed mode is set from S7 to S15, the same operation as in FIG. 17 can be realized without load of software. Since a low power consumption state can be set for each interrupt, an appropriate operation speed is set for an interrupt request that does not require high-speed processing, so that power consumption is not wasted. In addition, since the function block can be stopped while holding the internal state of the function block by the module stop, for example, if the DTC 2 is set as the module stop, it is possible to prevent the DTC 2 from using the bus to interrupt the operation of the CPU 1. This is effective when it is necessary to execute a high-speed interrupt processing routine.
[0131]
FIG. 32 representatively shows a 1-bit configuration of the low power consumption control register. As described above, bits 1 and 0 of the clock control register 132 and bits 7 and 2 of the module stop control register 133 constitute a low power consumption control register. In the configuration of FIG. 32, two OR circuits 1325 and 1326 are added to FIG. 16, and the dedicated write signal WR-LPCR is applied to the clock input terminal C via the OR circuit 1325. The contents of the data bus are input regardless of the address. Also, the read signal of the clocked buffer 1322 is supplied with the dedicated read signal RD-LPCR via the OR circuit 1326, and the contents of the register are output to the data bus regardless of the address. The dedicated write signal WR-LPCR and the dedicated read signal RD-LPCR are formed by, for example, the CPU 1 and have a signal common to bits 1 and 0 of the clock control register 132 and bits 7 and 2 of the module stop control register 133. Is done. In FIG. 32, the signals RD, WR, RD-LPCR, and WR-LPCR are shown as positive logic signals to facilitate understanding.
[0132]
<< Example of Sub Clock Oscillator >> FIG. 33 shows another example of the clock oscillator and the clock control circuit. In this example, a second oscillator 12A, a frequency divider 130A, a selector 131A, and a no overlap generating circuit 138 are added to FIG. For example, a crystal oscillator such as 32.768 kHz is connected to EXTALL and XTALL of the second oscillator 12A. As a single-chip microcomputer having two sets of oscillators, for example, there is one described in “H8 / 3834 HD6473834 HD6433834 Hardware Manual” issued by Hitachi, Ltd., September, 1992. The second frequency divider 130A performs frequency division in the same manner as described above, and the frequency-divided clock signals φOSC / 2, φOSC / 4, and φOSC / 8 are selected by the selector 131A based on control bits from the clock control register 132. . Based on the selected clock signal, the no-overlap generation circuit 138 generates two-phase no-overlap clock clock signals φ1L and φ2L, and supplies them to required functional blocks, for example, the CPU 1 and the timer 7. The no-overlap generation circuit 138 is different from the one built in each of the functional blocks so as to be compatible with a low operation frequency and a low voltage operation. Because of the low frequency, even if the two-phase clock signals φL1 and φL2 are supplied to the CPU 1, the timer 7, and the like, there is no disadvantage in power consumption.
[0133]
Although not particularly limited, the two-phase no-overlap clock signals φ1L and φ2L are used when a single-chip microcomputer is used for clock processing. The clock control register 132 has a watch mode bit WM. When this is set to a logical value "1", the single-chip microcomputer operates at the lowest operating frequency required for clock processing. The clock process is a process of updating the clock display at regular time intervals, such as every second, when the clock is included in the control target of the single-chip microcomputer. The CPU 1 causes the CPU 1 to execute a clock process by a timer interrupt performed at regular time intervals by a timer clocked by the clock signals φ1L and φ2L.
[0134]
FIG. 34 is a schematic block diagram of a single-chip microcomputer exclusively showing a mode of supplying the clock signals φ1L and φ2L from the clock control circuit 13 of FIG. 33 to other functional blocks. This block diagram considers, for example, the clock processing. In the single-chip microcomputer of FIG. 34, in addition to the clock control circuit 13 of FIG. 33, a CPU 1, a bus controller 3, an interrupt controller 4, input / output ports IOP1 to IOP11, and a timer 7 are representatively shown. NOV shown in each circuit block is a no-overlap generation circuit that forms a no-overlap two-phase clock signal from an input clock signal. The clock signal φB is supplied to the CPU 1, the bus controller 3, and the no-overlap generation circuit NOV of the interrupt controller 4 coupled to the internal buses IAB and IDB described in FIG. 1, and the internal buses PAB and PDB described in FIG. The clock signal φS is supplied to a timer 7 and a no-overlap generating circuit NOV of IOP1 to IOP11. Further, the above-mentioned no-overlapping two-phase clock signals φL1 and φL2 are supplied to the respective functional blocks 1, 3, 4, 7, and IOP1 to IOP11, and output from the no-overlap generating circuit NOV in the respective functional blocks. A selector SEL for selecting which of the two-phase clock signal or the two-phase clock signals φL1 and φL2 is used as the internal synchronization clock signal is provided. The selector of the timer 7 is selected according to a control bit of an internal control register set by the CPU 1 or the like. When the timer 7 includes a plurality of channels, the control register and the selector SEL may be provided for each channel. The selection state of the CPU 1, the bus controller 3, the interrupt controller 4, and the selector SEL of the input / output ports IOP1 to IOP11 is determined by a watch mode bit WM output from the clock control circuit 13.
[0135]
When the watch mode bit is set to the logical value "1", the timer 7 is set to a module stop state except for a predetermined channel. The predetermined channel of the timer 7 selects the clock signals φL1 and φL2 by the selector SEL using the control bit, and performs a clocking operation for intermittently performing a clock process using the clock signals φL1 and φL2 for a predetermined time. The timer interrupt signal is output every time. In the CPU 1, the bus controller 3, the interrupt controller 4, and the IOP1 to IOP11, the clock signals φL1 and φL2 are selected by the selectors based on the watch mode bit WM having the logical value “1”, so that these functional blocks have the low frequency for the clock. Clock signals φL1 and φL2. The timer 7 generates an interrupt signal for clock processing at regular intervals, and the CPU 1 intermittently performs clock processing in response thereto. When the watch mode bit WM is activated, the first oscillator 12 stops oscillating. The watch mode is released by the CPU 1 setting the watch mode bit WM to the logical value “0”.
[0136]
According to the above embodiment, the following effects can be obtained. [1] The system clock signals are φS and φB, and the dividing ratio of the system clock signal φB is made variable without increasing the total wiring capacitance of the clock signal wiring so much to secure the absolute reference clock of the functional block. In addition, the power consumption of the bus master can be reduced by changing the system clock signal φB, and the power consumption of the entire semiconductor integrated circuit can be reduced. By reducing power consumption, unnecessary radiation (the generation of undesired radio waves) can be reduced.
[0137]
[2] Since the constant frequency system clock signal φS is supplied to peripheral circuits such as the SCI and the timer, even if the frequency of the system clock signal φB to the CPU or the like is changed, the SCI bit rate or baud rate and the timer The clock cycle of the above can be kept constant, and even if the operating frequency of the CPU or the like is changed, it is not necessary to change the settings of those peripheral function blocks.
[0138]
[3] The clock control circuit 13 includes the register means 132 in which information for selecting the frequency division ratio of the system clock signal φB can be set by the bus master. Can be arbitrarily selected.
[0139]
[4] The data bus is supplied with an internal data bus IDB supplied with a system clock signal φB and connected to a functional block such as a CPU, and an internal data bus connected with a functional block supplied with a system clock signal φS and operated as a bus slave. It is separated into a bus PDB. By connecting a function block that frequently starts a bus cycle, such as a bus master such as a CPU, to a data bus different from the bus slave, the load on the frequently accessed data bus is reduced, contributing to low power consumption. I do. Also, it can contribute to speeding up. By holding the previous value of the data bus, which is relatively infrequently used for access, by the hold circuits HD1 and HD2, the number of times of charging and discharging on the data bus can be reduced to contribute to low power consumption. .
[0140]
[5] By supplying system clock signals φS and φB as one-phase clock signals to the function blocks and generating a two-phase clock signal inside each function block, the total wiring capacity of the clock signal wiring can be reduced. Power consumption can be reduced.
[0141]
[6] When a prescaler clock signal is used, a prescaler clock signal with a low frequency division ratio is internally generated for each functional block, and a prescaler clock signal with a large frequency division ratio is generated in common, thereby greatly increasing the logic scale. By not using a signal having a large signal change frequency as a signal between functional blocks, power consumption can be reduced.
[0142]
[7] The inter-function block signal from the bus slave to the bus master is synchronized with φ1S as described with reference to FIGS. 20 and 23, for example, to facilitate the interface.
[0143]
[8] By making it possible to hold the internal state of the functional block and limiting the portion to which the clock is always supplied, it is possible to limit signal changes even during operation and reduce power consumption. Further, even if the clock is stopped, by maintaining the internal state, the burden of resetting by software can be reduced.
[0144]
[9] Divide the internal bus including the data bus, divide the capacity, and suppress the signal change for the inactive bus, so that the signal that changes in one operation is charged / discharged. The required capacity can be reduced, and the power consumption can be reduced.
[0145]
[10] An event detection circuit, such as an interrupt controller, for detecting information on an interrupt or a change in a signal at an external terminal is provided. When an event occurs, the frequency division ratio of φB is automatically changed. By changing the state of the module stop or the like, it is possible to reduce the time from when an event occurs to when a desired process is performed, thereby improving the processing performance. At the time of the change, the information before the change is saved in, for example, a stack area, and the new information is loaded together with, for example, a vector, so that an arbitrary setting can be performed.
[0146]
[11] By making it possible to output clock signals corresponding to the clock signals φS and φB to the outside and to prohibit the output by software, the clock signal φS can be used as a reference clock of the external semiconductor integrated circuit, φB can be used as a control signal of the bus control circuit. In addition, if unnecessary, output is prohibited, so that power consumption, coupling noise, and unnecessary radiation can be reduced.
[0147]
Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it is needless to say that various modifications can be made without departing from the gist of the invention.
[0148]
For example, the case where the clock signal is made asymmetric is not limited to the above embodiment. In any case where operation is unnecessary, one can be stopped at a high level and the other at a low level. For example, it can be applied to a case where the CPU is in a wait state. If all the timing circuits are of a static type, the clock signal does not become asymmetric, and φB in the middle speed mode can be a clock signal with a duty ratio of 50%.
[0149]
The clock control register may be readable / writable from the CPU, or may be changeable by setting an external terminal. For example, the initial setting value of the clock control register may be changed by inputting a predetermined terminal. When a predetermined terminal is reset at a low level, it operates with a high-speed clock, and then operates at a low speed with the setting of the CPU. When the predetermined terminal is reset at a high level, it operates with a low-speed clock, and then at a setting of the CPU. To enable high-speed operation.
[0150]
The details of the bus timing can be variously changed. Although the timings of IAB / IDB and PAB / PDB are the same, they may be shifted. The event may include, for example, an external bus release. When the bus is released to the outside, the bus master can automatically enter the medium speed mode, or the DTC can be set to the module stop state. The low power consumption information provided as a vector is not limited to 8 bits. Any number of bits can be used. A plurality of sets of dedicated read signals and dedicated write signals may be provided.
[0151]
The configuration of the low power consumption control register can be variously changed. The specific circuit configurations of the dynamic circuit and the static circuit can be variously changed. For example, the static circuit can be configured by a flip-flop. Further, the clock is not limited to two-phase no overlap. Three or more phases or an overlap clock can be used. The clocks of some phases may be made longer and the clocks of the other phases may be made shorter.
[0152]
Although a case has been described where a DTC is incorporated as a data transfer device, this may be a DMA controller (DMAC). DTC in the embodiment may be read as DMAC. These need not be functional blocks independent of the CPU, and may be realized as a part of the CPU. In this case, a name such as micro DMA, macro service, or intelligent I / O service may be used. The other functional blocks of the single-chip microcomputer are not restricted at all. The number of functional blocks and the method of specifying a module stop can also be set arbitrarily.
[0153]
In the above description, the case where the invention made by the inventor is mainly applied to a single-chip microcomputer as a background of application has been described. However, the present invention is not limited to this, and it is applicable to other semiconductor integrated circuits. The present invention is applicable, and at least the present invention can be applied to a semiconductor integrated circuit included in a system that operates in synchronization with a clock.
[0154]
【The invention's effect】
The following is a brief description of an effect obtained by a representative one of the inventions disclosed in the present application.
[0155]
[1] A second system clock signal (φS) having a constant frequency is supplied in common to a plurality of functional blocks, a frequency division ratio is selectable, and a frequency is set to be equal to or lower than the second system clock signal. By supplying the system clock signal (φB) to a predetermined functional block, the operating frequency is changed according to the state of the functional block to which the first system clock signal (φB) is supplied, thereby achieving low power consumption. Can be. At this time, even if the frequency of the first system clock signal is changed, the operating speeds of the plurality of functional blocks operated in response to the second system clock signal (φS) are not changed. In controlling power consumption by changing the frequency of the system clock signal, there is no processing for resetting the operating conditions for a plurality of functional blocks that are operated in response to the second system clock signal (φS). No need.
[0156]
[2] The function block to which the first system clock signal is supplied via the first clock signal wiring is a bus master, so that the bus master is supplied with a system clock signal having a variable frequency division ratio. Become. In a data processor such as a microcomputer, a CPU as a bus master generally frequently starts a bus cycle for fetching instructions and data, which is effective in reducing power consumption.
[0157]
[3] By making the function block to which the second system clock signal is supplied via the second clock signal wiring a bus slave, even if the frequency of the system clock signal of the bus master is changed, the serial communication interface The bit rate or baud rate, the time period of the timer, and the like can be kept constant, and the setting change of these peripheral function blocks can be eliminated.
[0158]
[4] By adopting the register means (132) in which the information for selecting the division ratio of the first clock signal (φB) can be set by the bus master, the division ratio can be determined by the bus master such as the CPU. The choice can be made arbitrarily.
[0159]
[5] By connecting a function block that frequently starts a bus cycle like a bus master such as a CPU to a data bus different from a bus slave, the load on a frequently accessed data bus is reduced. In this regard, low power consumption is achieved. By holding (previous value holding) the previous value of the data bus that is relatively infrequently used for access by the hold circuit, the number of times of charging and discharging on the data bus is reduced, thereby contributing to low power consumption. .
[0160]
[6] The two-phase no-overlap clock signals generated based on the first and second system clock signals are partially made to coincide in phase, and synchronized with the timing when the phases coincide, Changing a signal to be supplied from a function block operated in synchronization with the second system clock signal to a function block operated in synchronization with the first system clock signal (a function block whose operation speed can be relatively slowed down). This facilitates the interface between the functional blocks having different system clock signal frequencies, in other words, the timing design for the interface can be facilitated.
[0161]
[7] The first-phase clock signals of the two non-overlapping two-phase clock signals generated based on the first and second system clock signals have phases in which the low-level periods coincide. Since the second-phase clock signals have phases in which the high-level periods are matched, the output and input of each functional block can be synchronized with either the first-phase or the second-phase clock signal. A period of one cycle or more of the second system clock signal (φS) can be secured between the function blocks having different system clock signals from the data output to inputting and latching the data. In other words, the interface between the functional blocks different from the above can be simplified, in other words, the timing design for the interface can be facilitated.
[0162]
[8] When the output from the output circuit that selectively outputs the first system clock signal (φB) and the second system clock signal (φS) to the outside is set to the non-selection state, the clock of the output circuit is output. By forcing the input wiring to a predetermined level, when external output of the system clock signal is not required, charging and discharging of the clock input wiring can be suppressed, thereby contributing to low power consumption.
[0163]
[9] By individually suppressing the generation of an internal clock signal or the like for each functional block, the change of the internal clock signal is stopped in the unused internal function block, and the power due to the charge / discharge current due to the useless change of the clock signal. Consumption can be reduced. At this time, by maintaining the internal state when the internal clock signal is stopped, it is possible to save the trouble of setting the internal circuit again when the operation restart is selected.
[0164]
[10] Low power consumption can be realized by suppressing the generation of the internal timing signal by making the own operation unselected. By maintaining the internal state when the change of the internal timing signal is stopped, it is possible to save the trouble of resetting the internal circuit when restarting the operation.
[0165]
[11] A circuit that is operated in response to a no-overlap two-phase internal timing signal is connected in series to a dynamic circuit that is dynamically operated in response to the first-phase timing signal and to the dynamic circuit And a static circuit that is statically operated in response to the timing signal of the second phase. Is supplied to the static circuit, even if the information holding time due to the output load capacitance of the dynamic circuit is finite, the period in which the dynamic circuit should hold the information is shortened, and the first system clock The range in which the frequency of the signal can be reduced can be widened. Further, the physical scale of the circuit can be reduced as compared with the case where both are configured by static latch circuits.
[0166]
[12] The selection state of the system clock signal frequency when a predetermined event occurs by forcing the frequency of the first system clock signal based on the event detection even if the set system clock signal frequency is low. Can be forced to a predetermined state, for example, the highest frequency selection state, so that the time required for performing a desired process in response to a predetermined event can be reduced.
[0167]
[13] The process of forcing the system clock signal to a specific frequency can be simplified by forcing the system clock signal frequency by rewriting a predetermined storage area (MSME) to a predetermined value upon occurrence of an event.
[0168]
[14] When returning from the exceptional processing requested by the central processing unit due to the occurrence of an event, the central processing unit returns the storage area (MSME) to a predetermined value, thereby storing information for selectively designating a frequency. It is not necessary to save and restore the values of the areas (CKS1, CKS2) themselves.
[0169]
[15] When the functional block that receives the system clock signal whose frequency is forcibly is a data transfer controller other than the central processing unit, the data transfer controller that has requested the exceptional processing due to the occurrence of the event ends the exceptional processing. Is output, thereby returning the storage area (MSME) to a predetermined value, thereby restoring the system clock signal without burdening the central processing unit or software.
[0170]
[16] A register means (133) for rewritably holding information for inhibiting the formation of the internal clock signal in units of functional blocks is provided, and the register means is controlled by the internal clock signal based on occurrence of a predetermined event such as reset. By initializing to a state in which the formation of is formed, power consumption in an initial state when a predetermined event such as a reset occurs can be reduced.
[0171]
[17] By using control information paired with a vector such as an interrupt vector to force the frequency of a system clock signal, low power consumption can be finely set according to the type of event.
[0172]
[18] When using the control information of a pair with a vector such as the above-mentioned interrupt vector, when an event occurs, the current information for low power consumption control is saved by the control information of the pair with the vector so as not to be lost. After the exceptional processing requested by the occurrence of the event, the power control state can be returned to the state immediately before the occurrence of the event.
[0173]
[19] A prescaler clock signal with a low frequency division ratio that can be generated by the prescaler is not supplied from the prescaler, but is generated individually by the frequency divider in the functional block, so that a clock signal with a low frequency division ratio can also be generated from the prescaler. Power consumption can be reduced as compared with the case where the power is directly supplied to a plurality of functional blocks.
[Brief description of the drawings]
FIG. 1 is a block diagram of a single-chip microcomputer as one embodiment of a semiconductor integrated circuit according to the present invention.
FIG. 2 is a block diagram showing a modification of the single-chip microcomputer of FIG.
FIG. 3A shows an example of the configuration of a typical logic circuit of each functional block, and FIG. 3B shows an example of a sequential circuit formed of a CMOS dynamic circuit, which is used in the single-chip microcomputer of this embodiment. FIG. 4 is an explanatory diagram showing an example of the CMOS dynamic circuit shown in FIG.
FIG. 4 is a block diagram illustrating an example of a prescaler.
FIG. 5 is an explanatory diagram showing operation timings of an example of the prescaler by (A) to (I).
FIG. 6 is a block diagram illustrating an example of a PWM timer.
FIG. 7 illustrates an example of a no-overlap generation circuit by (A), an example of a clock control circuit by (B), and an example of a no-overlap generation circuit employed in the WDT by (C). FIG.
FIG. 8 is an operation timing chart of an example of the PWM timer of FIG. 6;
9 is a block diagram showing an example of a clock oscillator and a clock control circuit of the single-chip microcomputer shown in FIG.
10A is an explanatory diagram illustrating an example of a clock signal selection mode based on logical values of an MSME bit, a CKS1 bit, and a CKS0 bit, and FIG.
11A and 11B are explanatory diagrams showing examples of a register configuration of a module stop control register for controlling a module stop mode and a register configuration of a clock control register for controlling a medium speed mode.
FIG. 12 is an explanatory diagram showing MSTP7 to MSTP5 in the module stop control register by (A) to (C).
FIG. 13 is an explanatory diagram showing MSTP4 to MSTP3 in the module stop control register by (A) and (B).
FIG. 14 is an explanatory diagram showing a clock control register by (A) to (C).
FIG. 15 is a schematic operation flowchart focusing on a system clock signal in the single-chip microcomputer of the present embodiment.
FIG. 16 is a block diagram showing a schematic example of an MSME bit.
FIG. 17 is an example operation timing chart when an interrupt request occurs.
FIG. 18 is an example operation timing chart when a DTC activation request occurs.
FIG. 19 is a schematic explanatory diagram of a first interface specification between a bus master and a bus slave.
FIG. 20 is a timing chart of an example of a bus master clock and a bus slave clock according to FIG. 19;
FIG. 21 is a schematic explanatory diagram of a second interface specification between a bus master and a bus slave.
FIG. 22 is a timing chart of an example of a bus master clock and a bus slave clock according to FIG. 21;
FIG. 23 is another operation timing chart of the bus master clock and the bus slave clock.
FIG. 24 is a timing chart of an example of a bus interface in a read operation for a bus slave.
FIG. 25 is a timing chart of an example of a bus interface in a write operation for a bus slave.
FIG. 26 is an explanatory diagram of an example of a configuration for selectively enabling external output of clock signals φS and φB.
FIG. 27 is an explanatory diagram of an example of a configuration in which either one of clock signals φS or φB can be selectively externally output;
28 is an explanatory diagram showing PHIS bits required for the configuration of FIG. 27 by (A) and (B).
FIG. 29 is a schematic block diagram showing another example of division of the internal bus of the single-chip microcomputer.
FIG. 30 is a diagram illustrating an example of a vector array specifying a low power consumption state and a stack in that case;
FIG. 31 is an example of an operation timing chart at the time of exception processing and at the time of return in an embodiment in which low power consumption information is arranged in a vector.
FIG. 32 is an example block diagram representatively showing a configuration of one bit of a low power consumption control register.
FIG. 33 is a block diagram showing another example of the clock oscillator and the clock control circuit.
34 is a schematic block diagram of a single-chip microcomputer exclusively showing a mode of supplying clock signals φ1L and φ2L from the clock control circuit of FIG. 33 to other functional blocks.
[Explanation of symbols]
1 Central processing unit (CPU)
2 Data transfer controller (DTC)
3 Bus controller
4 Interrupt controller
5 ROM
6 RAM
7 Timer (PWM timer)
700 No overlap generation circuit
710 Clock control circuit
720 divider
8 Watchdog timer (WDT)
9 Serial Communication Interface (SCI))
10 Analog / Digital (A / D) converter
12 Clock oscillator
13 Clock control circuit
130 divider
131 Selector
132 Clock control register
1325 DTC transfer end signal
133 Module stop control register
1300,1301,1307 AND gate
1310, 1311 Wiring for external output of system clock signal
14 Prescaler
IOP60, IOP61 I / O port
IDB, IAB Internal bus
PDB, PAB Internal bus
φOSC clock signal
φS, φB system clock signal
L1, L2 clock signal wiring
φ1S, φ2S No overlap two phase clock signal
φ1B, φ2B No overlap two phase clock signal
φ1-PWM, φ2-PWM No overlap two-phase timing signal
MSTP module stop signal
MSTPPSC Prescaler module stop signal

Claims (8)

A first functional block that executes exception processing and other processing in synchronization with the first system clock signal;
An event detection circuit for detecting occurrence of an event and outputting a request signal requesting execution of exception processing to the first functional block;
A second functional block for generating the above event;
A control circuit for changing the frequency of the first system clock signal, the control circuit changing the first system clock signal to a predetermined frequency in response to the request signal. Semiconductor integrated circuit. In claim 1,
The control circuit includes:
First register means having a first storage area and a second storage area;
Receiving a plurality of clock signals of different frequencies including the predetermined frequency and outputting the clock signal of the predetermined frequency as the first system clock signal when the first storage area is in the first state. When the first storage area is in the second state, one of the plurality of clock signals is output as the first system clock signal in accordance with the information held in the second storage area. A semiconductor integrated circuit comprising a selector. In claim 2,
The semiconductor integrated circuit according to claim 1, wherein the first functional block includes a central processing unit that enables the first storage area to be set to the second state when returning from the exception processing. In claim 3,
The first functional block includes a data transfer controller that outputs a termination signal in response to termination of the exception processing, wherein the termination signal sets the first storage area to the second state. Semiconductor integrated circuit. A central processing unit that fetches information from a vector area in a memory corresponding to the exception processing and operates according to a first system clock signal to respond to the exception processing request;
An event detection circuit that detects the occurrence of an event and outputs a request for exception processing to the central processing unit;
First register means for holding information designating the frequency of the first system clock signal;
A peripheral circuit having a clock signal forming circuit for receiving the second system clock signal and forming an internal clock signal, and operating in accordance with the formed internal clock signal;
Second register means for holding information for controlling formation of an internal clock signal by a clock signal forming circuit in the peripheral circuit,
The information to be set in the first register means and the second register means is held in an area in the memory corresponding to the vector area, and the information is stored in the first register when the exception processing is requested. And a second register means. In claim 5,
The central processing unit saves the information held in the first register means and the second register means to a stack area of the memory before executing the exception processing,
After the completion of the exception processing, the information is taken out from the area in the memory corresponding to the vector area, and is set in the first register means and the second register means. . A CPU that operates according to a first clock signal and performs a first process and an exception process;
An event detection circuit for generating a request signal for requesting the CPU to execute exception processing by detecting an event;
A plurality of peripheral modules each operating in accordance with a second clock signal commonly supplied to each;
A clock control circuit for receiving a predetermined clock signal,
The clock control circuit, in response to control information in a register, variably divides the predetermined clock signal to generate the first clock signal having a variable frequency,
The clock control circuit generates the second clock signal having one frequency based on the predetermined clock signal,
The frequency of the first clock signal is variable, the frequency of the second clock signal is not variable,
Further, the clock control circuit has a control circuit for changing a frequency of the first clock signal in response to a request signal generated by the event detection circuit. In claim 7,
The first clock signal has a first frequency when the CPU is executing the first process;
In response to the detection of the event, the control information in the register is changed to control information for the detected event,
The first clock signal has a second frequency during the exception processing;
In response to the completion of the exception processing, the control information is re-stored in the register,
The semiconductor integrated circuit according to claim 1, wherein the one clock signal has the first frequency after completion of the exception processing.

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