JP2004080020A - Method for forming a ferroelectric semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory having a small thermal budget and durable electrodes.
A low stress, smooth iridium is formed on a semiconductor structure, and a low stress, smooth, pure phase iridium oxide is formed on the low stress, smooth iridium. A method for forming a ferroelectric semiconductor device 10, comprising a step 54 and a step 56 of forming a ferroelectric material on the iridium oxide. I will provide a.
[Selection] Fig. 6

Description

The present invention relates to ferroelectric semiconductor devices, and more particularly, to electrodes used with ferroelectric materials.

In the course of the development of the electronics industry, new technologies are being developed according to several trends. First, products that are smaller and do not require frequent battery replacement, such as mobile phones, personal audio systems, and digital cameras, are desired. Second, these products are smaller and more portable. , Larger computing power and larger storage capacity are required. Third, these devices are expected to retain information and images without loss of battery even after battery exhaustion.

Such products use non-volatile memories such as electrically erasable programmable read only memories (EEPROMs) and flash EEPROMs because these memories can hold data without power supply. These memories include a memory cell array, and each memory cell includes a memory cell capacitor and a memory cell access transistor.

製品 Non-volatile memories such as FRAM (ferroelectric random access memory), EEPROM and flash EEPROM are used in such products because these memories can hold data without supplying power. These memories include a memory cell array, and each memory cell includes a memory cell capacitor and a memory cell access transistor.

Basically, memory cells use capacitors to hold charge. The ability to retain this charge is called "capacitance," and the capacitance of a given capacitor is determined by the dielectric constant of the capacitor dielectric, the effective area of the capacitor electrode, and the thickness of the capacitor dielectric layer. Is a function of In principle, if the thickness of the dielectric layer is reduced, the effective area of the capacitor electrode is increased, and the dielectric constant of the capacitor dielectric is increased, the capacitance can be increased. From a viewpoint, it is desirable to be thin and have a large capacity.

However, reducing the thickness of the dielectric layer of the capacitor to less than 100 ° typically results in holes through the thin dielectric layer due to Fowler-Nordheim hot electron injection. As a result, the reliability of the capacitor decreases.

(4) Increasing the effective area of the capacitor electrode usually complicates the structure of the capacitor and increases the cost. For example, a three-dimensional capacitor structure such as a stack type or a trench type is employed in a 4 MB DRAM, but it is difficult to apply these structures to a 16 MB or 64 MB DRAM. In other words, in the case of a stacked capacitor, the step becomes relatively steep due to the height of the stacked capacitor on the memory cell transistor, and in the case of a trench capacitor, the size is reduced to the size required for a 64 MB DRAM. Then, a leakage current occurs between the trenches.

In order to increase the dielectric constant of the capacitor dielectric, it is necessary to use a material having a relatively large dielectric constant. At present, silicon dioxide (SiO ₂ ) having a dielectric constant of about 10 is used, but the dielectric constant of yttria (Y ₂ O ₃ ), tantalum pentoxide (Ta ₂ O ₅ ), titanium dioxide (TiO ₂ ), etc. Larger materials have also been tried.

Recently, perovskite oxides having even higher dielectric constants of hundreds to thousands have been studied. Examples of the perovskite oxide has such _{PZT (PbZr X Ti (1-} X) O 3) or _{BST (Ba X Sr (1-} X) TiO 3) and STO (SrTiO _3), strongly use these A new family of memory called dielectric random access memory (FeRAM) has been provided. Ferroelectric materials exhibit a spontaneous polarization phenomenon that results in excellent charge retention and improved non-volatility. The use of a ferroelectric material as the dielectric layer of the capacitor can provide a dielectric equivalent to a 10 ° oxide layer with a thickness of several hundred Angstroms.

Ferroelectric memories are not only nonvolatile, but also have the advantage that they are much easier to combine with logic circuits than existing memories such as flash, static random access memory (SRAM), or DRAM. are doing. Thus, this technique combines the non-volatility of flash with the ease of cell size and scaling of DRAM.

At this time, there are many different ferroelectric materials, and a huge number of different combinations of ferroelectric materials are being studied, many of which are at a standstill.

Ferroelectric two main rival memory (contender) is _{SBT (SrBi 2 Ta 2 O 9} ) and _{PZT (PbZr X Ti (1-} X) O 3).

An advantage of using SBT is that a noble metal electrode such as platinum having high corrosion resistance can be used. However, on the other hand, it has the disadvantage that a high temperature deposition process above 650 ° C. is required. Standard logic circuits associated with ferroelectric memories have a maximum overall allowable temperature limit (ie, thermal budget) that can be applied during manufacturing, and the high temperature deposition process Due to the consumption of this thermal budget, it is difficult to integrate the SBT process into a standard silicon semiconductor process.

An advantage of using PZT is that the deposition can be performed at low temperatures of 400-450 ° C. However, there is a disadvantage that a platinum electrode cannot be used due to reliability problems such as imprint and fatigue.

Therefore, obtaining a ferroelectric memory having a small thermal budget and durable electrodes is a major problem in the prior art.

As a further major challenge, ferroelectric materials must also be very thin in order to be compatible with the voltages used in current CMOS semiconductor technology, and ferroelectric materials must be of very high quality. It is extremely important that there is a very smooth surface and no pinhole defects. In order to achieve these properties, the durable electrode described above must have a very smooth surface for subsequent deposition of ferroelectric material.

Although solutions to these problems have been sought for many years, those skilled in the art have not been able to avoid them.

The present invention provides a method for forming a ferroelectric semiconductor device. Smooth low-stress iridium is formed on a semiconductor structure (semiconductor substrate). An iridium oxide having a low stress, smooth, and pure phase structure is deposited on the iridium to form a ferroelectric material on the iridium oxide. According to this method of forming a semiconductor device using iridium and iridium oxide, a ferroelectric material having a durable electrode, very high quality, uniform material thickness, and a small thermal budget is used. Memory is provided.

実 施 Some embodiments of the present invention have other advantages in addition to or in place of those mentioned above. These advantages will become apparent to those skilled in the art by reference to the following detailed description when taken in conjunction with the accompanying drawings.

Referring now to FIG. 1, there is shown a cross-sectional view of a three-dimensional ferroelectric memory integrated circuit 10 according to the present invention. It will be appreciated that the invention is equally applicable to two-dimensional ferroelectric memory integrated circuits (not shown).

The semiconductor substrate 12 has a shallow trench insulating oxide layer 14, gate and gate dielectrics 16 and 18, and source / drain regions 20-22. A bit line 24 is formed in an interlayer dielectric (hereinafter referred to as “ILD”) layer 26 in contact with one source / drain region 21, and buried contacts 28 and 30 form the ILD layer 26. It is formed through and in contact with the source / drain regions 20 and 22, respectively.

Lower electrodes 32 and 34 are formed in contact with embedded contacts 28 and 30, respectively. Prior to depositing these lower electrodes 32 and 34, a diffusion barrier (typically aluminum titanium nitride (TiAlN)) (not shown) is provided to prevent interaction between buried contacts 28 and 30 and the ferroelectric capacitor. accumulate. A ferroelectric layer 36 is deposited over the buried contacts 28 and 30. Then, an upper electrode 38 is deposited on the ferroelectric layer 36. The lower electrode 32 and the upper electrode 38 will be described later in more detail.

Basically, the gate and gate dielectrics 16 and 18 and the source / drain regions 20 to 22 form the semiconductor transistor of the ferroelectric memory integrated circuit 10, and the lower electrodes 32 and 34, the ferroelectric layer 36 The upper electrode 38 forms the memory capacitors 40 and 42.

The lower electrodes 32 and 34 and the upper electrode 38 are formed of a noble metal or a compound of iridium (Ir). On the other hand, the dielectric layer 36 is made of a material such as bismuth strontium tantalate (SBT) having a chemical formula of SrBi ₂ Ta ₂ O ₉ or lead zirconate titanate (PZT) having a chemical formula of PbZr _x Ti _(1-X) O _3. Can be formed.

Referring now to FIG. 2, there is shown an enlarged cross-sectional view of the memory capacitor 40 in an intermediate stage of fabrication according to the present invention, showing the lower electrode 32 deposited in place.

下部 Conventionally, the lower electrode 32 and the upper electrode 38 are made of platinum. However, experiments have shown that in the case of platinum, oxygen diffuses through the grain boundaries into the lower semiconductor transistor (shown in FIG. 1) and oxidation occurs in undesirable regions of the semiconductor transistor.

By the time iridium is used as the lower electrode 32 and can be used as a diffusion barrier, it has also been found that iridium slows down the diffusion of this oxygen.

Iridium can be deposited by, for example, physical vapor deposition (hereinafter referred to as “PVD”) 43 such as sputtering. However, when iridium is integrated into a ferroelectric material to form a practical device, stress will play a significant role and sputtering will result in the deposition of high stress thin films. .

応 力 It has been found that stress can be minimized while maintaining a sufficiently small thermal budget so that it can be incorporated into semiconductor processes. Here, the heater temperature for sputtering in this case is in the range of 200 ° C. to 550 ° C., preferably 550 ° C.

Sputter deposition of iridium at a heater temperature of 550 ° C. deposits a metal iridium thin film with a tensile stress of 200 MPa to 1000 MPa, which was measured with an optimal tensile stress of about 700 MPa and an atomic force microscope (AFM). In some cases, it is defined as a low stress deposit having an rms roughness of about 1 nm, which is below the rms roughness of 3 nm which defines a smooth surface. Iridium is deposited with a resistivity of about 14 μΩcm.

Furthermore, optimizing the position of the process (which is the distance between the heater and the wafer) to be in the range of 55 mm to 80 mm (specifically, about 65 mm) results in a uniformity of iridium thickness on the wafer of 94 mm. % To 98.5%. Typical sheet resistance, within wafer nonuniformity, for 50 nm iridium thin films is about 1.5%, and wafer-to-wafer non-uniformity is less than 1%. It is. The deposition rate of iridium ranges from 670 ° / min to 770 ° / min, specifically about 720 ° / min using 700 W DC power, but this deposition rate increases linearly with increasing power. I do.

Referring now to FIG. 3, there is shown an enlarged cross-sectional view of the memory capacitor 40 at a further intermediate stage of fabrication according to the present invention.

プ ラ Conventionally, the use of platinum with ferroelectric materials has led to durability and reliability issues. A similar problem occurs when only iridium is used. However, if an iridium oxide coating 33 is deposited on the iridium electrode 32, the reliability can be reduced from one million to 10E12 memory cycles (in some cases, up to 10E14 memory cycles). I know it can be improved.

It can be seen that iridium oxide (IrO ₂ ) can be grown at a predetermined position by sputtering 45, and the morphology, pure compatibility and structure of the surface can be controlled by the oxygen (O ₂ ) content at the time of sputtering. ing. As used herein, the term "surface morphology" relates to surface properties, including smoothness, and "pure phase" refers to one phase due to X-ray diffraction. "Texture" refers to the orientation of the particles, referring to the material where only the crystal structure peak is shown.

Through extensive experiments, various important parameters for depositing iridium oxide have been widely determined.

For example, it has been found that the surface of iridium oxide grown at 550 ° C. and 350 W in an atmosphere containing 60% or more oxygen becomes rough. To obtain a smooth surface, the oxygen content must be kept below about 50%.

It was also found that the IrO ₂ thin film grown at 350 W with 35% oxygen had a smooth rms roughness of about 1 nm, and the thin film grown at 350 W with 70% oxygen had an rms roughness of about 23 nm. I have. In the latter case, facets (or facets) are present in some of the particles. This is observed in all thin films grown in excess oxygen and is related to a microstructural change from the (200) crystalline structure to a polycrystalline structure. Pure-phase IrO ₂ has a columnar microstructure.

Further, the pure phase thin film of IrO ₂ uses 350 W, in an atmosphere containing more than 30% oxygen at 400 ° C. (the rest is argon (Ar)), and in an atmosphere containing more than 35% oxygen at 550 ° C. It is also known that it can be obtained only in. At 700 W, 50% or more oxygen is required to obtain a pure phase IrO ₂ thin film.

Further, by using magnetron reactive sputtering, iridium oxide is grown at a temperature of 400 ° C. to 450 ° C. using a DC power of 350 W to 700 W in an oxygen atmosphere containing more than 20% of oxygen, thereby achieving a high texture. It has also been found that the (200) pure phase IrO ₂ thin film can be optimized.

From the above results, the tensile stress is 500 MPa to 1500 MPa, the rms roughness is less than 3 nm, and a low stress and smooth IrO ₂ thin film can be formed.

Referring now to FIG. 4, there is shown an enlarged cross-sectional view of the memory capacitor 40 at another further intermediate stage of fabrication according to the present invention.

Metal oxide chemical vapor deposition (MOCVD) on optimized IrO ₂ at relatively high wafer temperatures of 600-610 ° C. without reducing this oxide It is known that the ferroelectric layer 36 can be deposited. This process produces a layer of very high quality, very thin and uniform in thickness, and free of pinholes.

Referring to FIG. 5, there is shown an enlarged sectional view of a memory capacitor according to the present invention.

A frontside IrO ₂ coating 37 has been deposited. It has been found that this frontside coating 37 can be grown at low power (ie, 350 W). Deposited in an atmosphere containing 30% to 40% oxygen, IrO ₂ of the rms roughness of about 3nm is obtained. Note that IrO ₂ requires at least 35% oxygen when deposited on an Ir surface, but can be deposited with 30% oxygen on a PZT surface. The data shows a correlation between the structure of IrO ₂ and its roughness. For example, IrO ₂ grown at 700 W in 50% oxygen is (200) oriented and fairly smooth. As the thin film becomes polycrystalline, the surface roughness increases.

The iridium upper electrode 38 is deposited in the same manner as the lower electrode 32.

Since stress plays an increasingly important role in the case of miniaturized microelectronic devices, experiments are being conducted to reduce the stress of iridium and iridium oxide grown by the methods described above. . It has been found that the stress of a thin film grown at 550 ° C. using 700 W power can be reduced by about 33% by annealing at 450 ° C. to 600 ° C. for about 2 minutes in nitrogen (N ₂ ).

Referring to FIG. 6, a method 50 according to the present invention is shown in a simplified flowchart. The method 50 includes forming a low stress, smooth iridium on the semiconductor structure 52 and forming a low stress, smooth, pure phase iridium oxide on the low stress, smooth iridium. Step 54 and Step 56 of forming a ferroelectric material on the iridium oxide are included.

While the present invention has been described with reference to certain preferred embodiments, those skilled in the art will recognize that numerous alternatives, modifications and variations will be apparent from the foregoing description. Accordingly, all such alternatives, modifications and variations that fall within the spirit and scope of the appended claims are also included within the scope of the present invention. Also, all matter set forth herein or shown in the accompanying drawings should be construed as illustrative and not limiting.

1 is a sectional view of a three-dimensional ferroelectric memory integrated circuit according to the present invention. FIG. 4 is an enlarged sectional view of a memory capacitor in an intermediate stage of manufacturing according to the present invention. FIG. 4 is an enlarged cross-sectional view of the memory capacitor at a further intermediate stage of the manufacturing according to the invention. FIG. 5 is an enlarged cross-sectional view of a memory capacitor at another further intermediate stage of the manufacturing according to the present invention. FIG. 3 is an enlarged sectional view of a memory capacitor according to the present invention. 3 is a simple flowchart illustrating the method according to the present invention.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 10 Ferroelectric semiconductor device 12 Semiconductor structure 32, 34, 38 Iridium 33, 37 Iridium oxide 36 Ferroelectric material

Claims (10)

Forming low stress, smooth iridium on the semiconductor structure;
Forming a low stress, smooth, iridium oxide having a pure phase structure on the low stress, smooth iridium;
Forming a ferroelectric material on the iridium oxide. The method of claim 1, wherein the step of forming low stress, smooth iridium forms iridium having a tensile stress of 200 MPa to 1000 MPa and an rms roughness of less than 3 nm. The method of claim 1 wherein the step of forming a low stress, smooth iridium oxide is to form an iridium oxide having a tensile stress of 500 MPa to 1500 MPa and an rms roughness of less than 3 nm. The method of claim 1, wherein the step of forming a low stress, smooth iridium oxide uses physical deposition in an atmosphere containing 20% to 50% oxygen. The step of forming a low stress, smooth iridium oxide is using a 350 W to 700 W physical deposition method in an atmosphere at a temperature of 400 ° C. to 450 ° C. and 20% to 50% oxygen. Item 2. The method according to Item 1. Annealing the iridium and the iridium oxide at 450 ° C. to 600 ° C .;
Annealing the iridium or a combination of the iridium and the iridium oxide prior to the deposition of the iridium oxide. A semiconductor structure;
Low-stress, smooth iridium located on the semiconductor structure;
An iridium oxide having a low-stress, smooth, pure-phase structure, which is located on the low-stress, smooth iridium;
A ferroelectric material located on the iridium oxide. The device of claim 7, wherein the low stress, smooth iridium has a tensile stress of 200 MPa to 1000 MPa and an rms roughness of less than 3 nm. The device of claim 7, wherein the low stress, smooth iridium oxide has a tensile stress of 500 MPa to 1500 MPa and an rms roughness of less than 3 nm. The device of claim 7, wherein the ferroelectric material is a ferroelectric material selected from the group consisting of bismuth strontium tantalate, lead zirconate titanate, and combinations thereof.

Images